AD AD9887AKSZ-1001 Dual interface for flat panel display Datasheet

Dual Interface for
Flat Panel Display
AD9887A
FEATURES
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
REF
REFIN
RAIN
CLAMP
CLAMP
A/D
BAIN
CLAMP
A/D
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SOGIN
SCL
SDA
A1
A0
8
A/D
GAIN
REFOUT
8
8
8
ROUTA
8
ROUTB
8
GOUTA
8
GOUTB
8
BOUTA
8
2
DATACK
HSOUT
SYNC
PROCESSING
AND CLOCK
GENERATION
VSOUT
SOGOUT
8
SCDT
8
MUXES
Analog interface
170 MSPS maximum conversion rate
Programmable analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
Full sync processing
Midscale clamping
4:2:2 output format mode
Digital interface
DVI 1.0-compatible interface
170 MHz operation (2 pixels/clock mode)
High skew tolerance of 1 full input clock
Sync detect for hot plugging
Supports high bandwidth digital content protection
SERIAL REGISTER
AND
POWER MANAGEMENT
8
8
8
8
DIGITAL INTERFACE
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
8
8
8
DVI
RECEIVER
2
RED A
RED B
GREEN A
GREEN B
BLUE A
BLUE B
8
ROUTA
8
ROUTB
8
GOUTA
HSOUT
8
GOUTB
VSOUT
8
BOUTA
8
BOUTB
2
DATACK
DATACK
SOGOUT
DE
DE
HSOUT
GENERAL DESCRIPTION
VSOUT
DDCSCL
DDCSDA
MCL
MDA
Analog Interface
Digital Interface
The complete 8-bit, 170 MSPS, monolithic analog interface is
optimized for capturing RGB graphics signals from personal
computers and workstations. Its 170 MSPS encode rate capability
and full-power analog bandwidth of 330 MHz support resolutions
of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes
a 170 MHz triple ADC with internal 1.25 V reference; a phaselocked loop (PLL); and programmable gain, offset, and clamp
controls. The user provides only a 3.3 V power supply, analog
input, and Hsync. Three-state CMOS outputs can be powered
from 2.5 V to 3.3 V. The analog interface also offers full sync
processing for composite sync and sync-on-green (SOG) applications. The AD9887A on-chip PLL generates a pixel clock from
Hsync with output frequencies ranging from 12 MHz to 170 MHz.
PLL clock jitter is typically 500 ps p-p at 170 MSPS.
The AD9887A contains a DVI 1.0-compatible receiver and
supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The
receiver operates with true color (24-bit) panels in one or two
pixel(s) per clock mode and features an intrapair skew tolerance
of up to one full clock cycle. With the inclusion of HDCP,
displays can receive encrypted video content. The AD9887A
allows for authentication of a video receiver, decryption of encoded
data at the receiver, and renewability of authentication during
transmission, as specified by the HDCP v1.0 protocol. Fabricated
in an advanced CMOS process, the AD9887A is provided in a
160-lead, surface-mount, plastic MQFP and is specified over the
0°C to 70°C temperature range. The AD9887A is also available
in an RoHS compliant package.
HDCP
AD9887A
02838-001
The AD9887A offers an analog interface receiver and a digital
visual interface (DVI) receiver integrated on a single chip,
supports high bandwidth digital content protection (HDCP),
and is software and pin-to-pin compatible with the AD9887.
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD9887A
TABLE OF CONTENTS
Features .............................................................................................. 1
Hot-Plug Detect.......................................................................... 27
Applications....................................................................................... 1
Power Management ................................................................... 27
General Description ......................................................................... 1
Scan Function ............................................................................. 28
Functional Block Diagram .............................................................. 1
Theory of Operation—Digital Interface...................................... 29
Revision History ............................................................................... 2
Capturing Encoded Data........................................................... 29
Specifications..................................................................................... 3
Data Frames ................................................................................ 29
Analog Interface ........................................................................... 3
Special Characters ...................................................................... 29
Digital Interface ............................................................................ 5
Channel Resynchronization...................................................... 29
Absolute Maximum Ratings............................................................ 7
Data Decoder .............................................................................. 29
Explanation of Test Levels ........................................................... 7
HDCP .......................................................................................... 29
ESD Caution.................................................................................. 7
General Timing Diagrams—Digital Interface............................ 31
Pin Configuration and Function Descriptions............................. 8
Timing Mode Diagrams—Digital Interface ........................... 31
Pin Function Details—Pins Shared Between Digital and
Analog Interfaces........................................................................ 11
2-Wire Serial Register Map ........................................................... 32
Pin Function Details—Analog Interface ................................. 13
Theory of Operation—Sync Processing ...................................... 48
Pin Function Details—Digital Interface.................................. 16
Sync Stripper ............................................................................... 48
Theory of Operation and Design Guide—Analog Interface .... 17
Sync Separator ............................................................................ 48
General Description................................................................... 17
PCB Layout Recommendations.................................................... 49
Input Signal Handling................................................................ 17
Analog Interface Inputs ............................................................. 49
HSYNC and VSYNC Inputs...................................................... 17
Digital Interface Inputs.............................................................. 49
Clamping ..................................................................................... 17
Power Supply Bypassing ............................................................ 49
Gain and Offset Control............................................................ 18
PLL ............................................................................................... 50
Sync-on-Green Input ................................................................. 19
Outputs—Both Data and Clocks.............................................. 50
Clock Generation ....................................................................... 19
Digital Inputs .............................................................................. 50
Alternate Pixel Sampling Mode ................................................ 22
Voltage Reference ....................................................................... 50
Timing—Analog Interface ........................................................ 23
Outline Dimensions ....................................................................... 51
Theory of Operation—Interface Detection ................................ 27
Ordering Guide .......................................................................... 51
2-Wire Serial Control Register Details.................................... 35
Active Interface Detection and Selection ................................ 27
REVISION HISTORY
3/07—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Figure 28...................................................................... 27
Changes to Figure 37 and Figure 40............................................. 31
12/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added Pb-Free Package .....................................................Universal
Changes to Figure 1.......................................................................... 1
Changes to Specifications ................................................................ 4
Changes to Table 4.......................................................................... 10
Deleted Analog Interface Pin List Table ...................................... 11
Added Figure 3................................................................................ 18
Added TV Section in Table 7........................................................ 22
Deleted Digital Interface Pin List Table....................................... 24
Changes to Theory of Operation
(Interface Detection) Section........................................................ 28
Added Hot-Plug Detect Section ................................................... 28
Changes to Table 8.......................................................................... 29
Changes to Figure 32...................................................................... 32
Changes to Control Bits Section................................................... 44
Change to Figure 42 ....................................................................... 48
Updated Outline Dimensions....................................................... 53
Changes to Ordering Guide .......................................................... 53
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 52
AD9887A
SPECIFICATIONS
ANALOG INTERFACE
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.
Table 1.
AD9887AKS-100
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUTS
Voltage Range
Minimum
Maximum
Gain Tempco
Bias Current
Full-Scale Matching
Offset Adjustment
Range
REFERENCE OUTPUTS
Voltage Range
Temperature Coefficient
SWITCHING
PERFORMANCE 1
Max Conversion Rate
Min Conversion Rate
Clock-to-Data Skew,
tSKEW
Serial Port Timing
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Max PLL Clock Rate
Min PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
Temp
Test
Level
25°C
Full
25°C
Full
25°C
I
VI
I
VI
I
Full
Full
25°C
25°C
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
Full
Full
V
V
Full
Full
Full
VI
IV
IV
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
Min
Typ
8
Max
AD9887AKS-140
Min
±0.5
+1.15/−1.0
+1.15/−1.0
±0.5 ±1.40
±1.75
Guaranteed
Typ
8
+1.25/−1.0
+1.25/−1.0
±0.5 ±1.4
±2.5
Guaranteed
48
43
1.3
90
4.7
4.0
250
4.7
4.0
100
4.7
4.0
15
100
110
500
0.5
1.0
48
150
1
1
8.0
53
43
4.7
4.0
250
4.7
4.0
100
4.7
4.0
15
140
10
110
440
10
Rev. B | Page 3 of 52
12
650 3
7003
10
+2.5
−1.5
4.7
4.0
250
4.7
4.0
100
4.7
4.0
15
170
110
370
10
Unit
Bits
LSB
LSB
LSB
LSB
V p-p
V p-p
ppm/°C
μA
μA
% FS
% FS
V
ppm/°C
170
10
+2.5
−1.5
12
700 2
10002
48
1
1
8.0
53
1.3
90
140
10
+2.5
−1.5
+1.25/−1.0
+1.50/−1.0
±1.0 ±2.25
±2.75
Guaranteed
1.3
90
100
Max
±0.8
150
1
1
8.0
53
Typ
8
0.5
1.0
135
43
Min
±0.5
0.5
1.0
Max
AD9887AKS-170
12
500 4
7004
MSPS
MSPS
ns
μs
μs
ns
μs
μs
ns
μs
μs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
AD9887A
AD9887AKS-100
Parameter
DIGITAL INPUTS
Voltage High, VIH
Voltage Low, VIL
Current High, VIH
Current Low, VIL
Capacitance
DIGITAL OUTPUTS
Voltage High, VOH
Voltage Low, VOL
Duty Cycle
DATACK, DATACK
Output Coding
POWER SUPPLIES
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current, VD
IDD Supply Current, VDD 5
IPVD Supply Current, PVD
Total Supply Current5
Power-Down Supply
Current
DYNAMIC PERFORMANCE
Analog Bandwidth,
Full Power
Transient Response
Overvoltage Recovery
Time
Signal-to-Noise Ratio
(SNR) 6
fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θJA Junction-to-Ambient
Thermal Resistance 7
AD9887AKS-140
AD9887AKS-170
Temp
Test
Level
Full
Full
Full
Full
25°C
VI
VI
IV
IV
V
2.6
Full
Full
VI
VI
2.4
Full
IV
45
55
60
Binary
45
55
60
Binary
45
55
65
Binary
%
Full
Full
Full
25°C
25°C
25°C
Full
Full
IV
IV
IV
V
V
V
VI
VI
3.15
2.2
3.15
3.3
3.3
3.3
167
33
43
243
90
3.15
2.2
3.15
3.3
3.3
3.3
185
46
43
274
90
3.15
2.2
3.15
3.3
3.3
3.3
230
55
60
345
90
V
V
V
mA
mA
mA
mA
mA
25°C
V
330
330
330
MHz
25°C
25°C
V
V
2
1.5
2
1.5
2
1.5
ns
ns
25°C
V
46
46
45
dB
Full
V
60
60
60
dBc
V
37
37
37
°C/W
Min
Typ
Max
Min
Typ
Max
2.6
Min
0.8
−1.0
1.0
3
3
Drive strength = 11.
VCO range = 01, charge-pump current = 001, PLL divider = 1693.
3
VCO range = 10, charge-pump current = 110, PLL divider = 1600.
4
VCO range = 11, charge-pump current = 110, PLL divider = 2159.
5
DEMUX = 1, DATACK and DATACK load = 10 pF, data load = 5 pF.
6
Using external pixel clock.
7
Simulated typical performance with package mounted to a 4-layer board.
2
Rev. B | Page 4 of 52
0.8
−1.0
1.0
V
V
μA
μA
pF
2.4
0.4
1
Unit
3
2.4
0.4
330
120
Max
2.6
0.8
−1.0
1.0
3.45
3.45
3.45
Typ
3.45
3.45
3.45
360
120
0.4
3.45
3.45
3.45
390
120
V
V
AD9887A
DIGITAL INTERFACE
VD = 3.3 V, VDD = 3.3 V, clock = maximum, unless otherwise noted.
Table 2.
AD9887AKS
Parameter
RESOLUTION
DC DIGITAL I/O SPECIFICATIONS
High Level Input Voltage, VIH
Low Level Input Voltage, VIL
High Level Output Voltage, VOH
Low Level Output Voltage, VOL
Input Clamp Voltage, VCINL
Input Clamp Voltage, VCIPL
Output Clamp Voltage, VCONL
Output Clamp Voltage, VCOPL
Output Leakage Current, IOL
DC SPECIFICATIONS
Output High Drive, IOHD (VOUT = VOH)
Conditions
Temp
Min
Typ
8
Max
ICL = −18 mA
ICL = +18 mA
ICL = −18 mA
ICL = +18 mA
High impedance
Full
Output drive = high
Output drive = med
Output drive = low
Full
Full
Full
IV
IV
IV
13
8
5
mA
mA
mA
Output Low Drive, IOLD (VOUT = VOL)
Output drive = high
Output drive = med
Output drive = low
Full
Full
Full
IV
IV
IV
−9
−7
−5
mA
mA
mA
DATACK High Drive, IOHC (VOUT = VOH)
Output drive = high
Output drive = med
Output drive = low
Full
Full
Full
IV
IV
IV
25
12
8
mA
mA
mA
DATACK Low Drive, IOLC (VOUT = VOL)
Output drive = high
Output drive = med
Output drive = low
Full
Full
Full
Full
IV
IV
IV
IV
−25
−19
−8
75
800
mA
mA
mA
mA
Full
Full
IV
IV
3.15
2.2
3.3
3.3
3.45
3.45
V
V
Full
25°C
255°C
255°C
IV
V
V
IV
VI
3.15
3.3
350
40
130
520
3.45
V
mA
mA
mA
mA
PVD Supply Voltage
ID Supply Current 1
IDD Supply Current1, 2
IPVD Supply Current1
Total Supply Current with HDCP1, 2
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew, TDPS
Channel-to-Channel Differential Input Skew,
TCCS
Low-to-High Transition Time for Data and
Controls, DLHT
Minimum value for two pixels
per clock mode
2.6
Unit
Bits
VI
VI
VI
VI
IV
IV
IV
IV
IV
Differential Input Voltage,
Single-Ended Amplitude
POWER SUPPLIES
VD Supply Voltage
VDD Supply Voltage
Full
Full
Full
Full
Test
Level
V
0.8
2.4
0.4
GND − 0.8
VDD + 0.8
GND − 0.8
VDD + 0.8
+10
−10
560
V
V
V
V
V
V
μA
Full
Full
IV
IV
360
1.0
Output drive = high; CL = 10 pF
Full
IV
2.5
ps
Clock
period
ns
Output drive = med; CL = 7 pF
Output drive = low; CL = 5 pF
Full
Full
IV
IV
3.1
5.4
ns
ns
Rev. B | Page 5 of 52
AD9887A
AD9887AKS
Parameter
Low-to-High Transition Time (DLHT) for DATACK
High-to-Low Transition Time (DHLT) for Data
High-to-Low Transition Time (DHLT) for DATACK
Conditions
Output drive = high; CL = 10 pF
Output drive = med; CL = 7 pF
Output drive = low; CL = 5 pF
Output drive = high; CL = 10 pF
Output drive = med; CL = 7 pF
Output drive = low; CL = 5 pF
Output drive = high; CL =10 pF
Output drive = med; CL = 7 pF
Output drive = low; CL = 5 pF
Clock-to-Data Skew, tSKEW 3
Duty Cycle, DATACK, DATACK3
DATACK Frequency (fCIP)
DATACK Frequency (fCIP)
1 pixel/clock
2 pixels/clock
1
The typical pattern contains a gray-scale area, output drive = high.
DATACK and DATACK load = 10 pF, data load = 5 pF, and HDCP disabled.
3
Drive strength = 11.
2
Rev. B | Page 6 of 52
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
0
45
Max
1.2
1.6
2.3
2.6
3.0
3.7
1.4
1.6
2.4
4.0
55
Full
Full
VI
IV
20
10
140
85
Min
Typ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
% of
period
high
MHz
MHz
AD9887A
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Table 3.
Parameter
VD
VDD
Analog Inputs
VREFIN
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
3.6 V
3.6 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to +85°C
−65°C to +150°C
150°C
150°C
I.
II.
III.
IV.
V.
VI.
100% production tested.
100% production tested at 25°C; sample tested at
specified temperatures.
Sample tested only.
Guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design
and characterization testing.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 7 of 52
AD9887A
121
122
125
124
123
126
128
127
129
130
131
132
DATACK
DATACK
GND
VDD
GND
GND
SCANIN
GND
VD
REFOUT
REFIN
VD
VD
GND
GND
133
134
135
136
138
137
139
140
143
142
141
144
145
147
146
149
148
150
151
152
153
156
155
157
158
154
120 RMIDSCV
119 RAIN
1
PIN 1
IDENTIFIER
2
3
118 RCLAMP V
117 VD
4
116 GND
115 VD
5
6
9
114 VD
113 GND
112 GND
10
111
11
110
7
8
12
109
13
108
14
107
15
106
105
AD9887A
17
104
TOP VIEW
(Not to Scale)
18
19
103
102
20
101
21
22
100
99
23
98
24
97
25
96
26
95
27
94
28
93
29
92
30
31
91
90
32
89
33
88
34
87
35
86
36
85
37
84
38
83
80
79
77
78
76
75
73
74
72
71
70
69
68
67
66
65
64
63
62
61
59
60
58
57
56
54
55
53
52
51
50
49
48
47
45
46
44
43
NC = NO CONNECT
42
82
81
41
39
40
Figure 2. Pin Configuration
Rev. B | Page 8 of 52
GMIDSCV
GAIN
GCLAMP V
SOGIN
VD
GND
VD
VD
GND
GND
BMIDSCV
BAIN
BCLAMP V
VD
GND
VD
GND
CKINV
CLAMP
SDA
SCL
A0
A1
PVD
PVD
GND
GND
COAST
CKEXT
HSYNC
VSYNC
02838-002
16
GND
GND
VDD
GND
SCANOUT
CTL0
CTL1
CTL2
MCL
SCANCLK
VD
GND
RTERM
VD
VD
Rx2+
Rx2–
GND
Rx1+
Rx1–
GND
Rx0+
Rx0–
GND
RxC+
RxC–
VD
VD
GND
VD
MDA
DDCSDA
DDCSCL
GND
PVD
GND
PVD
FILT
PVD
GND
VDD
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
VDD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
VDD
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
VDD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
159
160
RED B<0>
RED B<1>
RED B<2>
RED B<3>
RED B<4>
RED B<5>
RED B<6>
RED B<7>
GND
VDD
RED A<0>
RED A<1>
RED A<2>
RED A<3>
RED A<4>
RED A<5>
RED A<6>
RED A<7>
GND
VDD
SOGOUT
HSOUT
VSOUT
DE
SCDT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9887A
Table 4. Pin Function Descriptions
Pin Type
Analog Video Data Inputs
Sync/Clock Inputs
Sync Outputs
Voltage References
Clamp Voltages
PLL Filter
Power Supplies
Serial Port
Mnemonic
RAIN
GAIN
BAIN
HSYNC
VSYNC
SOGIN
CLAMP
COAST
CKEXT
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Pin No.
119
110
100
82
81
108
93
84
83
Interface
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1.25 V
94
139
138
140
126
Analog
Analog/Digital
Analog/Digital
Analog
Analog
REFIN
RMIDSCV
RCLAMPV
GMIDSCV
GCLAMPV
BMIDSCV
BCLAMPV
FILT
VD
Description
Analog Input for Red Channel
Analog Input for Green Channel
Analog Input for Blue Channel
Horizontal Sync Input
Vertical Sync Input
Sync-on-Green Input
External Clamp Input (Optional)
PLL Coast Signal Input (Optional)
External Pixel Clock Input (to Bypass the PLL) to VDD
or Ground (Optional)
ADC Sampling Clock Invert (Optional)
Horizontal Sync Output
Vertical Sync Output
Sync-on-Green Slicer Output or Raw Hsync
Internal Reference Output (bypass with 0.1 μF to
Ground)
Reference Input (1.25 V ± 10%)
Red Channel Midscale Clamp Voltage Output
Red Channel Midscale Clamp Voltage Input
Green Channel Midscale Clamp Voltage Output
Green Channel Midscale Clamp Voltage Input
Blue Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Input
External Filter Connection (Component of PLL)
Main Power Supply
1.25 V ± 10%
0.5 V ± 50%
0.0 V to 0.75 V
0.5 V ± 50%
0.0 V to 0.75 V
0.5 V ± 50%
0.0 V to 0.75 V
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog/Digital
VDD
Output Power Supply
3.3 V ± 5%
PVD
PLL Power Supply
3.3 V ± 5%
GND
Ground
0V
SDA
Serial Port Data I/O
3.3 V CMOS
125
120
118
111
109
101
99
78
51, 54, 55,
67, 68, 70,
96, 98,
104, 105,
107, 114,
115, 117,
123, 124,
127
1, 11, 21,
31, 43,
132, 141,
151
75, 77,
79, 87, 88
2, 12, 22,
32, 41, 42,
44, 52, 58,
61, 64, 69,
74, 76, 80,
85, 86, 95,
97, 102,
103, 106,
112, 113,
116, 121,
122, 128,
130, 131,
133, 142,
152
92
CKINV
HSOUT
VSOUT
SOGOUT
REFOUT
Rev. B | Page 9 of 52
3.3 V ± 5%
Analog/Digital
Analog/Digital
Analog/Digital
Analog/Digital
AD9887A
Pin Type
2-Wire Serial Interface
Data Outputs
Mnemonic
SCL
A0
A1
RED B[7:0]
GREEN
B[7:0]
BLUE B[7:0]
RED A[7:0]
Data Clock Outputs
Sync Detect
Scan Function
Digital Video Data
Inputs
Digital Video Clock
Inputs
Data Enable
Control Bit
Termination Control
HDCP
Description
Serial Port Data Clock (100 kHz Maximum)
Serial Port Address Input 1
Serial Port Address Input 2
Data Output, Red Channel, Port B/Odd, Bit 7 is the
MSB
Data Output, Green Channel, Port B/Odd
Value
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Pin No.
91
90
89
153 to
160
13 to 20
Interface
Analog/Digital
Analog/Digital
Analog/Digital
Analog/Digital
Data Output, Blue, Port B/Odd
Data Output, Red Channel, Port A/Even
3.3 V CMOS
3.3 V CMOS
Analog/Digital
Analog/Digital
3.3 V CMOS
33 to 40
143 to
150
3 to 10
Data Output, Green Channel, Port A/Even
3.3 V CMOS
Analog/Digital
Analog/Digital
GREEN
A[7:0]
BLUE
A[7:0]
DATACK
DATACK
SCDT
SCANIN
SCANOUT
SCANCLK
Rx0+
Data Output, Blue Channel, Port A/Even
3.3 V CMOS
23 to 30
Analog/Digital
Data Output Clock
Data Output Clock Complement
Sync Detect Output
Input for Scan Function
Output for Scan Function
Clock for Scan Function
Digital Differential Input Channel 0 True
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
134
135
136
129
45
50
62
Analog/Digital
Analog/Digital
Analog/Digital
Analog/Digital
Analog/Digital
Analog/Digital
Digital
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
Digital Differential Input Channel 0 Complement
Digital Differential Input Channel 1 True
Digital Differential Input Channel 1 Complement
Digital Differential Input Channel 2 True
Digital Differential Input Channel 2 Complement
Digital Differential Data Clock True
63
59
60
56
57
65
Digital
Digital
Digital
Digital
Digital
Digital
RxC−
DE
CTL0, CTL1,
CTL2
RTERM
DDCSCL
DDCSDA
MCL
MDA
Digital Differential Data Clock Complement
Data Enable
Digital Control Outputs
3.3 V CMOS
3.3 V CMOS
66
137
46 to 48
Digital
Digital
Digital
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
53
73
72
49
71
Digital
Digital
Digital
Digital
Digital
Internal Termination Resistance Set Pin
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
Rev. B | Page 10 of 52
AD9887A
PIN FUNCTION DETAILS—PINS SHARED BETWEEN DIGITAL AND ANALOG INTERFACES
Sync Outputs
Data Clock Outputs
HSOUT
Horizontal Sync Output
DATACK Data Output Clock
The horizontal sync output is a reconstructed
version of the video Hsync, phase-aligned with
DATACK. The polarity of this output can be
controlled via a serial bus bit. In analog interface
mode, the placement and duration are variable. In
digital interface mode, the placement and duration
are set by the graphics transmitter.
DATACK Data Output Clock Complement
VSOUT
Like the data outputs, the data clock outputs are
shared between the two interfaces. They also behave
differently, depending on which interface is active.
See the Theory of Operation and Design Guide—
Analog Interface and the Theory of Operation—
Digital Interface sections for details on how these
pins behave.
Vertical Sync Output
The Vsync is separated from a composite signal or
a direct pass-through of the Vsync input. The polarity
of this output can be controlled via a serial bus bit.
The placement and duration in all modes are set by
the graphics transmitter.
Sync Detect
SCDT
Chip Active/Inactive Detect Output
The logic for the SCDT pin is analog interface
HSYNC detection or digital interface DE detection.
Therefore, the SCDT pin switches to logic low under
two conditions: when neither interface is active, or
when the chip is in full power-down mode. The data
outputs are automatically set to three-state when
SCDT is low. This pin can be read by a controller to
identify periods of inactivity.
2-Wire Serial Port
SDA
Serial Port Data I/O
SCL
Serial Port Data Clock
A0
Serial Port Address Input 1
A1
Serial Port Address Input 2
Scan Function
For a full description of the 2-wire serial register
and how it works, see the 2-Wire Serial Control
Port section.
SCANIN
By using the scan function, 48 bits of data can be
loaded into the data outputs. Data is input serially
through this pin, clocked with the SCANCLK pin,
and comes through the outputs as parallel words.
This function is useful for loading known data into
a graphics controller chip for testing purposes.
Data Outputs
RED A
Data Output, Red Channel, Port A/Even
RED B
Data Output, Red Channel, Port B/Odd
GREEN A Data Output, Green Channel, Port A/Even
SCANOUT Data Output for Scan Function
GREEN B Data Output, Green Channel, Port B/Odd
BLUE A
Data Output, Blue Channel, Port A/Even
BLUE B
Data Output, Blue Channel, Port B/Odd
Data Input for Scan Function
The data input serially into the SCANIN register can
be read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
These outputs are the main data outputs. Bit 7 is the
MSB. These outputs are shared between the two
interfaces.
SCANCLK
Rev. B | Page 11 of 52
Data Clock for Scan Function
This pin clocks the data for the scan function.
It controls both data input and output.
AD9887A
Power Supplies
VD
PVD
Main Power Supply
The most sensitive portion of the AD9887A is the
clock generation circuitry. These pins provide
power to the clock PLL and help the user design for
optimal performance. The designer should provide
noise-free power to these pins.
These pins supply power to the main elements of
the circuit. They should be filtered to be as quiet
as possible.
VDD
Digital Output Power Supply
These supply pins are identified separately from the
VD pins; therefore, special care can be taken to
minimize output noise transferred into the sensitive
analog circuitry.
Clock Generator Power Supply
GND
If the AD9887A is interfacing with lower voltage
logic, VDD can be connected to a lower supply
voltage (as low as 2.2 V) for compatibility.
Rev. B | Page 12 of 52
Ground
This is the ground return for all circuitry on the
chip. It is recommended that the application circuit
board have a single, solid ground plane.
AD9887A
PIN FUNCTION DETAILS—ANALOG INTERFACE
When not used, leave this input unconnected. For
more details on this function and how it should be
configured, refer to the Sync-on-Green Input section.
Analog Video Data Inputs
RAIN
GAIN
BAIN
Analog Input for Red Channel
Analog Input for Green Channel
Analog Input for Blue Channel
CLAMP
This logic input can be used to define the time
during which the input signal is clamped to the
reference dc level (ground for RGB, midscale for
YUV). It should be used when the reference dc level
is known to be present on the analog input channels,
typically during a period called the back porch of
the graphics signal following Hsync. The CLAMP
pin is enabled by setting control bit EXTCLMP to 1
(the default at power-up is 0). When disabled, this
pin is ignored and the clamp timing is determined
internally by counting the delay and duration from
the trailing edge of the HSYNC input. The logic
sense of this pin is controlled by CLAMPOL. When
not used, this pin must be grounded and EXTCLMP
must be programmed to 0.
These are the high impedance inputs that accept
graphics signals from the red, green, and blue
channels, respectively. For RGB, the three channels
are identical and can be used for any color, but colors
are assigned for convenient reference. For proper
4:2:2 formatting in a YUV application, the Y channel
must be connected to the GAIN input, U must be
connected to the BAIN input, and V must be
connected to the RAIN input.
These pins accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be ac-coupled
to these pins to support clamp operation.
External Inputs
HSYNC
Horizontal Sync Input
This input receives a logic signal that establishes the
horizontal timing reference and provides the frequency reference for pixel clock generation.
COAST
The input includes a Schmitt trigger for noise
immunity with a nominal input threshold of 1.5 V.
The logic sense of this pin is controlled by coast
polarity. When not used, this pin can be grounded
with coast polarity programmed to 1, or tied high
with coast polarity programmed to 0. Coast polarity
defaults to 1 at power-up.
Electrostatic discharge (ESD) protection diodes
conduct heavily if this pin is driven more than 0.5 V
above the maximum tolerance voltage (3.3 V) or
more than 0.5 V below ground.
CKEXT
Vertical Sync Input
This is the input for vertical sync.
Sync/Clock Inputs
SOGIN
Clock Generator Coast Input (Optional)
This input can be used to stop the pixel clock generator
from synchronizing with Hsync while maintaining
the clock at its current frequency and phase. This is
useful when processing signals from sources that
fail to produce horizontal sync pulses when in the
vertical interval. The coast signal is generally not
required for PC-generated signals. For applications
requiring coast, it is provided through the internal
coast found in the sync processing engine.
The logic sense of this pin is controlled by Serial
Register 0x0F, Bit 7 (Hsync polarity). Only the leading
edge of Hsync is active; the trailing edge is ignored.
When Hsync polarity = 0, the falling edge of Hsync
is used. When Hsync polarity = 1, the rising edge is
active.
VSYNC
External Clamp Input (Optional)
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the green
channel. The pin is connected to a high speed comparator with an internally generated threshold that is
0.15 V above the negative peak of the input signal.
When connected to an ac-coupled graphics signal
with embedded sync, it produces a noninverting
digital output on SOGOUT.
Rev. B | Page 13 of 52
External Clock Input (Optional)
This pin can be used to provide an external clock to
the AD9887A in place of the clock internally
generated from HSYNC. It is enabled by programming CKEXT to 1. When an external clock is used,
all other internal functions, including the clock
phase adjustment, operate normally. When not
used, this pin should be tied to VDD or to ground
and CKEXT should be programmed to 0.
AD9887A
CKINV
REFIN
Sampling Clock Inversion (Optional)
This pin can be used to invert the pixel sampling
clock, which has the effect of shifting the sampling
phase 180°. This supports the alternate pixel
sampling mode, wherein higher frequency input
signals (up to 340 MPPS) can be captured by
sampling the odd pixels and capturing the even
pixels on the subsequent frame.
This pin should be used only during blanking
intervals (typically vertical blanking), because it
might produce several samples of corrupted data
during the phase shift.
The reference input accepts the master reference
voltage for all AD9887A internal circuitry (1.25 V ±
10%). It can be driven directly by the REFOUT pin.
Its high impedance presents a very light load to the
reference source.
This pin should always be bypassed to ground with
a 0.1 μF capacitor.
PLL Filter
FILT
Sync Outputs
HSOUT
Horizontal Sync Output
A reconstructed, phase-aligned version of the HSYNC
input. Both the polarity and duration of this output
can be programmed via serial bus registers.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with respect to
horizontal sync can be determined.
External Filter Connection
For proper operation, the pixel clock generator, PLL,
requires an external filter. Connect the filter shown
in Figure 11 to this pin. For optimal performance,
minimize noise and parasitics on this node.
CKINV should be grounded when not used.
Either or both signals can be used, depending on
the timing mode and the interface design used.
Reference Input
Data Outputs
RED A
Data Output, Red Channel, Port A/Even
RED B
Data Output, Red Channel, Port B/Odd
GREEN A Data Output, Green Channel, Port A/Even
GREEN B Data Output, Green Channel, Port B/Odd
BLUE A
Data Output, Blue Channel, Port A/Even
BLUE B
Data Output, Blue Channel, Port B/Odd
These are the main data outputs. Bit 7 is the MSB.
SOGOUT Sync-on-Green Slicer Output
This pin can be programmed to output either the
composite sync output from the sync-on-green slicer
comparator or an unprocessed, but delayed, version
of the HSYNC input. See the sync processing block
diagram (Figure 43) to see how this pin is connected.
Voltage References
REFOUT Internal Reference Output
This is the output from the internal 1.25 V band gap
reference. This output is intended to drive relatively
light loads. It can drive the AD9887A reference input
directly, but should be externally buffered if it is used
to drive other loads, as well.
The absolute accuracy of this output is ±4%, and the
temperature coefficient is ±50 ppm, which is adequate
for most AD9887A applications. If higher accuracy
is required, an external reference can be used instead.
When using an external reference, connect this pin
to ground through a 0.1 μF capacitor.
Rev. B | Page 14 of 52
Each channel has two ports. When the part is operated
in single-channel mode (DEMUX = 0), all data
presented to Port A and Port B is placed in a high
impedance state. Programming demux to 1 establishes
the dual-channel mode, wherein alternate pixels are
presented to the Port A and Port B of each channel.
These appear simultaneously; two pixels are presented
at the time of every second input pixel when PAR is
set to 1 (parallel mode). When PAR is set to 0, pixel
data appears alternately on the two ports, one new
sample with each incoming pixel (interleaved mode).
In dual-channel mode, the first pixel after Hsync is
routed to Port A. The second pixel goes to Port B,
the third to Port A, and so on.
The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted as well.
The DATACK, DATACK, and HSOUT outputs are
also moved; therefore, the timing relationship among
the signals is maintained.
AD9887A
RMIDSCV
Red Channel Midscale Clamp Voltage Output
Data Clock Outputs
GMIDSCV
Green Channel Midscale Clamp Voltage Output
DATACK Data Output Clock
BMIDSCV
Blue Channel Midscale Clamp Voltage Output
DATACK Data Output Clock Complement
RCLAMPV
Red Channel Midscale Clamp Voltage Input
GCLAMPV
Green Channel Midscale Clamp Voltage Input
BCLAMPV
Blue Channel Midscale Clamp Voltage Input
These differential data clock output signals are used to
strobe the output data and HSOUT into external logic.
These pins are part of the circuit that provides a
voltage reference for midscale clamping used in the
capture of YUV and YPbPr input signals. These
pins should be grounded through 0.1 μF capacitors,
as shown in Figure 4.
These signals are produced by the internal clock
generator and are synchronous with the internal
pixel sampling clock.
When the AD9887A is operated in single-channel
mode, the output frequency is equal to the pixel
sampling frequency. When the AD9887A is operated
in dual-channel mode, the clock frequency is half
the pixel frequency.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted as
well. The Data, DATACK, DATACK, and HSOUT
outputs are moved; therefore, the timing
relationship among the signals is maintained.
Rev. B | Page 15 of 52
AD9887A
PIN FUNCTION DETAILS—DIGITAL INTERFACE
Digital Video Data Inputs
Data Enable
Rx0+
Digital Differential Input Channel 0 True
DE
Rx0−
Digital Differential Input Channel 0 Complement
Rx1+
Digital Differential Input Channel 1 True
Rx1−
Digital Differential Input Channel 1 Complement
Rx2+
Digital Differential Input Channel 2 True
HDCP
Rx2−
Digital Differential Input Channel 2 Complement
DDCSCL HDCP Slave Serial Port Data Clock
These pins receive three pairs of differential, low
voltage, swing input pixel data from a digital
graphics transmitter.
Digital Video Clock Inputs
RxC+
Digital Differential Data Clock True
RxC−
Digital Differential Data Clock Complement
This pin outputs the state of data enable (DE). The
AD9887A decodes DE from the incoming stream of
data. The DE signal is high during active video and
low when there is no active video.
For use in communicating with the HDCP-enabled
DVI transmitter.
DDCSDA HDCP Slave Serial Port Data I/O
For use in communicating with the HDCP-enabled
DVI transmitter.
MCL
These pins receive the differential, low voltage,
swing input pixel clock from a digital graphics
transmitter.
HDCP Master Serial Port Data Clock
Connects the EEPROM for reading the encrypted
HDCP keys.
MDA
Termination Control
RTERM
Data Enable
HDCP Master Serial Port Data I/O
Connects the EEPROM for reading the encrypted
HDCP keys.
Internal Termination Set Pin
This pin is used to set the termination resistance for
all digital interface high speed inputs. To set this pin,
place a resistor of 10 times the desired input termination resistance between this pin (Pin 53) and the
ground supply. Typically, the value of this resistor
should be 500 Ω.
CTL
Rev. B | Page 16 of 52
Digital Control Outputs
These pins output the control signals for the red and
green channels. CTL0 and CTL1 correspond to the
red channel input, and CTL2 and CTL3 correspond
to the green channel input.
AD9887A
THEORY OF OPERATION AND DESIGN GUIDE—ANALOG INTERFACE
47nF
RGB
INPUT
GENERAL DESCRIPTION
The AD9887A is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The device is ideal for implementing a computer
interface in HDTV monitors or for serving as the front end to
high performance video scan converters.
Implemented in a high performance CMOS process, the interface
can capture signals with pixel rates of up to 170 MHz, or of up
to 340 MHz with an alternate pixel sampling mode.
The AD9887A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a 2-wire
serial interface. Full integration of these sensitive analog functions
makes system design straightforward and less sensitive to the
physical and electrical environment.
With an operating temperature range of 0°C to 70°C, the device
requires no special environmental considerations.
INPUT SIGNAL HANDLING
The AD9887A has three high impedance analog input pins for
the red, green, and blue channels that accommodate signals
ranging from 0.5 V to 1.0 V p-p.
RAIN
GAIN
BAIN
02838-003
75Ω
Figure 3. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The AD9887A receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. It is possible to
operate the AD9887A without applying Hsync (using an
external clock), but several of the chip’s features are unavailable.
Therefore, it is recommended to provide Hsync. It can be in the
form of either a sync signal directly from the graphics source or
a preprocessed TTL- or CMOS-level signal.
The HSYNC input includes a Schmitt-trigger buffer and is capable
of handling signals that have long rise times with superior noise
immunity. In typical PC-based graphics systems, the sync signals
are simply TTL-level drivers feeding unshielded wires in the
monitor cable. As such, no termination is required or desired.
When the VSYNC input is selected as the source for Vsync, it is
used for coast generation and passed through to the VSOUT pin.
Serial Control Port
Signals are typically brought onto the interface board via a DVI-I
connector, a 15-lead D connector, or BNC connectors. The
AD9887A should be located as close as is practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 Ω) to the IC input pins.
The serial control ports are designed for 3.3 V logic. If there are
5 V drivers on the bus, the serial control port pins should be
protected with 150 Ω series resistors placed between the pull-up
resistors and the input pins.
At this point, the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9887A inputs through 47 nF capacitors. These capacitors
form part of the dc-restoration circuit (see Figure 3).
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD), but can operate with a VDD as low as
2.5 V for compatibility with 2.5 V logic.
In an ideal world of perfectly matched impedances, the best
performance would be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9887A
(330 MHz) would track the input signal continuously as it moves
from one pixel level to the next and would digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise that result in excessive ringing
and distortion of the input waveform. This makes it difficult to
establish a sampling phase that provides good image quality.
A small inductor in series with the input can be effective in rolling
off the input bandwidth slightly and providing a high quality signal
over a wider range of conditions. Using a Fair-Rite #2508051217Z0
high speed signal chip bead inductor in the circuit of Figure 3
provides good results in most applications.
RGB Clamping
Output Signal Handling
CLAMPING
To digitize the incoming signal properly, adjust the dc offset of
the input to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, the black level is at 300 mV, and the white level is at
approximately 1.0 V. Some common RGB line amplifier boxes
use emitter-follower buffers to split signals and increase drive
capability. This introduces a 700 mV dc offset to the signal.
Clamping removes this offset to allow proper capture.
Rev. B | Page 17 of 52
AD9887A
An offset is then introduced that results in the ADCs producing a
black output (Code 0x00) when the known black input is present.
The offset remains in place when other signal levels are processed,
and the entire signal is shifted to eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually always
a period following Hsync, called the back porch, when a good
black reference is provided. This is the time when clamping
should be done.
clamped to either midscale or ground independently. These bits
(Bit 0 to Bit 2) are located in Register 0x0F.
The midscale reference voltage that each ADC clamps to is
independently provided on the RMIDSCV, GMIDSCV, and BMIDSCV
pins. Each converter must have its own midscale reference,
because both offset adjustment and gain adjustment for each
converter affect the dc level of midscale.
During clamping, the Y and V converters are clamped to their
respective midscale reference inputs. These inputs are Pin BCLAMPV
and Pin RCLAMPV for the U and V converters, respectively. The
typical connections for both RGB and YUV clamping are shown
in Figure 4. Note that even if midscale clamping is not required,
all midscale voltage outputs should be connected to ground
through a 0.1 μF capacitor.
RMIDSCV
RCLAMPV
0.1μF
The clamp timing can be established by using the CLAMP pin
at the appropriate time (with EXTCLMP = 1). The polarity of
this signal is set by the clamp polarity bit.
An easier method of clamp timing uses the AD9887A internal
clamp timing generator. The clamp placement register is
programmed with the number of pixel clocks that should pass
after the trailing edge of Hsync before clamping starts. A second
register (clamp duration) sets the duration of the clamp. These
are both 8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync, and the back porch (black reference) always follows
Hsync. To establish clamping, set the clamp placement to 0x08
(to provide eight pixel periods for the graphics signal to
stabilize after sync) and set the clamp duration to 0x14 (to allow
the clamp 20 pixel periods to re-establish the black reference).
The value of the external input coupling capacitor affects the
performance of the clamp. If the value is too small, there is an
amplitude change during a horizontal line time (between
clamping intervals). If the capacitor is too large, it takes an
excessively long time for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovery from a step error of 100 mV to
within ½ LSB in 10 lines, using a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV Clamping
YUV signals are slightly different from RGB signals in that the
dc-reference level (black level in RGB signals) is at the midpoint
of the U and V video signals. For these signals, it may be necessary
to clamp to the midscale range of the ADC range (0x80), rather
than to the bottom of the ADC range (0x00).
Clamping to midscale, rather than to ground, can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that it can be
GMIDSCV
GCLAMPV
0.1μF
BMIDSCV
BCLAMPV
0.1μF
02838-044
The key to clamping is to identify a time when the graphics
system is known to be producing a black signal. Originating
from CRT displays, the electron beam is blanked by sending
a black level during horizontal retrace to prevent disturbing the
image. Most graphics systems maintain this format of sending a
black level between active video lines.
Figure 4. Typical Clamp Configuration for RGB and YUV Applications
GAIN AND OFFSET CONTROL
A block diagram of the gain and offset control integrated with
each ADC is shown in Figure 5.
The AD9887A can accommodate input signals of 0.5 V to 1.0 V
full scale. The full-scale range is set in three 8-bit registers (red
gain, green gain, and blue gain).
Code 0 gives the minimum input range (a maximum of 0.5 V);
Code 255 corresponds to the maximum input range (a minimum
of 1.0 V). Increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (red offset,
green offset, and blue offset) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range; therefore, if the
input range is doubled (from 0.5 V to 1.0 V), the offset step size
is also doubled (from 2 mV per step to 4 mV per step).
Figure 6 and Figure 7 illustrate the interaction of gain and offset
controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, which is controlled by the gain
setting. Therefore, changing the full-scale range changes the
offset (see Figure 6). The change is minimal if the offset setting
is near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same
amount as the zero-scale level.
Rev. B | Page 18 of 52
AD9887A
OFFSET
7
GAIN
8
DAC
DAC
The value of the capacitor must be 1 nF ± 20%. If sync-on-green
is not used, this connection is not required and SOGIN should
be left unconnected. (Note that the sync-on-green signal is always
negative polarity.) See the Theory of Operation—Sync Processing
section for more information.
REF
47nF
RAIN
IN
ADC
x1.2
47nF
8
BAIN
47nF
VOFF
1nF
SOGIN
Figure 5. ADC Block Diagram (Single-Channel Output)
02838-006
GAIN
02838-010
CLAMP
Figure 8. Typical Clamp Configuration for RGB and YUV Applications
CLOCK GENERATION
OFFSET = 0x7F
A phase-locked loop (PLL) is used to generate the pixel clock.
The HSYNC input provides a reference frequency for the PLL.
A voltage-controlled oscillator (VCO) generates a much higher
pixel clock frequency. This is divided by the PLL divide value
(MSBs in Register 0x01 and LSBs in Register 0x02) and phase
compared with the HSYNC input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
OFFSET = 0x3F
INPUT RANGE (V)
1.0
OFFSET = 0x00
0.5
OFFSET = 0x7F
OFFSET = 0x3F
0
0x00
0xFF
GAIN
02838-005
OFFSET = 0x00
Figure 6. Gain and Offset Control
0V
0V
INPUT RANGE
VOFF
(128 CODES)
PIXEL CLOCK
INVALID SAMPLE TIMES
02838-011
VOFF
(128 CODES)
INPUT RANGE
OFFSET
RANGE
0.5V
OFFSET RANGE
1V
The stability of this clock is important for providing the clearest,
most stable image. During each pixel time, there is a period when
the signal slews from the old pixel amplitude and settles at its
new value. Then, the input voltage is stable until the signal slews
to a new value (see Figure 9). The ratio of the slewing time to the
stable time is a function of the bandwidth of the graphics DAC,
the bandwidth of the transmission system (cable and termination),
and the overall pixel rate. Clearly, if the dynamic characteristics
of the system remain fixed, the slewing and settling times are
likewise fixed. Subtract these times from the total pixel period to
determine the stable period. At higher pixel frequencies, both the
total cycle time and stable pixel time are shorter.
02838-007
Figure 7. Relationship of Offset Range to Input Range
SYNC-ON-GREEN INPUT
The sync-on-green input operates in two steps. First, with the
aid of a negative peak detector, it sets a baseline clamp level
from the incoming video signal. Second, it sets the sync trigger
level (nominally 150 mV above the negative peak). The exact
trigger level is variable and can be programmed via Register 0x11.
The sync-on-green input must be ac-coupled to the green analog
input through its own capacitor, as shown in Figure 8.
Rev. B | Page 19 of 52
Figure 9. Pixel Sampling Times
AD9887A
•
6
5
JITTER (%)
4
3
Table 5. VCO Frequency Ranges
2
176.0
02838-008
PIXEL CLOCK (MHz)
162.0
158.0
135.0
94.5
108.0
85.5
78.7
75.0
65.0
58.2
50.0
40.0
36.0
31.5
25.1
1
0
Any jitter in the clock reduces the precision with which the
sampling time can be determined and, thus, must be subtracted
from the stable pixel time. The AD9887A clock generation
circuit is designed to minimize jitter to less than 6% of the total
pixel time in all operating modes, making its effect on valid
sampling time negligible (see Figure 10).
The PLL characteristics are determined by the loop-filter design,
the PLL charge-pump current, and the VCO range setting. The
loop-filter design is illustrated in Figure 11. Recommended settings
of VCO range and charge-pump current for VESA standard
display modes are listed in Table 7.
CP
0.0039μF
PVD
CZ
0.039μF
RZ
3.3kΩ
PV0
0
1
0
1
Pixel Clock Range (MHz)
12 to 37
37 to 74
74 to 140
140 to 170
The 3-Bit Charge-Pump Current Register. This register
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table 6.
Table 6. Charge-Pump Current/Control Bits
Ip2
0
0
0
0
1
1
1
1
•
02838-009
FILT
PV1
0
0
1
1
•
Figure 10. Pixel Clock Jitter vs. Frequency
Figure 11. PLL Loop-Filter Detail
The following programmable registers are provided to optimize
the performance of the PLL:
•
The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO range register sets this operating range.
Because there are only three possible regions, just 2 LSBs of
the VCO range register are used. The frequency ranges for
the lowest and highest regions are shown in Table 5.
The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 12 MHz to 170 MHz. The
divisor register controls the exact multiplication factor. This
register can be set to any value between 221 and 4095. (The
divide ratio used is the programmed divide ratio plus one.)
Rev. B | Page 20 of 52
Ip1
0
0
1
1
0
0
1
1
Ip0
0
1
0
1
0
1
0
1
Current (μA)
50
100
150
250
350
500
750
1500
The 5-Bit Phase Adjust Register. The phase of the
generated sampling clock can be shifted to locate an
optimum sampling point within a clock cycle. The phaseadjust register provides 32 phase-shift steps of 11.25° each.
The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjustment is operational
even if the pixel clock is provided externally. The COAST
signal allows the PLL to continue to run at the same frequency
in the absence of the incoming Hsync signal. This can be
used during the vertical sync period or any other time that
the Hsync signal is unavailable. The polarity of the coast
signal can be set through the COAST polarity bit, and the
polarity of the Hsync signal can be set through the HSYNC
polarity bit. If not using automatic polarity detection, set
the HSYNC and COAST polarity bits to match the polarity
of their respective signals.
AD9887A
Table 7. Recommended VCO Range and Charge-Pump Current Settings for Standard Display Formats
Standard
VGA
Resolution
640 × 480
SVGA
800 × 600
XGA
1024 × 768
SXGA
1280 × 1024
UXGA
TV
1600 × 1200
480i
480p
720p
1080i
1080p
Refresh Rate (Hz)
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
85
60
60
60
60
60
60
Horizontal
Frequency (kHz)
31.5
37.7
3735
43.3
35.1
3739
4831
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
91.1
75.0
15.75
31.47
45.0
33.75
33.75
Rev. B | Page 21 of 52
Pixel Rate (MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
157.500
162.000
13.51
27
74.250
74.250
148.5
VCORNGE
00
00
00
00
00
01
01
01
01
01
10
10
10
10
10
10
11
10
00
00
10
10
11
CURRENT
011
100
100
101
101
011
011
011
100
101
011
011
011
100
100
101
101
101
001
100
011
010
011
ALTERNATE PIXEL SAMPLING MODE
Logic 1 input on CKINV (Pin 94) inverts the nominal ADC
clock. CKINV can be switched between frames to implement
the alternate pixel sampling mode. This allows higher effective
image resolution to be achieved at lower pixel rates, but with
lower frame rates.
On one frame, even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be
reconstructed. This is very similar to the interlacing process
used in broadcast television systems, but the interlacing is vertical
instead of horizontal. The frame data is presented to the display
at the full desired refresh rate (usually 60 Hz) so that no flicker
artifacts are added.
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
Figure 14. Even Pixels from Frame 2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
02838-017
E
E2
E2
Figure 15. Combined Frame Output from Graphics Controller
02838-014
O
E2
02838-016
AD9887A
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
Figure 12. Odd and Even Pixels in a Frame
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
02838-018
O1
Figure 16. Subsequent Frame from Controller
02838-015
O1
Figure 13. Odd Pixels from Frame 1
Rev. B | Page 22 of 52
AD9887A
Three things happen to Hsync in the AD9887A. First, the polarity
of the HSYNC input is determined and, thus, has a known output
polarity. The known output polarity can be programmed either
active high or active low (Register 0x04, Bit 4). Second, HSOUT
is aligned with DATACK and data outputs. Third, the duration
of HSOUT (in pixel clocks) is set via Register 0x07. Use the
HSOUT signal to drive the rest of the display system.
TIMING—ANALOG INTERFACE
The timing diagrams (Figure 18 through Figure 27) show the
operation of the AD9887A analog interface in all clock modes.
The part establishes timing by sending the pixel corresponding
with the leading edge of Hsync to Data Port A. In dual-channel
mode, the next sample is sent to Data Port B. Subsequent samples
are alternated between the A and B data ports. In single-channel
mode, data is only sent to Data Port A, and Data Port B is placed
in a high impedance state.
Coast Timing
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the coast
input and function are unnecessary and should not be used.
In some systems, however, Hsync is disturbed during the vertical
sync (Vsync) period, and sometimes Hsync pulses disappear.
In other systems, such as those that use composite sync (Csync)
signals or those that embed sync-on-green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it attempts to lock on to this new frequency and changes
frequency by the end of the Vsync period. It then requires a few
lines of correct Hsync timing to recover at the beginning of a new
frame, resulting in a tearing of the image at the top of the display.
The output data clock signal is created so that its rising edge
always occurs between transitions of Data Port A and can be
used to latch the output data externally.
PXCK
ANY OUTPUT
SIGNAL
tSKEW
tDCYCLE
02838-019
DATACK
(OUTPUT)
DATA OUT
tPER
Figure 17. Analog Output Timing
Hsync Timing
Horizontal sync is processed in the AD9887A to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can operate in this manner
for several lines without significant frequency drift.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with respect
to Hsync through a full 360° in 32 steps via the phase adjust
register to optimize the pixel sampling time. Display systems
use Hsync to align memory and display write cycles; therefore,
it is important to have a stable timing relationship between the
HSYNC output (HSOUT) and data clock (DATACK).
RGBIN
P0
P1
P2
P3
P4
P5
P6
Coast can be provided by the graphics controller, or it can be
internally generated by the AD9887A sync processing engine.
P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
D1
D2
D3
D4
D5
D6
02838-020
DOUTA
HSOUT
Figure 18. Single-Channel Mode (Analog Interface)
Rev. B | Page 23 of 52
AD9887A
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
DOUTA
D2
D4
02838-021
D0
HSOUT
Figure 19. Single-Channel Mode, Alternate Pixel Sampling (Even Pixels, Analog Interface)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
D1
D3
D5
D7
02838-022
DOUTA
HSOUT
Figure 20. Single-Channel Mode, Alternate Pixel Sampling (Odd Pixels, Analog Interface)
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
D0
DOUTB
D2
D1
D4
D3
D5
HSOUT
Figure 21. Dual-Channel Mode, Interleaved Outputs (Analog Interface), Outphase = 0
Rev. B | Page 24 of 52
02838-023
DOUTA
AD9887A
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
8-PIPE DELAY
ADCCK
DATACK
D0
D2
D4
DOUTB
D1
D3
D5
02838-024
DOUTA
HSOUT
Figure 22. Dual-Channel Mode, Parallel Outputs (Analog Interface), Outphase = 0
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
D4
D0
DOUTB
D2
D6
02838-025
DOUTA
HSOUT
Figure 23. Dual-Channel Mode, Interleaved Outputs, Alternate Pixel Sampling (Even Pixels, Analog Interface), Outphase = 0
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
8-PIPE DELAY
ADCCK
DATACK
D1
DOUTB
D5
D3
D7
HSOUT
Figure 24. Dual-Channel Mode, Interleaved Outputs, Alternate Pixel Sampling (Odd Pixels, Analog Interface), Outphase = 0
Rev. B | Page 25 of 52
02838-026
DOUTA
AD9887A
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DOUTA
D0
D4
DOUTB
D2
D6
02838-027
DATACK
HSOUT
Figure 25. Dual-Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Even Pixels, Analog Interface), Outphase = 0
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
8.5-PIPE DELAY
ADCCK
DOUTA
D1
D5
DOUTB
D3
D7
02838-028
DATACK
HSOUT
Figure 26. Dual-Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Odd Pixels, Analog Interface), Outphase = 0
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
7-PIPE DELAY
ADCCK
DATACK
Y0
Y1
Y2
Y3
Y4
Y5
ROUTA
U0
V0
U2
V2
U4
V4
02838-029
GOUTA
HSOUT
Figure 27. 4:2:2 Output Mode
Rev. B | Page 26 of 52
AD9887A
THEORY OF OPERATION—INTERFACE DETECTION
ACTIVE INTERFACE DETECTION AND SELECTION
HOT-PLUG DETECT
For interface detection in the AD9887A, the system should
determine the correct interface and set the chip appropriately
through the serial bus. An external circuit should be used to
determine if the digital interface is active. A typical schematic
for this detection function is shown in Figure 28.
In some HDCP-enabled applications it may be desirable to be
able to switch between the analog and DVI interfaces without
having an DVI plug/unplug event. In these applications, the circuit
in Figure 29 should be used for the hot-plug detect connection.
The FET switch should be controlled by the system-level software
to force an HPD event whenever the selected interface is switched
from the analog input to the DVI input.
3.3V
11kΩ
10kΩ
1
CLK+
CLK–
9
HIGH SPEED
COMPARATOR
+
10
8
LT1715
2
6
–
0.1µF
5
10kΩ
CLK
ACTIVE
1.0µF
10kΩ
10kΩ
1 = DVI CLOCK ACTIVE
0 = DVI CLOCK NOT ACTIVE
Figure 28. External Digital Interface Clock Detect Circuit
02838-043
0.1µF
+5V
HPD
14
15
1kΩ
HPD CONTROL BIT
02838-046
It is recommended that the system implement the interface
selection criteria, as described in Table 8. Because the digital
interface clock detect bit (0x11[4]) has been unreliable in some
applications, it is recommended that the active interface override
bit (0x12[7]) be set to 1. This allows the system to select the
interface through the serial bus register active interface select
(AIS) bit (0x12[6]). This selection should be based on the analog
interface detect obtained by OR’ing Bit 7, Bit 6, and Bit 5 of
Register 0x11 and on the digital interface detect obtained through
the external circuitry shown in Figure 28. When both interfaces
are active, priority must be determined by the system and the
appropriate interface must be selected via the AIS bit.
Figure 29. Manual Hot-Plug Detect
POWER MANAGEMENT
The AD9887A is a dual-interface device with shared outputs.
Because only one interface can be used at a time, the unused
interface should be powered down. When the analog interface is
being used, most of the digital interface circuitry can be powered
down and vice versa. This helps to minimize the total power
dissipation of the AD9887A. In addition, if neither interface has
activity on it, both interfaces should be powered down.
The correct power-down state is set by selecting an interface to
be active through the serial bus when either or both interfaces
are active, and by setting the power-down register bit (0x12[0])
to 0 when neither interface has activity on it. In a given power
mode, not all circuitry in the inactive interface is powered down
completely. When the digital interface is active, Hsync detect
circuitry is not powered down. SOG, outputs, and the band gap
reference are powered up if either interface is active. The serial
bus stays active even if the entire chip is powered down.
Table 8. Interface Selection and Power-Down Controls
PowerDown
1
1
0
Active Interface
Override
(0x12[7])
1
1
X
Analog Interface
Detect (0x11[7],
0x11[6], or 0x11[5])
X
X
0
Digital Interface
Detect (from
External Circuit)
X
X
0
AIS
0
1
X
Active
Interface
Analog
Digital
None
1
1
0
1
1
Digital
1
1
1
0
0
Analog
1
1
1
1
0
Analog
1
1
1
1
1
Digital
Rev. B | Page 27 of 52
Description
Force the analog interface active.
Force the digital interface active.
Neither interface is detected. Both
interfaces are powered down and
the SCDT pin is set to Logic 0.
The digital interface is detected.
Power down the analog interface.
The analog interface is detected.
Power down the digital interface.
Both interfaces are detected. The
analog interface has priority.
Both interfaces are detected. The
digital interface has priority.
AD9887A
After the next clock cycle, the first bit is shifted to RED A<6> and
the next bit appears at RED A<7>. After 48 clock cycles, the first
bit is shifted to the BLUE B<0> output and the 48th bit appears
at the RED A<7> output. If SCANCLK continues after 48 cycles,
the data continues to be shifted from RED A<7> to BLUE B<0>
and comes out of the SCANOUT pin as serial data upon the falling
edge of SCANCLK. This is illustrated in Figure 30. A setup time (tSU)
of 3 ns should be more than adequate; no hold time (tHOLD) is
required (0 ns). This is illustrated in Figure 31.
SCAN FUNCTION
The scan function is intended as a pseudo JTAG function for the
manufacturing test of the board. The ordinary operation of the
AD9887A is disabled during scanning. To enable the scan function,
set Register 0x14, Bit 2, to 1. To scan data to all 48 digital outputs,
apply 48 serial bits of data and 48 clock cycles (typically 5 MHz,
maximum of 20 MHz) to the SCANIN and SCANCLK pins,
respectively. The data is shifted in upon the rising edge of SCANCLK.
The first serial bit shifted in appears at the RED A<7> output after
one clock cycle.
SCANCLK
RED A<7>
BLUE B<0>
SCANOUT
BIT 2
BIT 3
BIT 47
BIT 48
X
BIT 1
BIT 2
BIT 3
BIT 46
BIT 47
BIT 48
X
X
X
X
X
X
BIT 1
BIT 2
X
X
X
X
X
BIT 1
BIT 2
Figure 30. Scan Timing
SCANCLK
SCANIN
tSU = 3ns
tHOLD = 0ns
Figure 31. Scan Set-up and Hold Times
Rev. B | Page 28 of 52
02838-012
BIT 1
02838-013
SCANIN
AD9887A
THEORY OF OPERATION—DIGITAL INTERFACE
CAPTURING ENCODED DATA
HDCP
The first step in recovering encoded data is to capture the raw data.
To accomplish this, the AD9887A uses a high speed, phase-locked
loop (PLL) to generate clocks capable of oversampling the data
at the correct frequencies. The data capture circuitry continuously
monitors the incoming data during horizontal and vertical
blanking periods (when DE is low) and independently selects
the best sampling phase for each data channel. The phase information is stored and used until the next blanking period (one
video line).
The AD9887A contains circuitry necessary for decrypting
a high-bandwidth digital content protection (HDCP) encoded
DVI video stream. A typical HDCP implementation is shown in
Figure 32. Several features of the AD9887A make decryption
possible and ease the implementation of HDCP.
DATA FRAMES
The digital interface data is captured in groups, called data
frames, of 10 bits each. During the active data period, each
frame is made up of nine encoded video data bits and one dcbalancing bit. The data capture block receives this data serially,
but outputs each frame in parallel, 10-bit words.
SPECIAL CHARACTERS
During periods of horizontal or vertical blanking (when DE is
low), the digital transmitter transmits special characters that are
used to set the video frame boundaries and the phase recovery
loop for each channel. There are four special characters that can
be received. They are used to identify the top, bottom, left side,
and right side of each video frame. The data receiver can differentiate these special characters from active data, because the
special characters have a different number of transitions per
data frame.
CHANNEL RESYNCHRONIZATION
The purpose of the channel resynchronization block is to
resynchronize the three data channels to a single internal data
clock. Even if all three data channels are on different phases of
the PLL clock (0°, 120°, and 240°), this block can resynchronize
the channels from a worst-case skew of one full input period
(8.93 ns at 170 MHz).
DATA DECODER
The data decoder receives frames of data and sync signals from
the data capture block in 10-bit, parallel words and decodes
them into groups of eight RGB/YUV bits, two control bits, and
a data enable (DE) bit.
The basic components of HDCP are included in the AD9887A.
A slave serial bus connects to the DDC clock and the DDC data
pins on the DVI connector to allow the HDCP-enabled DVI
transmitter to coordinate the HDCP algorithm with the
AD9887A. A second serial port (MDA/MCL) allows the
AD9887A to read the HDCP keys and key selection vector
(KSV) stored in an external serial EEPROM. When transmitting
encrypted video, the DVI transmitter enables HDCP through
the DDC port.
The AD9887A then decodes the DVI stream using information
provided by the transmitter, HDCP keys, and KSV. The AD9887A
allows the MDA and MCL pins to be three-state, using the
MDA/MCL three-state bit (Register 0x1B, Bit 7) in the
configuration registers. The three-state feature allows the EEPROM
to be programmed in-circuit. The MDA/MCL port must be
three-state before attempting to program the EEPROM using an
external master. The keys are stored in an I2C®-compatible 3.3 V
serial EEPROM of at least 512 bytes. The EEPROM should have
a device address of 0xA0.
Proprietary software licensed from Analog Devices, Inc. encrypts
the keys and creates properly formatted EEPROM images for
use in a production environment. Encrypting the keys helps
maintain the confidentiality of the HDCP keys, as required by
the HDCP v1.0 specification. The AD9887A includes hardware
for decrypting the keys in the external EEPROM.
ADI provides a royalty-free license for the proprietary software
needed by customers to encrypt the keys between the AD9887A
and the EEPROM only after customers provide evidence of a
completed HDCP Adopter’s License Agreement and sign the Analog
Devices Software License Agreement. The Adopter’s License
Agreement is maintained by Digital Content Protection, LLC
and can be downloaded from www.digital-cp.com. To obtain the
Analog Devices Software License Agreement, contact the Display
Electronics Product Line directly by sending an email to
[email protected].
Rev. B | Page 29 of 52
AD9887A
3.3V
DVI
CONNECTOR
DDC CLOCK
5kΩ
D
5kΩ
3.3V
PULL-UP
RESISTORS
150Ω
S
2kΩ
DDCSCL
SERIES
RESISTOR
DDC DATA
D
DDCSDA
S
MCL
AD9887A
3.3V
MDA
Figure 32. HDCP Implementation Using the AD9887A
Rev. B | Page 30 of 52
PULL-UP
RESISTORS
SCL
EEPROM
10kΩ
PULL-UP
RESISTOR
DVI-VCC
2kΩ
SDA
02838-045
3.3V
AD9887A
GENERAL TIMING DIAGRAMS—DIGITAL INTERFACE
80%
80%
TIMING MODE DIAGRAMS—DIGITAL INTERFACE
INTERNAL
ODCLK
tST
DLHT
DLHT
DATACK
02838-031
20%
20%
DE
Figure 33. Digital Output Rise and Fall Times
FIRST
PIXEL
SECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
TCIP, RCIP
02838-035
QE[23:0]
QO[23:0]
TCIH, RCIH
TCIL, RCIL
02838-032
Figure 37. One Pixel per Clock (DATACK Inverted)
INTERNAL
ODCLK
tST
Figure 34. Clock Cycle/High/Low Times
DATACK
DE
Rx0
FIRST
PIXEL
SECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
Rx1
02838-036
QE[23:0]
VDIFF = 0V
QO[23:0]
VDIFF = 0V
Figure 38. One Pixel per Clock (DATACK Not Inverted)
02838-033
tCCS
Rx2
Figure 35. Channel-to-Channel Skew Timing
INTERNAL
ODCLK
DATACK
(INTERNAL)
tST
DATACK
02838-034
tSKEW
QE[23:0]
FIRST PIXEL
THIRD PIXEL
QO[23:0]
SECOND PIXEL
FOURTH PIXEL
Figure 36. DVI Output Timing
Figure 39. Two Pixels per Clock
INTERNAL
ODCLK
tST
DATACK
DE
QE[23:0]
QO[23:0]
FIRST PIXEL
THIRD PIXEL
SECOND PIXEL
FOURTH PIXEL
Figure 40. Two Pixels per Clock (DATACK Inverted)
Rev. B | Page 31 of 52
02838-038
DATACK
(PIN)
02838-037
DE
DATA OUT
AD9887A
2-WIRE SERIAL REGISTER MAP
The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write
and read the control registers through the 2-line serial interface port.
Table 9. Control Register Map
Address
0x00
Read and
Write, or
Read Only
RO
Bits
7:0
0x01
R/W
7:0
01101001
PLL Divide Ratio
MSBs
0x02
R/W
7:4
1101****
0x03
R/W
7:2
1*******
PLL Divide Ratio
LSBs
Clock Generator
Controls
Default
Value
Register Name
Chip Revision
*01*****
***001**
0x04
0x05
R/W
R/W
7:3
7:0
10000***
10000000
Clock Phase Adjust
Clamp Placement
0x06
0x07
R/W
R/W
7:0
7:0
10000000
00100000
0x08
R/W
7:0
10000000
Clamp Duration
Hsync Output
Pulse Width
REDGAIN
0x09
R/W
7:0
10000000
GREENGAIN
0x0A
R/W
7:0
10000000
BLUEGAIN
0x0B
R/W
7:1
1000000*
REDOFST
0x0C
R/W
7:1
1000000*
GREENOFST
0x0D
R/W
7:1
1000000*
BLUEOFST
0x0E
R/W
7:3
1*******
Mode Control 1
*1******
**0*****
***0****
0x0F
R/W
7:0
****0***
1*******
*1******
**0*****
PLL and Clamp
Control
Description
Bit 7 through Bit 4 represent functional revisions to the analog
interface. Bit 3 through Bit 0 represent nonfunctional related
revisions. Revision 0 = 0000 0000.
This register is for Bits[11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first when
a change is needed. (This gives the PLL more time to lock.) 1
This register is for Bits[3:0] of the PLL divider. Links to the PLL divide
ratio MSBs to make a 12-bit value.1
Bit 7—Must be set to 1 for proper device operation.
Bits[6:5]—VCO Range Select. Selects VCO frequency range (see the
PLL section).
Bits[4:2]—Charge-Pump Current. Varies the current that drives the
low-pass filter (see the PLL section).
Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32)
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
Sets the number of pixel clocks that HSOUT remains active.
Controls ADC input range (contrast) of red channel. Bigger values
result in less contrast.
Controls ADC input range (contrast) of green channel. Bigger values
result in less contrast.
Controls ADC input range (contrast) of blue channel. Bigger values
result in less contrast.
Controls dc offset (brightness) of red channel. Bigger values decrease
brightness.
Controls dc offset (brightness) of green channel. Bigger values
decrease brightness.
Controls dc offset (brightness) of blue channel. Bigger values decrease
brightness.
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. Logic 0 = single-channel mode; Logic 1 = dual-channel mode.
Bit 6—Output Mode. Determines interleaved or parallel output mode.
Logic 0 = interleaved mode; Logic 1 = parallel mode.
Bit 5—Output Port Phase (OUTPHASE). Determines which port outputs
the first data byte after Hsync. Logic 0 = B port; Logic 1 = A port.
Bit 4—HSYNC Output Polarity. Logic 0 = logic high sync; Logic 1 =
logic low sync.
Bit 3—VSYNC Output Invert. Logic 0 = invert; Logic 1 = no invert.
Bit 7—HSYNC Input Polarity. Indicates the polarity of incoming HSYNC
signal to the PLL. Logic 0 = active low; Logic 1 = active high.
Bit 6—COAST Input Polarity. Changes polarity of external coast signal.
Logic 0 = active low; Logic 1 = active high.
Bit 5—Clamp Input Signal Source (EXTCLMP). Chooses between HSYNC
for CLAMP signal and another external signal to be used for clamping.
Logic 0 = HSYNC; Logic 1 = externally provided clamp signal.
Rev. B | Page 32 of 52
AD9887A
Address
Read and
Write, or
Read Only
Bits
Default
Value
***1****
Register Name
****0***
*****0**
******0*
*******0
0x10
R/W
7:2
0*******
Mode Control 2
*0******
**11****
****0***
*****1**
0x11
RO
7:1
1*******
Sync Detection
and Active
Interface Control
*1******
**1*****
***1****
****1***
*****1**
******1*
0x12
R/W
7:0
0*******
*0******
**0*****
***0****
****0***
Active Interface
Description
Bit 4—Clamp Input Signal Polarity (name also same as Bit 6). Valid only
with external CLAMP signal. Logic 0 = active low; Logic 1 = active high.
Bit 3—External Clock Select (EXTCLK). Shuts down the PLL and allows
the use of an external clock to drive the part. Logic 0 = uses internal
PLL; Logic 1 = bypasses the internal PLL.
Bit 2—Red Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 120 and 118)
Bit 1—Green Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 111 and 109)
Bit 0—Blue Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 101 and 99)
Bit 7—CKINV: Data Output Clock Invert. Logic 0 = not inverted;
Logic 1 = inverted (digital interface only).
Bit 6—Pixel Select. Selects either one or two pixels per clock mode.
Logic 0 = one pixel/clock; Logic 1 = two pixels/clock (digital interface
only).
Bit 5, 4—Output Drive. Selects among high, medium, and low output
drive strength. Logic 11 or Logic 10 = high, Logic 01 = medium, and
Logic 00 = low.
Bit 3—PDO: High Impedance Outputs. Logic 0 = normal; Logic 1 =
high impedance.
Bit 2—Sync Detect Polarity. This bit sets the polarity for the SCDT pin.
Logic 1 = active high; Logic 0 = active low.
Bit 7—Analog Interface HSYNC Detect. It is set to Logic 1 if Hsync is
present on the analog interface; otherwise, it is set to Logic 0.
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1 if
sync is present on the green video input; otherwise, it is set to 0.
Bit 5—Analog Interface VSYNC Detect. It is set to Logic 1 if Vsync is
present on the analog interface; otherwise, it is set to Logic 0.
Bit 4—Digital Interface Clock Detect. It is set to Logic 1 if the clock is
present on the digital interface; otherwise, it is set to Logic 0.
Bit 3—Active Interface (AI). This bit indicates which interface is active.
Logic 0 = analog interface; Logic 1 = digital interface.
Bit 2—Active Hsync (AHS). This bit indicates which analog Hsync is being
used. Logic 0 = HSYNC input pin; Logic 1 = Hsync from sync-on-green.
Bit 1—Active Vsync (AVS). This bit indicates which analog Vsync is being
used. Logic 0 = VSYNC input pin; Logic 1 = Vsync from sync-on-green.
Bit 7—Active Interface Override (AIO). If set to Logic 1, the user can
select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 0x11.
Bit 6—Active Interface Select (AIS). Logic 0 selects the analog interface
as active. Logic 1 selects the digital interface as active. Note that the
indicated interface is active only if Bit 7 is set to Logic 1 or if both
interfaces are active (Bit 6 or Bit 7 and Bit 4 = Logic 1 in Register 0x11).
Bit 5—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 4. If set to Logic 0, the active interface is
selected via Bit 2 in Register 0x11.
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects sync-on-green as the active sync. Note that the indicated
Hsync is used only if Bit 5 is set to Logic 1 or if both syncs are active
(Bit 6 and Bit 7 = Logic 1 in Register 0x11).
Bit 3—Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 2. If set to Logic 0, the active interface is
selected via Bit 1 in Register 0x11.
Rev. B | Page 33 of 52
AD9887A
Address
Read and
Write, or
Read Only
Bits
Default
Value
*****0**
Register Name
0x1D
RO
7:0
*_*****
Description
Bit 2—Output Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separator output as the active Vsync. Note
that the indicated Vsync is used only if Bit 3 is set to Logic 1.
Bit 1—COAST Select. Logic 0 selects the COAST input pin used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 0—PWRDN. Full Chip Power-Down, active low. Logic 0 = full chip
power-down; Logic 1 = normal.
Sync Separator Threshold. Sets the number of clock cycles that the sync
separator counts before toggling high or low. This should be set to a
number greater than the maximum Hsync or equalization pulse width.
Bit 4—Must be set to 1 for proper operation.
Bit 3—Must be set to 0 for proper operation.
Bit 2—Scan Enable. Logic 0 = scan function disabled; Logic 1 = scan
function enabled.
Bit 1—COAST Input Polarity Override. Logic 0 = polarity determined by
chip; Logic 1 = polarity determined by user via Bit 6 in Register 0x0F.
Bit 0—HSYNC Input Polarity Override. Logic 0 = polarity determined
by chip; Logic 1 = polarity determined by user via Bit 7 in Register 0x0F.
Bit 7—Hsync Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
Bit 6—Vsync Output Polarity Status. Logic 0 = active high; Logic 1 =
active low.
Bit 5—Coast Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
Bits[7:3]—Sync-on-Green Slicer Threshold.
Bit 2—Must be set to 0 for proper operation.
Sets the number of Hsyncs prior to Vsync before which coast goes
active.
Sets the number of Hsyncs following Vsync before coast goes active.
Must be set to default for proper operation.
Must be set to 01000001 for proper operation.
Set to 0x00 for autogain mode and 0x10 for manual-gain mode
Bits [7:3]—Set to 00000*** for autogain mode and 00101*** for
manual-gain mode
Bit 2—CbCr Output Order.
Bit 1—Must be set to 0 for standard input sampling.
Bit 0—Output Format Mode Select. Logic 1 = 4:4:4 mode; Logic 0 =
4:2:2 mode.
HDCP Keys Detected. Logic 0 = not detected; Logic 1 = detected.
0x1E
R/W
7:0
11111111
Must set to 0xFF for proper operation.
0x1F
R/W
7:0
10000100
Must set to 0x84 for proper operation.
0x20
R/W
7:0
0*******
Bit 7—HDCP A0 Serial Address Bit. For Logic 0, Address = 0x74. For
Logic 1, Address = 0x76.
Bit 6—MDA Pin Select. For Logic 0, Pin 49 = Ctrl3 signal. For Logic 1,
Pin 49 = MDA for HDCP.
Bit 5—Analog Input Bandwidth Control. Logic 0 = high.
******0*
*******1
0x13
R/W
7:0
00100000
Sync Separator
Threshold
0x14
R/W
7:0
***1****
****0***
*****0**
Control Bits
******0*
*******0
0x15
RO
7:5
0*******
Polarity Status
*0******
**0*****
0x16
R/W
7:2
Control Bits
7:0
10111***
*****1**
00000000
0x17
R/W
0x18
0x19
0x1A
0x1B
0x1C
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
7:0
00000000
00000000
11111111
00000000
00000***
Postcoast
Test Register
Test
*****1**
******1*
*******1
Precoast
4:2:2 Control
*0******
**0*****
***0****
Bit 4—MDA/MCL Three-State. Logic 0 = three-state; Logic 1 = normal
operation.
Bit 3—External Oscillator. Logic 1 = internal; Logic 0 = use external
oscillator on A0.
Normal Operation.
****1***
*****0**
0x21
R/W
7:0
00000000
TDMS Gain Control
Set to 0x00 for autogain mode and 0x64 for manual-gain mode.
Rev. B | Page 34 of 52
AD9887A
Address
0x22
Read and
Write, or
Read Only
R/W
Bits
7:0
Default
Value
00000000
0x23
R/W
7:0
00000000
Must be set to 0x2A for proper operation.
0x24
R/W
7:0
00000000
Must be set to default.
0x25
R/W
7:0
11110000
Must be set to default.
0x26
R/W
7:0
11111111
Must be set to default.
00001111
Must be set to default
0x27
1
Register Name
Description
Must be set to default.
The AD9887A only updates the PLL divide ratio when the LSBs are written to Register 0x02.
0x02 7:4
2-WIRE SERIAL CONTROL REGISTER DETAILS
PLL Divide Ratio LSBs
The 4 LSBs of the 12-bit PLL divide ratio PLLDIV. The
operational divide ratio is PLLDIV + 1.
Chip Identification
0x00 7:0 Chip Revision
Bit 7 through Bit 4 represent functional revisions to the
analog interface. Changes in these bits generally indicate
that software and/or hardware changes are required for
the chip to work properly. Bit 3 through Bit 0 represent
nonfunctional related revisions and are reset to 0000
when the MSBs are changed. Changes in these bits are
considered transparent to the user.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9887A updates the full divide ratio only when
the user writes to this register.
Clock Generator Controls
0x03 7
Test
Must be set to 1 for proper device operation.
PLL Divider Control
0x01 7:0 PLL Divide Ratio MSBs
0x03 6:5
VCO Range Select
The 8 MSBs of the 12-bit PLL divide ratio PLLDIV. (The
operational divide ratio is PLLDIV + 1.)
Two bits that establish the operating range of the clock
generator.
The PLL derives a pixel clock from the incoming Hsync
signal. The pixel clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead)
per line. This is typically 20% to 30% more than the
number of active pixels in the display.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The 12-bit value of the PLL divider supports divide ratios
from 221 to 4095. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency. VESA has established
standard timing specifications that help determine the value
for PLLDIV as a function of horizontal and vertical display
resolution and frame rate (Table 7). However, many computer systems do not conform precisely to the recommendations, and these numbers should be used only as a
guide. The display system manufacturer should provide
automatic or manual means for optimizing PLLDIV. An
incorrectly set PLLDIV usually produces one or more
vertical noise bars on the display. The greater the error, the
greater the number of bars produced. The power-up default
of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx).
The PLL provides the best jitter performance at high
frequencies. To output low pixel rates while minimizing
jitter, the PLL operates at a higher frequency and divides
down the clock rate afterwards. Table 10 shows the pixel
rates for each VCO range setting. The PLL output divisor
is automatically selected with the VCO range setting.
Table 10. VCO Ranges
VCORNGE
00
01
10
11
The AD9887A updates the full divide ratio only when
the LSBs are changed. Writing to this register by itself
does not trigger an update.
Rev. B | Page 35 of 52
Pixel Rate Range
12 to 37
37 to 74
74 to 140
140 to 170
The power-up default value is 01.
AD9887A
0x03 4–2
For the best results, the clamp duration should be set to
include the majority of the black reference signal time
that follows the Hsync signal trailing edge. Insufficient
clamping time can produce brightness changes at the top
of the screen and can cause slow recovery from large
changes in the average picture level (APL) or brightness.
CURRENT Charge-Pump Current
Three bits that establish the current driving the loop
filter in the clock generator.
Table 11. Charge-Pump Currents
CURRENT
000
001
010
011
100
101
110
111
Current (μA)
50
100
150
250
350
500
750
1500
When EXTCLMP = 1, this register is ignored.
Hsync Pulse Width
0x07 7:0 Hsync Output Pulse Width
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9887A counts the number of pixel clock cycles
set in this register. This triggers the trailing edge of the
Hsync output, which is also phase adjusted.
See Table 7 for the recommended CURRENT settings.
The power-up default value is CURRENT = 001.
0x04 7:3
Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps
across one pixel period. Each step represents an 11.2°
shift in sampling phase.
Input Gain
0x08 7:0 Red Channel Gain Adjust (REDGAIN)
An 8-bit word that sets the gain of the red channel.
The AD9887A can accommodate input signals with a
full-scale range between 0.5 V and 1.5 V p-p. Setting
REDGAIN to 255 corresponds to an input range of
1.0 V. A REDGAIN of 0 establishes an input range of
0.5 V. Note that increasing REDGAIN results in the
picture having less contrast because the input signal uses
fewer of the available converter codes (see Figure 6).
The power-up default value is 16.
Clamp Timing
0x05 7:0 Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated
internally at a position established by the clamp
placement for a duration set by the clamp duration.
Clamping is started [clamp placement] pixel periods
after the trailing edge of Hsync. The clamp placement
can be programmed to any value between 1 and 255.
A value of 0 is not supported.
The clamp should be placed during a time when the
input signal presents a stable black-level reference,
usually during a period between Hsync and the image
called the back porch. When EXTCLMP = 1, this
register is ignored.
0x06 7:0
0x09 7:0
Green Channel Gain Adjust (GREENGAIN)
An 8-bit word that sets the gain of the green channel. See
REDGAIN (0x08).
0x0A 7:0
Blue Channel Gain Adjust (BLUEGAIN)
An 8-bit word that sets the gain of the blue channel. See
REDGAIN (0x08).
Input Offset
0x0B 7:1 Red Channel Offset Adjust (REDOFST)
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated
internally at a position established by the clamp
placement for a duration set by the clamp duration.
Clamping is started [clamp placement] pixel periods
after the trailing edge of Hsync and continues for [clamp
duration] pixel periods. The clamp duration can be
programmed to a value between 1 and 255. A value of 0
is not supported.
Rev. B | Page 36 of 52
A 7-bit offset binary word that sets the dc offset of the
red channel (REDOFST). An offset adjustment of 1 LSB
equals approximately 1 LSB change in the ADC offset.
Therefore, the absolute magnitude of the offset adjustment
scales as the gain of the channel changes. A nominal setting
of 63 results in the channel nominally clamping to Code 00
during the back porch clamping interval. An offset setting
of 127 results in the channel clamping to Code 63 of the
ADC. An offset setting of 0 clamps to Code −63 (off the
bottom of the range). Increasing the value of red offset
decreases the brightness of the channel.
AD9887A
0x0C 7:1
Green Channel Offset Adjust (GREENOFST)
0x0E 5
A 7-bit offset binary word that sets the dc offset of the
green channel. See REDOFST (0B).
0x0D 7:1
Blue Channel Offset Adjust (BLUEOFST)
One bit that determines whether even or odd pixels go to
Port A.
Table 14. Output Port Phase (OUTPHASE) Settings
A 7-bit offset binary word that sets the dc offset of the
blue channel. See REDOFST (0B).
Mode Control 1
0x0E 7
Channel Mode
OUTPHASE
1
0
Table 12. Channel Mode Settings
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
Function
All data goes to Port A
Alternate pixels go to Port A and Port B
When DEMUX = 0, this bit is ignored because data
always comes out of only Port A.
When DEMUX = 0, Port B outputs are in a high impedance state. The maximum data rate for single-port mode
is 100 MHz. The timing diagrams show the effects of
this option.
0x0E 4
Output Mode
Table 15. HSYNC Output Polarity Settings
A bit that determines whether all pixels are
simultaneously presented to Port A and Port B upon
every second DATACK rising edge or alternately
presented to Port A and Port B upon successive
DATACK rising edges.
Setting
0
1
HSYNC
Logic 1 (negative polarity)
Logic 0 (positive polarity)
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
Table 13. Output Mode Settings
PARALLEL
0
1
HSYNC Output Polarity
One bit that determines the polarity of the HSYNC
output and the SOG output. Table 15 shows the effect of
this option. SYNC indicates the logic state of the sync
pulse.
The power-up default value is 1.
0x0E 6
First Pixel After Hsync
Port B
Port A
In normal operation (OUTPHASE = 0) when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented to Port A,
every subsequent odd sample goes to Port A, and all
even samples go to Port B.
A bit that determines whether all pixels are presented to
a single port (Port A), or if alternating pixels are demultiplexed to Port A and Port B.
DEMUX
0
1
Output Port Phase
Function
Data is interleaved
Data is simultaneous upon every other data clock
When in single-port mode (DEMUX = 0), this bit is
ignored. The timing diagrams (Figure 18 through Figure 27
and Figure 37 through Figure 39) show the effects of this
option.
0x0E 3
VSYNC Output Invert
One bit that inverts the polarity of the VSYNC output.
Table 16 shows the effect of this option.
Table 16. VSYNC Output Polarity Settings
Setting
0
1
The power-up default value is PARALLEL = 1.
VSYNC Output
Invert
No invert
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
Rev. B | Page 37 of 52
AD9887A
0x0F 7
Logic 1 enables the external CLAMP input pin. The
three channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
HSYNC Input Polarity
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL HSYNC input.
Table 17. HSYNC Input Polarity (HSPOL) Settings
HSPOL
0
1
The power-up default value is EXTCLMP = 0.
Function
Active low
Active high
0x0F 4
Active low is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which
is the falling edge. The rising edge has no effect.
Active high is inverted from the traditional Hsync, with
a positive-going pulse; therefore, timing is based on the
leading edge of Hsync, which is now the rising edge.
A bit that determines the polarity of the externally
provided CLAMP signal.
Table 20. CLAMP Input Signal Polarity (EXTCLMP) Settings
EXTCLMP
0
1
0x0F 6
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
The power-up default value is CLAMPOL = 1.
Function
Active low
Active high
Table 21. External Clock Select (EXTCLK) Settings
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL divide ratio (PLLDIV) is ignored and the
clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
0x0F 2
This function must be used with the COAST polarity
override bit (Register 0x14, Bit 1).
Red Clamp Select
A bit that determines whether the red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr (or
YUV), the Y channel is referenced to ground, but the
CbCr channels are referenced to midscale. Clamping to
midscale actually clamps to Pin 118, RCLAMPV.
The power-up default value is CSTPOL = 1.
0x0F 5
Function
Internally generated clock
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
Active low means that the clock generator ignores HSYNC
inputs when coast is low and continues operating at the
same nominal frequency until coast goes high.
Active high means that the clock generator ignores HSYNC
inputs when coast is high and continues operating at the
same nominal frequency until coast goes low.
External Clock Select
A bit that determines the source of the pixel clock.
EXTCLK
0
1
Table 18. COAST Input Polarity (CSTPOL) Settings
CSTPOL
0
1
Logic 1 means that the circuit clamps when CLAMP is low
and passes the signal to the ADC when CLAMP is high.
0x0F 3
COAST Input Polarity
Function
Active low
Active high
Logic 0 means that the circuit clamps when CLAMP is high
and passes the signal to the ADC when CLAMP is low.
The device operates if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which might
generate clamping errors.
The power-up default value is HSPOL = 1.
CLAMP Input Signal Polarity
Clamp Input Signal Source
A bit that determines the source of clamp timing.
Table 19. Clamp Input Signal Source (EXTCLMP) Settings
Table 22. Red Clamp Select Settings
EXTCLMP
0
1
Clamp
0
1
Function
Internally generated clamp
Externally provided clamp signal
Logic 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and
duration is counted from the trailing edge of Hsync.
Rev. B | Page 38 of 52
Function
Clamp to ground
Clamp to midscale (Pin 118)
The default setting for this register is 0.
AD9887A
0x0F 1
Green Clamp Select
0x10 5, 4
A bit that determines whether the green channel is
clamped to ground or to midscale.
These two bits select the drive strength for the high
speed digital outputs (all data output and clock output
pins). Higher drive strength results in faster rise/fall
times and enables easier capture of data in general.
Lower drive strength results in slower rise/fall times and
reduces EMI and digitally generated power supply noise.
The exact timing specifications for each of these modes
are specified in Table 7.
Table 23. Green Clamp Select Settings
Clamp
0
1
Function
Clamp to ground
Clamp to midscale (Pin 109)
The default setting for this register is 0.
0x0F 0
Blue Clamp Select
Table 27. Output Drive Strength Settings
Bit 5
1
0
0
A bit that determines whether the blue channel is
clamped to ground or to midscale.
Table 24. Blue Clamp Select Settings
Clamp
0
1
Function
Clamp to ground
Clamp to midscale (Pin 99)
0x10 3
A control bit for the inversion of the output data clocks
(Pin 134 and Pin 135). This function only works for the
digital interface. When not inverted, data is output upon
the trailing edge of the data clock. See Figure 37 through
Figure 40 for how this affects timing.
Power-Down Outputs (PDO)
Table 28. Power-Down Output (PDO) Settings
PDO
0
1
Function
Normal operation
Three-state
The default for this register is 0. This option works on
both the analog and digital interfaces.
Table 25. Data Output Clock Invert (CKINV) Settings
0x10 2
Function
Not inverted
Inverted
Sync Detect Polarity
This pin controls the polarity of the sync detect output
pin (Pin 136).
The default for this register is 0.
Table 29. Sync Detect Polarity Settings
Pixel Select
This bit selects either one or two pixels per clock mode
for the digital interface. It determines whether the
output is from a single port (even port only) at the full
data rate, or from two ports (both even and odd ports) at
half the full data rate per port. Logic 0 selects one pixel
per clock (even port only). Logic 1 selects two pixels per
clock (both ports). See the Digital Interface Timing
Diagrams (Figure 37 through Figure 40) for visual
representations of this function. Note that this function
operates exactly like the demux function on the analog
interface.
Polarity
0
1
Table 26. Pixel Select Settings
Pixel Select
0
1
Result
High drive strength
Medium drive strength
Low drive strength
This bit can put the outputs into a high impedance mode.
This applies to all outputs except SOGOUT and REFOUT.
Mode Control 2
0x10 7
Data Output Clock Invert (CKINV)
0x10 6
Bit 4
X
1
0
The default for this register is 11. This option works on
both the analog and digital interfaces.
The default setting for this register is 0.
CKINV
0
1
Output Drive
Function
One pixel per clock
Two pixels per clock
The default for this register is 0.
Rev. B | Page 39 of 52
Function
Activity = Logic 1 output
Activity = Logic 0 output
The default for this register is 0. This option works on
both the analog and digital interfaces.
AD9887A
SYNC Detection/Active Interface Control
0x11 7
Analog Interface HSYNC Detect
0x11 3
This bit indicates which interface should be active,
analog or digital. It checks for activity on the analog and
digital interfaces, then determines which should be
active according to the conditions outlined in Table 34.
Specifically, analog interface detection is determined by
OR’ing Bit 7, Bit 6, and Bit 5 from this register.
This bit is used to indicate when activity is detected on
the HSYNC input pin (Pin 82). If HSYNC is held high or
low, activity is not detected.
Table 30. Analog Interface HSYNC Detection Results
Detect
0
1
Function
No activity detected
Activity detected
Digital interface detection is determined by Bit 4 in this
register. If both interfaces are detected, the user can determine which has priority via Bit 6 in Register 0x12. The
user can override this function via Bit 7 in Register 0x12.
If the override bit is set to Logic 1, this bit is forced to the
set state of Bit 6 in Register 0x12.
Figure 43 shows where this function is implemented.
0x11 6
Analog Interface Sync-on-Green Detect
This bit is used to indicate when sync activity is detected
on the sync-on-green input pin (Pin 108).
Table 31. Analog Interface Sync-on-Green Detection Results
Detect
0
1
Function
No activity detected
Activity detected
Figure 43 shows where this function is implemented.
Warning: Even if no sync is present on the green video
input, normal video might trigger activity.
0x11 5
Analog Interface VSYNC Detect
Table 34. Active Interface Results
Bits 7, 6, or 5
(Analog
Detection)
0
Bit 4
(Digital
Detection)
0
Override1
0
0
1
1
X
1
0
1
X
0
0
0
1
The override bit is Bit 7 in Register 0x12.
AI = 0 means analog interface.
3
AI = 1 means digital interface.
2
0x11 2
Function
No activity detected
Activity detected
Figure 43 shows where this function is implemented.
Digital Interface Clock Detect
This indicates when activity is detected on the digital
interface clock input. Because this register is unreliable
in certain applications, an external DVI clock detect
shown in Figure 28 is recommended.
Table 33. Digital Interface Clock Detection Results
Detect
0
1
Function
No activity detected
Activity detected
Figure 43 shows where this function is implemented.
Active Hsync (AHS)
This bit determines which Hsync to use for the analog
interface, the HSYNC input or the sync-on-green. It uses
Bit 7 and Bit 6 in this register for inputs when determining
which should be active. Similar to the previous bit, if both
Hsync and sync-on-green are detected, the user can determine which has priority via Bit 4 in Register 0x12. The
user can override this function via Bit 5 in Register 0x12.
If the override bit is set to Logic 1, this bit is forced to the
set state of Bit 4 in Register 0x12.
Table 32. Analog Interface VSYNC Detection Results
0x11 4
AI2, 3
Soft power-down
(seek mode)
1
0
Bit 6 in Register 0x12
Bit 6 in Register 0x12
1
This bit indicates when activity is detected on the
VSYNC input pin (Pin 81). If VSYNC is held high or
low, activity is not detected.
Detect
0
1
Active Interface (AI)
Table 35. Active Hsync Results
Bit 7
(HSYNC Detect)
0
Bit 6
(SOG Detect)
0
Override1
0
0
1
1
1
0
1
0
0
0
X
X
1
1
The override bit is Bit 5 in Register 0x12.
AHS = 0 means HSYNC input.
3
AHS = 1 means SOG input.
2
Rev. B | Page 40 of 52
AHS2, 3
Bit 4 in
Register 0x12
1
0
Bit 4 in
Register 0x12
Bit 4 in
Register 0x12
AD9887A
0x11 1
0x12 4
Active VSYNC (AVS)
This bit determines which VSYNC to use for the analog
interface, the VSYNC input or the sync separator output.
If both VSYNC and composite SOG are detected, VSYNC
is selected. The user can override this function via Bit 3
in Register 0x12. If the override bit is set to Logic 1, this
bit is forced to the set state of Bit 2 in Register 0x12.
Table 36. Active VSYNC Results
Bit 5 (VSYNC Detect)
0
1
X
Override
0
0
1
1
2, 3
AVS
0
1
Bit 2 in Register 0x12
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit (Bit 5) is set.
Alternately, it is used to determine the active Hsync
when the override bit is not set, but both Hsyncs are
detected.
Table 40. Active Hsync Select Settings
Select
0
1
Result
HSYNC input
Sync-on-green input
The default for this register is 0.
0x12 3
Active Vsync Override
1
The override bit is Bit 3 in Register 0x12.
2
AVS = 0 means VSYNC input.
3
AVS = 1 means sync separator.
0x12 7
Active Interface Override (AIO)
Set this bit (Bit 3 in Register 0x11) to Logic 1 to override
the automatic interface selection. When overriding the
automatic interface selection, the active interface is set
via Bit 6 in this register.
Table 37. Active Interface Override Settings
AIO
0
1
This bit is used to override the automatic Vsync selection
(Bit 1 in Register 0x11). To initiate this, set this bit to
Logic 1. When overriding the automatic Vsync selection,
the active interface is set via Bit 2 in this register.
Result
Autodetermines the active interface
Override, Bit 6 determines the active interface
Table 41. Active VSYNC Override Settings
Override
0
1
The default for this register is 0.
0x12 2
6
Active Interface Select (AIS)
This bit is used under two conditions. It is used to select
the active interface when the override bit (Bit 7) is set.
Alternately, it is used to determine the active interface
when the override bit is not set, but both interfaces are
detected.
Table 42. Active VSYNC Select Settings
Select
0
1
The default for this register is 0.
The default for this register is 0.
Table 43. Coast Select Settings
Active HSYNC Override
This bit is used to override the automatic HSYNC selection
(Bit 2 in Register 0x11). To initiate, set this bit to Logic 1.
When overriding the automatic HSYNC selection, the
active HSYNC is set via Bit 4 in this register.
Select
0
1
Table 39. Active HSYNC Override Settings
Override
0
1
Coast Select
This bit is used to select which coast source is active, the
COAST input pin or Vsync. If Vsync is selected, users
must decide whether to use the VSYNC input pin or the
output from the sync separator (Bit 3 and Bit 2).
Result
Analog interface
Digital interface
0x12 5
Result
VSYNC input
Sync separator output
0x12 1
Table 38. Active Interface Select Settings
AIS
0
1
Active Vsync Select
This bit is used to select the active Vsync when the
override bit (Bit 3) is set.
The default for this register is 0.
12
Result
Autodetermines the active Vsync
Override, Bit 2 determines the active Vsync
Result
Autodetermines the active interface
Override, Bit 4 determines the active interface
The default for this register is 0.
Rev. B | Page 41 of 52
Result
COAST input pin
Vsync (see above text)
AD9887A
0x12 0
0x14 0
PWRDN
This bit can be used to fully power down both interfaces
of the chip. See the Power Management section for
details on which blocks are actually powered down. Note
that the chip is unable to detect incoming activity while
fully powered down.
Table 44. Power-Down Settings
Select
0
1
Result
Power down
Normal operation
This register is used to override the internal circuitry
that determines the polarity of the Hsync signal going
into the PLL.
Table 47. HSYNC Input Polarity Override Setting
Override Bit
0
1
0x15 7
This register is used to set the responsiveness of the sync
separator. It sets the number of 5 MHz clock pulses the
sync separator counts before toggling high or low. It works
like a low-pass filter to ignore Hsync pulses in order to
extract the Vsync signal. This register should be set to a
number greater than the maximum Hsync pulse width.
Table 48. Detected HSYNC Input Polarity Status
Status
0
1
Table 49. Detected Vsync Input Polarity Status
Status
0
1
Table 46. COAST Input Polarity Override Settings
Override Bit
0
1
COAST Input Polarity Status
This bit reports the status of the COAST input polarity
detection circuit. It can be used to determine the polarity
of the coast input. The location of the detection circuit is
shown in the Figure 43.
The default for scan enable is 0 (disabled).
This register is used to override the internal circuitry
that determines the polarity of the coast signal going
into the PLL.
Result
Vsync input polarity is active low.
Vsync input polarity is active high.
0x15 5
Result
Scan function disabled
Scan function enabled
COAST Input Polarity Override
VSYNC Output Polarity Status
This bit reports the status of the VSYNC output polarity
detection circuit. It can be used to determine the polarity
of the VSYNC input. The location of the detection
circuit is shown in the Figure 43.
Control Bits
0x14 2
Scan Enable
0x14 1
Result
HSYNC input polarity is negative.
HSYNC input polarity is positive.
0x15 6
The default for this register is 32.
This register is used to enable the scan function. When
this function is enabled, data can be loaded into the
AD9887A outputs serially. The scan function utilizes
three pins: SCANIN, SCANOUT, and SCANCLK. These pins
are described in the Scan Function section.
HSYNC Input Polarity Status
This bit reports the status of the HSYNC input polarity
detection circuit. It can be used to determine the polarity
of the HSYNC input. The location of the detection
circuit is shown in the Figure 43.
Digital Control
0x13 7:0 Sync Separator Threshold
Scan Enable
0
1
Result
HSYNC input polarity determined by chip
HSYNC input polarity determined by user
The default for HSYNC input polarity override is 0.
The default for this register is 1.
Table 45. Scan Enable Settings
HSYNC Input Polarity Override
Table 50. Detected COAST Input Polarity Status
Status
0
1
Result
Coast input polarity is negative.
Coast input polarity is positive.
0x16 7–3
Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
sync-on-green slicer to be adjusted. This register adjusts
the comparator threshold in 10 mV steps. A setting of 0
results in a 330 mV threshold; a setting of 31 results in a
10 mV threshold. The default setting is 23, which corresponds to a threshold value of 70 mV.
Result
Coast polarity determined by chip
Coast polarity determined by user
The default for coast polarity override is 0.
Rev. B | Page 42 of 52
AD9887A
0x17 7:0
Precoast
0x1C 0
This register allows the coast signal to be applied prior to
the Vsync signal. This is necessary in cases where preequalization pulses are present. This register defines the
number of edges that are filtered before Vsync on a
composite sync.
The default is 0.
0x18 7:0
Postcoast
This register allows the coast signal to be applied
following the Vsync signal. This is necessary when
postequalization pulses are present. This register defines
the number of edges that are filtered after Vsync on a
composite sync.
Table 52. 4:2:2 Output Mode Select
Select
1
0
Must be set to default.
0x1D 6
HDCP Keys Detected
This bit indicates the presence of HDCP keys read from
the external EEPROM.
HDCP Key Status
HDCP keys present
HDCP keys not present
Test
Must be set to 0x41 for proper operation.
0x1B 7:0
0x1E 7:0
Test
0x1C 7:3
0x1F 7:0
0x20 7
Must be set to 00000*** for autogain mode and 00101***
for manual-gain mode.
CbCr Output Order
In 4:2:2 mode, the red and blue channels can be
interchanged to help satisfy board layout or timing
requirements, but the green channel must be configured
for Y. Register 0x1C, Bit 2, controls the order that the
U/V (CbCr) data is output. If this bit is high, the red
channel data precedes the blue channel data. If this bit is
low, the blue channel data precedes the red channel data.
See the example in Table 51.
Table 51. 4:2:2 Input/Output Configuration
Channel
Red
Input
Connection
Y
Green
Blue
Y
U
Output Format
V/U if 0x1C Bit 2 = 1;
U/V if 0x1C Bit 2 = 0
Y
High impedance
HDCP A0 Serial Address Bit
This bit sets the value of the A0 bit for the DDC
serial port.
Table 54. HDCP A0 Serial Address
Select
1
0
Serial Address
A0 bit = 1, address = 0x76
A0 bit = 0, address = 0x74
The default setting is 0.
0x20 6
MDA Pin Select
This bit sets the function of Pin 49 to MDA when set at 1.
Table 55. MDA Pin Select
Select
1
0
Output Mode
Pin 49 = MDA for HDCP
Pin 49 = CTL3 signal
The default setting is 0.
0x20 5
Analog Input Bandwidth Control
This bit controls the analog input bandwidth.
Test Bits
Must be set to 0 for standard input sampling.
Test Register
Must be set to 0x84 for proper operation.
Test
0x1C 2
Test Register
Must be set to 0xFF for proper operation.
Must be set to 0x00 for autogain mode and 0x10 for
manual-gain mode.
0x1C 1
Output Mode
4:4:4
4:2:2
Select
1
0
Test
0x1A 7:0
4:2:2 mode can be used to reduce the number of data
lines used from 24 to 16 for applications using YUV,
YCbCr, or YPbPr graphics signals. See Figure 27 for a
timing diagram for this mode.
Table 53. HDCP Key Status
The default is 0.
0x19 7:0
4:2:2 Output Mode Select
Table 56. Analog Input Bandwidth Control
Select
0
1
Input Bandwidth
High analog input bandwidth
Low analog input bandwidth
The default setting 0.
Rev. B | Page 43 of 52
AD9887A
0x20 4
MDA/MCL Three-State
0x21 7:0
This bit allows the MDA/MCL lines to be three-stated
so that the HDCP key EEPROM can be programmed
in-circuit.
Set to 0x00 for autogain mode and 0x64 for manualgain mode.
0x22 7:0
Table 57. MDA/MCL Three-State
Select
1
0
0x23 7:0
0x24 7:0
0x25 7:0
Oscillator
Use internal oscillator
Use external oscillator on A0 pin
Test Register
Must be set to 0xF0 for proper operation.
0x26 7:0
Table 58. External Oscillator Select
Test Register
Must be set to 0xFF for proper operation.
0x27 7:0
Test Register
Must be set to 0x0F for proper operation.
The default setting is 0.
View HDCP Mask
This bit allows the HDCP mask to be output on the RGB
channels.
Table 59. View HDCP Mask
Select
1
0
Test Register
Must be set to 0x00 for proper operation.
External Oscillator
This bit allows use of either the internal oscillator or an
external one supplied on the A0 pin.
0x20 2
Test Register
Must be set to 0x2A for proper operation.
The default setting is 0.
Select
1
0
Test Register
Must be set to 0x00 for proper operation.
MDA/MCL Output
Normal operation
MDA/MCL set to three-state
0x20 3
Test Register
Output Mode
HDCP mask output to RGB channel
Normal operation
Rev. B | Page 44 of 52
AD9887A
2-Wire Serial Control Port
Data Transfer via Serial Interface
A 2-wire serial interface control port is provided. Up to four
AD9887A devices can be connected to the 2-wire serial
interface, with each device having a unique address.
For each byte of data read or written, the MSB is the first bit of
the sequence.
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The analog flat panel interface
acts as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL
is high, the serial interface interprets that action as a start or
stop sequence.
There are five components to serial bus operation:
•
•
•
•
•
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
The first eight bits of data transferred after a start signal comprise
a 7-bit slave address (the first seven bits) and a single R/W bit
(the eighth bit). The R/W bit indicates the direction of data transfer,
reading from (1) or writing to (0) the slave device. If the transmitted slave address matches the address of the device (set by
the state of the A1 and A0 input pins listed in Table 60), the
AD9887A acknowledges it by bringing SDA low on the ninth
SCL pulse. If the addresses do not match, the AD9887A does
not acknowledge it.
Table 60. Serial Port Addresses
Bit 6
A5
0
0
0
0
Bit 5
A4
0
0
0
0
Writing data to a specific control register of the AD9887A
requires writing to its 8-bit address after the slave address has
been established. This control register address is the base
address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data
byte intended for the base address is established. If more bytes
are transferred than there are available addresses, the address
does not increment and remains at its maximum value of 0x1D.
Any base address higher than 0x1D does not produce an
acknowledge signal.
Data is read from the control registers of the AD9887A in a
similar manner. Reading requires two data transfer operations.
When the serial interface is inactive (SCL and SDA are high),
communication is initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slaved devices that a data transfer sequence
is coming.
Bit 7
A6 (MSB)
1
1
1
1
If the AD9887A does not acknowledge the master device
during a write sequence, the SDA remains high so that the
master can generate a stop signal. If the master device does
not acknowledge the AD9887A during a read sequence, the
AD9887A interprets this as the end of the data. The SDA
remains high so that the master can generate a stop signal.
Bit 4
A3
1
1
1
1
Bit 3
A2
1
1
1
1
Bit 2
A1
0
0
1
1
The base address must be written with the R/W bit of the slave
address byte low to set up a sequential read operation.
Reading begins at the previously established base address with
the R/W bit of the slave address byte high. The address of the
read register auto-increments after each byte is transferred.
To terminate a read/write sequence to the AD9887A, a stop
signal must be sent. A stop signal comprises a low-to-high
transition of SDA while SCL is high. The timing for the
read/write operations is shown in Figure 41; a typical byte
transfer is shown in Figure 42.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generating
a stop signal to terminate the current communication. This is
used to change the mode of communication (read, write) between
the slave and master without releasing the serial interface lines.
Bit 1
A0
0
1
0
1
Rev. B | Page 45 of 52
AD9887A
SDA
tBUFF
tDHO
tDSU
tSTAH
tSTASU
tSTOSU
tDAL
02838-039
SCL
tDAH
Figure 41. Serial Port R/W Timing
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
02838-040
SDA
SCL
Figure 42. Serial Interface—Typical Byte Transfer
Rev. B | Page 46 of 52
AD9887A
Serial Interface Read/Write Examples
Write to one of the following control registers:
•
•
•
•
•
Start signal
Slave address byte (R/W bit = low)
Base address byte
Data byte to base address
Stop signal
Write to four of the following consecutive control registers:
•
•
•
•
•
•
•
•
Start signal
Slave address byte (R/W bit = low)
Base address byte
Data byte to base address
Data byte to (base address + 1)
Data byte to (base address + 2)
Data byte to (base address + 3)
Stop signal
Read from four of the following consecutive control registers:
•
•
•
•
•
•
•
•
•
•
Start signal
Slave address byte (R/W bit = low)
Base address byte
Start signal
Slave address byte (R/W bit = high)
Data byte from base address
Data byte from (base address + 1)
Data byte from (base address + 2)
Data byte from (base address + 3)
Stop signal
Table 61. Control of Sync Block Muxes via the Serial Register
Mux
No.
1 and 2
Serial Bus,
Control Bit
0x12, Bit 4
Control
Bit State
0
1
Result
Pass Hsync
Pass sync-on-green
3
0x12, Bit 1
0
1
Pass coast
Pass Vsync
4
0x12, Bit 2
0
1
Pass Vsync
Pass sync separator signals
5, 6,
and 7
0x11, Bit 3
0
Pass digital interface signals
1
Pass analog interface signals
Read from one of the following control registers:
•
•
•
•
•
•
•
Start signal
Slave address byte (R/W bit = low)
Base address byte
Start signal
Slave address byte (R/W bit = high)
Data byte from base address
Stop signal
Rev. B | Page 47 of 52
AD9887A
THEORY OF OPERATION—SYNC PROCESSING
The basic idea is that the counter counts up when Hsync pulses
are present. Since Hsync pulses are relatively short in width, the
counter only reaches a value of N before the pulse ends. It then
starts counting down, eventually reaching 0 before the next
Hsync pulse arrives. The specific value of N varies among video
modes, but is always less than 255. For example, with a 1 μs
width Hsync, the counter only reaches 5 (1 μs/200 ns = 5).
When Vsync is present on the composite sync, the counter also
counts up. Because the Vsync signal is much longer, it counts to
a higher number M. For most video modes, M is at least 255.
Therefore, Vsync can be detected on the composite sync signal
by detecting when the counter counts to higher than N. The
specific count that triggers detection, the threshold count (T),
can be programmed through the serial Register 0x0F. Once
Vsync is detected, there is a similar process to detect when it
becomes inactive. Upon detection, the counter first resets to 0,
then counts up when Vsync disappears. Similar to the previous
case, it detects the absence of Vsync when the counter reaches
T. In this way, it rejects noise and/or serration pulses. Once
Vsync is detected to be absent, the counter resets to 0 and
begins the cycle again.
SYNC STRIPPER
The purpose of the sync stripper is to extract the sync signal
from the green graphics channel. A sync signal is not present on
all graphics systems, only those with sync-on-green. The sync
signal is extracted from the green channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a trigger level that is 0.15 V above the clamped level. The
output signal is typically a composite sync signal containing
both Hsync and Vsync.
SYNC SEPARATOR
A sync separator extracts the Vsync signal from a composite
sync signal by using a low-pass filter-like or integrator-like
operation. It works on the idea that the Vsync signal stays active
much longer than the Hsync signal. Therefore, it rejects any signal
shorter than a threshold value, which is somewhere in the range
between an Hsync pulse width and a Vsync pulse width.
The sync separator on the AD9887A is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.)
SYNC STRIPPER
NEGATIVE PEAK
CLAMP
ACTIVITY
DETECT
SYNC SEPARATOR
COMP
SYNC
INTEGRATOR
VSYNC
1/S
SOG
MUX 1
HSYNC IN
SOG OUT
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNC OUT
HSYNC
CLOCK
GENERATOR
MUX 2
HSYNC OUT
PIXEL CLOCK
COAST
COAST
MUX 3
POLARITY
DETECT
AD9887A
POLARITY
INVERT
ACTIVITY
DETECT
POLARITY
DETECT
MUX 4
Figure 43. Sync Processing Block Diagram
Rev. B | Page 48 of 52
VSYNC OUT
02838-041
VSYNC IN
AD9887A
PCB LAYOUT RECOMMENDATIONS
The AD9887A is a high performance, high speed analog device.
To optimize its performance, it is important to have a well laid
out board. The following is a guide for designing a board using
the AD9887A.
The fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the side of the PC board opposite from the AD9887A, because
this interposes resistive vias in the path.
ANALOG INTERFACE INPUTS
The bypass capacitors should physically be located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
•
•
Minimize the trace length running into the graphics inputs.
This is accomplished by placing the AD9887A as close as
possible to the graphics VGA connector. Long input trace
lengths are undesirable because they pick up noise from
the board and other external sources.
Place the 75 Ω termination resistors as close to the AD9887A
chip as possible. Any additional trace length between the
termination resistors and the input of the AD9887A
increases the magnitude of reflections, which corrupts the
graphics signal.
Use 75 Ω matched impedance traces. Trace impedances
other than 75 Ω also increase the chance of reflections.
The AD9887A has very high input bandwidth (330 MHz).
Although this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it means that it also captures any
high frequency noise present. Therefore, it is important to reduce
the amount of noise coupled to the inputs. Avoid running any
digital traces near the analog inputs. Due to the high bandwidth
of the AD9887A, sometimes low-pass filtering the analog inputs
can help reduce noise. (For many applications, filtering is unnecessary.) Experiments have shown that placing a series ferrite
bead in front of the 75 Ω termination resistor can filter out
excess noise. Specifically, the part used was the #2508051217Z0
from Fair-Rite, but each application might work best with a
different bead value. Alternatively, placing a 100 Ω to 120 Ω
resistor between the 75 Ω termination resistor and the input
coupling capacitor can also be beneficial.
DIGITAL INTERFACE INPUTS
Some graphics controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVD, from a different,
cleaner power source (for example, from a 12 V supply).
It is recommended to use a single ground plane for the entire
board. Experience shows that noise performance is the same or
better with a single ground plane. Using multiple ground planes
can be detrimental because each separate ground plane is
smaller and can result in long ground loops.
In some cases, using separate ground planes is unavoidable. For
these cases, it is recommended to place at least a single ground
plane under the AD9887A. The location of the split should be at
the receiver of the digital outputs. For these cases, it is even
more important to place components wisely because the current
loops are much longer, and current takes the path of least
resistance. An example of a current loop follows.
LAN
DP
UN
RO
G
E
POWER PLANE
AD988
7A
DI
GI
T
AL
POWER SUPPLY BYPASSING
GI
TA
L
CE
DI
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is only necessary to have one bypass
capacitor.
GR
OU N
D PL A
NE
DIGITAL DATA R
VE R
E C EI
Figure 44. Example of a Current Loop
Rev. B | Page 49 of 52
TPUT T
OU
RA
Each differential input pair (Rx0+, Rx0−, RxC+, RxC−, and so
on) should be routed together using 50 Ω strip line routing
techniques kept as short as possible. No other components
should be placed on these inputs (for example, no clamping
diodes). Every effort should be made to route these signals on a
single layer (component layer) with no vias.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful regulation,
filtering, and bypassing. It is highly desirable to provide separate
regulated supplies for each of the analog circuitry groups (VD
and PVD).
02838-042
•
ANALO
G
Using the following layout techniques on the graphics inputs is
extremely important.
AD9887A
PLL
Place the PLL loop filter components as close as possible to the
FILT pin. Do not place any digital or other high frequency
traces near these components. Use the values suggested in the
Specifications section with 10% tolerances or less.
OUTPUTS—BOTH DATA AND CLOCKS
Try to minimize the trace length that the digital outputs must
drive. Longer traces have higher capacitance, requiring more
current and causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
Adding a series resistor with a value of 22 Ω to 100 Ω can suppress
reflections, reduce EMI, and reduce the current spikes inside of
the AD9887A. However, if 50 Ω traces are used on the PCB, the
data outputs should not need these resistors. A 22 Ω resistor on
the DATACK output should provide good impedance matching
that further reduces reflections. If EMI or current spiking is a
concern, it is recommended to use a lower drive strength setting.
If series resistors are used, place them as close as possible to the
AD9887A pins, but try not to add vias or extra length to the
output trace.
keeping traces short and connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the AD9887A, creating digital
noise on the power supplies.
DIGITAL INPUTS
The digital inputs on the AD9887A are designed to work with
3.3 V signals.
Any noise in the HSYNC input trace produces jitter in the
system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
VOLTAGE REFERENCE
The voltage reference should be bypassed with a 0.1 μF
capacitor. Place it as close as possible to the AD9887A pin.
Make the ground connection as short as possible.
REFOUT is easily connected to REFIN with a short trace.
Avoid making this trace longer than necessary.
When using an external reference, the REFOUT output,
although unused, still needs to be bypassed with a 0.1 μF
capacitor to avoid ringing.
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can be accomplished easily by
Rev. B | Page 50 of 52
AD9887A
OUTLINE DIMENSIONS
1.03
0.88
0.73
31.45
31.20 SQ
30.95
4.10
MAX
120
121
81
80
SEATING
PLANE
28.20
28.00 SQ
27.80
TOP VIEW
(PINS DOWN)
10°
6°
2°
3.60
3.40
3.20
VIEW A
PIN 1
160
0.23
0.11
0.65 BSC
LEAD PITCH
7°
0°
0.50
0.25
41
40
1
0.10
COPLANARITY
0.40
0.22
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-022DD-1
Figure 45. 160-Lead Metric Quad Flat Package [MQFP]
(S-160)
Dimension shown in millimeters
ORDERING GUIDE
Model
AD9887AKS-100
AD9887AKSZ-100 1
AD9887AKS-140
AD9887AKSZ-1401
AD9887AKS-170
AD9887AKSZ-1701
AD9887A/PCB
1
Max Speed (MHz) Analog
100
100
140
140
170
170
DVI
100
100
140
140
170
170
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Z = RoHS Compliant Part.
Rev. B | Page 51 of 52
Package Description
160-Lead Metric Quad Flatpack
160-Lead Metric Quad Flatpack
160-Lead Metric Quad Flatpack
160-Lead Metric Quad Flatpack
160-Lead Metric Quad Flatpack
160-Lead Metric Quad Flatpack
Evaluation Kit
Package Option
S-160
S-160
S-160
S-160
S-160
S-160
AD9887A
NOTES
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02838-0-3/07(B)
T
T
Rev. B | Page 52 of 52