LANSDALE MC145407P 5 volt only driver/receiver rs232 eia-232-e and ccitt v.28 Datasheet

ML145407
5 Volt Only Driver/Receiver
RS232 EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145407
The ML145407 is a silicon–gate CMOS IC that combines three
drivers and three receivers to fulfill the electrical specifications of
RS232 EIA–232–E and CCITT V.28 while operating from a single + 5
V power supply. A voltage doubler and inverter convert the + 5V to ±
10 V. This is accomplished through an on–board 20 kHz oscillator
and four inexpensive external electrolytic capacitors. The three drivers
and three receivers of the ML145407 are virtually identical to those of
the ML145406. Therefore, for applications requiring more than three
drivers and/or three receivers, an ML145406 can be powered from an
ML145407, since the ML145407 charge pumps have been designed to
guarantee ± 5 V at the output of up to six drivers. Thus, the
ML145407 provides a high–performance, low–power, stand–alone
solution or, with the ML145406, a + 5 V only, high–performance
two–chip solution.
This device offers the following performance features:
• Operating Temperature Range = TA –40° to +85°C
Drivers
• ± 7.5 V Output Swing
• 300Ω Power–Off Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Slew Rate Range Limited from 4 V/µs to 30 V/µs
P DIP 20 = RP
PLASTIC DIP
CASE 738
20
1
SOG 20 = -6P
SOG PACKAGE
CASE 751D
20
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20
MC145407P
MC145407DW
ML145407RP
ML145407-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
C2+
GND
Receivers
• + 25 V Input Range
• 3 to 7 kΩ Input Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
C2–
VSS
Charge Pumps
• + 5 V to ± 10 V Dual Charge Pump Architecture
• Supply Outputs Capable of Driving Three On–Chip Drivers and
Three Drivers on the ML145406 Simultaneously
• Requires Four Inexpensive Electrolytic Capacitors
• On–Chip 20 kHz Oscillator
Rx1
Tx1
Rx2
Tx2
Rx3
Tx3
1
20 C1+
2
19
3
18
4
17
5
R
R
8
9
10
C1–
VDD
DO1
D 15 DI1
6
7
16
VCC
14
DO2
D 13 DI2
R
12
DO3
D 11 DI3
D = DRIVER
R = RECEIVER
Page 1 of 8
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Issue A
ML145407
LANSDALE Semiconductor, Inc.
FUNCTION DIAGRAM
CHARGE PUMPS
OSC
GND
VCC
VOLTAGE
DOUBLER
C3
+
C4
VOLTAGE
INVERTER
+
VDD
C1
+
C1 – C1 +
C2 +
C2 –
DRIVER
RECEIVER
VDD
VDD
VDD
VCC
*
15 kΩ
Rx
+
VSS
* Proctection circuit
VCC
DO
–
5.4 k
Page 2 of 8
VSS
C2
+
300 Ω
LEVEL
SHIFT
Tx
+
DI
–
1.4 V
1.0 V
1.8 V
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VSS
Issue A
ML145407
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS (Voltage polarities referenced to GND)
Rating
DC Supply Voltages
Input Voltage Range
Symbol
Value
Unit
VCC
– 0.5 to + 6.0
V
VIR
Rx1 – Rx3 Inputs
DI1 – DI3 Inputs
V
VSS – 15 to VDD + 15
– 0.5 to (VCC + 0.5)
DC Current per Pin
I
± 100
mA
Power Dissipation
PD
1
W
TA
– 40 to + 85
°C
Tstg
– 85 to + 150
°C
Operating Temperature Range
Storage Temperature Range
This device contains protection circuitry to
protect the inputs against damage due to high
static voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that the voltages at the DI and DO pins
be constrained to the range GND VDI VCC
and GND VDO ≤ V CC. Also, the voltage at
the Rx pin should be constrained to (VSS
– 15 V) ≤ VRx1 – Rx3 (VDD + 15 V), and Tx
should be constrained to VSS VTx1 – Tx3
VDD.
Unused inputs must always be tied to
appropriate logic voltage level (e.g., GND or
VCC for DI, and GND for Rx).
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V; C1, C2, C3, C4 = 10 µF; TA = – 40 to + 85°C)
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
VCC
4.5
5
5.5
V
Quiescent Supply Current
(Outputs unloaded, inputs low)
ICC
—
1.2
3.0
mA
Iload = 0 mA
Iload = 5 mA
Iload = 10 mA
VDD
8.5
7.5
6
10
9.5
9
11
—
—
V
Iload = 0 mA
Iload = 5 mA
Iload = 10 mA
VSS
– 8.5
– 7.5
–6
– 10
– 9.2
– 8.6
–11
—
—
Parameter
Output Voltage
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V; VCC = + 5 V ± 10%; C1, C2, C3, C4 = 10 µF; TA = – 40 to + 85°C)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Turn–on Threshold
VDO1 – DO3 = VOL
Rx1 – Rx3
Von
1.35
1.8
2.35
V
Input Turn–off Threshold
VDO1 – DO3 = VOH
Rx1 – Rx3
Voff
0.75
1.0
1.25
V
Input Threshold Hysteresis (Von – Voff)
Rx1 – Rx3
Vhys
0.6
0.8
—
V
Input Resistance
Rx1 – Rx3
Rin
3.0
5.4
7.0
kΩ
High–Level Output Voltage
VRx1 – Rx3 = – 3 V to – 25 V
IOH = – 20 µA
IOH = – 1 mA
DO1 – DO3
VOH
Low–Level Output Voltage
VRx1 – Rx3 = + 3 V to + 25 V
IOL = + 20 µA
IOL = + 1.6 mA
DO1 – DO3
Page 3 of 8
V
VCC – 0.1
VCC – 0.7
—
—
VOL
V
—
—
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—
4.3
0.01
0.5
0.1
0.7
Issue A
ML145407
LANSDALE Semiconductor, Inc.
DRIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V: VCC = +5 V ± 10%; C1, C2, C3, C4 = 10 µF; TA = –40 to +85°C)
Characteristic
Digital Input Voltage
Logic 0
Logic 1
DI1 – DI3
Input Current
GND ≤ VDI1 – DI3 ≤ VCC
DI1 – DI3
Symbol
Min
Typ
Max
Unit
VIL
VIH
—
2.0
—
—
0.8
—
Iin
—
—
± 1.0
µA
V
Output High Voltage
VDI1 – DI3 = Logic 0, RL = 3.0 kΩ
Tx1 – Tx3
Tx1 – Tx6*
VOH
6
5
7.5
6.5
—
—
V
Output Low Voltage
VDI1 – DI3 = Logic 1, RL = 3.0 kΩ
Tx1 – Tx3
Tx1 – Tx6*
VOL
–6
–5
– 7.5
– 6.5
—
—
V
Tx1 – Tx3
Zoff
300
—
—
Ω
Tx1 – Tx3
Tx1 – Tx3 shorted to GND**
Tx1 – Tx3 shorted to ± 15 V***
ISC
—
—
—
—
± 60
± 100
Off Source Impedance (Figure 1)
Output Short–Circuit Current
VCC = + 5.5 V
mA
* Specifications for an ML145407 powering an ML145406 with three additional drivers/receivers.
** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits could be exceeded.
*** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (VCC = + 5 V ± 10%; C1, C2, C3, C4 = 10 µF; TA = – 40 to + 85°C; See Figures 2 and 3)
Characteristic
Symbol
Min
Typ
Max
Unit
Drivers
Propagation Delay Time
Low–to–High
RL = 3 kΩ, CL = 50 pF or 2500 pF
Tx1 – Tx3
High–to–Low
RL = 3 kΩ, CL = 50 pF or 2500 pF
Output Slew Rate
Minimum Load: RL = 7 kΩ, CL = 0 pF
µs
tPLH
—
0.5
1
—
0.5
1
—
9.0
± 30
4.0
—
—
tPLH
—
—
1
tPHL
—
—
1
tPHL
Tx1 – Tx3
SR
Maximum Load: RL = 3 kΩ, CL = 2500 pF
V/µs
Receivers (CL = 50 pF)
Propagation Delay Time
Low–to–High
µs
DO1 – DO3
High–to–Low
Output Rise Time
DO1 – DO3
tr
—
250
400
ns
Output Fall Time
DO1 – DO3
tf
—
40
100
ns
Page 4 of 8
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Issue A
ML145407
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
17
19
VDD VCC
15
DI1
6
Tx1
Tx2 8
13 DI2
11
VCC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic power supply. This pin should have a 0.33 µF capacitor to ground.
DI3
GND
Ground (Pin 2)
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
Vin = ± 2 V
10
Tx3
VDD
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler and
the positive power supply input of the driver/receiver sections of
the device. This pin requires an external storage capacitor to filter the 50% duty cycle voltage generated by the charge pump.
Vin
Rout =
I
VSS GND
4
2
Figure 1. Power–Off Source Resistance
DRIVERS
VSS
Negative Power Supply (Pin 4)
This is the negative output of the on–chip voltage
doubler/inverter and the negative power supply input of the
driver/receiver sections of the device. This pin requires an
external storage capacitor to filter the 50% duty cycle voltage
generated by the charge pump.
3V
DI1 – DI3
50%
0V
tf
tr
VOH
90%
Tx1 – Tx3
10%
VOL
tPLH
tPHL
RECEIVERS
+3V
Rx1 – Rx3
50%
0V
tPHL
tPLH
VOH
90%
50%
10%
DO1 – DO3
tf
VOL
tr
Figure 2. Switching Characteristics
DRIVERS
3V
Tx1 – Tx3
–3V
tSLH
SLEW RATE (SR) =
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
DO pin to swing up to VCC.
DO1, DO2, DO3
Data Output (Pins 16, 14, 12)
These are the receiver digital output pins, which swing from
VCC to GND. Each output pin is capable of driving one
LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the drivers. Input voltage levels on these pins must be between VCC
and GND.
3V
–3V
tSHL
– 3 V – (3 V)
3 V – ( – 3 V)
OR
tSLH
tSHL
Figure 3. Slew Rate Characterization
Page 5 of 8
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler and
inverter, which generate the VDD and VSS voltages.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
These are the EIA–232–E transmit signal output pins,which
swing toward VDD and VSS. A logic 1 at a DI input causes the
corresponding Tx output to swing toward VSS. A logic 0 causes the output to swing toward VDD. The actual levels and slew
rate achieved will depend on the output loading (RL\\CL).
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
ESD CONSIDERATIONS
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or indirectly can cause damage to gate oxides and transistor junctions
by coupling a portion of the energy from the I/O pin to the
power supply busses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 7 shows a technique
which will clamp the ESD voltage at approximately + 15 V
using the MMBZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
0.1 µF capacitors.
10 µF charge pump caps to illustrate its capability in driving a
companion ML145406 or ML145403. If there is no requirement to support a second interface device and/or the charge
pump is not being used to power any other components, the
ML145407 is capable of complying with EIA–232–E and V.28
with smaller value charge pump caps.Table 1 summarizes driver performance with both 2.2 µF and1.0µF charge pump caps.
Table 1. Typical Performance
Parameter
Tx VOH @ 25°C
OPERATION WITH SMALLER VALUE CHARGE
PUMP CAPS
The ML145407 is characterized in the electrical tables using
2.2 µF
1.0 µF
7.3
7.2
Tx VOH @ 85°C
7.2
7.1
Tx VOL @ 25°C
– 6.5
– 6.4
Tx VOL @ 85°C
– 6.1
– 6.0
Tx Slew Rate @ 25°C
8.0 V/µs
8.0 V/µs
Tx Slew Rate @ 85°C
7.0 V/µs
7.0 V/µs
+5V
0.1 µF
20
DTMF
INPUT
CDSI RTLA
RDSI
20 kΩ
TIP
16
18
CFB
10
0.1 µF
VSS BYPASS
Xout
CD
8
1.0 µF
C2 – VDD
19
VCC C1 –
1.0 µF
1
C1 +
C2 +
15 DI1
16 DO1
3
11
TxD
5
RxD
ML145442
OR
RxA1
ML145443
17 +
3
3.579
MHz
0.1 µF
1.0 µF
13
Tx1
DI2
SQT
ExI
LB
Rx1
0.1 µF 19
VAG
4
CDT
0.1 µF
CCDT
MODE
VSS
12
CDA
8
2
ML145407
14
Tx2
2
Rx2
DI3
10 kΩ
FB
6
5
10 kΩ
10 kΩ
RING
VDD
Xin 9
DSI
600:600
*
0.1 µF
VDD BYPASS
6
VDD
17
TxA
15
RxA2
0.1 µF
RTx
10 µF 600
+
10 kΩ
1
TLA
0.1 µF
8
7
EIA–232–E
DB–25
CONNECTOR
3
7
9
Rx3
13
7
CCDA
0.1 µF
1.0 µF
VSS
4
GND
2
* Line protection circuit
Figure 4. 5 V, 300 Baud Modem with EIA–232–E Interface
Page 6 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
+5V
1 V
DD
2
Rx1
3
Tx1
4 Rx2
5
6
7
8
VCC 16
15
DO1
14
DI1
13
DO2
ML145406
12
Tx2
DI2
11
Rx3
DO3
10
Tx3
DI3
9
GND
VSS
1
C1+
C2+
10 µF
20
2
19
GND
VCC
18
3 C2–
C1–
4 V
17
VDD
SS
5
16
Rx1 ML145407 DO1
6
Tx1
DI1 15
14
7
Rx2
DO2
8 Tx2
13
DI2
9
12
Rx3
DO3
11
10
Tx3
DI3
10 µF
10 µF
10 µF
Figure 5. ML145406/ML145407 5 V Only Solution for up to Six EIA–232–E Drivers and Receivers
+5 V
+ 10 V
C2
C2+
GND
C2–
VSS
C4
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
C1+
0.1 µF
VCC
C1–
VDD
0.1 µF
Figure 6. Two Supply Configuration (ML145407 Generates V SS Only)
+5 V
MMBZ15VDLT × 6
C2
C2+
GND
C2–
VSS
C4
Rx1
Tx1
TO
CONNECTOR
Rx2
Tx2
Rx3
Tx3
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
C1+
C1
VCC
0.1 µF
C1–
VDD
DO1
C3
0.1 µF
DI1
DO2
DI2
DO3
DI3
Figure 7. ESD Protection Scheme
Page 7 of 8
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Issue A
ML145407
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145407RP)
PLASTIC DIP
CASE 738–03
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
L
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T A
M
M
SOG 20 = -6P
(ML145407-6P)
SOG PACKAGE
CASE 751D–04
–A–
20
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
G
K
SEATING
PLANE
B
M
INCHES
MILLIMETERS
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
0°
15°
0.020 0.040
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
11
–B–
T
DIM
A
B
C
D
E
F
G
J
K
L
M
N
X 45
DIM
A
B
C
D
F
G
J
K
M
P
R
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
M
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 8 of 8
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Issue A