NV25M01 Product Preview 1 Mb SPI Serial CMOS EEPROM Description The NV25M01 is a 1M−bit Serial CMOS EEPROM device internally organized as 128Kx8 bits. It features a 256−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device features software and hardware write protection, including partial as well as full array protection. On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications. www.onsemi.com SOIC−8 DW SUFFIX CASE 751BD TSSOP−8 DT SUFFIX CASE 948AL Features • • • • • • • • • • • • • • 10 MHz Capability 1.8 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 256−byte Page Write Buffer Identification Page with Permanent Write Protection Self−timed Write Cycle Hardware and Software Protection Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Automotive Grade 2 Temperature Range (105°C) 8 lead SOIC and TSSOP Packages This Device is Pb−Free, Halogen Free/BFR Free and is RoHS Compliant PIN CONFIGURATIONS CS SO WP VSS SOIC (DW), TSSOP (DT) (Top View) PIN FUNCTION Pin Name Function CS Chip Select SO Serial Data Output WP Write Protect VSS Ground SI VCC VCC HOLD SCK SI 1 Serial Data Input SCK HOLD Serial Clock Hold Transmission Input SI VCC CS WP NV25M01 Power Supply SO ORDERING INFORMATION HOLD See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. SCK VSS Figure 1. Functional Symbol This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2016 September, 2016 − Rev. P1 1 Publication Order Number: NV25M01/D NV25M01 MARKING DIAGRAMS TM1A AYMXXX G W25M1A AYMXXX (TSSOP−8) (SOIC−8) TM1A A Y M XXX W25M1A = Specific Device Code A = Assembly Location Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number G = Specific Device Code = Assembly Location = Production Year (Last Digit) = Production Month (1−9, O, N, D) = Last Three Digits of = Assembly Lot Number = Pb−Free Microdot Table 1. MAXIMUM RATINGS Parameter Ratings Units Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program / Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C 4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D. C. OPERATING CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +105°C, unless otherwise specified) Symbol Parameter ICCR Supply Current (Read Mode) ICCW Test Conditions SO open Min Max Units VCC = 1.8 V, fSCK = 5 MHz 1.2 mA VCC = 2.5 V, fSCK = 10 MHz 1.8 mA VCC = 5.5 V, fSCK = 10 MHz 3 mA 3 mA 3 mA 2 mA Supply Current (Write Mode) ISB Standby Current VIN = GND or VCC, CS = VCC IL Input Leakage Current VIN = GND or VCC ILO Output Leakage Current CS = VCC, VOUT = GND or VCC −2 2 mA VIL Input Low Voltage VCC ≥ 2.5 V −0.5 0.3VCC V VIH Input High Voltage VOL VOH Output Low Voltage Output High Voltage −2 VCC < 2.5 V −0.5 0.25VCC VCC ≥ 2.5 V 0.7VCC VCC + 0.5 VCC < 2.5 V 0.75VCC VCC + 0.5 VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 VCC < 2.5 V, IOL = 150 mA 0.2 VCC ≥ 2.5 V, IOH = −1.6 mA VCC − 0.8 VCC < 2.5 V, IOH = −100 mA VCC − 0.2 V V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 NV25M01 Table 4. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) (Note 5) Test Symbol COUT CIN Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Min Typ Max Units VOUT = 0 V 8 pF VIN = 0 V 8 pF 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 5. A.C. CHARACTERISTICS (TA = −40°C to +105°C, unless otherwise specified.) (Note 6) VCC = 1.8 V − 5.5 V Symbol Parameter VCC = 2.5 V − 5.5 V Min Max Min Max Units 5 DC 10 MHz fSCK Clock Frequency DC tSU Data Setup Time 20 10 ns tH Data Hold Time 20 10 ns tWH SCK High Time 75 40 ns tWL SCK Low Time 75 40 ns tLZ HOLD to Output Low Z 50 25 ns tRI (Note 8) Input Rise Time 2 2 ms tFI (Note 8) Input Fall Time 2 2 ms tHD HOLD Setup Time 0 0 ns tCD HOLD Hold Time 10 10 ns tV Output Valid from Clock Low 75 tDIS Output Disable Time 50 20 ns tHZ HOLD to Output High Z 100 25 ns tCS CS High Time 80 40 ns tCSS CS Setup Time 60 30 ns tCSH CS Hold Time 60 30 ns tCNS CS Inactive Setup Time 60 30 tCNH CS Inactive Hold Time 60 30 tWPS WP Setup Time 10 10 ns tWPH WP Hold Time 10 10 ns Write Cycle Time 0 ns Output Hold Time tWC (Note 7) 0 40 tHO ns 5 5 ms 6. AC Test Conditions: Input Pulse Voltages: 0.2 VCC to 0.8 VCC for VCC ≥ 2.5 V & 0.15 VCC to 0.85 VCC for VCC < 2.5 V Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 6. POWER−UP TIMING (Notes 8 and 9) Parameter Symbol Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 3 NV25M01 Pin Description Functional Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and the NV25M01. CS: The chip select input pin is used to enable/disable the NV25M01. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and NV25M01 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When the WP pin is tied low and the WPEN bit in the Status Register is set to “1”, writing to the Status Register is disabled. HOLD: The HOLD input pin is used to pause transmission between host and NV25M01, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, it is recommended the HOLD input to be tied to VCC, either directly or through a resistor. The NV25M01 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. The instruction set and associated op−codes are listed in Table 7. Reading data stored in the NV25M01 is accomplished by providing the READ command and an address. Writing to the NV25M01 requires a WRITE command, address and data. After a high to low transition on the CS input pin, the NV25M01 will accept any one of the six instruction op−codes listed in Table 7 and will ignore all other possible 8−bit combinations. The communication protocol follows the timing illustrated in Figure 2. The NV25M01 features an Identification Page (256 bytes) which can be accessed for Read and Write operations when the IPL bit in the Status Register is set to “1”. The user can also choose to make the Identification Page permanently write protected. Table 7. INSTRUCTION SET Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory tCS CS tCSS tCNH tWH tWL tCNS tCSH SCK tSU tH tRI tFI VALID IN SI tV tV tDIS tHO SO HI− Z VALID OUT Figure 2. Synchronous Data Timing www.onsemi.com 4 HI− Z NV25M01 Status Register prevents writing to the status register and to the block protected sections of memory. While hardware write protection is active, only the non−block protected memory can be written. Hardware write protection is disabled when the WP pin is high or the WPEN bit is 0. The WPEN bit, WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 10. The IPL (Identification Page Latch) bit determines whether the Identification Page (IPL = 1) or main memory array (IPL = 0) will be accessed for Read or Write operations. The IPL bit is set by the user with the WRSR command and is volatile. The IPL bit is automatically reset after a read/write operations. The LIP bit is set by the user with the WRSR command and is non−volatile. When set to 1, the Identification Page is permanently write protected (locked in Read−only mode). Note: The IPL and LIP bits cannot be set within the same WRSR instruction. If the user attempts to set both the IPL and LIP bits at the same time, these bits will remain unchanged. The Status Register, described in Table 8, contains status and control bits. The RDY (Ready) bit indicates whether the device is busy executing a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only. The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. This condition Table 8. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN IPL 0 LIP BP1 BP0 WEL RDY Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 None No Protection 0 1 18000h−1FFFFh Quarter Array Protection 1 0 10000h−1FFFFh Half Array Protection 1 1 00000h−1FFFFh Full Array Protection Array Address Protected Protection Table 10. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable www.onsemi.com 5 NV25M01 Write Enable and Write Disable Write Operations The NV25M01 device powers up into a write disable state. The Write Enable Latch (WEL) bit must be set before attempting to write to memory or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by the BP0 and BP1 status register bits. The internal Write Enable Latch and the correspon–ding Status Register WEL bit are set by sending the WREN instruction to the NV25M01. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior any WRITE or WRSR instruction. The internal Write Enable Latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. CS SCK SI 0 0 0 0 1 0 1 0 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI 0 0 0 0 0 1 0 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Figure 4. WRDI Timing www.onsemi.com 6 0 NV25M01 Byte Write page, thus possibly overwriting previoualy loaded data. Following completion of the write cycle, the NV25M01 is automatically returned to the write disable state. Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 24−bit address and a data byte as shown in Figure 5. Only 17 significant address bits are used by the NV25M01. The rest are don’t care bits, as shown in Table 11. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). Write Identification Page The 256−byte Identification Page (IP) can be written with user data using the same Write commands sequences that are used for writing to the main memory array (Figure 6). The IPL Status Register bit must be set (IPL = 1), before attempting to write to the IP. Address bits [A23:A17] and [A14:A8] are Don’t Care and address bits [A7:A0] determine the starting byte address within the Identification Page. Address bits [A16:A15] must point to a location outside the protected area defined by Write Protection bits BP1 and BP0. When the entire memory is write protected (BP1, BP0 = 1,1), write requests to the IP will be ignored. A write request to the IP is also ignored if the LIP Status Register bit is set to 1 (the page is locked in Read−only mode). Page Write After sending the first data byte to the NV25M01, the host may continue sending data, up to a total of 256 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the Table 11. BYTE ADDRESS Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses Main Memory Array A16 − A0 A23 – A17 24 Identification Page (A16:15) and A7 − A0 A23 – A17 & A14 − A8 24 CS 0 1 2 3 4 5 6 7 8 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 0 BYTE ADDRESS* 1 AN 0 DATA IN A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SO * Please check the Byte Address Table (Table 11) Note: Dashed Line = mode (1, 1) Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 29 30 31 32−39 40−47 32+(N−1)x8−1....32+(N−1)x8 32+Nx8−1 SCK BYTE ADDRESS* OPCODE SI SO 0 0 0 0 0 0 1 0 DATA IN Data Data A0 Byte 1 Byte 2 AN HIGH IMPEDANCE * Please check the Byte Address Table (Table 11) Note: Dashed Line = mode (1, 1) Figure 6. Page WRITE Timing www.onsemi.com 7 Data Byte N 0 7..1 NV25M01 Write Status Register Write Protection The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3, 4, 6 and 7 can be written using the WRSR command. The Write Protect (WP) input can be used to protect against inadvertently altering Block Protect bits BP0 and BP1. When WP is low and the WPEN bit is set to “1”, write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to “0”. The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 MSB HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Note: Dashed Line = mode (1, 1) Figure 8. WP Timing www.onsemi.com 8 3 NV25M01 Read Operations for Read from main memory array (Figure 9). The IPL bit from the Status Register must be set (IPL = 1) before attempting to read from the IP. The [A7:A0] are the address significant bits that point to the data byte shifted out on the SO pin. If the CS continues to be held low, the internal address register defined by [A7:A0] bits is automatically incremented and the next data byte from the IP is shifted out. The byte address must not exceed the 256−byte page boundary. Read from Memory Array To read from memory, the host sends a READ instruction followed by a 24−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the NV25M01 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Status Register To read the status register, the host sends a RDSR command. After receiving the last bit of the command, the NV25M01 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. Read Identification Page Reading the additional 256−byte Identification Page (IP) is achieved using the same Read command sequence as used CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCK OPCODE SI 0 0 0 0 0 BYTE ADDRESS* 1 0 1 A0 AN DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 2 1 0 MSB * Please check the Byte Address Table (Table 11). Note: Dashed Line = mode (1, 1) Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE SI SO 0 0 0 0 0 DATA OUT HIGH IMPEDANCE MSB Note: Dashed Line = mode (1, 1) Figure 10. RDSR Timing www.onsemi.com 9 3 0 NV25M01 Hold Operation below the POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The NV25M01 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op−code will be ignored and the serial output pin (SO) will remain in the high impedance state. The HOLD input can be used to pause communication between host and NV25M01. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri−stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The NV25M01 device incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops CS tCD tCD SCK tHD tHD HOLD tHZ SO HIGH IMPEDANCE tLZ Note: Dashed Line = mode (1, 1) Figure 11. HOLD Timing www.onsemi.com 10 NV25M01 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. www.onsemi.com 11 NV25M01 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL ISSUE O b SYMBOL MIN NOM E1 E MAX 1.20 A A1 0.05 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. www.onsemi.com 12 NV25M01 ORDERING INFORMATION (Note 10) Specific Device Marking Package Type NV25M01DWUTG W25M1A NV25M01DTUTG TM1A Device Order Number Temperature Range Lead Finish Shipping (Note 11) SOIC−8 (Pb−Free) (−40°C to +105°C) NiPdAu 3,000 Units / Tape & Reel TSSOP−8 (Pb−Free) (−40°C to +105°C) NiPdAu 3,000 Units / Tape & Reel 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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