LINER LTC3225-1 2-cell supercapacitor charger Datasheet

LTC3226
2-Cell Supercapacitor
Charger with Backup
PowerPath Controller
DESCRIPTION
FEATURES
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1x/2x Multimode Charge Pump Supercapacitor
Charger
Automatic Cell Balancing
Ideal Diode Main PowerPath™ Controller
(VIN to VOUT)
Internal 2A LDO Backup Supply (CPO to VOUT)
Automatic Main/Backup Switchover
Input Voltage Range: 2.5V to 5.5V
Programmable SCAP Charge Voltage
Programmable Input Current Limit (315mA Max)
No Load IVIN = 55μA (Typical)
Low Profile, 16-Lead 3mm × 3mm QFN Package
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The LTC®3226 is a 2-cell series supercapacitor charger with
a backup PowerPath controller. It includes a charge pump
supercapacitor charger with programmable output voltage,
a low dropout regulator, and a power-fail comparator for
switching between normal and backup modes.
The constant input current supercapacitor charger is
designed to charge two supercapacitors in series to a
resistor-programmable output voltage of 2.5V to 5.3V.
The charger input current limit is programmable by an
external resistor at up to 315mA.
The internal backup LDO is powered from the supercapacitors and provides up to 2A peak output current with
an adjustable output voltage. When the input supply falls
below the power-fail threshold, the LTC3226 automatically
enters a backup state in which the supercapacitors power
the output through the LDO. The input supply power-fail
voltage level is programmed by an external resistor divider.
APPLICATIONS
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Smart Power Meters
Battery-Powered Industrial/Medical Equipment
3.3V Solid-State Drives
Industrial Alarms
Data Backup Supplies
Battery Hold-Up Supplies
Low input noise, low quiescent current and a compact
footprint make the LTC3226 ideally suited for small, batterypowered applications. Internal current limit and thermal
shutdown circuitry allow the device to survive a continuous short-circuit from the PROG or CPO pins to ground.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
3.3V Backup Supply
MPEXT
VIN
LDO
2.2μF
1.96M
GATE
6
VOUT
255k
LDO_FB
RST_FB
1.2V
PFI
+
–
+
1.21M
C
2.2μF
PROG
33.2k
VMID
CSC
1.2F
CHARGE
PUMP
GND
4
VOUT
3
VIN
2
BACKUP
BACKUP MODE
MODE
(LDO IN
(LDO IN
REGULATION) DROPOUT)
0
–1
1.21M
CSC = 1.2F
COUT = 47μF
ILOAD = 2A
CPO
1
3.83M
CPO_FB
EN_CHG
PFO
RST
CAPGOOD
5V
CPO
VIN
C–
80.6k
5
COUT
47μF
VOLTAGE (V)
LTC3226
VIN
3.3V
Automatic Normal-to-Backup
Mode Switchover
TO LOAD
(2A)
PFO (2V/DIV)
0
0.4
0.8
1.2
TIME (SECONDS)
1.6
2.0
3226 TA01b
3226 TA01a
3226fa
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LTC3226
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN, VOUT, VMID, CPO, RST, PFO,
CAPGOOD, LDO_FB ..................................... –0.3V to 6V
EN_CHG, PFI, RST_FB,
CPO_FB Voltage ............–0.3V to Max (VIN, CPO) + 0.3V
Operating Junction Temperature Range
(Note 3) ...................................................... –40 to 125°C
Storage Temperature Range ......................–65 to 150°C
VIN
VMID
C+
CPO
TOP VIEW
16 15 14 13
12 C–
VOUT 1
PFO 2
11 CAPGOOD
17
GND
PFI 3
10 CPO_FB
LDO_FB 4
8
RST
GATE
7
EN_CHG
6
RST_FB
9
5
PROG
UD PACKAGE
16-LEAD (3mm w 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 58.7°C/W (NOTE 2)
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3226EUD#PBF
LTC3226EUD#TRPBF
LFZV
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LTC3226IUD#PBF
LTC3226IUD#TRPBF
LFZV
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3226fa
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LTC3226
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). VIN = 3.3V, VCPO = 5V, VOUT = 3.3V, VMID = 1/2 VCPO
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Supply Range
IVIN(ST)
VIN Quiescent Current in Normal Mode
VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO
10
μA
ICPO(ST)
CPO Quiescent Current in Normal Mode
VPFI > 1.2V, VCPO_FB > 1.2V, VIN < VCPO
20
μA
IVOUT(ST)
VOUT Quiescent Current in Normal Mode
VOUT = VIN, VPFI > 1.2V, VCPO_FB > 1.2V,
VIN < VCPO
5
μA
ICPO(BU)
CPO Quiescent Current in Backup Mode
VPFI < 1.2V, VLDO_FB > 0.8V, VCPO > VOUT
24
μA
IVOUT(BU)
VOUT Quiescent Current in Backup Mode
VIN = 0V, VPFI < 1.2V, VLDO_FB > 0.8V,
VCPO > VOUT
3
μA
l
TYP
2.5
MAX
5.5
UNITS
V
Ideal Diode Controller
VFWD(EDA)
VRTO
External Ideal Diode Forward Voltage (VIN-VOUT) IVOUT = 2mA
Fast Turn-Off Voltage (VIN-VOUT)
VIN Falling
15
mV
–45
mV
Fast Turn-On Voltage (VIN-VOUT)
45
mV
VOUT Falling
Charge Pump Supercapacitor Charger
VCPO_FB
l
CPO_FB Pin Threshold for Entering Sleep Mode
1.18
CPO_FB Pin Hysteresis for Exiting Sleep Mode
1.21
1.24
20
VCPO_FB = 1.3V
l
–50
V
mV
ICPO_FB
Charge Pump FB Pin Input Leakage
fOSC
CLK Frequency
ROL
Effective Open-Loop Output Impedance (Note 4) VCPO = 4.5V, CFLY = 1μF
VPROG
PROG Pin Servo Voltage
VCPO_FB < 1.2V
IVIN(ILIM)
Input Current Limit
RPROG = 33.3k, VCPO = 0V
360
mA
hPROG
Ratio of VIN Input Current Limit to PROG Pin
Current
RPROG = 33.3k, VCPO = 0V
10,500
A/A
ICHRG(1x)
CPO Pin Charging Current (1x Mode)
VIN = 3.8V, RPROG = 33.3k, VCPO = 3V
315
mA
ICHRG(2x)
CPO Pin Charging Current (2x Mode)
RPROG = 33.3k
ISC
Short-Circuit Charge Current
PROG Pin Grounded, VCPO = 0V
VMODE
0.75
50
0.9
1.05
6
l
0.98
1.0
nA
MHz
Ω
1.02
V
157.5
mA
600
mA
VIN to CPO Voltage Differential for Switching
Mode from 1x to 2x
200
mV
1x/2x Mode Comparator Hysteresis
120
mV
VCLAMP
Maximum Voltage Across Either Supercapacitor
After Charging
l
2.65
2.75
V
VSTACK
Maximum Supercapacitor Stack Voltage
l
5.3
5.5
V
VMID
VMID Output Voltage
VMID Current Sourcing Capability
VMID < VCPO/2, VCPO_FB > 1.24V
VMID Current Sinking Capability
VMID > VCPO/2, VCPO_FB > 1.24V
CPO_FB Pin Hysteresis for CAPGOOD
CAPGOOD Output Low Voltage
ISINK = 5mA
CAPGOOD High Impedance Leakage Current
VCAPGOOD = 5V
V
4.5
mA
5.5
l
CPO_FB Pin Threshold Voltage (Rising) for
CAPGOOD
2.5
l
1.09
1.11
mA
1.13
V
20
mV
65
mV
1
μA
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LTC3226
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). VIN = 3.3V, VCPO = 5V, VOUT = 3.3V, VMID = 1/2 VCPO
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
0.82
V
LDO
Minimum CPO Voltage for LDO Operation
VLDO_FB
IVOUT = 1mA
Load Regulation ΔVLDO_FB/ΔIOUT
1mA < IVOUT < 2A
LDO FET RDS(ON)
VCPO = 3.6V
ILDO_FB(LEAK) LDO_FB Input Leakage Current
ILIM
2.4
l
LDO FB Servo Voltage
0.76
V
2.7
mV/A
200
VLDO_FB = 0.9V
l
LDO Current Limit
–60
mΩ
60
2
4
l
0.72
0.74
l
–50
nA
A
RST_FB, RST
VRST_FB(TH)
RST_FB Threshold (Falling Edge)
VRST_FB(HYS)
RST_FB Hysteresis
IRST_FB(LEAK)
RST_FB Input Leakage Current
VRST_FB = 0.9V
RST Output Low Voltage
ISINK = 5mA
RST High Impedance Leakage Current
VRST = 5V
0.76
20
mV
50
65
l
nA
mV
1
RST Delay (RST_FB Rising)
V
290
μA
ms
Power-Fail Comparator
VPFI(TH)
PFI Input Threshold (Falling Edge)
VPFI(HYS)
PFI input Hysteresis
IPFI(LEAK)
IPFO(LEAK)
l
1.175
1.2
1.225
20
PFI Input Leakage Current
VPFI = 0.5V
PFO Output Low Voltage
ISINK = 5mA
PFO High Impedance Leakage Current
VPFO = 5V
l
–50
mV
50
65
l
nA
mV
1
PFI Delay to PFO (PFI Falling)
V
0.5
μA
μs
EN_CHG
VIH
Input High Voltage
l
VIL
Input Low Voltage
l
IIH
Input High Current
l
IIL
Input Low Current
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much greater than
58.7°C/W.
Note 3: The LTC3226 is tested under pulsed load conditions such that TA ≈ TJ.
The LTC3226E is guaranteed to meet specifications from 0°C to 85°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
1.3
V
0.4
V
–1
1
μA
–1
1
μA
correlation with statistical process controls. The LTC3226I is guaranteed
over the full –40°C to 125°C operating junction temperature range. The
junction temperature, TJ, is calculated from the ambient temperature, TA,
and power dissipation, PD, according to the formula:
TJ = TA + (PD • 58.7°C/W)
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated thermal package thermal
resistance and the environmental factor.
Note 4: Output not in regulation; ROL = (2 • VIN – VCPO)/ICPO.
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LTC3226
TYPICAL PERFORMANCE CHARACTERISTICS
LDO Load Regulation
LDO Regulation Voltage
vs Temperature
LDO Supply Regulation
3.310
3.300
CPO = 4V
VOUT SET TO 3.3V
3.285
3.280
3.315
3.300
3.295
3.270
0.001
0.01
0.1
IOUT (A)
1
3.290
3226 G01
3.285
–45 –25
15 35 55 75
TEMPERATURE (°C)
LDO Output Transient Step
Response Waveform
980
VIN = 3.3V
960
T = 90°C
150
FREQUENCY (kHz)
T = 25°C
200
VOUT
50mV/DIV
AC-COUPLED
T = –40°C
100
1000mA
IOUT
50
4.2
3.7
3.2
CPO VOLTAGE (V)
2.7
940
T = 25°C
920
900
880
T = 90°C
840
3226 G05
500μs/DIV
5.2
4.7
T = –45°C
860
500mA
0
2.2
3.6
3.8
4.0 4.2 4.4
4.6
CPO VOLTAGE (V)
4.8
Charge Pump Input Current
vs CPO Output Voltage
RPROG = 33.3k
Charge Pump Charging Current
vs CPO Output Voltage
400
VIN = 3.8V
400
VIN = 3.8V
200
RPROG = 100k
150
100
50
1x MODE
0
1
2
3
CPO VOLTAGE (V)
300
200
RPROG = 100k
150
5
3226 G07
370
360
350
100
0
RPROG = 33.2k
VCPO = 0V
380
RPROG = 50k
250
50
2x MODE
4
390
IIN (mA)
RPROG = 50k
250
0
RPROG = 33.3k
Charge Pump Input Current
vs VIN with CPO Grounded
350
CPO CHARGE CURRENT (mA)
INPUT CURRENT LIMIT (mA)
350
300
5.0
3226 G06
3226 G04
400
115
Charge Pump Oscillator Frequency
vs VCPO and Temperature
LOAD = 500mA
250
95
3226 G03
300
RDS(ON) (mΩ)
–5
3226 G02
LDO FET On-Resistance
vs CPO Voltage and Temperature
350
3.305
3.295
3.280
3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2
CPO VOLTAGE (V)
10
3.310
3.300
3.290
3.285
3.275
VCPO = 5V
IOUT = 1mA
3.320
VOUT (V)
3.290
3.325
IOUT = 10μA
VOUT SET TO 3.3V
3.305
LDO OUTPUT VOLTAGE (V)
3.295
VOUT (V)
TA = 25°C, unless otherwise noted.
1x MODE
0
1
2
3
CPO VOLTAGE (V)
4
90°C
25°C
–45°C
340
2x MODE
5
3226 G08
330
3.3
3.6
3.9
4.2
VIN (V)
4.5
4.8
5.1
3226 G09
3226fa
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LTC3226
TYPICAL PERFORMANCE CHARACTERISTICS
Leakage Balancer Source and
Sink Capability
VMID Shunt Regulator Voltage
vs Current and Temperature
8
2.65
6
VMID VOLTAGE (V)
VMID
SOURCING
CURRENT
4
90°C
25°C
–45°C
2
0
–2
VMID
SINKING
CURRENT
–4
–6
0
0.5
1
1.5 2 2.5 3 3.5
VMID VOLTAGE (V)
4
5
ONLY LEAKAGE
BALANCER
ACTIVE
4
2.60
2.50
VIN = 3.3V
VCPO = 5V
5
1
10
100
VMID CURRENT (mA)
Charge Profile When Top
Capacitor = Bottom Capacitor
VOLTAGE (V)
VOLTAGE (V)
2
1
1000
–50
0
50
VIN – VOUT (mV)
100
3226 G12
VIN
3
VMID
2
VMID CLAMPED
2x
MODE (SHUNT ACTIVE)
1
1x
MODE
2x
MODE
–1
1x
MODE
0
RPROG = 33.2k
CSC = 1.2F
TIME (5 SECONDS/DIV)
–1
3226 G13
Charge Profile When Top
Capacitor < Bottom Capacitor
RPROG = 33.2k, CSC = 1.2F
EXTRA 1.5F BETWEEN CPO
AND VMID
3226 G14
TIME (5 SECONDS/DIV)
Normal-to-Back-Up Mode
Switching Transient Waveform
4
6
VOUT
5
CPO
VIN
3
VIN
3
VMID
2
1
1x
MODE
2x
MODE
TOP CAP
CLAMPED
RPROG = 33.2k,
CSC = 1.2F, EXTRA
1.5F BETWEEN
VMID AND GND
TIME (5 SECONDS/DIV)
3226 G15
VOLTAGE (V)
VOLTAGE (V)
–4
–5
–100
CPO
4
VIN
VMID
–1
–3
5
CPO
3
0
FAST
ON
6
5
4
FORWARD
VOLTAGE
Charge Profile When Top
Capacitor > Bottom Capacitor
6
0
0
–1
3226 G11
3226 G10
4
1
–2
90°C
25°C
–45°C
2.45
4.5
LINEAR
REGION
3
SHUNT
REGULATOR
ACTIVE
2.55
2.40
0.1
FAST
OFF
2
IGATE (μA)
VIN = 3.3V, VCPO = 5V
10 VMID SHUNT REG OFF
VMID CURRENT (mA)
Ideal Diode Gate Current
vs (VIN-VOUT)
2.70
12
–8
TA = 25°C, unless otherwise noted.
2
PFO
(1V/DIV)
1
CSC = 1.2F
COUT = 47μF
ILOAD = 2A
0
0
100
200
300
TIME (μs)
400
500
3226 G16
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LTC3226
PIN FUNCTIONS
VOUT (Pin 1): Voltage Output. This pin is used to provide
power to an external load from either the primary input
supply (VIN) or the supercapacitor (CPO) if the primary
input supply is not available. VOUT should be bypassed
with a low ESR ceramic capacitor of at least 47μF capacitance to GND.
PFO (Pin 2): Open-Drain Power-Fail Status Output. This
pin is pulled to ground by an internal N-channel MOSFET
when the PFI input is below 1.2V. Once the PFI input recovers, this pin becomes high impedance.
PFI (Pin 3): Power-Fail Input. High impedance input to
an accurate comparator with a 1.2V falling threshold and
20mV hysteresis. This pin controls the state of the PFO
output pin and the operating mode of the LTC3226.
LDO_FB (Pin 4): Internal LDO Feedback Pin. The voltage
on this pin is compared to the internal reference voltage
(0.8V) by the error amplifier to keep the output in regulation. An external resistor divider is required between VOUT,
LDO_FB and GND to program the LDO output voltage. See
the Applications Information section.
GATE (Pin 5): External FET Gate Pin. This pin is driven
by an internal ideal diode controller to regulate VOUT to
15mV below VIN.
RST_FB (Pin 6): Reset Comparator Input. High impedance input to an accurate comparator with a 0.74V falling
threshold and 20mV hysteresis. This pin controls the
state of the RST output pin. An external resistor divider
is required between VOUT, RST_FB and GND. It can be
the same resistor divider as the LDO_FB divider. See the
Applications Information section.
RST (Pin 7): Open-Drain Status Output of the RESET
Comparator. This pin is pulled to ground by an internal
N-channel MOSFET whenever the RST_FB pin voltage falls
below 0.74V. Once the RST_FB pin voltage recovers, the
pin becomes high impedance after a 290ms delay indicating that VOUT is within 7.5% of its programmed value.
EN_CHG (Pin 8): Enable Pin for the Charge Pump Supercapacitor Charger with an Internal Pull-Up. Tie this pin to
a voltage below 0.4V to disable the internal charge pump.
PROG (Pin 9): Charger Input Current Limit Programming
Pin. A resistor connected between this pin and GND sets
the input current limit for the charger. See the Applications
Information section.
CPO_FB (Pin 10): Feedback Pin for the Charge Pump. The
voltage on this pin is compared to the internal reference
voltage (1.2V) to keep the charge pump output CPO in
regulation. An external resistor divider is required between
CPO, CPO_FB and GND to program the CPO output voltage. See the Applications Information section.
CAPGOOD (Pin 11): Open-Drain Status Output of the
CPO Voltage. This pin is pulled to ground by an internal
N-channel MOSFET until CPO_FB pin reaches 1.11V. Once
the CPO_FB pin exceeds 1.11V, this pin becomes high
impedance indicating that the CPO voltage is within 7.5%
of its target value.
C– (Pin 12): Internal Charge Pump Flying Capacitor
Negative Terminal.
VIN (Pin 13): Primary Input Supply. This pin supplies power
to the VOUT pin through an external P-channel MOSFET
and also to the supercapacitors attached to the CPO and
VMID pins. VIN should be bypassed to GND with a low
ESR ceramic capacitor of at least 2.2μF depending on the
load transient.
VMID (Pin 14): Midpoint of Two Series Supercapacitors.
C+ (Pin 15): Internal Charge Pump Flying Capacitor Positive
Terminal. A 1μF to 10μF X5R or X7R ceramic capacitor
should be connected from C+ to C–.
CPO (Pin 16): Backup Supply Pin. Connect CPO to the top
plate of the top supercapacitor. This pin receives power
from VIN through an internal charge pump doubler and
supplies power to VOUT through an internal LDO when the
primary input supply has failed.
GND (Exposed Pad Pin 17): Ground. The exposed pad
should be connected to a continuous ground plane on
the second layer of the printed circuit board by several
vias directly under the part to achieve optimal thermal
performance.
3226fa
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LTC3226
BLOCK DIAGRAM
EXTERNAL PFET
5
GATE
VIN
2.5V TO 5.5V
13
2
PFI
RPF2
1.2V
– +
+–
VOUT
COUT
IDEAL DIODE
CONTROLLER
PFO
RPF1
3
15mV
VIN
–
LDO_FB
LDO
+
–
+
–
RST_FB
4
RFB1
6
RFB2
0.8V
+
0.74V
RST
7
DELAY
CPO
8
EN_CHG
VMID
1x/2x MODE
CHARGE PUMP
CPO_FB
+
–
9
–
2.65V CLAMP/
BALANCER
1V
1.11V
16
14
10
CSC
RCP1
RCP2
CAPGOOD
11
+
PROG
RPROG
GND
17
C+
15
C–
12
3226 F01
2.2μF
Figure 1. LTC3226 Block Diagram
3226fa
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LTC3226
OPERATION
The LTC3226 is a 2-cell series supercapacitor charger
designed to back up a Li-ion battery or any system rail
in the range of 2.5V to 5.3V. It has four principal circuit
components: a dual mode (1x/2x) charge pump with an
integrated balancer and a voltage clamp, an LDO to supply
the load current from the charge stored on the supercapacitor, an ideal diode controller to control the gate of the
external FET between VIN and VOUT, and a PFI comparator
to decide whether to activate the charge pump to charge the
supercapacitor stack or to activate the LDO to supply the
load when VIN falls below an externally programmed value.
The LTC3226 has two modes of operation: normal and
backup. If VIN is above an externally programmable PFI
threshold voltage, the part is in normal mode in which
power flows from VIN to VOUT through the external FET
and the internal charge pump stays on to top off the
supercapacitor stack. If VIN is below this PFI threshold,
the part is in backup mode. In this mode, the internal
charge pump is turned off, the external FET is turned off
and the LDO is turned on to supply the load current from
the stored charge.
CHARGE PUMP
One of the principal circuit components of the LTC3226
is a dual mode low noise constant frequency (0.9MHz)
regulated charge pump which transfers charge from VIN
and stores it onto the supercapacitor stack at the CPO pin.
The target or termination voltage on the CPO pin is programmed by an external resistor divider using the CPO_FB
pin. The input current limit to the charger is programmed
by an external resistor between the PROG pin and ground.
The charge pump turns on when VIN exceeds the externally
programmable PFI threshold. At the beginning of the charge
cycle when the CPO pin voltage is less than VIN, the charge
pump is in 1x mode (linear mode) in which the charge pump
acts as a pass element and charges the supercapacitor with
a charge current that is limited by the programmed input
current limit. As the CPO voltage rises to within 200mV of
the input supply voltage, the charge pump switches to 2x
mode (doubler mode) in which the average charge current
is approximately equal to half the input current limit. As the
CPO voltage exceeds the target value by approximately 1%,
the charge pump switches turn off and the charge pump
enters the sleep mode. In sleep mode, most of the charge
pump control circuitry is turned off to minimize quiescent
current. As the supercapacitor discharges due to leakage
and internal quiescent current load, the CPO pin voltage
slowly drops. When the CPO pin voltage drops 1% below
the programmed voltage, the charge pump turns on to
replenish charge on the supercapacitor and the cycle continues. The charge pump can be turned off by pulling the
EN_CHG pin below 0.4V. However, by default, the charge
pump is always enabled via an internal low current pull-up
circuit if the EN_CHG pin is left floating.
Voltage Clamp
The LTC3226 charge pump is equipped with circuitry to
limit the voltage across any supercapacitor in the stack
to a maximum allowable preset voltage of 2.65V. If the
voltage across the top capacitor (VMID-VCPO) ever gets
to 2.65V before the CPO pin reaches the target voltage,
the charge pump stops charging the top of the stack via
the CPO pin, switches to 1x mode and delivers charge
directly to the bottom capacitor via the VMID pin until the
stack voltage reaches its programmed value. If the voltage
across the bottom capacitor reaches 2.65V before the
stack gets to its target value, the charge pump continues
to deliver charge to the top of the stack via the CPO pin
and a shunt regulator turns on to bleed charge off of the
bottom capacitor and prevents the VMID pin voltage from
rising any further. The shunt regulator is able to shunt the
maximum allowable charge current which is approximately
315mA (in 1x mode). In the event both capacitors exceed
2.65V, the charge pump enters sleep mode by turning off
most of its circuitry.
Leakage Balancer
The LTC3226 is equipped with an internal leakage balancing amplifier which servos the VMID pin voltage to exactly
half of the CPO pin voltage. However, it has limited source
(~4.5mA) and sink (~5.5mA) capability. It is designed to
handle slight mismatch of the supercapacitors due to
leakage currents; not to correct any gross mismatch due
to defects. The balancer is only active as long as the input
supply voltage is above the PFI threshold. The internal balancer eliminates the need for external balancing resistors.
3226fa
9
LTC3226
OPERATION
CAPGOOD Status Output
The LTC3226 charge pump includes a comparator to report the status of the supercapacitors via an open-drain
NMOS transistor on the CAPGOOD pin. This pin is pulled
to ground until the CPO pin voltage rises to within 7.5%
of the programmed value. Once the CPO pin is above this
threshold, the CAPGOOD pin goes high impedance.
PROG Pin Short-Circuit Protection
Typically the maximum current that the LTC3226 charge
pump can deliver is set by the PROG resistor. However, if
for any reason, the PROG pin gets shorted to GND, or the
user chooses a PROG resistor value which is far smaller
than recommended, the charge pump input current is
limited to an internally set value of approximately 600mA.
Also the maximum current that can be sourced from the
PROG pin is limited by an internal resistor to less than 1mA.
LOW DROPOUT REGULATOR (LDO)
Another principal circuit component of the LTC3226 is the
low dropout regulator (LDO) which transfers power from
the supercapacitor stack to VOUT through a pass element
with an RDS(ON) of approximately 200mΩ. This LDO has
a current limit internally set to 4A. In the event that the
input supply voltage falls below the PFI threshold, the PFI
comparator promptly turns on the LDO to supply the necessary load without letting the VOUT rail droop too much.
However, to prevent unrestricted current flow from the
input to the supercapacitors through the ideal diode, the
LDO is turned off until the CPO voltage is greater than VIN
by 100mV typical. The LDO output voltage is programmed
through an external resistor divider via the LDO_FB pin.
threshold voltage. In backup mode, the charge pump
shuts off and the LDO powers the load as long as there
is enough charge stored on the supercapacitors. The PFI
threshold voltage is programmed by an external resistor
divider via the PFI pin. The output of the PFI comparator
also drives the gate of an open-drain NMOS to report the
status via the PFO pin. In normal mode, the PFO pin is
high Impedance but in backup mode, the pin is pulled
down to ground.
IDEAL DIODE CONTROLLER
The LTC3226 contains an ideal diode controller which
controls the gate of an external PFET connected between
the input, VIN, and the output, VOUT, through the GATE
pin. Under normal operating conditions, this external FET
constitutes the main power path from input to output. For
very light loads, the controller maintains a 15mV delta
across the FET between the input and output voltage. In
the event VIN suddenly drops below VOUT, the controller
quickly turns the FET completely off to prevent any reverse
conduction from VOUT back to the input supply.
RESET COMPARATOR
The LTC3226 contains a RESET comparator which monitors VOUT under all operating modes via the RST_FB pin
and reports the status via an open-drain NMOS transistor on the RST pin. At any time, if VOUT falls 7.5% from
its programmed value, it pulls the RST pin low almost
instantaneously. However, on the rising edge the comparator waits 290ms after VOUT crosses the threshold before
making the RST pin high impedance.
GLOBAL THERMAL SHUTDOWN
POWER-FAIL (PFI) COMPARATOR
The LTC3226 contains a fast comparator which switches
the part from normal to backup mode in the event the
input voltage, VIN, falls below an externally programmed
The LTC3226 includes a global thermal shutdown which
shuts down the entire part in the event the die temperature
exceeds 152°C. It resumes normal operation once the
temperature drops by about 15°C to approximately 137°C.
3226fa
10
LTC3226
APPLICATIONS INFORMATION
Programming the Supercapacitor
Termination Voltage (CPO)
Programming the Input Voltage Threshold for the
Power-Fail Comparator
The termination voltage of the supercapacitor stack on
the CPO pin can be programmed for any voltage between
2.5V to 5.3V by using a resistor divider from the CPO pin
to GND via the CPO_FB pin such that:
The input voltage threshold below which the power-fail
status pin PFO indicates a power-fail condition and the
LTC3226 switches the internal LDO on can be programmed
by using a resistor divider from the VIN pin to GND via the
PFI pin such that:
⎛ R ⎞
VCPO = VCPO _ FB • ⎜ 1+ CP1 ⎟
⎝ RCP2 ⎠
⎛ R ⎞
VIN(PFO _ HI_ LO) = VPFI • ⎜ 1+ PF1 ⎟
⎝ RPF2 ⎠
where VCPO_FB is 1.2V. See the block diagram in Figure 1.
Typical values for RCP1 and RCP2 are in the range of 40k
to 5M.
Programming the Input Current Limit for the Charger
The input current limit for the LTC3226 charge pump is
programmed by using a single resistor from the PROG
pin to ground. The input current limit is typically 10,500
times the current out of the PROG pin. The PROG pin
voltage always servos to 1V as long as the part is not in
sleep mode. The program resistor and the input current
limit are calculated using the following equations:
RPROG = 10,500 •
1V
IVIN(ILIM)
, IVIN(ILIM) = 10,500 •
1V
RPROG
where IVIN(ILIM) is the input current limit for the charge
pump charger. The maximum allowable input current limit
of 315mA can be achieved by using a PROG resistor of
33.2k. To maximize the charge transfer rate, the charge
pump operates in 1x mode when the supercapacitor voltage
is less than the input voltage and the charge current out of
CPO pin is only limited by the programmed input current
limit. However, in 2x mode, the average charge current is
approximately half the input current limit.
where VPFI is 1.2V. See Figure 1. Typical values for RPF1
and RPF2 are in the range of 40k to 5M. For a smooth
transition from normal to back-up mode, the PFI threshold
should be set 50mV to 100mV above the programmed
LDO output voltage, VOUT.
The input voltage above which the power-fail status pin
PFO is high impedance and the supercapacitor charger
and the ideal diode are enabled is:
⎛ R ⎞
VIN(PFO _ LO _ HI) = VPFI + VPFI(HYS) • ⎜ 1+ PF1 ⎟
⎝ RPF2 ⎠
(
)
where VPFI(HYS) is the hysteresis of the PFI comparator. It
is internally set to a typical value of 20mV.
The hysteresis can be increased externally by adding a
resistor, RH, in series with a diode, D1, between the PFO and
PFI pins as shown in Figure 2. This network will increase
the low-to-high VIN threshold for PFO while keeping the
high-to-low threshold intact. The increase in hysteresis
at the input can be calculated as shown:
(
)
ΔVIN(HYS) = VPFI + VPFI(HYS) – VF •
RPF1
RH
3226fa
11
LTC3226
APPLICATIONS INFORMATION
where VF is the forward voltage of the diode. As an example, if RPF1 = 200k, RPF2 = 120k, RH = 2M, and VF =
0.4V, the additional hysteresis provided by this network
can be calculated using the above equation as follows:
ΔVIN(HYS) = (1.2 + 0.02 – 0.4) V •
VOUT
VIN
RPF1
RH
470k
LTC3226
PFO
PFI
RPF2
200kΩ
= 82mV
2MΩ
D1
3226 F02
Figure 2. Increasing PFI Comparator Hysteresis Externally
Programming the LDO Output Voltage (VOUT)
The LDO output voltage in backup mode can be programmed for any voltage between 2.5V to 5.3V by using a
resistor divider from the VOUT pin to GND via the LDO_FB
pin such that:
⎛ R ⎞
VOUT = VLDO _ FB • ⎜ 1+ FB1 ⎟
⎝ RFB2 ⎠
where VLDO_FB is 0.8V. See the Block Diagram in Figure 1.
Typical values for RFB1 and RFB2 are in the range of 40k to
500k. Too small a resistor will result in a large quiescent
current whereas too large a resistor coupled with LDO_FB
pin capacitance will create an additional pole and may
cause loop instability.
Programming the Reset Threshold
The threshold for the reset comparator can be programmed
by using a resistor divider from the VOUT pin to GND via
the RST_FB pin such that:
⎛ R ⎞
VOUT = VRST _ FB • ⎜ 1+ FB1 ⎟
⎝ RFB2 ⎠
where VRST_FB is 0.74V. See Figure 1. Typical values for
RFB1 and RFB3 are in the range of 40k to 5M. In most applications, the LDO_FB and RST_FB pins can be shorted
together and only one resistor divider between VOUT and
GND is needed to set VOUT and the reset threshold 7.5%
below the VOUT programmed voltage. However, the reset
threshold can be set independent of VOUT by an additional
resistor divider.
Effective Open-Loop Output Resistance (ROL) of the
Charge Pump
The effective open-loop output resistance (ROL) of a charge
pump determines the strength of a charge pump. The value
of this parameter depends on many factors such as the
oscillator frequency (fOSC), value of the flying capacitor
(CFLY), the nonoverlap time, the internal switch resistances
(RS), and the ESR of the external capacitors. A first order
approximation of ROL is given below:
ROL ≅ 2 Σ RS +
S=1to 4
1
fOSC • CFLY
For the LTC3226 charge pump, the sum of the switch
resistances is approximately 2.5Ω in a typical application where VIN = 3.3V and VCPO = 5V. For CFLY = 1μF and
fOSC = 1MHz, the effective open-loop output resistance
of the charge pump can be approximated from the above
equation as follows:
ROL ≅ 2 • 2.5Ω +
1
= 6Ω
1MHz • 1µF
Maximum Available Charge Current
In the absence of any internal current limit, the maximum
available current out of a charge pump in 2x mode can be
calculated from the charge pump input and output voltage
and the effective open-loop output resistance ROL using
the following equation:
ICHRG =
2VIN – VCPO
ROL
For example, if the LTC3226 charge pump (ROL ≅ 6Ω)
has to charge a supercapacitor to 5V from 2.5V input,
the charge current available when VCPO = 4.8V can be
calculated as follows:
ICHRG =
2 • 2.5V – 4.8V
= 33.3mA
6Ω
3226fa
12
LTC3226
APPLICATIONS INFORMATION
So even if the charge pump input current limit is programmed for 315mA (RPROG = 33.2k), the actual charge
current will be considerably less than 157.5mA (half of
programmed limit) in 2x mode for very low input supply.
For VIN = 2.5V, the CPO voltage above which the charge
current will decrease from the programmed value of
157.5mA (RPROG = 33.2k) can be calculated from the
previous equation as follows:
VCPO = (2 • 2.5V – 157.5mA • 6Ω) = 4.055V
Choosing the LDO Output Capacitor
In the event VIN falls below the programmed PFI threshold,
the PFI comparator turns off the charge pump and turns
on the internal LDO to supply the load from the backedup supercapacitor storage. However, due to the delay
associated with the PFI comparator and LDO circuitry, it
could be up to 2μs before the LDO is capable of supplying
the load demand at VOUT. In order to prevent VOUT from
drooping too much during this transition, a 47μF ceramic
capacitor is recommended at the VOUT terminal. For any
output capacitance, COUT, delay, Δt, and load current,
ILOAD, the drop in VOUT, ∆V, can be calculated using the
following equation:
ILOAD = COUT •
ΔV
Δt
For example, if VOUT can not tolerate more than 100mV
drop under a maximum load of 2A during this transition,
the minimum capacitance required at the LDO output can
be calculated using the above equation as follows:
2µs
COUT(MIN) = 2A •
= 40µF
100mV
Charging a Single Supercapacitor
The LTC3226 can also be used to charge a single supercapacitor by connecting two series-connected matched
ceramic capacitors with a minimum capacitance of 100μF
in parallel with the supercapacitor as shown in Figure 3.
Supercapacitor Manufacturers
Refer to the following table for supercapacitor manufacturers.
Table 1. Supercapacitor Manufacturers
CAP-XX
www.cap-xx.com
NESS CAP
www.nesscap.com
Maxwell
www.maxwell.com
Bussmann
www.cooperbussmann.com
AVX
www.avx.com
Illinois Capacitor
www.illinoiscapacitor.com
Tecate Group
www.tecategroup.com
CPO
LTC3226
C1
CSUP
VMID
C2
GND
3226 F03
Figure 3. Charging a Single Supercapacitor
Board Layout Considerations
Due to high switching frequency and high transient currents produced by the LTC3226 charge pump, careful
board layout is necessary for optimum performance. A true
ground plane and short connections to all of the external
capacitors will improve performance.
Also, to be able to deliver maximum load current from
the LDO under all conditions, it is critical that the exposed
metal pad on the backside of the QFN package has a good
thermal contact to the PC board ground plane. Lack of
proper thermal contact can cause the junction temperature
to exceed the threshold for thermal shutdown.
3226fa
13
LTC3226
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 p0.05
3.50 p 0.05
1.45 p 0.05
2.10 p 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 p 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
15
PIN 1
TOP MARK
(NOTE 6)
16
0.40 p 0.10
1
1.45 p 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
3226fa
14
LTC3226
REVISION HISTORY
REV
DATE
DESCRIPTION
A
5/12
Added Note 3 to operating junction temperature range
PAGE NUMBER
Modified basic default conditions for Electrical Characteristics
Modified test conditions for Note 3
2
3, 4
4
3226fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3226
TYPICAL APPLICATION
Li-Ion Backup Supply
TO LOAD
MPEXT
Li-Ion
+
VIN
C1
4.7μF
GATE
R1
2.21M
VOUT
CPO
PFI
R2
1.21M
5V
VMID
R6
1.21M
LTC3226
CFLY
2.2μF
H/L
C+
CPO_FB
C–
LDO_FB
RST_FB
PROG
GND
R3
255k
47μF
R4
80.6k
470k
470k
470k
RST
PFO
CAPGOOD
EN_CHG
RPROG
33.2k
CSC
1.2F
R4
3.83M
μP
CSC: CAP-XX HS230
MPEXT: VISHAY Si2333
3226 TA02
RELATED PARTS
PART
NUMBER
DESCRIPTION
COMMENTS
LTC3225/
LTC3225-1
150mA Supercapacitor Charger
Low Noise, Constant Frequency Charging of Two Series Supercapacitors. Automatic
Cell Balancing Prevents Capacitor Overvoltage During Charging. Programmable Charge
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LT3485
Photoflash Capacitor Chargers with Output
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Integrated IGBT Driver; Voltage Output Monitor; Uses Small Transformers: 5.8mm
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from 1.8V Up to 10V. No Output Voltage Divider Needed; No External Schottky Diode
Required. Charges Any Size Photoflash Capacitor; 10-Lead (3mm × 3mm) DFN Package
LTC3625/
LTC3625-1
1A High Efficiency 2-Cell Supercapacitor
Charger with Automatic Cell Balancing
High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors. Automatic
Cell Balancing Prevents Capacitor Overvoltage During Charging. Programmable
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to 5.5V, Selectable 2.4V/2.65V Regulation per Cell (LTC3625). Selectable 2V/2.25V
Regulation per Cell (LTC3625-1), Low No-Load Quiescent Current: 23μA.
12-lead 3mm × 4mm DFN Package
LT3750
Capacitor Charger Controller
Charges Any Size Capacitor; Easily Adjustable Output Voltage. Drives High Current
NMOS FETs; Primary-Side Sense—No Output Voltage Divider Necessary. Wide Input
Range: 3V to 24V; Drives Gate to VCC – 2V. 10-Lead MS Package
LT3751
High Voltage Capacitor Charger Controller with
Regulation
Charges Any Size Capacitor; Low Noise Output in Voltage Regulation Mode. Stable
Operation Under a No-Load Condition; Integrated 2A MOSFET Gate Driver with
Rail-to-Rail Operation for VCC ≤ 8V. Selectable 5.6V or 10.5V Internal Gate Drive Voltage
Clamp; User-Selectable Over/Undervoltage Detect. Easily Adjustable Output Voltage;
Primary or Secondary Side Output Voltage Sense. Wide Input VCC Voltage Range
(5V to 24V). 20-Pin QFN 4mm × 5mm and 20-Lead TSSOP Packages
LTC4425
Supercapacitor Charger with Current Limited
Ideal Diode
Constant-Current/Constant-Voltage Linear Charger for 2-cell Series Supercapacitor
Stack. VIN: Li-Ion/Polymer Battery, a USB Port, or a 2.7V to 5.5V Current-Limited
Supply. 2A Charge Current, Auto Cell Balancing, 20μA Quiescent Current, Shutdown
Current <2μA. Low Profile 12-Pin 3mm × 3mm DFN or a 12-Lead MSOP Package
3226fa
16 Linear Technology Corporation
LT 0512 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011