TI1 LME49810TB/NOPB Lme49810 200v audio power amplifier driver with baker clamp Datasheet

LME49810
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LME49810 200V Audio Power Amplifier Driver with Baker Clamp
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FEATURES
DESCRIPTION
•
•
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The LME49810 is a high fidelity audio power amplifier
driver designed for demanding consumer and proaudio applications. Amplifier output power may be
scaled by changing the supply voltage and number of
power transistors. The LME49810’s minimum output
current is 50mA. When using a discrete output stage
the LME49810 is capable of delivering in excess of
300 watts into a single-ended 8Ω load.
1
2
Very High Voltage Operation
Output Clamp Logic Output
Thermal Shutdown and Mute
Customizable External Compensation
Scalable Output Power
APPLICATIONS
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Guitar Amplifiers
Powered Studio Monitors
Powered Subwoofers
Pro Audio
Audio Video Receivers
High Voltage Industrial Applications
KEY SPECIFICATIONS
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Wide operating voltage range: ±20V to ±100V
Slew Rate: 50V/μs (Typ)
Output Drive Current: 60mA (Typ)
PSRR (f = DC): 110dB (Typ)
THD+N (f = 1kHz): 0.0007 (Typ)
Unique to the LME49810 is an internal Baker Clamp.
This clamp insures that the amplifier output does not
saturate when over driven. The resultant “soft
clipping” of high level audio signals suppresses
undesirable audio artifacts generated when
conventional solid state amplifiers are driven hard into
clipping.
The LME49810 includes thermal shutdown circuitry
that activates when the die temperature exceeds
150°C. The LME49810’s mute function, when
activated, mutes the input drive signal and forces the
amplifier output to a quiescent state.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LME49810
SNAS391C – MAY 2007 – REVISED APRIL 2013
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Typical Application
+ VCC
+
+ 5V
RM
33 k :
Mute
CS
0.1 PF
Osense
Mute
Control
+ VCC
Source
Audio Input CIN
10 PF
RIN
243 :
IN+
Q2
RB2
1.21 k:
+
RS
6.81 k :
RE1
0.25 :
QMULT
INCi
220 PF
Q1
BiasP
-
BiasM
Ri
243:
RP
200:
RB1
348:
RSB
2.2 k :
RE2
0.25 :
8:
Q4
Sink
Q3
Comp
CC
10 pF
Baker
Circuitry and
Clip Flag
RL
+ 5V
- VEE
Clpflag
GND
+
LED
RC
470 :
CS
0.1 PF
- VEE
RF
6.81 k :
Figure 1. LME49810 Audio Amplifier Schematic
Connection Diagram
15
+VCC
14
Source
13
Sink
12
BiasP
11
10
9
8
7
6
5
4
3
2
1
BiasM
-VEE
NC
Osense
NC
Comp
ININ+
GND
Mute
ClpFlag
Figure 2. 15-Pin PFM (Top View)
See NDN0015A Package
2
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PIN DESCRIPTIONS
Pin
Pin Name
Description
1
ClpFlag
2
Mute
Mute Control
3
GND
Device Ground
4
IN+
Non-Inverting Input
5
IN–
Inverting Input
6
Comp
External Compensation Connection
7
NC
No Connect, Pin electrically isolated
8
Osense
9
NC
10
–VEE
Negative Power Supply
11
BiasM
Negative External Bias Control
12
BiasP
Positive External Bias Control
13
Sink
Output Sink
14
Source
15
+VCC
Baker Clamp Clip Flag Output
Output Sense
No Connect, Pin electrically isolated
Output Source
Positive Power Supply
+VCC
ClpFlag
Mute
10k
Mute
Control
Baker
Clamp
GND
Source
BiasP
INGm
Amp
BiasM
IN+
Baker
Clamp
Reference
and
Protection
50k
12.5k
Sink
Gm
Amp
10k
Osense
Comp
-VEE
Figure 3. LME49810 Simplified Schematic
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
Supply Voltage |V+| + |V-|
200V
Differential Input Voltage
±6V
Common Mode Input Range
0.4VEE to 0.4VCC
Power Dissipation (4)
4W
(5)
1kV
ESD Susceptibility (6)
200V
ESD Susceptibility
Junction Temperature (TJMAX) (7)
Soldering Information
150°C
PFM Package (10 seconds)
260°C
Storage Temperature
–40°C to +150°C
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
θJA
73°C/W
θJC
4°C/W
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJC, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJC or the number given in Absolute Maximum Ratings,
whichever is lower. For the LME49810, TJMAX = 150°C and the typical θJC is 4°C/W.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF - 240pF discharged through all pins.
The maximum operating junction temperature is 150°C.
OPERATING RATINGS
TMIN ≤ TA ≤ TMAX
Temperature Range
−40°C ≤ TA ≤ +8 5°C
±20V ≤ VSUPPLY ≤ ±100V
Supply Voltage
ELECTRICAL CHARACTERISTICS VCC = +100V, VEE = –100V (1) (2)
The following specifications apply for IMUTE = 100μA, unless otherwise specified. Limits apply for TA = 25°C, CC = 10pF, and
AV = 29dB.
Symbol
Parameter
Conditions
LME49810
Typical (3)
Limits (4) (5)
Units
(Limits)
18
mA (max)
ICC
Quiescent Power Supply Current
VCM = 0V, VO = 0V, IO = 0A
11
IEE
Quiescent Power Supply Current
VCM = 0V, VO = 0V, IO = 0A
13
mA (max)
THD+N
Total Harmonic Distortion + Noise
No Load, BW = 30kHz, VOUT = 30VRMS,
f = 1kHz
0.0007
% (max)
AV
Open Loop Gain
f = DC
f = 1kHz, VIN = 1mVRMS
120
88
dB
dB
VOM
Output Voltage Swing
THD+N = 0.05%, f = 1kHz
67.5
V RMS
VNOISE
Output Noise
BW = 30kHz,
A-weighted
50
34
150
μV
μV (max)
IOUT
Output Current
Current from Source to Sink Pins
60
50
mA (min)
100
50
200
μA (min)
μA (max)
IMUTE
(1)
(2)
(3)
(4)
(5)
4
Current into Mute Pin
To activate the amplifier
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Data sheet min and max specification limits are specified by design, test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS VCC = +100V, VEE = –100V(1)(2) (continued)
The following specifications apply for IMUTE = 100μA, unless otherwise specified. Limits apply for TA = 25°C, CC = 10pF, and
AV = 29dB.
Symbol
Parameter
LME49810
Conditions
Typical (3)
Limits (4) (5)
Units
(Limits)
SR
Slew Rate
VIN = 1VP-P, f = 10kHz square Wave
50
VOS
Input Offset Voltage
VCM = 0V, IO= 0mA
1
3
mV (max)
V/μs(min)
IB
Input Bias Current
VCM = 0V, IO= 0mA
100
200
nA (max)
PSRR
Power Supply Rejection Ratio
f = DC, Input Referred
110
105
dB (min)
VCLIP
Baker Clamp Clipping Voltage
Clip Output
Source pin
Sink pin
97.2
–96.4
95.5
–95.5
V (max)
V (min)
VBC
Baker Clamp Flag Output Voltage
IFLAG = 4.7mA
0.4
VBA
Bias P&M Pin Open Voltage
BiasP - BiasM
10
V
IBIAS
Bias Adjust Function Current
2.8
mA
V
+VCC
+
+5V
TEST
SIGNAL
INPUT
CIN
220 PF
RM
33 k:
RIN
243:
CS1
0.1 PF
Mute
Mute
Control
Source
BiasP
IN+
+
R1
10:
RS
6.81 k:
GND
OUTPUT
IN-
Ci
220 PF
-
R2
10:
BiasM
Ri
243:
Sink
Comp
Baker
Circuitry and
Clip Flag
Osense
CC
10 pF
+5V
Clpflag
CS2
+ 0.1 PF
RC
1 k:
-VEE
RF
6.81 k:
Figure 4. LME49810 Test Circuit Schematic (DC Coupled)
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TYPICAL PERFORMANCE CHARACTERISTICS
Data taken with Bandwidth = 30kHz, AV = 29dB, CC = 10pF, and TA = 25°C except where specified.
THD+N vs Frequency
+VCC = –VEE = 20V, VO = 10V
10
10
1
1
0.1
BW=80 kHz
0.01
THD+N (%)
THD+N (%)
THD+N vs Frequency
+VCC = –VEE = 20V, VO = 5V
0.001
0.1
0.01
BW=80 kHz
0.001
BW=30 kHz
20
100
BW=30 kHz
10k 20k
1k
0.0001
10k 20k
1k
FREQUENCY (Hz)
Figure 6.
THD+N vs Frequency
+VCC = –VEE = 50V, VO = 14V
THD+N vs Frequency
+VCC = –VEE = 50V, VO = 20V
10
1
1
0.1
0.01
BW=80 kHz
0.1
0.01
BW=80 kHz
0.001
0.001
BW=30 kHz
20
100
10k 20k
1k
0.0001
BW=30 kHz
20
100
10k 20k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7.
Figure 8.
THD+N vs Frequency
+VCC = –VEE = 100V, VO = 14V
THD+N vs Frequency
+VCC = –VEE = 50V, VO = 30V
10
10
1
1
THD+N (%)
THD+N (%)
100
Figure 5.
10
0.0001
20
FREQUENCY (Hz)
THD+N (%)
THD+N (%)
0.0001
0.1
0.01
0.1
BW=80 kHz
0.01
BW=80 kHz
0.001
0.001
BW=30 kHz
0.0001
6
BW=30 kHz
20
100
1k
10k 20k
0.0001
20
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9.
Figure 10.
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10k 20k
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Data taken with Bandwidth = 30kHz, AV = 29dB, CC = 10pF, and TA = 25°C except where specified.
THD+N vs Output Voltage
+VCC = –VEE = 100V, f = 20Hz
10
10
1
1
THD+N (%)
THD+N (%)
THD+N vs Output Voltage
+VCC = – VEE = 50V, f = 20Hz
0.1
BW=80 kHz
0.01
0.001
0.1
BW=80 kHz
0.01
0.001
BW=30 kHz
BW=30 kHz
2
10
20
50
0.0001
100m
10
50 100
OUTPUT VOLTAGE (Vrms)
Figure 11.
Figure 12.
THD+N vs Output Voltage
+VCC = –VEE = 50V, f = 1kHz
THD+N vs Output Voltage
+VCC = – VEE = 100V, f = 1kHz
1
1
THD+N (%)
10
0.1
BW=80 kHz
0.01
1
0.1
BW=80 kHz
0.01
0.001
BW=30 kHz
0.0001
100m
1
OUTPUT VOLTAGE (Vrms)
10
0.001
THD+N (%)
1
BW=30 kHz
2
10
20
50
0.0001
100m
1
10
50 100
OUTPUT VOLTAGE (Vrms)
OUTPUT VOLTAGE (Vrms)
Figure 13.
Figure 14.
THD+N vs Output Voltage
+VCC = –VEE = 50V, f = 20kHz
THD+N vs Output Voltage
+VCC = –VEE = 100V, f = 20kHz
10
10
1
1
THD+N (%)
THD+N (%)
0.0001
100m
0.1
BW=80 kHz
0.01
0.001
0.1
BW=80 kHz
0.01
0.001
BW=30 kHz
0.0001
100m
1
BW=30 kHz
2
10
20
50
100m
1
10
OUTPUT VOLTAGE (Vrms)
OUTPUT VOLTAGE (Vrms)
Figure 15.
Figure 16.
50 100
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Data taken with Bandwidth = 30kHz, AV = 29dB, CC = 10pF, and TA = 25°C except where specified.
THD+N vs Output Voltage
+VCC = –VEE = 20V, f = 1kHz
10
10
1
1
THD+N (%)
THD+N (%)
THD+N vs Output Voltage
+VCC = –VEE = 20V, f = 20Hz
0.1
BW=80 kHz
0.01
0.001
1
BW=80 kHz
0.01
0.001
BW=30 kHz
0.0001
100m
0.1
2
10
20
BW=30 kHz
0.0001
100m
1
2
10
20
OUTPUT VOLTAGE (Vrms)
OUTPUT VOLTAGE (Vrms)
Figure 17.
Figure 18.
THD+N vs Output Voltage
+VCC = –VEE = 20V, f = 20kHz
Closed Loop Frequency Response
+VCC = –VEE = 50V, VIN = 1VRMS
10
3
2
1
THD+N (%)
1
GAIN (dB)
0.1
BW=80 kHz
0.01
0
-1
0.001
-2
BW=30 kHz
0.0001
100m
1
2
10
-3
20
20
100
10k
1k
200k
OUTPUT VOLTAGE (Vrms)
FREQUENCY (Hz)
Figure 19.
Figure 20.
Closed Loop Frequency Response
+VCC = –VEE = 100V, VIN = 1VRMS
PSRR vs Frequency
+VCC = –VEE = 100V,
No Filters, Input referred, VRIPPLE = 1VRMS on VCC pin
3
-60
2
-70
-80
PSRR (dB)
GAIN (dB)
1
0
-1
-100
-110
-2
-3
20
-90
-120
100
1k
10k
200k
-130
20
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21.
8
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Data taken with Bandwidth = 30kHz, AV = 29dB, CC = 10pF, and TA = 25°C except where specified.
PSRR vs Frequency
+VCC = –VEE = 100V,
No Filters, Input referred, VRIPPLE = 1VRMS on VEE pin
Mute Attenuation vs IMUTE
+VCC = –VEE = 100V
20
0
0
MUTE ATTENUATION (dB)
-20
PSRR (dB)
-40
-60
-80
-100
-20
-40
-60
fIN = 20 kHz
-80
-100
-120
-120
20
100
1k
10k
fIN = 1 kHz
-140
0.1
100k
10
1
FREQUENCY (Hz)
Figure 23.
Figure 24.
Output Voltage vs Supply Voltage
Slew Rate vs Compensation Capacitor
+VCC = –VEE = 100V, VIN = 1.2VP 10kHz squarewave
70
60
80
SLEW RATE (V/Ps)
OUTPUT VOTLAGE (VRMS)
100
THD+N = 10%
60
40
THD+N = 0.05%
20
50
40
30
20
10
0
0
0
20
40
60
80
100
0
30
40
50
60
Figure 26.
Supply Current vs Supply Voltage
Input Offset Voltage vs Supply Voltage
7
INPUT OFFSET VOLTAGE (mV)
24
20
16
8
20
Figure 25.
28
12
10
COMPENSATION CAPACITOR (pF)
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT (mA)
1k
100
IMUTE (PA)
IEE
ICC
4
6
5
4
3
2
1
0
20 30 40 50 60 70 80 90 100 110 120
0
20 30 40 50 60 70 80 90 100 110 120
SUPPLY VOTAGE (±V)
SUPPLY VOLTAGE (±V)
Figure 27.
Figure 28.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Data taken with Bandwidth = 30kHz, AV = 29dB, CC = 10pF, and TA = 25°C except where specified.
200
180
160
160
140
140
120
120
100
100
80
80
60
60
40
40
20
20
0
0
-20
10
100
1k
10k 100k 1M
120
100
80
CMRR (dB)
200
180
CMRR vs Frequency
+VCC = –VEE = 100V
PHASE MARGIN (o)
GAIN (dB)
Open Loop Gain and Phase Margin
+VCC = –VEE = 100V
60
40
20
-20
10M 100M
0
10
100
1k
10k
100k
Figure 29.
Figure 30.
Noise Floor
+VCC = –VEE = 50V, VIN = 0V
Noise Floor
+VCC = –VEE = 100V, VIN = 0V
1m
1m
500P
500P
200P
BW=30 kHz
100P
1M
FREQUENCY (Hz)
OUTPUT NOISE (VRMS)
OUTPUT NOISE (VRMS)
FREQUENCY (Hz)
50P
20P
200P
BW=30 kHz
100P
50P
20P
A-WEIGHTED
A-WEIGHTED
10P
10P
20
100
1k
20
10k 20k
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31.
Figure 32.
10k 20k
Baker Clamp Flag Output
+VCC = –VEE = 100V, VIN = 4VRMS, fIN = 20kHz
Ch1: Output, Ch2: CLPFLAG Output
Figure 33.
10
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APPLICATION INFORMATION
MUTE FUNCTION
The mute function of the LME49810 is controlled by the amount of current that flows into the MUTE pin.
LME49810 typically requires 50μA to 100μA of mute current flowing in order to be in “play” mode. This can be
done by connecting a reference voltage (VMUTE) to the MUTE pin through a resistor (RM). The following formula
can be used to calculate the mute current.
IMUTE = (VMUTE-0.7V) / (RM+10kΩ) (A)
(1)
The 10kΩ resistor value in Equation (1) is internal. Please refer to Figure 3, LME49810 Simplified Schematic, for
additional details. For example, if a 5V voltage is connected through a 33kΩ resistor to the MUTE pin, then the
mute current will be 100μA, according to Equation (1). Consequently, RM can be changed to suit any other
reference voltage requirement. The LME49810 will enter Mute mode if IMUTE is less than 1μA which can be
accomplished by shorting the MUTE pin to ground or by floating the MUTE pin. It is not recommended that more
than 200μA flow into the MUTE pin because damage to LME49810 may occur and device may not function
properly.
BAKER CLAMP AND CLAMP FLAG OUTPUT
The LME49810 features a Baker Clamp function with corresponding CLPFLAG output pin. The clamp function
keeps all transistors in linear operation when the output goes into clipping. In addition, when the output goes into
clipping, a logic low level appears at the CLPFLAG pin. The CLPFLGAG pin can be used to drive an LED or
some other visual display as shown by Figure 1. The value of logic low voltage varies and depends on IFLAG. For
example, if IFLAG is 4.7mA then a voltage (VBC) of 0.4V will appear at the CLPFLAG output pin. The smooth
response of the Baker Clamp and the corresponding CLPFLAG logic output is shown in the scope photo below:
+VCC = -VEE = 100V,
VIN = 4VRMS,
fIN = 1kHz,
RC = 1kΩ Ch1: Output,
Ch2: CLPFLAG Output
Figure 34.
The CLPFLAG pin can source up to 10mA, and since the CLPFLAG output is an open collector output as shown
by Figure 3, LME49810 Simplified Schematic, it should never be left to float under normal operation. If CLPFLAG
pin is not used, then it should be connected through a resistor to a reference voltage so that IFLAG is below
10mA. For example, a resistor of 1k can be used with a 5V reference voltage. This will give the IFLAG of 4.7mA. In
a typical LED setup, if +5V reference voltage is not available, the following circuit using a Zener diode can be
used to power the CLPFLAG pin from the higher supply voltage rails of the LME49810. The power dissipation
rating of RZ will need to be at-least ½W if using a 5V Zener Diode. Alternately, the following basic formula can be
used to find the proper power rating of RZ : PDZ = (VCC - VZ)2/RZ (W). This formula can also be used to meet the
design requirements of any other reference voltage that the user desires.
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50V-100V
RZ
RM
22 k:
470:
TO CLPFLAG PIN
IN4733
THERMAL PROTECTION
The LME49810 has a thermal protection scheme to prevent long-term thermal stress of the device. When the
temperature on the die exceeds 150°C, the LME49810 goes into thermal shutdown. The LME49810 starts
operating again when the die temperature drops to about 145°C, but if the temperature again begins to rise,
shutdown will occur again above 150°C. Therefore, the device is allowed to heat up to a relatively high
temperature if the fault condition is temporary, but a sustained fault will cause the device to cycle between the
thermal shutdown temperature limits of 150°C and 145°C. This greatly reduces the stress imposed on the IC by
thermal cycling, which in turn improves its reliability under sustained fault conditions. Since the die temperature is
directly dependent upon the heat sink used, the heat sink should be chosen so that thermal shutdown is not
activated during normal operation. Using the best heat sink possible within the cost and space constraints of the
system will improve the long-term reliability of any power semiconductor device, as discussed in the
DETERMINING THE CORRECT HEAT SINK section.
POWER DISSIPATION
When in “play” mode, the LME49810 draws a constant amount of current, regardless of the input signal
amplitude. Consequently, the power dissipation is constant for a given supply voltage and can be computed with
the equation PDMAX = ICC * (VCC – VEE). For a quick calculation of PDMAX, approximate the current to be 11mA
and multiply it by the total supply voltage (the current varies slightly from this value over the operating range).
DETERMINING THE CORRECT HEAT SINK
The choice of a heat sink for a high-power audio amplifier is made entirely to keep the die temperature at a level
such that the thermal protection circuitry is not activated under normal circumstances.
The thermal resistance from the die to the outside air, θJA (junction to ambient), is a combination of three thermal
resistances, θJC (junction to case), θCS (case to sink), and θSA (sink to ambient). The thermal resistance, θJC
(junction to case), of the LME49810 is 4°C/W. Using Thermalloy Thermacote thermal compound, the thermal
resistance, θCS (case to sink), is about 0.2°C/W. Since convection heat flow (power dissipation) is analogous to
current flow, thermal resistance is analogous to electrical resistance, and temperature drops are analogous to
voltage drops, the power dissipation out of the LME49810 is equal to the following:
PDMAX = (TJMAX−TAMB) / θJA
where
•
•
•
12
TJMAX = 150°C
TAMB is the system ambient temperature
θJA = θJC + θCS + θSA
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Once the maximum package power dissipation has been calculated using Equation (2), the maximum thermal
resistance, θSA, (heat sink to ambient) in °C/W for a heat sink can be calculated. This calculation is made using
Equation (3) which is derived by solving for θSA from Equation (2).
θSA = [(TJMAX−TAMB)−PDMAX(θJC +θCS)] / PDMAX
(3)
Again it must be noted that the value of θSA is dependent upon the system designer's amplifier requirements. If
the ambient temperature that the audio amplifier is to be working under is higher than 25°C, then the thermal
resistance for the heat sink, given all other things are equal, will need to be smaller.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components is required to meet the design targets of an application. The choice of
external component values that will affect gain and low frequency response are discussed below.
The overall gain of the amplifier is set by resistors RF and Ri for the non-inverting configuration shown in
Figure 1. The gain is found by Equation (4) below given Ri = RIN and RF = RS.
AV = RF / Ri (V/V)
(4)
For best Noise performance, lower values of resistors are used. A value of 243 is commonly used for Ri and
setting the value for RF for desired gain. For the LME49810 the gain should be set no lower than 10V/V. Gain
settings below 10V/V may experience instability.
The combination of Ri and Ci (see Figure 1) creates a high pass filter. The gain at low frequency and therefore
the response is determined by these components. The -3dB point can be determined from Equation (5) shown
below:
fi = 1 / (2πRiCi) (Hz)
(5)
If an input coupling capacitor (CIN) is used to block DC from the inputs as shown in Figure 1, there will be
another high pass filter created with the combination of CIN and RIN. The resulting -3dB frequency response due
to the combination of CIN and RIN can be found from Equation (6) shown below:
fIN = 1 / (2πRINCIN) (Hz)
(6)
For best audio performance, the input capacitor should not be used. Without the input capacitor, any DC bias
from the source will be transferred to the load. The feedback capacitor (Ci) is used to set the gain at DC to unity.
Because a large value is required for a low frequency -3dB point, the capacitor is an electrolytic type. An
additional small value, high quality film capacitor may be used in parallel with the feedback resistor to improve
high frequency sonic performance. If DC offset in the output stage is acceptable without the feedback capacitor,
it may be removed but DC gain will now be equal to AC gain.
COMPENSATION CAPACITOR
The compensation capacitor (CC) is one of the most critical external components in value, placement and type.
The capacitor should be placed close to the LME49810 and a silver mica type will give good performance. The
value of the capacitor will affect slew rate and stability. The highest slew rate is possible while also maintaining
stability through out the power and frequency range of operation results in the best audio performance. The value
shown in Figure 1 should be considered a starting value with optimization done on the bench and in listening
testing. Please refer to Slew Rate vs. CC Graph in TYPICAL PERFORMANCE CHARACTERISTICS for
determining the proper slew rate for your particular application.
SUPPLY BYPASSING
The LME49810 has excellent power supply rejection and does not require a regulated supply. However, to
eliminate possible oscillations all op amps and power op amps should have their supply leads bypassed with lowinductance capacitors having short leads and located close to the package terminals. Inadequate power supply
bypassing will manifest itself by a low frequency oscillation known as “motorboating” or by high frequency
instabilities. These instabilities can be eliminated through multiple bypassing utilizing a large electrolytic capacitor
(10μF or larger) which is used to absorb low frequency variations and a small ceramic capacitor (0.1μF) to
prevent any high frequency feedback through the power supply lines. If adequate bypassing is not provided the
current in the supply leads which is a rectified component of the load current may be fed back into internal
circuitry. This signal causes low distortion at high frequencies requiring that the supplies be bypassed at the
package terminals with an electrolytic capacitor of 470μF or more.
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LME49810
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OUTPUT STAGE USING BIPOLAR TRANSISTORS
With a properly designed output stage and supply voltage of ±100V, an output power up to 500W can be
generated at 0.05% THD+N into an 8Ω speaker load. With an output current of several amperes, the output
transistors need substantial base current drive because power transistors usually have quite low current
gain—typical hfe of 50 or so. To increase the current gain, audio amplifiers commonly use Darlington style
devices. Power transistors should be mounted together with the VBE multiplier transistor on the same heat sink to
avoid thermal run away. Please see the section BIASING TECHNIQUES AND AVOIDING THERMAL
RUNAWAY for additional information.
BIASING TECHNIQUES AND AVOIDING THERMAL RUNAWAY
A class AB amplifier has some amount of distortion called Crossover distortion. To effectively minimize the
crossover distortion from the output, a VBE multiplier may be used instead of two biasing diodes. The LME49810
has two dedicated pins (BIASM and BIASP) for Bias setup and provide a constant current source of about 2.8mA.
A VBE multiplier normally consists of a bipolar transistor (QMULT, see Figure 1) and two resistors (RB1 and RB2,
see Figure 1). A trim pot can also be added in series with RB1 for optional bias adjustment. A properly designed
output stage, combine with a VBE multiplier, can eliminate the trim pot and virtually eliminate crossover distortion.
The VCE voltage of QMULT (also called BIAS of the output stage) can be set by following formula:
VBIAS = VBE(1+RB2/RB1) (V)
(7)
When using a bipolar output stage with the LME49810 (as in Figure 1), the designer must beware of thermal
runaway. Thermal runaway is a result of the temperature dependence of VBE (an inherent property of the
transistor). As temperature increases, VBE decreases. In practice, current flowing through a bipolar transistor
heats up the transistor, which lowers the VBE. This in turn increases the current gain, and the cycle repeats. If the
system is not designed properly this positive feedback mechanism can destroy the bipolar transistors used in the
output stage. One of the recommended methods of preventing thermal runaway is to use the same heat sink on
the bipolar output stage transistor together with VBE multiplier transistor. When the VBE multiplier transistor is
mounted to the same heat sink as the bipolar output stage transistors, it temperature will track that of the output
transistors. Its VBE is dependent upon temperature as well, and so it will draw more current as the output
transistors heat up, reducing the bias voltage to compensate. This will limit the base current into the output
transistors, which counteracts thermal runaway. Another widely popular method of preventing thermal runaway is
to use low value emitter degeneration resistors (RE1 and RE2). As current increases, the voltage at the emitter
also increases, which decreases the voltage across the base and emitter. This mechanism helps to limit the
current and counteracts thermal runaway.
LAYOUT CONSIDERATION AND AVOIDING GROUND LOOPS
A proper layout is virtually essential for a high performance audio amplifier. It is very important to return the load
ground, supply grounds of output transistors, and the low level (feedback and input) grounds to the circuit board
common ground point through separate paths. When ground is routed in this fashion, it is called a star ground or
a single point ground. It is advisable to keep the supply decoupling capacitors of 0.1μF close as possible to
LME49810 to reduce the effects of PCB trace resistance and inductance. Following the general rules will
optimize the PCB layout and avoid ground loops problems:
a. Make use of symmetrical placement of components.
b. Make high current traces, such as output path traces, as wide as possible to accomodate output stage
current requirement.
c. To reduce the PCB trace resistance and inductance, same ground returns paths should be as short as
possible. If possible, make the output traces short and equal in length.
d. To reduce the PCB trace resistance and inductance, ground returns paths should be as short as possible.
e. If possible, star ground or a single point ground should be observed. Advanced planning before starting the
PCB can improve audio performance.
14
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LME49810
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SNAS391C – MAY 2007 – REVISED APRIL 2013
Demo Board Schematic
+VCC
+
+5V
TEST
SIGNAL
INPUT
CIN
220 PF
RM
33 k:
RIN
243:
Mute
Mute
Control
CS1
0.1 PF
Source
BiasP
J1
IN+
+
RS
6.81 k:
GND
R1
10:
RB
10:
J2
OUTPUT
INCi
220 PF
-
R2
10:
BiasM
Ri
243:
Sink
Comp
Osense
Baker
Circuitry
and Clip
Flag
Cc
10 pF
+5V
Clpflag
LED
+
Rc
470:
CS2
0.1 PF
-VEE
RF
6.81 k:
Figure 35. LME49810 Test Demo Board Schematic
Demonstration Board Layout
Figure 36. Silkscreen Layer
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15
LME49810
SNAS391C – MAY 2007 – REVISED APRIL 2013
www.ti.com
Figure 37. Top Layer
Figure 38. Bottom Layer
16
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LME49810
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SNAS391C – MAY 2007 – REVISED APRIL 2013
REVISION HISTORY
Rev
Date
Description
1.0
05/24/07
Initial WEB release.
1.01
05/29/07
Few text edits.
1.02
09/17/07
Edited curve 20216724.
C
04/05/13
Changed layout of National Data Sheet to TI format.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LME49810TB/NOPB
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
TO-OTHER
NDN
15
24
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-20 to 85
LME49810
TB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2015
Addendum-Page 2
MECHANICAL DATA
NDN0015A
TB15A (Rev A)
www.ti.com
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