STMicroelectronics M48Z128V-85PM1 5.0 v or 3.3 v, 1 mbit (128 kbit x 8) zeropowerâ® sram Datasheet

M48Z128
M48Z128Y, M48Z128V
5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■
Conventional SRAM operation; unlimited
WRITE cycles
■
10 years of data retention in the absence of
power
■
Battery internally isolated until power is first
applied
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages:
(VPFD = power-fail deselect voltage)
– M48Z128: VCC = 4.75 to 5.5 V
4.5 V ≤ VPFD ≤ 4.75 V
– M48Z128Y: VCC = 4.5 to 5.5 V
4.2 V ≤ VPFD ≤ 4.5 V
– M48Z128V: VCC = 3.0 to 3.6 V
2.8 V ≤ VPFD ≤ 3.0 V
(contact ST sales office for availability)
■
Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
July 2010
Doc ID 2426 Rev 5
32
1
PMDIP32 module (PM)
1/20
www.st.com
1
Contents
M48Z128, M48Z128Y, M48Z128V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 2426 Rev 5
3/20
List of figures
M48Z128, M48Z128Y, M48Z128V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
4/20
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
1
Description
Description
The M48Z128/Y/V ZEROPOWER® RAM is a 128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated batterybacked memory solution.
The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard
128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
module houses the M48Z128/Y/V silicon with a long-life lithium button cell in a single
package.
Figure 1.
Logic diagram
VCC
17
8
A0-A16
W
DQ0-DQ7
M48Z128
M48Z128Y
M48Z128V
E
G
VSS
Table 1.
AI01194
Signal names
A0-A16
DQ0-DQ7
Address inputs
Data inputs / outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
Doc ID 2426 Rev 5
5/20
Description
M48Z128, M48Z128Y, M48Z128V
Figure 2.
DIP connections
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 3.
1
32
2
31
30
3
29
4
28
5
27
6
26
7
8 M48Z128 25
M48Z128Y
24
9
M48Z128V
23
10
22
11
21
12
20
13
14
19
15
18
17
16
VCC
A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01195
Block diagram
VCC
A0-A16
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
DQ0-DQ7
SRAM ARRAY
E
W
G
INTERNAL
BATTERY
VSS
6/20
Doc ID 2426 Rev 5
AI01196
M48Z128, M48Z128Y, M48Z128V
2
Operating modes
Operating modes
The M48Z128/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
Table 2.
Operating modes
Mode
VCC
E
G
W
DQ0-DQ7
Power
4.75 to 5.5 V
or
4.5 to 5.5 V
or
3.0 to 3.6 V
VIH
X
X
High Z
Standby
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery backup mode
Deselect
WRITE
READ
READ
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
1. See Table 10 on page 15 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
2.1
READ mode
The M48Z128/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
1,048,576 locations in the static storage array. Thus, the unique address specified by the 17
address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E and G (output enable) access times are
also satisfied. If the E and G access times are not met, valid data will be available after the
later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of
the eight three-state data I/O signals is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address
inputs are changed while E and G remain low, output data will remain valid for output data
hold time (tAXQX) but will go indeterminate until the next address access.
Doc ID 2426 Rev 5
7/20
Operating modes
M48Z128, M48Z128Y, M48Z128V
Figure 4.
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
A0-A16
VALID
tAXQX
tAVQV
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DATA OUT
DQ0-DQ7
AI01197
Note:
WRITE enable (W) = high.
Figure 5.
Address controlled, READ mode AC waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DATA VALID
DQ0-DQ7
AI01078
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.
Table 3.
READ mode AC characteristics
M48Z128/Y M48Z128/Y/V M48Z128/Y/V
Parameter(1)
Symbol
–70
Min
–85
Max
70
Min
–120
Max
85
Min
Unit
Max
tAVAV
READ cycle time
tAVQV
Address valid to output valid
70
85
120
ns
tELQV
Chip enable low to output valid
70
85
120
ns
tGLQV
Output enable low to output valid
35
120
45
ns
60
ns
tELQX(2) Chip enable low to output transition
5
5
5
ns
tGLQX(2) Output enable low to output transition
3
3
3
ns
tEHQZ(2)
tGHQZ(2)
tAXQX
Chip enable high to output Hi-Z
30
35
45
ns
Output enable high to output Hi-Z
20
25
35
ns
Address transition to output transition
5
5
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. CL = 5 pF.
8/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
2.2
Operating modes
WRITE mode
The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or
tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention;
although, if the output bus has been activated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
Figure 6.
WRITE enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A16
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01198
Note:
Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A16
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DATA INPUT
DQ0-DQ7
tDVEH
Note:
AI01199
Output enable (G) = high.
Doc ID 2426 Rev 5
9/20
Operating modes
Table 4.
Symbol
M48Z128, M48Z128Y, M48Z128V
WRITE mode AC characteristics
M48Z128/Y
M48Z128/Y/V
M48Z128/Y/V
–70
–85
–120
Parameter(1)
Min
Max
Min
Max
Min
Unit
Max
tAVAV
WRITE cycle time
70
85
120
ns
tAVWL
Address valid to WRITE enable Low
0
0
0
ns
tAVEL
Address valid to chip enable low
0
0
0
ns
tWLWH
WRITE enable pulse width
55
65
85
ns
tELEH
Chip enable low to chip enable high
55
75
100
ns
tWHAX
WRITE enable high to address transition
5
5
5
ns
tEHAX
Chip enable high to address transition
15
15
15
ns
tDVWH
Input valid to WRITE enable high
30
35
45
ns
tDVEH
Input valid to chip enable high
30
35
45
ns
tWHDX
WRITE enable high to input transition
0
0
0
ns
tEHDX
Chip enable high to input transition
10
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
10
25
10
30
ns
40
ns
tAVWH
Address valid to WRITE enable high
65
75
100
ns
tAVEH
Address valid to chip enable high
65
75
100
ns
WRITE enable high to output transition
5
5
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z128/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, write protection takes
place. When VCC drops below VSO, the control circuit switches power to the internal energy
source which preserves data.
The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is disconnected, and the power supply
is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
2.4
Operating modes
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 8.
Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
Doc ID 2426 Rev 5
11/20
Maximum ratings
3
M48Z128, M48Z128Y, M48Z128V
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
TA
Parameter
Ambient operating temperature
Value
Unit
0 to 70
°C
TSTG
Storage temperature (VCC off, oscillator off)
–40 to 85
°C
TBIAS
Temperature under bias
–10 to 70
°C
260
°C
–0.3 to 7
V
M48Z128/Y
–0.3 to 7.0
V
M48Z128V
–0.3 to 4.6
V
TSLD(1)
Lead solder temperature for 10 seconds
VIO
Input or output voltages
VCC
Supply voltage
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
Caution:
12/20
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
4
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC)
M48Z128/Y
M48Z128V
Unit
4.75 to 5.5 V or 4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load capacitance (CL)
Ambient operating temperature (TA)
100
50
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC measurement load circuit
650Ω
DEVICE
UNDER
TEST
1.75V
CL = 100pF
or 50pF(1)
CL includes JIG capacitance
AI03630
1. 50 pF for M48Z128V (3.3 V).
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input capacitance
-
10
pF
Input / output capacitance
-
10
pF
1. Effective capacitance measured with power supply at 5 V (M48Z128/Y) or 3.3 V (M48Z128V); sampled
only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 2426 Rev 5
13/20
DC and AC parameters
Table 8.
M48Z128, M48Z128Y, M48Z128V
DC characteristics
Sym
Parameter
Test condition(1)
M48Z128/Y
M48Z128V
–70 / –85 / –120
–85 / –120
Min
ILI
ILO(2)
Input leakage current
Output leakage current
Max
Min
Unit
Max
0 V ≤ VIN ≤ VCC
±1
±1
µA
0 V ≤ VOUT ≤ VCC
±1
±1
µA
E = VIL
Outputs open
105
50
mA
E = VIH
7
4
mA
E = VCC – 0.2 V
4
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input high voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
0.4
V
VOH
Output high voltage
IOH = –1 mA
0.4
2.4
2.2
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where
noted).
2. Outputs deselected.
14/20
Doc ID 2426 Rev 5
V
M48Z128, M48Z128Y, M48Z128V
DC and AC parameters
Figure 10. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tDR
tFB
tRB
tER
tWP
E
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
Table 9.
Power down/up AC characteristics
Parameter(1)
Symbol
tF(2)
tFB(3)
Min
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
Max
300
M48Z128/Y
10
M48Z128V
150
Unit
µs
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tWP
Write protect time
tER
E recovery time
M48Z128/Y
40
150
M48Z128V
40
250
40
120
µs
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR(3)
Expected data retention time
Min
Typ
Max
Unit
M48Z128
4.5
4.6
4.75
V
M48Z128Y
4.2
4.3
4.5
V
M48Z128V
2.8
2.9
3.0
V
M48Z128/Y
3.0
V
M48Z128V
2.5
V
10
YEARS
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
3. At 25 °C; VCC = 0 V.
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Package mechanical data
5
M48Z128, M48Z128Y, M48Z128V
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note:
Drawing is not to scale.
Table 11.
PMDIP32 – 32-pin plastic DIP module, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
9.27
A1
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
16/20
38.1
Typ
1.5
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
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M48Z128, M48Z128Y, M48Z128V
6
Part numbering
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
128Y
–70
PM
1
Device type
M48Z
Supply voltage and write protect voltage
128 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
128Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
128V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed
–70 = 70 ns (for M48Z128/Y)
–85 = 85 ns (for M48Z128/Y/V)
–120 = 120 ns (for M48Z128/Y/V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
Shipping method
blank = ECOPACK® package, tubes
1. Contact local ST sales office for availability
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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Environmental information
7
M48Z128, M48Z128Y, M48Z128V
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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M48Z128, M48Z128Y, M48Z128V
8
Revision history
Revision history
Table 13.
Revision history
Date
Revision
Changes
May-1999
1
First issue
Document layout changed; surface-mount chip set solution added
13-Apr-2000
2
20-Jun-2000
2.1
tGLQX changed (Table 3)
19-Jul-2000
2.2
M48Z128V added
14-Sep-2001
3
07-Nov-2001
3.1
Remove chipset option from ordering Information (Table 12)
20-May-2002
3.2
Modify reflow time and temperature footnotes (Table 5)
18-Nov-2002
3.3
Modifying SMT solution text (Figure 2, 4;Table 2)
17-Sep-2003
3.4
Remove references to M68ZXXX (obsolete) parts (Figure 4; Table 2);
update disclaimer
22-Feb-2005
4
Reformatted; IR reflow, SO package updates (Table 5)
5
Reformatted document; updated Features, Section 3: Maximum ratings,
Table 11, 12; added ECOPACK® text to Section 5; added Section 7:
Environmental information; removed SOH28, SNAPHAT® housing and
all references from datasheet.
20-Jul-2010
Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10)
Doc ID 2426 Rev 5
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M48Z128, M48Z128Y, M48Z128V
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