MTB75N05HD Preferred Device Power MOSFET 75 Amps, 50 Volts N−Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Short Heatsink Tab Manufactured − Not Sheared • Specially Designed Leadframe for Maximum Power Dissipation w http://onsemi.com 75 AMPERES 50 VOLTS RDS(on) = 9.5 mΩ N−Channel D G These devices are available in Pb−free package(s). Specifications herein apply to both standard and Pb−free devices. Please see our website at www.onsemi.com for specific Pb−free orderable part numbers, or contact your local ON Semiconductor sales office or representative. MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating S 4 D2PAK CASE 418B STYLE 2 2 1 Symbol Value Unit Drain−to−Source Voltage VDSS 50 Volts Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 50 Gate−to−Source Voltage − Continuous VGS ± 20 ID ID 75 65 225 Amps Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (minimum footprint, FR−4 board) PD 125 1.0 2.5 Watts W/°C Watts Operating and Storage Temperature Range TJ, Tstg − 55 to 150 °C EAS 500 mJ MTB75N05HD = Device Code Y = Year WW = Work Week RθJC RθJA RθJA 1.0 62.5 50 °C/W ORDERING INFORMATION Drain Current − Continuous Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 μs) Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 Ω) Thermal Resistance − Junction to Case − Junction to Ambient − Junction to Ambient (minimum footprint, FR−4 board) Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 s IDM TL 260 °C 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain MTB75N05HD YWW 1 Gate 2 Drain 3 Source Device Package Shipping MTB75N05HD D2PAK 50 Units/Rail MTB75N05HDT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 7 1 Publication Order Number: MTB75N05HD/D MTB75N05HD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 50 − − 54.9 − − Vdc mV/°C − − − − 10 100 − − 100 2.0 − − 6.3 4.0 − − 7.0 9.5 − − 0.63 − − 0.34 gFS 15 − − mhos pF OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0, ID = 250 μAdc) Temperature Coefficient (Positive) (Cpk ≥ 2) (Note 2) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) (VDS = 50 V, VGS = 0, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS μAdc nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) (Cpk ≥ 1.5) (Note 2) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 10 Vdc, ID = 20 Adc) (Cpk ≥ 3.0) (Note 2) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc) (Note 3) (ID = 75 A) (ID = 20 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) Vdc mV/°C mΩ Vdc DYNAMIC CHARACTERISTICS (Note 2) Input Capacitance Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Transfer Capacitance (Cpk ≥ 2.0) (Cpk ≥ 2.0) (Cpk ≥ 2.0) Ciss − 2600 3900 Coss − 1000 1300 Crss − 230 300 td(on) − 15 30 tr − 170 340 td(off) − 70 140 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 25 V, ID = 75 A, VGS = 10 V, RG = 9.1 Ω) Fall Time Gate Charge (VDS = 40 V, ID = 75 A, VGS = 10 V) ns tf − 100 200 QT − 71 100 Q1 − 13 − Q2 − 33 − Q3 − 26 − 0.97 0.80 0.68 − 1.00 − Vdc − − trr − 57 − ns ta − 40 − tb − 17 − QRR − 0.17 − − − 3.5 4.5 − − − 7.5 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 2) (IS = 75 A, VGS = 0) (Cpk ≥ 10) (IS = 20 A, VGS = 0) (IS = 20 A, VGS = 0, TJ = 125°C) Reverse Recovery Time (IS = 37.5 A, VGS = 0, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge VSD μC INTERNAL PACKAGE INDUCTANCE 1. 2. 3. 4. Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. Reflects Typical Values. Cpk = Absolute Value of (SPEC − AVG) / 3 * SIGMA). For accurate measurements, good Kelvin contact required. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH MTB75N05HD TYPICAL ELECTRICAL CHARACTERISTICS (Note 5) 160 160 TJ = 25°C 120 120 100 100 80 6V 60 40 5V 20 0 0.5 1 1.5 2 2.5 3 4 3.5 5 4.5 25°C 0 1 2 3 5 4 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.012 TJ = 100°C 0.01 0.008 25°C 0.006 −55 °C 0.004 20 40 60 80 100 120 140 0.009 7 8 140 160 TJ = 25°C 0.008 VGS = 10 V 0.007 15 V 0.006 0.005 0 20 40 60 80 100 120 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 10000 VGS = 10 V ID = 37.5 A VGS = 0 V 1.5 1000 TJ = 125°C 100 100°C I DSS, LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 100°C 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 0 60 0 0.014 0.002 80 20 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0 VDS ≥ 10 V 140 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 140 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 7V VGS = 10 V 1 10 0.5 25°C 0 −50 −25 0 25 50 75 100 125 150 0 0 5 10 15 20 25 30 35 40 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage 5. Pulse Tests: Pulse Width ≤ 250 μs, Duty Cycle ≤ 2%. http://onsemi.com 3 45 50 MTB75N05HD POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board−mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in a RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8000 VDS = 0 VGS = 0 TJ = 25°C C, CAPACITANCE (pF) 7000 6000 Ciss 5000 4000 3000 Ciss Crss Coss 2000 Crss 1000 0 10 5 0 VGS 5 10 15 20 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 25 12 60 QT 10 1000 8 100 6 Q2 30 TJ = 25°C ID = 75 A 4 20 t, TIME (ns) 40 Q1 TJ = 25°C ID = 75 A VDD = 35 V VGS = 10 V 50 VGS tf tr td(off) td(on) 10 10 2 0 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTB75N05HD VDS Q3 0 75 25 50 QG, TOTAL GATE CHARGE (nC) 0 1 1 10 RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 80 40 I S , SOURCE CURRENT (AMPS) I S , SOURCE CURRENT (AMPS) TJ = 25°C 70 VGS = 0 V 60 50 40 30 20 10 0 30 di/dt = 300 A/μs STANDARD CELL DENSITY trr HIGH CELL DENSITY trr tb ta 20 10 0 −10 −20 −30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 −40 −120 −100 −80 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) −40 −20 0 t, TIME (ns) Figure 10. Diode Forward Voltage versus Current Figure 11. Reverse Recovery Time (trr) http://onsemi.com 5 −60 20 40 60 80 MTB75N05HD SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 500 VGS = 20 V SINGLE PULSE TC = 25°C 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 10 μs 100 μs 10 1 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 ID = 75 A 450 400 350 300 250 200 150 100 50 0 25 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 12. Maximum Rated Forward Biased Safe Operating Area 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 175 Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature 1 D = 0.5 0.2 P(pk) 0.1 0.1 0.05 0.02 t1 t2 DUTY CYCLE, D = t1/t2 0.01 RθJC(t) = r(t) RθJC RθJC = 1.0°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) SINGLE PULSE 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 t, TIME (s) 1.0E−01 Figure 14. Thermal Response http://onsemi.com 6 1.0E+00 1.0E+01 MTB75N05HD PD, POWER DISSIPATION (WATTS) 3 RθJA = 50°C/W Board material = 0.065 mil FR−4 Mounted on the minimum recommended footprint Collector/Drain Pad Size ≈ 450 mils x 350 mils 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) Figure 15. D2PAK Power Derating Curve http://onsemi.com 7 150 MTB75N05HD PACKAGE DIMENSIONS D2PAK CASE 418B−03 ISSUE D C E −B− V 4 1 2 3 A S −T− SEATING PLANE K J G D 3 PL 0.13 (0.005) H M T B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 STYLE 2: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MTB75N05HD/D