TI1 BQ500101DPCR Nexfet power stage Datasheet

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bq500101
SLPS585 – MARCH 2016
bq500101 NexFET™ Power Stage
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
98% System Efficiency at 5 A
Max Rated Continuous Current 10 A, Peak 15 A
High-Frequency Operation (up to 600 kHz)
High-Density SON 3.5 × 4.5 mm Footprint
Ultra-Low Inductance Package
System Optimized PCB Footprint
3.3-V and 5-V PWM Signal Compatible
Input Voltages up to 24 V
Integrated Bootstrap Diode
Shoot-Through Protection
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
Optimized Power Stage Containing HighEfficiency Gate Drivers and FETs
Optimized for 15-W Wireless Power Transmitter
Designs
1
•
•
•
•
WPC (Qi) 1.2 Compliant Wireless Power
Transmitters for 15-W or 5-W Systems
Proprietary Wireless Chargers and Transmitters
Wirelessly Powered Industrial and Medical
Systems
For more information, see
www.ti.com/wirelesspower
3 Description
The bq500101 NexFET™ Power Stage is optimized
for wireless power applications covering the WPC
v1.2 medium power specification. The device can be
used for both the rail voltage control in fixed
frequency transmitter types as well as the coil drivers
for both fixed and variable frequency types. This
combination produces a high-current, high-efficiency,
and high-speed switching device in a small 3.5 × 4.5
mm outline package. In addition, the PCB footprint is
optimized to help reduce design time and simplify the
completion of the overall system design.
Device Information(1)
ORDER NUMBER
PACKAGE
BODY SIZE (NOM)
bq500101
DPC (9)
3.5 mm x 4.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
bq500101
(Voltage Regulation)
bq500100
(Current Sense
Monitor)
Efficiency (%)
19 V
bq501210
(Wireless Power
Transmitter Controller)
bq500101
bq500101
Typical Power Stage Efficiency and Power Loss
100
3.2
95
2.8
90
2.4
VDD = 5 V
85 VIN = 10 V
LSW = 6 PH
80 fSW = 130 kHz
TA = 25qC
75 Duty Cycle = 50%
2
1.6
1.2
70
0.8
65
0.4
Efficiency (%)
Power Loss (W)
0
8
10
60
0
2
4
6
VSW Current (A)
Power Loss (W)
spacer
Application Diagram
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLPS585 – MARCH 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
8.1 Application Information.............................................. 8
8.2 Typical Application ................................................... 8
8.3 System Example ..................................................... 11
9
9.1 Layout Guidelines ................................................... 13
9.2 Layout Example ...................................................... 13
9.3 Thermal Considerations .......................................... 14
10 Device and Documentation Support ................. 15
10.1 Trademarks ........................................................... 15
10.2 Electrostatic Discharge Caution ............................ 15
10.3 Glossary ................................................................ 15
11 Mechanical, Packaging, and Orderable
Information ........................................................... 16
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 7
8
Layout ................................................................... 13
11.1 Mechanical Drawing.............................................. 16
11.2 Recommended PCB Land Pattern........................ 17
11.3 Recommended Stencil Opening ........................... 17
Application and Implementation .......................... 8
4 Revision History
2
DATE
REVISION
NOTES
March 2016
*
Initial release.
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5 Pin Configuration and Functions
SON 3.5 × 4.5 mm
(Top View)
Pin Functions
PIN
NO.
DESCRIPTION
NAME
1
VDD
Supply voltage to gate drivers and internal circuitry.
2
VDD
Supply voltage to gate drivers and internal circuitry.
3
PGND
Power ground, needs to be connected to Pin 9 and PCB
4
VSW
Voltage switching node – pin connection to the inductor.
5
VIN
Input voltage pin. Connect input capacitors close to this pin.
6
BOOT_R
7
BOOT
Bootstrap capacitor CBOOT connections. Connect a minimum 0.1 µF 16 V X5R, ceramic cap CBOOT from BOOT to
BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is
integrated. Boot_R is internally connected to VSW.
8
PWM
Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET
gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates
low if greater than the tri-state shutdown hold-off time (t3HT)
9
PGND
Power ground
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6 Specifications
6.1 Absolute Maximum Ratings (1)
TA = 25°C (unless otherwise noted)
MIN
MAX
UNIT
VIN to PGND
–0.3
30
V
VSW to PGND , VIN to VSW
–0.3
30
V
–7
33
V
VDD to PGND
–0.3
6
V
PWM
–0.3
6
V
BOOT to PGND
–0.3
35
V
–2
38
V
–0.3
6
V
VSW to PGND, VIN to VSW (<10 ns)
BOOT to PGND (<10 ns)
BOOT to BOOT_R
BOOT to BOOT_R (duty cycle <0.2%)
8
V
PD
Power dissipation
8
W
TJ
Operating temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM)
(1)
UNIT
±2000
Charged device model (CDM) (2)
V
±500
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
VDD
Gate drive voltage
MIN
MAX
4.5
5.5
V
24
V
10
A
15
A
600
kHz
(1)
VIN
Input supply voltage
ISW
Continuous VSW current
ISW-PK
Peak VSW current (3)
ƒSW
Switching frequency
VIN = 10 V, VDD = 5 V, Duty cycle = 50%,
ƒSW = 130 kHz, LSW = 6 µH (2)
CBOOT = 0.1 µF (min)
On time duty cycle
(1)
(2)
(3)
UNIT
85%
Minimum PWM on time
40
Operating temperature
–40
ns
125
°C
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 2. Peak VSW Current is applied for tp = 10 ms, duty cycle ≤ 1%
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
RθJC
Junction-to-case (top of package) thermal resistance (1)
RθJB
Junction-to-board thermal resistance (2)
(1)
(2)
4
MIN
TYP
MAX
22.8
2.5
UNIT
°C/W
RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch
(1.52 mm) thick FR4 board.
RθJB value based on hottest board temperature within 1mm of the package.
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6.5 Electrical Characteristics
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power
loss (1)
VIN = 10 V, VDD = 5 V, ISW = 5 A, ƒSW = 130 kHz,
LSW = 6 µH , TJ = 25°C, Duty Cycle = 50%
0.53
W
Power
loss (1)
VIN = 10 V, VDD = 5 V, ISW = 5 A, ƒSW = 130 kHz,
LSW = 6 µH , TJ = 125°C, Duty Cycle = 50%
0.68
W
VIN
IQ
VIN quiescent current
PWM = Floating, VDD = 5 V, VIN= 24 V
IDD
Standby supply current
PWM = Float
IDD
Operating supply current
PWM = 50% Duty cycle, ƒSW = 130 kHz
1
µA
VDD
130
µA
2
mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD Rising
Power-on reset
VDD Falling
UVLO
4.15
3.7
Hysteresis
V
V
0.2
V
PWM I/O SPECIFICATIONS
Pull up to VDD
1700
RI
Input impedance
VIH
Logic level high
VIL
Logic level low
VIH
Hysteresis
VTS
Tri-state voltage
tTHOLD(off1)
Tri-state activation time
(falling) PWM
60
tTHOLD(off2)
Tri-state activation time (rising)
PWM
60
t3RD(PWM)
Tri-state exit time PWM
Pull down (to GND)
kΩ
800
2.65
0.6
0.2
1.3
V
2
ns
(1)
100
ns
240
mV
2
µA
BOOTSTRAP SWITCH
VFBST
Forward voltage
IF = 10 mA
IRLEAK
Reverse leakage (1)
VBOOT – VDD = 25 V
(1)
120
Specified by design
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7 Detailed Description
7.1 Overview
The bq500101 NexFET™ Power Stage is a highly optimized design for use in wireless power transmitter
designs. The bq500101 can also be used for synchronous buck applications.
7.2 Functional Block Diagram
VDD
VUVLO
DRVL
DRVH
Level Shift
+
+
7
BOOT
5
VIN
Control
FET
6 BOOT_R
+
+
1V
4
+
+
VDD
VSW
1 / 2 VDD
+
1V
1.7Meg
PWM
3-State
Logic
8
DRVL
Sync
FET
800k
PGND 3
6
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PGND
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7.3 Feature Description
7.3.1 Powering bq500101 And Gate Drivers
An external VDD voltage is required to supply the integrated gate driver device and provide the necessary gate
drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass VDD pin
to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap
supply to drive the Control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor CBOOT
between BOOT and BOOT_R pins. An optional RBOOT resistor in series with CBOOT can be used to slow down the
turn on speed of the Control FET and reduce voltage spikes on the VSW node. A typical 1 Ω to 4.7 Ω value is a
compromise between switching loss and VSW spike amplitude.
7.3.2 Undervoltage Lockout Protection (UVLO)
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control
FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H).,
Then the driver becomes operational and responds to PWM command. If VDD falls below the lower UVLO
threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the Control
FET and Sync FET gates actively low. Figure 1 shows this function.
VUVLO_H
VUVLO_L
VVDD
Driver On
UDG-12218
Figure 1. UVLO Operation
7.3.3 Integrated Boost-Switch
To maintain a BOOT-VSW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BOOT pin is replaced by a FET which is gated by the DRVL
signal.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The Power Stage bq500101 is a highly optimized design for wireless power transmitter applications using
NexFET devices with a 5-V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield
the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards
a more systems centric environment. The high-performance gate driver device integrated in the package helps
minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level
performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict
the product performance in the actual application.
8.2 Typical Application
V_SENSE
+19V
L1
4
C1
C2
1
2
VIN
VSW
VDD
BOOT
VDD
BOOT_R
C3
+5V
PGND
8
PWM
PAD
R7
5
R6
7
R8
R1
C6
6
C5
C4
3
R2
4
R4
9
1
R3
bq500101
2
R5
IN+
IN-
GND
V+
GND
OUT
5
3
C7
6
bq500100
I_SENSE
R9
+3.3V
C8
V33
C9
PWM_RAIL
C10
RAIL+
L1
4
RAIL1
DPWM-A
DPWM-A
V_SENSE
DPWM-B
DPWM-B
I_SENSE
V_SENSE
+5V
I_SENSE
2
VIN
VSW
VDD
BOOT
VDD
BOOT_R
C11
PGND
AGND / DGND
8
bq501210
PWM
PAD
5
C15
C12
7
7
C14
6
3
9
bq500101
DPWM-A
5
C13
6
3
9
VSW
VIN
BOOT
VDD
BOOT_R
VDD
4
+5V
1
2
C16
PGND
PAD
PWM
8
bq500101
DPWM-B
Figure 2. Application Schematic
8
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Typical Application (continued)
8.2.1 Application Curves
3
1.1
2.5
1
Power Loss, Normalized
2
1.5
1
0.5
0
2.5
4
VIN = 10 V
ƒSW = 130 kHz
5.5
7
Output Current (A)
VDD = 5 V
LSW = 6 µH
8.5
0.8
0.7
0.6
Typ
Max
1
0.9
0.5
-50
10
-25
VIN = 10 V
ƒSW = 130 kHz
Duty Cycle = 50%
Figure 3. Power Loss vs Output Current
10
Output Current (A)
10
Output Current (A)
12
8
6
4
D003
Duty Cycle = 50%
6
4
400 LFM
200 LFM
100 LFM
Nat. conv.
2
Min
Typ
0
0
10
VIN = 10 V
ƒSW = 130 kHz
20
30
40
50
60
Ambient Temperature (qC)
VDD = 5 V
LSW = 6 µH
70
80
90
0
20
40
60
80
100
Board Temperature (qC)
D004
VIN = 10 V
ƒSW = 130 kHz
Duty Cycle = 50%
Figure 5. Safe Operating Area – PCB Horizontal Mount
(1)
VDD = 5 V
LSW = 6 µH
120
140
D006
Duty Cycle = 50%
Figure 6. Typical Safe Operating Area
1.2
1.15
1.2
1.12
0.9
1.1
0.8
1.09
0.7
1.05
0.4
1.06
0.5
1
0.0
1.03
0.2
1
0.0
0.97
40
130
VIN = 10 V
ISW = 5 A
220
310
400
490
Switching Frequency (kHz)
VDD = 5 V
LSW = 6 µH
580
-0.2
670
Power Loss, Normalized
1.15
SOA Temperature Adj. (qC)
Power Loss, Normalized
150
8
0
0.95
-0.4
0.9
-0.8
0.85
0
2
4
D007
Duty Cycle = 50%
Figure 7. Normalized Power Loss vs Frequency
(1)
VDD = 5 V
LSW = 6 µH
125
Figure 4. Power Loss vs Temperature
12
2
0
25
50
75
100
TC - Junction Temperature (qC)
D002
ISW = 5 A
ƒSW = 130 kHz
6
8
10
12
Input Voltage (V)
VDD = 5 V
LSW = 6 µH
14
16
SOA Temperature Adj. (qC)
Power Loss (W)
TJ = 125°C, unless stated otherwise
-1.2
18
D008
Duty Cycle = 50%
Figure 8. Normalized Power Loss vs Input Voltage
LFM: Linear Feet per Minute (Air Flow Velocity)
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Typical Application (continued)
1.15
1.2
1.1
0.8
1.05
0.4
1
0.0
0.95
4
VIN = 10 V
ƒSW = 130 kHz
5
6
7
8
Output Inductance (PH)
VDD = 5 V
Duty Cycle = 50%
9
SOA Temperature Adj. (qC)
Power Loss, Normalized
TJ = 125°C, unless stated otherwise
-0.4
10
D010
ISW = 5 A
Figure 9. Normalized Power Loss vs Output Inductance
1. The Typical bq500101 System Characteristic curves are based on measurements made on a PCB design
with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1-oz. copper
thickness. See the System Example section for detailed explanation.
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TJ = 125°C, unless stated otherwise
8.3 System Example
8.3.1 Power Loss Curves
MOSFET centric parameters such as ON-resistance and gate charges are primarily needed by engineers to
estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas
Instruments has provided measured power loss performance curves. Figure 3 plots the power loss of the
bq500101 as a function of load current. This curve is measured by configuring and running the bq500101 as the
circuit shown in Figure 10. The measured power loss is the bq500101 device power loss which consists of both
input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)
(1)
The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
bq500101
Vin
VDD
Gate Drive
Voltage (VDD)
A
VIN
VDD
A
Input Current (IIN)
Boot
Gate Drive
Current (IDD)
BST
HSgate
V
DRVH
CBoot
Control
FET
Cin
V
Input Voltage
(VIN)
Boot_R
LL
PWM
Vsw
LSgate
PWM
DRVL
VSW
Sync
FET
LO
VO
A
Co
Output Current
(IOUT)
GND
PGND
Averaging
Circuit
V
Averaged Switched
Node Voltage
(VSW_AVG)
Figure 10. Power Loss Test Circuit
8.3.2 Safe Operating Area (SOA) Curves
The SOA curves in the bq500101 datasheet give engineers guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6 outline
the temperature and airflow conditions required for a given load current. The area under the curve dictates the
safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4.0"
(W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1-oz. copper thickness.
8.3.3 Normalized Curves
The normalized curves in the bq500101 data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
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System Example (continued)
8.3.3.1 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example below).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
8.3.3.1.1 Design Example
Operating Conditions: Output Current (lSW) = 9 A, Input Voltage (VIN ) = 8 V, Switching Frequency (ƒSW) = 300
kHz, Output Inductor (LSW) = 5 µH, Duty Cycle = 50%.
8.3.3.1.2 Calculating Power Loss
•
•
•
•
•
Typical Power Loss at 9 A = 1.78 W (Figure 3)
Normalized Power Loss for switching frequency ≈ 1.03 (Figure 7)
Normalized Power Loss for input voltage ≈ 0.96 (Figure 8)
Normalized Power Loss for output inductor ≈ 1.075 (Figure 9)
Final calculated Power Loss = 1.78 W × 1.03 × 0.96 × 1.075 ≈ 1.89 W
8.3.3.1.3 Calculating SOA Adjustments
•
•
•
•
SOA adjustment for switching frequency ≈ 0.20°C (Figure 7)
SOA adjustment for input voltage ≈ –0.30°C (Figure 8)
SOA adjustment for output inductor ≈ 0.60°C (Figure 9)
Final calculated SOA adjustment = 0.2 + (–0.3) + 0.6 ≈ 0.5°C
Figure 11. Power Stage bq500101 SOA, TA = 25°C
In the design example above, the estimated power loss of the bq500101 would increase to 1.89 W. In addition,
the maximum allowable board and/or ambient temperature would have to decrease by 0.5°C. Figure 11
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 0.5°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
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9 Layout
9.1 Layout Guidelines
9.1.1 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
9.1.2 Electrical Performance
The bq500101 has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then taken
with the PCB layout design and placement of the input capacitors, inductor and switch capacitors (SW
capacitors).
• The placement of the input capacitors relative to VIN and PGND pins of bq500101 device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
the ceramic input capacitor C1 needs to be placed as close as possible to the VIN and PGND pins (see
Figure 12). Notice if there are input capacitors on both sides of the board, an appropriate amount of VIN and
GND vias need to be added to interconnect both layers..
• The bootstrap cap CBOOT 0.1-µF 0603 16-V ceramic capacitor C4 in Figure 12 should be closely connected
between BOOT and BOOT_R pins.
• The switching node of the inductor should be placed relatively close to the Power Stage bq500101 VSW pins.
Minimizing the VSW node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. (1)
9.2 Layout Example
L1
GND
GND
C3
VDD
VDD
GND
1
8
2
7
3
6
PWM
BOOT
C4
BOOT_R
9
VSW
VSW
5
4
bq500101
VIN
GND
GND
C1
Figure 12. Recommended PCB Layout (Top Down View)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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9.3 Thermal Considerations
The bq500101 has the ability to use the GND planes as the primary thermal path. As such, the use of thermal
vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids
and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of
solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 12 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
14
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bq500101
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SLPS585 – MARCH 2016
10 Device and Documentation Support
10.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Mechanical Drawing
•°
c1
a1
D2
0.300
(x45°)
1
8
5
MILLIMETERS
DIM
16
4
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
0.800
0.900
1.000
0.031
0.035
0.039
a1
0.000
0.000
0.080
0.000
0.000
0.003
b
0.150
0.200
0.250
0.006
0.008
0.010
b1
2.000
2.200
2.400
0.079
0.087
0.095
b2
0.150
0.200
0.250
0.006
0.008
0.010
c1
0.150
0.200
0.250
0.006
0.008
0.010
D2
3.850
3.950
4.050
0.152
0.156
0.160
E
4.400
4.500
4.600
0.173
0.177
0.181
E1
3.400
3.500
3.600
0.134
0.138
0.142
E2
2.000
2.100
2.200
0.079
0.083
0.087
e
0.400 TYP
K
0.300 TYP
0.016 TYP
0.012 TYP
L
0.300
0.400
0.500
0.012
0.016
0.020
L1
0.180
0.230
0.280
0.007
0.009
0.011
θ
0.00
—
—
0.00
—
—
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11.2 Recommended PCB Land Pattern
(0.010)
0.250
(x18)
(0.006)
0.150
(0.006)
0.150
(0.016)
0.400
(0.024)
0.600 (x 2)
(0.008)
0.200
(x2)
(0.087)
2.200
R0.100
R0.100
0.225 ( x 2)
(0.009)
(0.088)
2.250
(0.012)
0.300
(0.159)
4.050
11.3 Recommended Stencil Opening
(0.008)
0.200
(0.008)
0.200
(0.029)
0.738 (x 8)
(0.016)
0.400
(0.015)
0.390
(0.014)
0.350
0.300
(0.012)
R0.100
0.850 (x8)
(0.033)
(0.012)
0.300
R0.100
0.225 ( x 2)
(0.004)
0.115
0.440 (0.017)
(0.009)
0.225
(0.008)
0.200
(0.087)
2.200
0.200
(0.008)
NOTE: Dimensions are in mm (inches).
Stencil is 100 µm thick.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ500101DPCR
ACTIVE
VSON-CLIP
DPC
8
2500
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
500101
BQ500101DPCT
ACTIVE
VSON-CLIP
DPC
8
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
500101
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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