LINER LTC2376-18 18-bit, 250ksps, low power sar adc with 102db snr Datasheet

LTC2376-18
18-Bit, 250ksps, Low Power
SAR ADC with 102dB SNR
DESCRIPTION
FEATURES
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250ksps Throughput Rate
±1.75LSB INL (Max)
Guaranteed 18-Bit No Missing Codes
Low Power: 3.4mW at 250ksps, 3.4μW at 250sps
102dB SNR (Typ) at fIN = 2kHz
–126dB THD (Typ) at fIN = 2kHz
Digital Gain Compression (DGC)
Guaranteed Operation to 125°C
2.5V Supply
Fully Differential Input Range ±VREF
VREF Input Range from 2.5V to 5.1V
No Pipeline Delay, No Cycle Latency
1.8V to 5V I/O Voltages
SPI-Compatible Serial I/O with Daisy-Chain Mode
Internal Conversion Clock
16-Lead MSOP and 4mm × 3mm DFN Packages
The LTC®2376-18 is a low noise, low power, high speed
18-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2376-18 has a
±VREF fully differential input range with VREF ranging from
2.5V to 5.1V. The LTC2376-18 consumes only 3.4mW and
achieves ±1.75LSB INL maximum, no missing codes at
18 bits with 102dB SNR.
The LTC2376-18 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2376-18
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing external timing considerations. The LTC2376-18 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
APPLICATIONS
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The LTC2376-18 features a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
Medical Imaging
High Speed Data Acquisition
Portable or Compact Instrumentation
Industrial Process Control
Low Power Battery-Operated Instrumentation
ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
2.5V
32k Point FFT fS = 250ksps, fIN = 2kHz
1.8V TO 5V
0
10μF
SNR = 102.3dB
THD = –126dB
SINAD = 102.2dB
SFDR = 127dB
–20
0.1μF
+
20Ω
0V
VREF
0V
IN+
LTC2376-18
3300pF
–
OVDD
VDD
6800pF
IN–
20Ω
6800pF
REF
GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
REF/DGC
2.5V TO 5.1V
237618 TA01
47μF
(X5R, 0805 SIZE)
SAMPLE CLOCK
VREF
AMPLITUDE (dBFS)
–40
VREF
–60
–80
–100
–120
–140
–160
–180
0
25
50
75
FREQUENCY (kHz)
100
125
237618 TA02
237618f
1
LTC2376-18
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF).................................................6V
Analog Input Voltage (Note 3)
IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V)
REF/DGC Input (Note 3) .... (GND –0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2376C ................................................ 0°C to 70°C
LTC2376I .............................................–40°C to 85°C
LTC2376H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
CHAIN
1
VDD
2
GND
3
+
4
IN–
5
GND
6
REF
7
REF/DGC
8
IN
16 GND
15 OVDD
17
GND
TOP VIEW
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF/DGC
14 SDO
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2376CMS-18#PBF
LTC2376CMS-18#TRPBF
237618
16-Lead Plastic MSOP
0°C to 70°C
LTC2376IMS-18#PBF
LTC2376IMS-18#TRPBF
237618
16-Lead Plastic MSOP
–40°C to 85°C
LTC2376HMS-18#PBF
LTC2376HMS-18#TRPBF
237618
16-Lead Plastic MSOP
–40°C to 125°C
LTC2376CDE-18#PBF
LTC2376CDE-18#TRPBF
23768
16-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2376IDE-18#PBF
LTC2376IDE-18#TRPBF
23768
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
237618f
2
LTC2376-18
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
MIN
(Note 5)
l
VIN –
Absolute Input Range (IN–)
(Note 5)
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
VCM
TYP
MAX
UNITS
–0.05
VREF + 0.05
l
–0.05
VREF + 0.05
V
l
–VREF
+VREF
V
Common-Mode Input Range
l
VREF/2–
0.1
VREF/2+
0.1
V
IIN
Analog Input Leakage Current
l
±1
μA
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
fIN = 125kHz
86
dB
VREF/2
V
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
Resolution
18
Bits
No Missing Codes
l
18
Bits
l
–1.75
±0.5
1.75
LSB
LSB
Transition Noise
0.7
(Note 6)
LSBRMS
INL
Integral Linearity Error
DNL
Differential Linearity Error
l
–0.5
±0.1
0.5
Bipolar Zero-Scale Error
l
–8
0
8
BZE
(Note 7)
Bipolar Zero-Scale Error Drift
FSE
UNITS
l
Bipolar Full-Scale Error
3
(Note 7)
l
–40
Bipolar Full-Scale Error Drift
±7
LSB
mLSB/°C
40
±0.05
LSB
ppm/°C
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER
CONDITIONS
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 2kHz, VREF = 5V
l
fIN = 2kHz, VREF = 5V, (H-Grade)
SNR
Signal-to-Noise Ratio
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
THD
SFDR
Total Harmonic Distortion
Spurious Free Dynamic Range
MIN
TYP
98.5
102
l
98
102
dB
l
l
l
99.3
97.5
94.1
102
100
97
dB
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 5V, REF/DGC = GND, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
l
98.8
97.1
93.6
102
100
97
dB
dB
dB
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l
l
l
–126
–127
–124
–106
–103
–106
dB
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 5V, REF/DGC = GND, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
l
–126
–127
–124
–104
–100
–104
dB
dB
dB
fIN = 2kHz, VREF = 5V
l
UNITS
dB
127
dB
–3dB Input Bandwidth
34
MHz
Aperture Delay
500
ps
4
ps
3.460
μs
Aperture Jitter
Transient Response
Full-Scale Step
105
MAX
237618f
3
LTC2376-18
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VREF
Reference Voltage
(Note 5)
l
MIN
IREF
Reference Input Current
(Note 9)
l
VIHDGC
High Level Input Voltage REF/DGC Pin
l
VILDGC
Low Level Input Voltage REF/DGC Pin
l
TYP
2.5
0.16
MAX
UNITS
5.1
V
0.2
mA
0.8VREF
V
0.2VREF
V
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
VIN = 0V to OVDD
0.8 • OVDD
V
–10
0.2 • OVDD
V
10
μA
5
pF
OVDD – 0.2
V
–10
0.2
V
10
μA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
Supply Voltage
CONDITIONS
OVDD
Supply Voltage
IVDD
IOVDD
IPD
IPD
Supply Current
Supply Current
Power Down Mode
Power Down Mode
250ksps Sample Rate
250ksps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
Conversion Done (IVDD + IOVDD + IREF, H-Grade)
PD
Power Dissipation
Power Down Mode
Power Down Mode
250ksps Sample Rate
Conversion Done (IVDD + IOVDD + IREF)
Conversion Done (IVDD + IOVDD + IREF, H-Grade)
MIN
TYP
MAX
UNITS
l
2.375
2.5
2.625
V
l
1.71
l
l
l
1.36
0.05
0.9
0.9
3.4
2.25
2.25
5.25
V
1.7
90
140
mA
mA
μA
μA
4.25
225
315
mW
μW
μW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
l
tCONV
Conversion Time
l
1.9
tACQ
Acquisition Time
l
3.460
tACQ = tCYC – tHOLD (Note 10)
MIN
tHOLD
Maximum Time Between Acquisitions
l
tCYC
Time Between Conversions
l
4
l
20
TYP
MAX
UNITS
250
ksps
3
μs
μs
540
ns
μs
tCNVH
CNV High Time
tBUSYLH
CNV↑ to BUSY Delay
CL = 20pF
l
ns
tCNVL
Minimum Low Time for CNV
(Note 11)
l
20
ns
tQUIET
SCK Quiet Time from CNV↑
(Note 10)
l
20
ns
13
ns
237618f
4
LTC2376-18
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
tSCK
SCK Period
(Notes 11, 12)
tSCKH
MIN
TYP
MAX
UNITS
l
10
ns
SCK High Time
l
4
ns
tSCKL
SCK Low Time
l
4
ns
tSSDISCK
SDI Setup Time From SCK↑
(Note 11)
l
4
ns
tHSDISCK
SDI Hold Time From SCK↑
(Note 11)
l
1
ns
13.5
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
tDSDO
SDO Data Valid Delay from SCK↑
CL = 20pF (Note 11)
l
tHSDO
SDO Data Remains Valid Delay from SCK ↑
CL = 20pF (Note 10)
l
tDSDOBUSYL
SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 10)
l
5
ns
16
ns
13
ns
tEN
Bus Enable Time After RDL↓
(Note 11)
l
tDIS
Bus Relinquish Time After RDL↑
(Note 11)
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 250kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
ns
9.5
1
ns
ns
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 00 0000 0000 0000 0000
and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tWIDTH
0.2*OVDD
tDELAY
tDELAY
0.8*OVDD
0.8*OVDD
0.2*OVDD
0.2*OVDD
50%
50%
237618 F01
Figure 1. Voltage Levels for Timing Specifications
237618f
5
LTC2376-18
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1.5
1.0
DC Histogram
0.5
80000
0.4
70000
0.3
0.5
0.0
–0.5
60000
0.1
0.0
–0.1
10000
0
–0.5
0
65536
131072
196608
OUTPUT CODE
262144
0
65536
131072
196608
OUTPUT CODE
237618 G01
–100
–120
100
98
97
96
95
–160
94
–180
50
75
FREQUENCY (kHz)
100
93
125
SINAD
99
–140
25
–90
101
–80
THD
2ND
3RD
SNR
102
–60
0
–80
103
SNR, SINAD (dBFS)
–40
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input Frequency
SNR = 102.3dB
THD = –126dB
SINAD = 102.2dB
SFDR = 127dB
–20
237618 G03
HARMONICS, THD (dBFS)
0
131069 131070 131071 131072 131073 131074
CODE
262144
237618 G02
32k Point FFT fS = 250ksps,
fIN = 2kHz
AMPLITUDE (dBFS)
40000
20000
–0.4
–1.5
50000
30000
–0.2
–0.3
–1.0
σ = 0.7
0.2
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
–100
–110
–120
–130
0
25
50
75
FREQUENCY (kHz)
100
–140
125
0
25
50
75
FREQUENCY (kHz)
100
237618 G06
237618 G05
237618 TA02
SNR, SINAD vs Input level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
103
103.0
125
–100
–105
HARMONICS, THD (dBFS)
102
SNR, SINAD (dBFS)
SNR, SINAD (dBFS)
102.5
SNR
SINAD
102.0
101
SNR
SINAD
100
99
101.5
–110
–115
THD
–120
2ND
–125
3RD
–130
–135
–140
98
–145
101.0
–40
97
–30
–20
–10
INPUT LEVEL (dB)
0
237618 G07
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
237618 G08
–150
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
237618 G09
237618f
6
LTC2376-18
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
SNR, SINAD vs Temperature,
fIN = 2kHz
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
THD, Harmonics vs Temperature,
fIN = 2kHz
105.0
INL/DNL vs Temperature
–115
1.0
104.5
103.5
103.0
–120
SINAD
102.5
102.0
101.5
INL/DNL ERROR (LSB)
SNR
HARMONICS, THD (dBFS)
SNR, SINAD (dBFS)
104.0
THD
–125
3RD
–130
2ND
101.0
0.5
MAX INL
MAX DNL
0
MIN DNL
MIN INL
–0.5
–135
100.5
100.0
–55 –35 –15
–140
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
237618 G10
Full-Scale Error vs Temperature
0
–2
–4
–8
–55 –35 –15
1.4
1.5
1.2
1.0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.8
0
0.6
–0.5
0.4
–1.0
IOVDD
–2.0
–55 –35 –15
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
237618 G14
Shutdown Current vs Temperature
237618 G15
Reference Current
vs Reference Voltage
CMRR vs Input Frequency
100
IVDD + IOVDD + IREF
0.18
0.16
40
REFERENCE CURRENT (mA)
95
35
90
30
CMRR (dB)
POWER-DOWN CURRENT (μA)
IREF
0.2
237618 G13
45
IVDD
1.0
0.5
–1.5
+FS
–6
Supply Current vs Temperature
2.0
POWER SUPPLY CURRENT (mA)
OFFSET ERROR (LSB)
FULL-SCALE ERROR (LSB)
2
237618 G12
Offset Error vs Temperature
–FS
4
5 25 45 65 85 105 125
TEMPERATURE (°C)
237618 G11
8
6
–1.0
–55 –35 –15
25
20
85
80
15
10
0.14
0.12
0.1
0.08
0.06
0.04
75
0.02
5
0
–55 –35 –15
70
5 25 45 65 85 105 125
TEMPERATURE (°C)
237618 G16
0
20
40
60
80
FREQUENCY (kHz)
100
120
237618 G17
0
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
5.0
237618 G18
237618f
7
LTC2376-18
PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2376-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2376-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by 0VDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0VDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in normal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by 0VDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic
capacitor.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by 0VDD.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47μF ceramic capacitor
(X5R, 0805 size).
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by 0VDD.
REF/DGC (Pin 8): When tied to REF, digital gain compression
is disabled and the LTC2376-18 defines full-scale according
to the ±VREF analog input range. When tied to GND, digital
gain compression is enabled and the LTC2376-18 defines
full-scale with inputs that swing between 10% and 90%
of the ±VREF analog input range.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0VDD.
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 5V
OVDD = 1.8V to 5V
LTC2376-18
IN+
+
18-BIT SAMPLING ADC
IN–
SPI
PORT
–
CONTROL LOGIC
CHAIN
SDO
RDL/SDI
SCK
CNV
BUSY
REF/DGC
GND
237618 BD01
237618f
8
LTC2376-18
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
CNV
CONVERT
POWER-DOWN
BUSY
HOLD
ACQUIRE
SCK
D17 D16 D15
SDO
D2 D1 D0
237618 TD01
237618f
9
LTC2376-18
APPLICATIONS INFORMATION
TRANSFER FUNCTION
The LTC2376-18 is a low noise, low power, high speed 18-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2376-18 supports a
large and flexible ±VREF fully differential input range with
VREF ranging from 2.5V to 5.1V, making it ideal for high
performance applications which require a wide dynamic
range. The LTC2376-18 achieves ±1.75LSB INL max, no
missing codes at 18 bits and 102dB SNR.
The LTC2376-18 digitizes the full-scale voltage of 2 × REF
into 218 levels, resulting in an LSB size of 38μV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
Fast 250ksps throughput with no cycle latency makes
the LTC2376-18 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The
LTC2376-18 dissipates only 3.4mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
The LTC2376-18 features a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
CONVERTER OPERATION
The LTC2376-18 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins to
sample the differential analog input voltage. A rising edge
on the CNV pin initiates a conversion. During the conversion
phase, the 18-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the
sampled input with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/262144) using
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 18-bit digital output
code for serial transfer.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/262144
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
237618 F02
Figure 2. LTC2376-18 Transfer Function
ANALOG INPUT
The analog inputs of the LTC2376-18 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
the CIN capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
REF
RON
40Ω
IN+
REF
IN–
RON
40Ω
CIN
45pF
CIN
45pF
BIAS
VOLTAGE
237618 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2376-18
237618f
10
LTC2376-18
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2376-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2376-18. The amplifier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC inputs draw.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
LPF2
SINGLE-ENDEDINPUT SIGNAL LPF1
500Ω
6800pF
20Ω
IN+
3300pF
6600pF
20Ω
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 600kHz
LTC2376-18
IN–
237618 F04
Figure 4. Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2376-18. The LT6350 ADC
driver is recommended for performing single-ended-todifferential conversions. The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±5V differential input range of the
LTC2376-18. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2376-18 up to 125°C.
Figure 5a shows the LT6350 being used to convert a 0V
to 5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the singleended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5b,
the LT6350 drives the LTC2376-18 to near full data sheet
performance.
The LT6350 can also be used to buffer and convert large
true bipolar signals which swing below ground to the
±5V differential input range of the LTC2376-18 in order
to maximize the signal swing that can be digitized. Figure 6a shows the LT6350 being used to convert a ±10V
true bipolar signal for use by the LTC2376-18. In this
case, the first amplifier in the LT6350 is configured as
an inverting amplifier stage, which acts to attenuate and
level shift the input signal to the 0V to 5V input range of
the LTC2376-18. In the inverting amplifier configuration,
the single-ended input signal source no longer directly
drives a high impedance input of the first amplifier. The
input impedance is instead set by resistor RIN. RIN must
be chosen carefully based on the source impedance of the
signal source. Higher values of RIN tend to degrade both
the noise and distortion of the LT6350 and LTC2376-18
as a system.
237618f
11
LTC2376-18
APPLICATIONS INFORMATION
LT6350
5V
8
0V
1
+
–
RINT
2
+
–
OUT1
RINT
0V
–
+
5V
5
OUT2
0V
–40
5V
4
10μF R4 = 402Ω
R3 = 2k
8
+
–
RINT
10V
0V
–10V
RIN = 2k
RINT
2
R1 = 499Ω
OUT1
+
–
0V
5V
–
+
5
OUT2
0V
VCM = VREF/2
220pF
237618 F06a
Figure 6a. LT6350 Converting a ±10V Single-Ended Signal to
a ±5V Differential Input Signal
SNR = 101dB
THD = –108.1dB
SINAD = 100.4dB
SFDR = 108.5dB
–20
LT6350
1
Figure 5a. LT6350 Converting a 0V-5V Single-Ended
Signal to a ±5V Differential Input Signal
0
R2 = 499Ω
200pF
VCM = VREF/2
237618 F05a
0
–60
–20
–80
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
VCM
5V
4
–100
–120
–140
–160
SNR = 100.8dB
THD = –100.1dB
SINAD = 97.9dB
SFDR = 102.3dB
–60
–80
–100
–120
–140
–180
0
25
50
75
FREQUENCY (kHz)
100
125
–160
237618 F05b
–180
0
Figure 5b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
25
50
75
FREQUENCY (kHz)
100
125
237618 F06b
Figure 6b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 6a
R1, R2, R3 and R4 must be selected in relation to RIN to
achieve the desired attenuation and to maintain a balanced
input impedance in the first amplifier. Table 1 shows the
resulting SNR and THD for several values of RIN, R1, R2,
R3 and R4 in this configuration. Figure 6b shows the resulting FFT when using the LT6350 as shown in Figure 6a.
5V
Table 1. SNR, THD vs RIN for ±10V Single-Ended Input Signal.
0V
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k
499
499
2k
402
100.8
–100
10k
2.49k
2.49k
10k
2k
100.5
–92
100k
24.9k
24.9k
100k
20k
100.2
–98
Fully Differential Inputs
To achieve the full distortion performance of the
LTC2376-18, a low distortion fully differential signal source
driven through the LT6203 configured as two unity gain
buffers as shown in Figure 7 can be used to get the full
data sheet THD specification of –126dB.
LT6203
3
0V
2
5V
+
–
1
+
–
7
0V
5V
5
6
5V
0V
237618 F07
Figure 7. LT6203 Buffering a Fully Differential Signal Source
Digital Gain Compression
The LTC2376-18 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be between 10% and 90% of the ±VREF analog input range. To
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the LT6350 to be powered off of
a single +5.5V supply since each input swings between
0.5V and 4.5V as shown in Figure 8. Needing only one
237618f
12
LTC2376-18
APPLICATIONS INFORMATION
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2376-18. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2376-18 up to 125°C. We recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size)
close to the REF pin.
5V
4.5V
0.5V
0V
237618 F08
Figure 8. Input Swing of the LTC2376 with Gain
Compression Enabled
positive supply to power the LT6350 results in additional
power savings for the entire system.
The REF pin of the LTC2376-18 draws charge (QCONV) from
the 47μF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2376-18 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
Figure 9a shows how to configure the LT6350 to accept a
±10V true bipolar input signal and attenuate and level shift
the signal to the reduced input range of the LTC2376-18
when digital gain compression is enabled. Figure 9b shows
an FFT plot with the LTC2376-18 being driven by the LT6350
with digital gain compression enabled.
ADC REFERENCE
The LTC2376-18 requires an external reference to define
its input range. A low noise, low temperature drift reference is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
When idling, the REF pin on the LTC2376-18 draws only
a small leakage current (< 1μA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 10, IREF quickly goes from approximately
VIN
5.5V
LTC6655-5
0
VOUT_F
5V
1k
4.5V
1k
LT6350
V+
6.04k
4
8
4.32k
10μF
+
–
1
10V
0V
–10V
RIN = 15k
2.5V
3
OUT1
0.5V
20Ω
RINT
RINT
6800pF
IN
+
IN
–
2
3.01k
VCM
20Ω
5
V–
OUT2
4.5V
6
VDD
LTC2376-18
3300pF
–
+
REF
AMPLITUDE (dBFS)
–40
47μF
VCM
10μF
SNR = 98.4dB
THD = –96.9dB
SINAD = 95.2dB
SFDR = 99.2dB
–20
VOUT_S
–60
–80
–100
–120
–140
REF/DGC
–160
237618 F09a
6800pF
–180
0
0.5V
25
50
75
FREQUENCY (kHz)
100
125
237618 F09b
Figure 9a. LT6350 Configured to Accept a ±10V Input Signal While Running Off of a
Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2376-18
Figure 9b. 32k Point FFT Plot
with fIN = 2kHz for Circuit Shown
in Figure 9a
CNV
IDLE
PERIOD
IDLE
PERIOD
237618 F10
Figure 10. CNV Waveform Showing Burst Sampling
237618f
13
LTC2376-18
APPLICATIONS INFORMATION
0μA to a maximum of 0.2mA at 250ksps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the reference output voltage will affect the accuracy of the output
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 reference is also recommended.
Signal-to-Noise Ratio (SNR)
DYNAMIC PERFORMANCE
Total Harmonic Distortion (THD)
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2376-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
Signal-to-Noise and Distortion Ratio (SINAD)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows that the LTC2376-18 achieves
a typical SINAD of 102dB at a 250kHz sampling rate with
a 2kHz input.
0
SNR = 102.3dB
THD = –126dB
SINAD = 102.2dB
SFDR = 127dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
25
50
75
FREQUENCY (kHz)
100
125
237618 F11
Figure 11. 32k Point FFT with fIN = 2kHz of the LTC2376-18
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 11 shows
that the LTC2376-18 achieves a typical SNR of 102dB at
a 250kHz sampling rate with a 2kHz input.
THD= 20log
V22 + V32 + V42 +…+ VN2
V1
POWER CONSIDERATIONS
The LTC2376-18 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2376-18 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2376-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2376-18
has a power-on-reset (POR) circuit that will reset the
LTC2376-18 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
237618f
14
LTC2376-18
APPLICATIONS INFORMATION
TIMING AND CONTROL
DIGITAL INTERFACE
CNV Timing
The LTC2376-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2376-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
Acquisition
A proprietary sampling architecture allows the LTC2376-18
to begin acquiring the input signal for the next conversion 527ns after the start of the current conversion. This
extends the acquisition time to 3.460μs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2376-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 3μs.
Auto Power-Down
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2376-18 is simple and
straightforward to use. The following sections describe the
operation of the LTC2376-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
1.6
POWER SUPPLY CURRENT (mA)
The LTC2376-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the
LTC2376-18. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2376-18 powers down and begins acquiring the
input signal.
1.4
1.2
IVDD
1.0
0.8
0.6
0.4
IREF
0.2
IOVDD
0
The LTC2376-18 automatically powers down after a conversion has been completed and powers up once a new
conversion is initiated on the rising edge of CNV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disable SDO and turn off SCK. The auto power-down feature
will reduce the power dissipation of the LTC2376-18 as
the sampling frequency is reduced. Since power is consumed only during a conversion, the LTC2376-18 remains
powered-down for a larger fraction of the conversion cycle
(tCYC) at lower sample rates, thereby reducing the average
power dissipation which scales with the sampling rate as
shown in Figure 12.
0
50
100
150
200
SAMPLING RATE (kHz)
250
237618 F12
Figure 12. Power Supply Current of the LTC2376-18
Versus Sampling Rate
237618f
15
LTC2376-18
TIMING DIAGRAMS
Normal Mode, Single Device
Figure 13 shows a single LTC2376-18 operated in normal
mode with CHAIN and RDL/SDI tied to ground. With RDL/
SDI grounded, SDO is enabled and the MSB(D17) of the
new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2376-18.
When CHAIN = 0, the LTC2376-18 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
CONVERT
DIGITAL HOST
CNV
BUSY
CHAIN
IRQ
LTC2376-18
RDL/SDI
SDO
DATA IN
SCK
CLK
237618 F13a
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
CONVERT
ACQUIRE
CHAIN = 0
RDL/SDI = 0
tCYC
tCNVH
tCNVL
CNV
tHOLD
tACQ
tACQ = tCYC – tHOLD
tCONV
BUSY
tSCK
tBUSYLH
tSCKH
1
SCK
2
3
tHSDO
tDSDOBUSYL
SDO
tQUIET
16
17
18
tSCKL
tDSDO
D17
D16
D15
D1
D0
237618 F13
Figure 13. Using a Single LTC2376-18 in Normal Mode
237618f
16
LTC2376-18
TIMING DIAGRAMS
Normal Mode, Multiple Devices
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2376-18 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 14,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
Figure 14 shows multiple LTC2376-18 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
RDLB
RDLA
CONVERT
CNV
CNV
CHAIN
CHAIN
LTC2376-18
SDO
B
BUSY
IRQ
LTC2376-18
DIGITAL HOST
SDO
A
RDL/SDI
RDL/SDI
SCK
SCK
DATA IN
CLK
237618 F14a
POWER-DOWN
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
ACQUIRE
CHAIN = 0
tCNVL
CNV
tHOLD
BUSY
tCONV
tBUSYLH
RDL/SDIA
RDL/SDIB
tSCK
SCK
1
2
tSCKH
3
14
15
16
tHSDO
SDO
D15A
D14A
D13A
17
18
19
30
31
32
tSCKL
tDSDO
tEN
Hi-Z
tQUIET
tDIS
D1A
D0A
Hi-Z
D15B
D14B
D13B
D1B
D0B
Hi-Z
237618 F14
Figure 14. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
237618f
17
LTC2376-18
TIMING DIAGRAMS
Chain Mode, Multiple Devices
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 15 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 18 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
When CHAIN = OVDD, the LTC2376-18 operates in chain
mode. In chain mode, SDO is always enabled and RDL/SDI
serves as the serial data input pin (SDI) where daisy-chain
data output from another ADC can be input.
CONVERT
OVDD
OVDD
CNV
CHAIN
RDL/SDI
DIGITAL HOST
LTC2376-18
RDL/SDI
SDO
A
CNV
CHAIN
LTC2376-18
IRQ
BUSY
B
DATA IN
SDO
SCK
SCK
CLK
237618 F15a
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
CHAIN = OVDD
RDL/SDIA = 0
tCYC
tCNVL
CNV
tHOLD
BUSY
tCONV
tBUSYLH
tSCKCH
SCK
1
2
3
16
17
tSSDISCK
18
19
20
34
35
36
tSCKL
tHSDO
tHSDISCK
SDOA = RDL/SDIB
tQUIET
tSCKH
tDSDO
D17A
D16A
D15A
D1A
D0A
D17B
D16B
D15B
D1B
D0B
tDSDOBUSYL
SDOB
D17A
D16A
D1A
D0A
237618 F15
Figure 15. Chain Mode Timing Diagram
237618f
18
LTC2376-18
BOARD LAYOUT
To obtain the best performance from the LTC2376-18
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1783A, the
evaluation kit for the LTC2376-18.
Partial Top Silkscreen
237618f
19
LTC2376-18
BOARD LAYOUT
Partial Layer 1 Component Side
Partial Layer 2 Ground Plane
237618f
20
LTC2376-18
BOARD LAYOUT
Partial Layer 3 PWR Plane
Partial Layer 4 Bottom Layer
237618f
21
AIN –
J8
E7
EXT
VREF/2
R14
0Ω
R39
0Ω
JP5
HD1X3-100
EXT_CM
AIN+
J4
COUPLING
AC
DC
3
2
1
C8
1μF
+2.5V
COUPLING
AC
DC
C46
1μF
C47
OPT C48
10μF
6.3V
5
4
+3.3V
C1
0.1μF
2
5
4
+3.3V
C2
0.1μF
R3
CLK
33Ω
TO CPLD
R41
OPT
R40
1k
R18
1k
R9
OPT
C49
OPT
3
V+
C43
0.1μF
C55
1μF
6
C45 V –
10μF
2 +IN2
8 +IN1
V–
C63
10μF
6.3V
C62
1μF
R37
OPT
R34
0Ω
C61
10μF
6.3V
C42
15pF
R32
0Ω
V+
C44
1μF
C57
0.1μF
C59
1μF
V+
OUT2 5
–IN1
OUT1 4
U15
7 LT6350CMS8
SHDN
U2
R6 3 U8
3
NC7SZ04P5X NC7SVU04P5X
1k
R15
OPT
HD1X3-100
JP2
CM
C18
OPT
C17
10μF
JP1
HD1X3-100
R5
49.9Ω
1206
2
2
J1
CLKIN
1
3
C5
0.1μF
2
R2
1k
+3.3V
1
3
C60
0.1μF
C58
OPT
R35
OPT
R36
20Ω
R45
ØΩ
R32
20Ω
R31
OPT
C11
0.1μF
9V TO 10V
R38
OPT
SDO
5
1
3
5
7
9
11
13
9V TO
10V
C40
6800pF
NPO
R19
0Ω
C7
0.1μF
IN–
LTC2376-18
IN+
C10
0.1μF
C6
10μF
6.3V
C39
6800pF R16
0Ω 4
NPO
C9
10μF
6.3V
C19
3300pF
1206 NPO
+2.5V
+3.3V
U20
LTC6655AHMS8-5
1
8
SHDN
GND
2
7
VIN
OUT_F
3
6
GND OUT_S
4
5
GND
GND
J3
DC590
2
4
6
8
10
12
14
CNV
SCK
SDO
BUSY
R7
1k
3
2
1
JP6
FS
C56
0.1μF
3
3
R17 R13
2k
1k
U9
NC7SZ04P5X
2
4
VSS
6
5
7
3
2
1
C15
0.1μF
U7
C14
0.1μF 8 24LC025-I/ST
VCC
SCL
SCK
SDA
WP
CNV
ARRAY
A2
EEPROM
A1
A0
4
5
+3.3V
R10
4.99k
R11
4.99k
CLKOUT
C16 1
0.1μF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
3
5
2 CNVST_33
FROM CPLD
U4
NC7SVU04P5X
+3.3V
C4
0.1μF
R12
4.99k
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
237618 BL
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
R4
7 33Ω 4
8
+3.3V
C3
0.1μF
R8
33Ω
DC590 DETECT
TO CPLD
5
PR\
Q
CLR\
Q\
2
D
VCC
1
CP
GND
+3.3V
C13
0.8VREF
0.1μF
VREF
6
U3
NL17SZ74
+3.3V
4
HD1X3-100
U6
OPT NC7SZ66P5X 5
CNV
VCC
9
2 B
A 1
13 SCK
OE 4
14 SDO
GND
11 BUSY
3
12 RD
C20
47μF
6.3V
0805
RDL/SDI
VDD 2
OVDD 15
REF 7
8
REF/DGC
GND
GND
GND
GND
+
–
–
+
22
3
6
10
16
1
R1
33Ω
LTC2376-18
BOARD LAYOUT
Partial Schematic of Demoboard
237618f
LTC2376-18
PACKAGE DESCRIPTION
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
0.70 ±0.05
2.20 ±0.05
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(SEE NOTE 6)
1.70 ± 0.05
16
R = 0.05
TYP
3.30 ±0.05
3.60 ±0.05
0.40 ± 0.10
9
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45°
CHAMFER
(DE16) DFN 0806 REV Ø
8
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.45 BSC
3.15 REF
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1
0.23 ± 0.05
0.45 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
16151413121110 9
3.20 – 3.45
(.126 – .136)
0.254
(.010)
DETAIL “A”
0o – 6o TYP
0.280 p 0.076
(.011 p .003)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.305 p 0.038
(.0120 p .0015)
TYP
0.53 p 0.152
(.021 p .006)
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
NOTE:
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1234567 8
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
237618f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2376-18
TYPICAL APPLICATION
LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When
Digital Gain Compression Is Enabled in the LTC2376-18
5.5V
VIN
LTC6655-5
VOUT_F
5V
VOUT_S
1k
47μF
VCM
10μF
4.5V
1k
LT6350
V+
6.04k
4
8
4.32k
10μF
+
–
RIN = 15k
OUT1
6800pF
0.5V
IN+
20Ω
RINT
RINT
2
–
+
IN–
20Ω
5
V–
3.01k
OUT2
4.5V
6
VCM
REF
VDD
LTC2376-18
3300pF
1
10V
0V
–10V
2.5V
3
6800pF
REF/DGC
237618 TA03
0.5V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2379-18
18-Bit, 1.6Msps Serial, Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range,
DGC, MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16
16-Bit, 2Msps Serial, Low Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
MSOP-16 and 4mm × 3mm DFN-16 Packages
ADCs
LTC2383-16/LTC2382-16/ 16-Bit, 1Msps/500ksps/250ksps Serial, Low Power ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin
LTC2381-16
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2393-16/LTC2392-16/ 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC
LTC2391-16
5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin
Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC1865/LTC1865L
16-Bit, 250ksps/150ksps 2-Channel μPower ADC
5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-10 Package
LTC2361
12-Bit, 250ksps, Serial ADC
2.35V to 3.6V, 3.3mW, 6- and 8-Lead TSOT-23 Packages
LTC2757
18-Bit, Single Parallel IOUT SoftSpan™ DAC
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm
LQFP-48 Package
LTC2641
16-Bit/14-Bit/12-Bit Single Serial VOUT DAC
±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
LTC2630
12-Bit/10-Bit/8-Bit Single VOUT DACs
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
LTC6655
Precision Low Drift Low Noise Buffered Reference
5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift Low Noise Buffered Reference
5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
DACS
REFERENCES
AMPLIFIERS
LT6350
Low Noise Single-Ended-to-Differential ADC Driver
Rail-to-Rail Input and Outputs, 240ns, 0.01% Settling Time
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with
Unity Gain/AV = 5/AV = 10
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at
1MHz, TSOT23-6 Package
LT6202/LT6203
Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low 1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
Power Amplifiers
LTC1992
Low Power, Fully Differential Input/Output Amplifier/
Driver Family
1mA Supply Current
237618f
24 Linear Technology Corporation
LT 0711 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2011