NCP5208 DDR−I/II Termination Regulator The NCP5208 is a linear regulator specifically designed for the active termination of DDR−I/II SDRAM. The device can be operated from a single supply voltage as low as 1.7 V. For DDR−I applications, the device is capable of sourcing and sinking current up to 1.5 A with the output voltage regulated to within "3% or better. A separate voltage feedback pin ensures superior load regulation against load and line changes. Protective features include soft−start, source/sink current limits and thermal shutdown. Open−drain VTT OK output (POK) is added for system monitoring. The shutdown pin can tri−state the regulator output for Suspend To RAM (STR) state. This device is available in a SOIC−8 package. http://onsemi.com SOIC−8 D SUFFIX CASE 751 1 MARKING DIAGRAM Features • • • • • • • • • • • • Supports Both DDR−I and DDR−II SDRAM Requirements Single Supply Voltage Operation as Low as 1.7 V Integrated Power MOSFETs Few External Components Needed Source and Sink Current Up to 1.5 A Load Regulation Within "3% Both Source and Sink Current Limits Open−Drain VTT OK (POK) Pin Shutdown Pin Thermal Shutdown Housed in SOIC−8 Package Pb−Free Package is Available Typical Applications • DDR Termination Voltage • Active Bus Termination (SSTL−2, SSTL−3) 8 N5208 ALYW G 1 A L Y W G PIN CONNECTIONS POK 1 8 VTT GND 2 7 PVIN VFB 3 6 AVIN 5 VDDQ SD VDDQ SD ORDERING INFORMATION AVIN Device NCP5208 NCP5208DR2 POK 2.5 V 4 (Top View) VDDQ 2.5 V = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package AVIN VTT PVIN VFB VTT NCP5208DR2G 1.25 V, 1.5 A COUT CIN Package Shipping† SOIC−8 2500/Tape & Reel SOIC−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. GND Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 5 1 Publication Order Number: NCP5208/D NCP5208 VDDQ AVIN VDDQ PVIN AVIN PVIN AVIN R POK − + M0 EN SD EN + VTT VTT R/50 − AVIN COUT M1 EN R VFB GND Figure 2. Simplified Functional Block Diagram PIN FUNCTION DESCRIPTION Pin Symbol Description 1 POK Open−drain VTT Power OK output 2 GND Ground 3 VFB Remote sensing Feedback pin for regulating VTT 4 SD Active low shutdown pin to tri−state VTT output, this pin is pulled high internally 5 VDDQ 6 AVIN Analog supply input, this powers all the internal control circuitry 7 PVIN Power supply input, this provides the rail voltage for the VTT output 8 VTT Termination Regulator output Reference input for VTT regulator MAXIMUM RATINGS Rating AVIN, PVIN, VDDQ, VFB, VTT to GND Symbol Value Unit − −0.3, 6.0 V VIO −0.3, 6.0 V VPOK −0.3, 6.0 V RJA_T 151 °C/W Operating Junction Temperature Range TJ −10 to +150 °C Operating Ambient Temperature Range TA 0 to +70 °C Storage Temperature Range Tstg −55 to +150 °C Input/Output Pins SD Open Drain Output Pins POK Thermal Characteristics SOIC−8 Package − Thermal Resistance, Junction−to−Air Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) v2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) v200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: "150 mA per JEDEC standard: JESD78. http://onsemi.com 2 NCP5208 ELECTRICAL CHARACTERISTICS (AVIN = 2.5 V, PVIN = 2.5 V, VDDQ = 2.5 V, COUT = 220 F, for typical values TA = 25°C, for min/max values TA = 0 to 70°C, unless otherwise noted.) Characteristic Analog Supply Input Power Supply Input Termination Voltage Output Conditions Symbol Min Typ Max Unit − AVIN 1.7 − 5.5 V − PVIN AVIN = 2.5 V, VDDQ = PVIN = 1.8 V IVTT = –0.6 A to +0.6 A VDDQ = 1.8 V, IVTT = 0 to +0.6 A VDDQ = 1.8 V, IVTT = 0 to –0.6 A VTT VDDQ = 2.5 V, IVTT = 0 to +1.5 A VDDQ = 2.5 V, IVTT = 0 to –1.5 A Analog Current Consumption − AVIN V 0.900 0.930 V 1.215 1.250 1.285 V − −18 − − 15 − mV − −20 − − 20 − mV VTT AVIN = PVIN = VDDQ = 2.5 V IVTT = –1.5 A to 1.5 A Load Regulation 1.7 0.870 No Load IAVIN − − 10 mA − ZVDDQ − 50 − k (Note 3) IVFB − − 20 nA Shutdown Pin Enable Threshold − VSD 1.14 1.24 1.34 V Shutdown Pin Hysteresis − VSDhys 0.40 0.55 0.68 V VDDQ = 2.5 V, VSD = 0 V VDDQ = 2.5 V, VSD = 2.5 V VDDQ = 2.5 V, VSD = 5.5 V ISD −15 − − − − − − 10 12 A VDDQ = 2.5 V, VSD = 0 V Ishut − − 15 A VTT Power OK Window Low Threshold (Note 4) POKLth − VDDQ × (1/2−0.02) − V VTT Power OK Window High Threshold (Note 4) POKHth − VDDQ × (1/2+ 0.02) − V IPOK = 5.0 mA RPOKL 7.0 − 20 VDDQ = 2.5 V, VPOK = 6.0 V IPOKleak − − 0.1 A VDDQ Input Impedance VFB Feedback Pin Input Current SHUTDOWN CONTROL Shutdown Pin Input Current Shutdown Analog Supply Current VTT POWER OK INDICATOR POK Pull−LOW Resistance POK Leakage Current OVER CURRENT PROTECTION Source Current Limit − ILIMsrc 1.65 2.1 2.9 A Sink Current Limit − ILIMsnk −2.9 −2.0 −1.65 A Thermal Shutdown Temperature (Note 3) TSD 120 135 150 °C Thermal Shutdown Hysteresis (Note 3) TSDhys − 30 − °C OVER TEMPERATURE PROTECTION 3. Values are not tested in production, guaranteed by design only. 4. Production test performed for AVIN = PVIN = VDDQ = 2.5 V only, 1.8 V performance guaranteed by design. http://onsemi.com 3 NCP5208 TYPICAL OPERATING CHARACTERISTICS 1.300 AVIN = 2.5 V PVIN = VDDQ = 1.8 V TA = 25°C 0.925 VTT, Output Voltage (V) VTT, Output Voltage (V) 0.950 0.900 0.875 0.850 −0.8 0.4 −0.6 −0.4 −0.2 0 0.2 0.6 IVTT, OUTPUT LOAD CURRENT (A) 0.8 1.275 1.250 1.225 1.200 −1.8 VTT, Sink Current Load Regulation (mV) VTT, Source Current Load Regulation (mV) 0 VDDQ = 1.8 V, IVTT = 0.6 A −4 −6 VDDQ = 2.5 V, IVTT = 1.5 A −8 −10 −12 −14 −16 −18 −20 PVIN = VDDQ, = AVIN = 2.5 V 0 10 60 20 30 40 50 TA, AMBIENT TEMPERATURE (°C) 1.8 70 20 PVIN = VDDQ, = AVIN = 2.5 V 18 16 14 12 VDDQ = 2.5 V, IVTT = 1.5 A 10 8 6 4 VDDQ = 1.8 V, IVTT = 0.6 A 2 0 0 Figure 5. Source Current Load Regulation vs. Ambient Temperature 10 60 20 30 40 50 TA, AMBIENT TEMPERATURE (°C) 70 Figure 6. Sink Current Load Regulation vs. Ambient Temperature 10 IAVIN, Analog Input Current (mA) 2.5 ILIM, Over Current Protection Limit (A) −1.4 −1.0 −0.6 −0.2 0.2 0.6 1.0 1.4 IVTT, OUTPUT LOAD CURRENT (A) Figure 4. VTT Output Voltage vs. Load Current (VDDQ = 2.5 V) Figure 3. VTT Output Voltage vs. Load Current (VDDQ = 1.8 V) −2 AVIN = 2.5 V PVIN = VDDQ = 2.5 V TA = 25°C Source Current 2.0 Sink Current 1.5 1.0 0.5 PVIN = AVIN = VDDQ = 2.5 V 0 PVIN = AVIN = VDDQ = 2.5 V IVTT = 0 A 8 6 4 2 0 0 10 20 30 40 50 60 TA, AMBIENT TEMPERATURE (°C) 70 0 Figure 7. Over Current Protection Limit vs. Ambient Temperature 10 20 30 40 50 60 TA, AMBIENT TEMPERATURE (°C) Figure 8. Analog Input Current vs. Ambient Temperature http://onsemi.com 4 70 NCP5208 TYPICAL OPERATING CHARACTERISTICS ZVDDQ, VDDQ Input Impedance () 55 52 49 46 PVIN = AVIN = VDDQ = 2.5 V IVTT = 0 A 43 40 0 10 20 30 40 50 60 TA, AMBIENT TEMPERATURE (°C) 70 Figure 9. VDDQ Input Impedance vs. Ambient Temperature TYPICAL OPERATING WAVEFORMS 0.4 ms ON, 1.6 ms OFF 0.4 ms ON, 1.6 ms OFF (PVIN = AVIN = VDDQ = 1.8 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 500 mA/Division (PVIN = AVIN = VDDQ = 1.8 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 500 mA/Division Figure 10. VTT Current Source Transient Figure 11. VTT Current Sink Transient 0.4 ms ON, 1.6 ms OFF 0.4 ms ON, 1.6 ms OFF (PVIN = AVIN = VDDQ = 2.5 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 1 A/Division (PVIN = AVIN = VDDQ = 2.5 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 1 A/Division Figure 12. VTT Current Source Transient Figure 13. VTT Current Sink Transient http://onsemi.com 5 NCP5208 TYPICAL OPERATING WAVEFORMS (PVIN = AVIN = VDDQ = 2.5 V, IVTT = 0 A) Upper Trace: VTT Output Waveform, 500 mV/Division Middle Trace: VTT Power OK Output, 2 V/Division Lower Trace: Shut−down Signal, 1 V/Division Time Scale: 500 s/Division (PVIN = AVIN = VDDQ = 1.8 V, IVTT = 0 A) Upper Trace: VTT Output Waveform, 500 mV/Division Middle Trace: VTT Power OK Output, 2 V/Division Lower Trace: Shut−down Signal, 1 V/Division Time Scale: 500 s/Division Figure 14. VTT Startup Waveform (VDDQ = 2.5 V) Figure 15. VTT Startup Waveform (VDDQ = 1.8 V) http://onsemi.com 6 NCP5208 DETAILED OPERATING DESCRIPTIONS General Termination Voltage Output Regulation The NCP5208 is a linear regulator with both sink and source current capabilities used for active termination of fast switching logic, DDR−I/II SDRAM terminations and active buses termination of SSTL−2/3 logic. This device can be operated from a single supply voltage as low as 1.7 V. For DDR−I applications, the device is capable of sourcing and sinking current up to 1.5 A with output voltage regulated to within ±3%. The separate voltage remote feedback pin ensures superior load and line regulation with fast tracking capability. Protective features include Soft−Start, Source/Sink Current Limits and internal Thermal Shutdown. Additionally, an open−drain VTT OK output signal (POK) is provided for system monitoring. The shutdown pin (SD) can be used to tri−state the regulator output for Suspend To RAM (STR) state. This device is available in a low profile, space saving SOIC−8 package. The NCP5208 includes a simple linear series regulator with a pair of control error amplifiers, which takes care of the current source and sink operations separately. The error amplifiers control a pair of MOSFETs to maintain the output voltage equal to the internal reference voltage for both current sink and source conditions. In order to avoid the MOSFETs turning on at the same time, a dead−band is implemented internally for safe operation. Regulator Shutdown Function The operation of the NCP5208 can be suspended by pulling the Shutdown (SD) pin to ground. When the device is stopped, the regulator output will be tri−stated for Suspend To RAM (STR) state in PC applications. The shutdown pin is internally pulled high by a small current source, if this feature is not used, this pin can be left open. VTT Power OK for System Monitoring NCP5208 provides an additional VTT power OK signal for system monitoring. The VTT Power OK (POK) pin goes low when the VTT voltage is in regulation and has settled within the allowed window. For memory termination applications, the system can check this pin to ensure the termination voltage quality before accessing the memory. The POK output is connected to a open−drain switching FET and the designer is free to pull this pin to any logic voltage level externally. When the VTT output is in regulation, the internal FET is turned on and pulls the power OK pin to ground. Supply Voltage Inputs For added flexibility, separate input pins are provided for each required supply input. AVIN is the device operating voltage, VDDQ is used to generate the internal reference for VTT output voltage control and PVIN is the power rail for the linear regulator. The device will regulate the output voltage, VTT, with respect to the internal voltage reference generated from VDDQ input and track the VDDQ changes closely. The separate PVIN pin allows the designer to isolate the high current PVIN line changes from coupling into the noise sensitive AVIN and VDDQ inputs. Since the AVIN supplies the control to the output power MOSFETs, PVIN should always be lower than or equal to AVIN. Over−current Protection for Sink and Source Operation In order to provide protection for the internal power MOSFETs, bi−directional current limit protection circuits are implemented. Current limit levels are internally set at 2.1 A typical for current source and 2.0 A typical for current sink at 2.5 V operation. Generation of Internal Reference Voltage The prime function of a termination regulator is to provide a termination voltage, VTT at its output, which can track the mid−point of the logic voltage level closely, i.e. ½(VDDQ). The VTT voltage is used to terminate the bus resistors. The NCP5208 generates a precise reference voltage internally with a built in dead−band to avoid upper and lower MOSFET shoot through. Thermal Shutdown with Hysteresis To guarantee safe operation, NCP5208 provides on−chip thermal shutdown protection. When the chip junction temperature exceeds 135_C typical, the part will shutdown. When the junction temperature falls back to 105_C typical, the device resumes normal operation. Remote Voltage Feedback Sensing The NCP5208 has a separate feedback pin to monitor the output voltage at the remote point. With this capability, the output voltage can be controlled precisely at the output capacitor so that any noise and fluctuations along the power path can be eliminated. http://onsemi.com 7 NCP5208 APPLICATIONS INFORMATION Typical Application Circuit Thermal Dissipation The NCP5208 is a highly integrated termination regulator. For most applications, an input and output capacitor and a pullup resistor for the power OK output, are the only external components needed. For typical application circuit, refer to Figure 1. The NCP5208 is a linear regulator, any current flow from/to VTT will result in internal power dissipation and generating heat. In order to prevent un−wanted shutdown of the device during operation, care should be taken to de−rate the power capability according to the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise, TR−MAX can be calculated from the equation in below: AVIN and VDDQ Supply AVIN provides power for the device to operate. This voltage must be kept clean and free from transients. A small capacitor, 1.0 F is recommended at this input to provide the required supply filtering and ripple rejection. VDDQ is primarily used to generate the internal voltage reference, so any noise or transient at this pin will be directly reflected at the VTT output. In order to avoid undesired interference injected into this pin, appropriate de−coupling and careful design of PCB layout is required. TR−MAX + TJ−MAX * TA−MAX Where TJ−MAX is the maximum allowable junction temperature and TA−MAX is the maximum expected ambient temperature. The maximum allowable power dissipation for a specific condition is given by: T PD−MAX + R−MAX RJA_T Input Capacitor Selection The NCP5208 does not require an input capacitor for stability, however it is still recommended for better overall performance during large load transients that can cause sudden drop of the power rail voltage. The input capacitor must be located as close as possible to the PVIN pin to avoid a transient voltage dip affecting the quality of AVIN and VDDQ. For typical DDR−I applications, a low ESR electrolytic capacitor of 100 F or larger is recommended. By adding a small ceramic capacitor of 0.1 F in parallel, the best high frequency transient filtering will result. If the device is located near the main supply bulk capacitors, the input capacitance can be reduced accordingly. Where PD−MAX is the maximum allowable power dissipation and RJA_T is Junction−to−Air thermal resistance for specific package. The thermal handling capability depends on several variables. Increasing the thickness and area of the copper and adding vias and airflow can improve the thermal performance. Output Capacitor Selection The NCP5208 is internally compensated and stable for any output capacitor with capacitance greater than 220 F and with ESR ranging from 2 m to 400 m The choice for this output capacitor is determined solely by the application and the requirements for load transient characteristic of VTT output. As a general recommendation, the capacitance should be larger than 220 F with low ESR for SSTL and DDR memory applications. http://onsemi.com 8 NCP5208 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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