Maxim MAX9387EUG Differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffer Datasheet

19-2617; Rev 1; 12/02
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
The differential inputs D_, D_ can be configured to
accept a single-ended signal when the unused complementary input is connected to the on-chip reference
output VBB. All the differential inputs have internal bias
and clamping circuits that ensure low-default output
states when the inputs are left open.
The MAX9386/MAX9387/MAX9388 operate with a wide
supply range | V CC - V EE | of 2.375V to 5.5V. The
MAX9386/MAX9388 are offered in 20-pin TSSOP and
QSOP packages. The MAX9387 is offered in 24-pin
TSSOP and QSOP packages.
Features
♦ 318ps (typ) Propagation Delay
♦ >2.7GHz Toggle Frequency
♦ 0.3ps(RMS) Random Jitter
♦ <14ps (max) at +25°C Output-to-Output Skew
(MAX9387)
♦ -2.375V to -5.5V Supplies for Differential
LVECL/ECL
♦ +2.375V to +5.5V Supplies for Differential
LVPECL/PECL
♦ Outputs Low for Open Inputs
♦ Dual Output Buffers (MAX9387)
♦ Pin Compatible with MC100EP57 (MAX9388EUP)
♦ >2kV ESD Protection (Human Body Model)
Ordering Information
PART
MAX9386EUP
TEMP
RANGE
PINPACKAGE
-40°C to +85°C 20 TSSOP
MAX9386EEP* -40°C to +85°C 20 QSOP
SELECTION
5:1 mux with 1
output buffer
5:1 mux with 1
output buffer
Ordering Information continued at end of data sheet.
*Future product—contact factory for availability.
Pin Configurations
Applications
High-Speed Telecom and Datacom Applications
Central Office Backplane Clock Distribution
DSLAM/DLC
TOP VIEW
DO 1
20 VCC
DO 2
19 SEL2
D1 3
18 SEL1
D1 4
D2 5
17 SEL0
MAX9386
16 Q
D2 6
15 Q
D3 7
14 VCC
D3 8
13 VBB1
D4 9
12 VBB2
D4 10
11 VEE
TSSOP/QSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9386/MAX9387/MAX9388
General Description
The MAX9386/MAX9387/MAX9388 are fully differential,
high-speed, low-jitter ECL/PECL multiplexers (muxes)
with output buffer(s). The devices are designed for
clock-and-data distribution applications, and feature
extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1
mux with a single output buffer. The MAX9387 is a 5:1
mux with dual output buffers, and is intended for use in
redundant systems. The MAX9388 is a 4:1 mux with a
single output buffer, and is pin compatible with the
MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function on the MAX9386/
MAX9387. The MAX9388 has two select inputs, SEL0
and SEL1. The mux select inputs are compatible with
ECL/PECL logic, and are internally referenced to the
on-chip output VBB, nominally VCC - 1.425V. The select
inputs accept signals between VCC and VEE. Internal
pulldowns to VEE ensure a low-default condition if the
select inputs are left open.
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
ABSOLUTE MAXIMUM RATINGS
20-Lead QSOP (derate 9.1mW/°C above +70°C) .......727mW
θJA in Still Air .........................................................+110°C/W
θJC ...........................................................................+34°C/W
24-Lead QSOP (derate 9.5mW/°C above +70°C) .......762mW
θJA in Still Air .........................................................+105°C/W
θJC ...........................................................................+34°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............≥2kV
Lead Temperature (soldering, 10s) .................................+300°C
VCC - VEE ...............................................................-0.3V to +6.0V
Inputs (D_, D_, SEL_) to VEE ......................-0.3V to (VCC + 0.3V)
D_ to D_ ..............................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
VBB_ Sink/Source Current ...............................................±600µA
Continuous Power Dissipation (TA = +70°C)
20-Lead TSSOP (derate 11.0mW/°C above +70°C) ....880mW
θJA in Still Air ...........................................................+91°C/W
θJC ...........................................................................+20°C/W
24-Lead TSSOP (derate 12.2mW/°C above +70°C) ....976mW
θJA in Still Air ...........................................................+82°C/W
θJC ...........................................................................+15°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
+25°C
MAX
MIN
TYP
+85°C
MAX
MIN
TYP
MAX
UNITS
INPUT (D_, D_, SEL_)
Single-Ended
Input High
Voltage
VIH
VBB connected to
the unused input
(Figure 1)
VCC 1.225
VCC - VCC 0.880 1.225
VCC - VCC 0.880 1.225
VCC 0.880
V
Single-Ended
Input Low
Voltage
VIL
VBB connected to
the unused input
(Figure 1)
VCC 1.945
VCC - VCC 1.625 1.945
VCC - VCC 1.625 1.945
VCC 1.625
V
Differential Input
High Voltage
VIHD
Figure 1
VEE +
1.2
VCC
VEE +
1.2
VCC
VEE +
1.2
VCC
V
Differential Input
Low Voltage
VILD
Figure 1
VEE
VCC 0.095
VEE
VCC 0.095
VEE
VCC 0.095
V
VCC - VEE
< 3.0V
0.095
VCC VEE
0.095
VCC VEE
0.095
VCC VEE
VCC - VEE
≥ 3.0V
0.095
3.000 0.095
3.000 0.095
3.000
-100
+100
+100
+100
Differential Input
Voltage
Input Current
2
VIHD - VILD Figure 1
IIN
VIH, VIL, VIHD, VILD
-100
-100
_______________________________________________________________________________________
V
µA
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
+25°C
MAX
MIN
TYP
+85°C
MAX
MIN
TYP
MAX
UNITS
OUTPUT (Q_, Q_)
Single-Ended
Output High
Voltage
VOH
Figure 2
VCC 1.145
VCC - VCC 0.895 1.145
VCC - VCC 0.895 1.145
VCC 0.895
V
Single-Ended
Output Low
Voltage
VOL
Figure 2
VCC 1.945
VCC - VCC 1.695 1.945
VCC - VCC 1.695 1.945
VCC 1.695
V
Differential
Output Voltage
VOH - VOL Figure 2
650
830
650
840
650
840
mV
REFERENCE OUTPUT (VBB_ )
Reference
Voltage Output
VBB1,
VBB2
IBB1 + IBB2 = ±0.5mA
(Note 5)
VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.525 1.425 1.325 1.525 1.425 1.325 1.525 1.425 1.325
V
POWER SUPPLY
Supply Current
(Note 6)
IEE
MAX9386
34
50
36
50
38
50
MAX9387
40
60
42
60
45
60
MAX9388
31
47
33
47
35
47
mA
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤ 2.5GHz input duty cycle
= 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN =
622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
PARAMETER
SYMBOL
CONDITIONS
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
222
309
377
238
318
395
254
333
431
ps
1.6
ns
Differential
Input-to-Output
Delay
tPLHD,
tPHLD
Figure 2
SEL_-to-Output
Delay
tPLH2,
tPHL2
Figure 4, input
transition time = 500ps
(20% to 80%) (Note 8)
Output-toOutput Skew
tSKOO
MAX9387 only, Figure 5
(Note 9)
3.9
26
3.9
14
8.0
26
ps
Input-to-Output
Skew
tSKIO
Figure 6 (Note 10)
7.3
53
7.7
50
8.3
50
ps
Part-to-Part Skew
tSKPP
(Note 11)
133
ps
1.64
111
1.4
130
_______________________________________________________________________________________
3
MAX9386/MAX9387/MAX9388
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
AC ELECTRICAL CHARACTERISTICS (continued)
VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤ 2.5GHz input duty cycle
= 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN =
622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
PARAMETER
SYMBOL
Added Random
Jitter (Note 12)
tRJ
Added
Deterministic
Jitter (Note 12)
TDJ
Switching
Frequency
fMAX
Select Toggle
Frequency
fSEL
Output Rise and
Fall Time (20%
to 80%)
t R , tF
CONDITIONS
Clock
pattern
PRBS
223 - 1
+25°C
TYP
MAX
fIN = 156MHz
0.3
fIN = 622MHz
0.3
fIN = 2.5GHz
MIN
+85°C
TYP
MAX
1.15
0.3
1.15
0.3
0.3
1.15
fIN = 156Mbps
33
fIN = 622Mbps
21
MIN
TYP
MAX
1.15
0.3
1.15
1.15
0.3
1.15
0.3
1.15
0.3
1.15
95
33
95
33
95
61
21
61
21
61
UNITS
ps(RMS)
psP-P
VOH - VOL ≥ 300mV,
Figure 2
Figure 2
-40°C
MIN
2.7
2.7
2.7
GHz
100
100
100
MHz
67
105
138
74
117
155
81
128
165
ps
Measurements are made with the device in thermal equilibrium.
Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative.
DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Single-ended data input operation using VBB_ is limited to (VCC - VEE) ≥ 3.0V.
Use VBB_ only for inputs that are on the same device as the VBB_ reference.
All pins open except VCC and VEE.
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the
differential input signal.
Note 11: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 12: Device jitter added to the differential input signal.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
4
_______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
OUTPUT VOLTAGE (mV)
45
40
35
30
140
RISE/FALL TIME (ps)
800
50
150
MAX9386 toc02
55
600
400
20
10
35
60
85
90
400
0
TEMPERATURE (°C)
800
1200 1600 2000 2400 2800
-15
360
35
60
85
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
350
340
TRANSITION TIME (ps)
350
10
TEMPERATURE (°C)
MAX9386 toc04
370
340
tPHLD
320
tPLHD
310
-40
FREQUENCY (MHz)
DIFFERENTIAL PROPAGATION DELAY
vs. INPUT HIGH VOLTAGE
330
110
300
MAX9386 toc05
-15
FALL
120
100
0
-40
130
RISE
200
25
PROPAGATION DELAY (ps)
SUPPLY CURRENT (mA)
1000
MAX9386 toc01
60
OUTPUT RISE/FALL
vs. TEMPERATURE
MAX9386 toc03
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
330
tPLHD
320
tPHLD
310
300
290
290
280
270
280
1.2
1.5
1.8
2.1
2.4
INPUT HIGH VOLTAGE (V)
2.7
3.0
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX9386/MAX9387/MAX9388
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50Ω ±1% to VCC - 2V, fIN = 1.5GHz, input duty cycle =
50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
MAX9386/MAX9388 Pin Description
PIN
NAME
FUNCTION
MAX9386
MAX9388
1
2
D0
Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.
2
3
D0
Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.
3
4
D1
Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.
4
5
D1
Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.
5
6
D2
Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.
6
7
D2
Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.
7
8
D3
Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.
8
9
D3
Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.
9
—
D4
Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.
10
—
D4
Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.
11
10, 11
VEE
Negative Supply
12
12
VBB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.
13
13
VBB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.
14, 20
1, 14
17, 20
VCC
Positive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
15
15
Q
Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
16
16
Q
Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
17
18
SEL0
Select Logic Input 0. Internal 120kΩ pulldown to VEE.
18
19
SEL1
Select Logic Input 1. Internal 120kΩ pulldown to VEE.
19
—
SEL2
Select Logic Input 2. Internal 120kΩ pulldown to VEE.
6
_______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
PIN
NAME
FUNCTION
MAX9387
Positive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors
as close to the device as possible with the smaller value capacitor closest to the device.
1, 18, 24
VCC
2
D0
Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.
3
D0
Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.
4
D1
Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.
5
D1
Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.
6
D2
Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.
7
D2
Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.
8
D3
Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.
9
D3
Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.
10
D4
Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.
11
D4
Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.
12, 13
VEE
Negative Supply
14
VBB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic capacitor. Otherwise
leave open.
15
VBB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic capacitor. Otherwise
leave open.
16
Q1
Inverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.
17
Q1
Noninverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.
19
Q0
Inverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.
20
Q0
Noninverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.
21
SEL0
Select Logic Input 0. Internal 120kΩ pulldown to VEE.
22
SEL1
Select Logic Input 1. Internal 120kΩ pulldown to VEE.
23
SEL2
Select Logic Input 2. Internal 120kΩ pulldown to VEE.
_______________________________________________________________________________________
7
MAX9386/MAX9387/MAX9388
MAX9387 Pin Description
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
VCC
VCC
VIHD (MAX)
VIHD - VILD
VIH
VILD (MAX)
VBB
VIL
VIHD (MIN)
VIHD - VILD
VILD (MIN)
VEE
VEE
SINGLE-ENDED INPUT VOLTAGE DEFINITION
DIFFERENTIAL INPUT VOLTAGE DEFINITION
Figure 1. Input Definitions
VIHD
D_
VIHD - VILD
VILD
D_
tPLHD
tPHLD
VOH
Q_
VOH - VOL
VOL
Q_
80%
VOH - VOL
80%
DIFFERENTIAL OUTPUT
WAVEFORM
0V (DIFFERENTIAL)
VOH - VOL
20%
20%
Q_ - Q_
tR
tF
Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram
VIH
D_ WHEN D_ = VBB
VBB
OR
VBB
VIL
D_ WHEN D_ = VBB
tPLH1
tPHL1
VOH
Q_
VOH - VOL
Q_
VOL
Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Diagram
8
_______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
MAX9386/MAX9387/MAX9388
VIHD
D_, D1
VIHD - VILD
VILD
D_, D1
VIH
VBB
SEL_ = VIL OR OPEN
SELO
VIL
tPLH2
tPHL2
VOH
Q_
VOH - VOL
VOL
Q_
Figure 4. Select Input (SEL0)-to-Output (Q_, Q_) Delay Timing Diagram
Q0
Q0
Q1
Q1
tSKOO
tSKOO
Figure 5. Output-to-Output Skew (tSKOO) Definition (MAX9387 Only)
D0
D0
Q0
Q0
tPLHD*
tPHLD*
tPLHD**
tPHLD**
D1 OR D2 OR D3
D1 OR D2 OR D3
Q0
Q0
tSKIO = | tPLHD* - tPLHD** | OR | tPHLD* - tPHLD** |
tPLHD*: MEASURED BETWEEN D0, D0 INPUT, AND OUTPUT.
tPLHD**: MEASURED BETWEEN ANY OTHER INPUT AND OUTPUT.
Figure 6. Input-to-Output Skew (tSKIO) Definition
_______________________________________________________________________________________
9
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
Detailed Description
The MAX9386/MAX9387/MAX9388 are fully differential,
high-speed, and low-jitter ECL/PECL muxes with output
buffer(s). The devices are designed for clock-and-data
distribution applications, and feature extremely low
propagation delays (318ps, typ) and output-to-output
skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a
single output buffer. The MAX9387 is a 5:1 mux with
dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single
output buffer, and is pin compatible with the
MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function on the MAX9386/
MAX9387. The MAX9388 has two select inputs, SEL0
and SEL1 (see Tables 1 and 2). The mux select inputs
are compatible with ECL/PECL logic, and are internally
referenced to the on-chip output VBB, nominally VCC 1.425V. The select inputs accept signals between VCC
and VEE. Internal 120kΩ pulldowns to VEE ensure a low
default condition if the select inputs are left open,
selecting the D0, D0 input.
The differential inputs D, D can be configured to accept
a single-ended signal when the unused complementary
input is connected to the on-chip reference voltage
Table 1. Mux Select Input Truth Table for
MAX9386/MAX9387
SEL2
SEL1
SEL0
DATA OUTPUT
L or open
L or open
L or open
D0*
L or open
L or open
H
D1
L or open
H
L or open
D2
L or open
H
H
D3
H
X
X
D4
*Default output when SEL0, SEL1, and SEL2 are left open.
Table 2. Mux Select Input Truth Table for
MAX9388
SEL1
SEL0
DATA OUTPUT
L or open
L or open
D0*
L or open
H
D1
H
L or open
D2
H
H
D3
VBB. The reference output voltages, VBB1 and VBB2,
provide the reference voltage for single-ended operation for each mux. A single-ended input of at least VBB_
±100mV or a differential input of at least 100mV switches
the outputs to the VOH and VOL levels specified in the
DC Electrical Characteristics. The maximum magnitude
of the differential input from D to D is ±3.0V. This limit
also applies to the difference between a single-ended
input and any reference voltage input.
Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously.
Single-Ended Operation
The recommended supply voltage for single-ended
operation is 3.0V to 5.5V. The differential inputs (D, D)
can be configured to accept single-ended inputs when
operating at supply voltages greater than 2.725V. In
single-ended mode operation, the unused complementary input needs to be connected to the on-chip reference voltage, VBB, as a reference. For example, the
differential D, D input is converted to a noninverting,
single-ended input by connecting VBB to D and connecting the single-ended input to D. Similarly, an inverting input is obtained by connecting VBB to D and
connecting the single-ended input to D. With a differential input configured as single ended (using VBB), the
single-ended input can be driven to VCC or VEE or with
a single-ended LVPECL/LVECL signal.
In single-ended mode operation, a user must ensure
that the supply voltage (VCC - V EE ) is greater than
2.725V. This is because the input high minimum level
must be at (VEE + 1.2V) or higher for proper operation.
The reference voltage, VBB, must be at least (VEE +
1.2V) for the same reason because it becomes the highlevel input when a single-ended input swings below it.
The minimum VBB output for the MAX9386/MAX9387/
MAX9388 is (VCC - 1.38V). Substituting the minimum
VBB output for (VBB = VEE + 1.2V) results in a minimum
supply (VCC - VEE) of 2.725V. Rounding up to standard
supplies gives the recommended single-ended operating supply ranges (VCC - VEE) of 3.0V to 5.5V.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If not used, leave it
open. The VBB reference can source or sink a total of
0.5mA (shared between VBB1 and VBB2), which is sufficient to drive five inputs.
*Default output when SEL0 and SEL1 are left open.
10
______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
Functional Block Diagram
Output Termination
Terminate the outputs through 50Ω to VCC - 2V or use
equivalent Thevenin terminations. Terminate each Q
and Q output with identical termination on each for minimal distortion. When a single-ended signal is taken
from the differential output, terminate both Q and Q.
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should be observed.
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors. For PECL, bypass
each VCC to VEE. For ECL, bypass each VEE to VCC.
Place the capacitors as close to the device as possible
with the 0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capacitors to ground. When using the VBB1 or VBB2 reference
outputs, bypass each one with a 0.01µF ceramic
capacitor to VCC. If the VBB1 or VBB2 reference outputs
are not used, they can be left open.
D0
D0
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 583
PROCESS: Bipolar
VEE
D1
D1
Q0 (Q*)
D2
Q0 (Q*)
MUX
D2
Q1*
D3
Q1*
D3
VBB1
D4**
VBB2
VCC
D4**
SEL0
250kΩ
150kΩ
SEL1
D_
D_
SEL2**
120kΩ
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity.
VCC
MAX9386
MAX9387
MAX9388
150kΩ
150kΩ
VEE
VEE
MAX9386 (*) DOES NOT HAVE Q1 AND Q1 OUTPUTS, AND
MAX9388 (**) DOES NOT HAVE D4, D4, AND SEL2 INPUTS.
Ordering Information (continued)
PART
TEMP
RANGE
PINPACKAGE
SELECTION
MAX9387EUG -40°C to +85°C 24 TSSOP
5:1 mux with 2
output buffers
MAX9387EEG* -40°C to +85°C 24 QSOP
5:1 mux with 2
output buffers
MAX9388EUP
-40°C to +85°C 20 TSSOP
MAX9388EEP* -40°C to +85°C 20 QSOP
4:1 mux with 1
output buffer
4:1 mux with 1
output buffer
*Future product—contact factory for availability.
______________________________________________________________________________________
11
MAX9386/MAX9387/MAX9388
Applications Information
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
MAX9386/MAX9387/MAX9388
Pin Configurations (continued)
TOP VIEW
VCC 1
20 VCC
VCC 1
24 VCC
DO 2
19 SEL1
DO 2
23 SEL2
DO 3
18 SEL0
DO 3
22 SEL1
17 VCC
D1 4
16 Q
D1 5
D2 6
15 Q
D2 6
19 Q0
D2 7
14 VCC
D2 7
18 VCC
D3 8
13 VBB1
D3 8
17 Q1
D3 9
12 VBB2
D3 9
16 Q1
VEE 10
11 VEE
D4 10
15 VBB1
D4 11
14 VBB2
VEE 12
13 VEE
D1 4
D1 5
MAX9388
TSSOP/QSOP
21 SEL0
MAX9387
20 Q0
TSSOP/QSOP
12
______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
TSSOP4.40mm.EPS
______________________________________________________________________________________
13
MAX9386/MAX9387/MAX9388
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.