TI LMP8278 High common mode, 14 x gain, precision current sensing amplifier Datasheet

LMP8278
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SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
LMP8278Q High Common Mode, 14 x Gain, Precision Current Sensing Amplifier
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FEATURES
DESCRIPTION
•
•
•
•
•
The LMP8278 is a fixed 14x gain precision current
sense amplifier. The part amplifies and filters small
differential signals in the presence of high common
mode voltages. The part operates from a single 5V
supply voltage. With an input common mode voltage
range from -2V to +28V the gain is very precise
(±0.5%). The part can handle common mode voltages
in the range -2V to +40V with relaxed specifications.
The LMP8278 is a member of the Linear Monolithic
Precision ( LMP™) family and is ideal for
unidirectional current sensing applications. The
parameter values that are shown in the Electrical
Characteristics table are 100% tested and all bold
values are also 100% tested over temperature,
unless otherwise noted.
1
23
•
•
•
TCVos ±15μV/°C Max
CMRR 80 dB Min
Input Offset Voltage ±2 mV max
CMVR −2V to 40V
Operating Ambient Temperature Range −40°C
to 125°C
Single Supply Operation
Min / Max Limits 100% Tested unless
Otherwise Noted
LMP8278Q Available in Automotive AEC-Q100
Grade 1 Qualified Version
APPLICATIONS
•
•
•
•
•
The part has a precise gain of 14x which is adequate
in most targeted applications to drive an ADC to its
full scale value. The fixed gain is achieved in two
separate stages, a preamplifier with a gain of 7x and
an output stage buffer amplifier with a gain of 2x. The
connection between the two stages of the signal path
is brought out on two pins to enable the possibility to
create an additional filter network around the output
buffer amplifier. These pins can also be used for
alternative configurations with different gain as
described in Application Information.
High Side and Low Side Driver Configuration
Current Sensing
Automotive Fuel Injection Control
Transmission Control
Power Steering
Battery Management Systems
The
LMP8278Q
incorporates
enhanced
manufacturing and support processes for the
automotive market, including defect detection
methodologies. Reliability qualification is compliant
with the requirements and temperature grades
defined in the AEC Q100 standard.
Typical Applications
D
IL
load
G
+5V
-
+5V
S
+5V
+
-
LMP8278
G
Inductive
Load
24V
LMP8278
-
-
+
+
D
28V
+
+
28V
Inductive
Load
+
LMP8278
S
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LMP8278
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Block Diagram
LMP8278
Vs
+IN
+
-IN
Output Buffer
Gain = 2
Preamplifier
Gain = 7
Proprietary
Level Shift
Circuit
OUT
-
Internal
Resistor
100 k:
GND
A1
A2
Connection Diagram
Top View
-IN
1
GND
2
A1
A2
8
+IN
7
VS
3
6
N/C
4
5
OUT
LMP8278
Figure 1. 8-Pin VSSOP Package
See Package Number DGK0008A
PIN DESCRIPTIONS
Power Supply
Inputs
Filter Network
Pin
Name
2
GND
Description
7
VS
Positive Supply Voltage
1
−IN
Negative Input
8
+IN
Positive Input
3
A1
Preamplifier output
Input from the external filter network and / or A1
Power Ground
4
A2
Output
5
OUT
Single ended output
NC
6
N/C
No Connect (floating)
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1)
(2)
Human Body
For input pins only
±8000V
For all other pins
±2000V
Machine Model
200V
Charge Device Model
1000V
Supply Voltage (VS - GND)
6V
Continuous Input Voltage (–IN and +IN)
(3)
−12V to 50V
Max Voltage at A1, A2 and OUT
VS +0.3V
Min Voltage at A1, A2 and OUT
GND -0.3V
−65°C to 150°C
Storage Temperature Range
Junction Temperature
(4)
150°C
For soldering specs see:
(1)
(2)
(3)
(4)
SNOA549C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are
measured with respect to the ground pin, unless otherwise specified.
Human Body Model per MIL-STD-883, Method 3015.7. Machine Model, per JESD22-A115-A. Field-Induced Charge-Device Model, per
JESD22-C101-C.
For the VSSOP package, the pitch of the solder pads is too narrow for reliable use at higher voltages (VCM >25V). Therefore, it is
strongly advised to add a conformal coating on the PCB assembled with the LMP8278 / LMP8278Q.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
Operating Ratings
(1)
Supply Voltage (VS – GND)
Temperature Range
4.5V to 5.5V
(2)
Package Thermal Resistance
−40°C to +125°C
(2)
8-Pin VSSOP (θJA)
(1)
(2)
230°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are
measured with respect to the ground pin, unless otherwise specified.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
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5.0V Electrical Characteristics
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(1)
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 5.0V, GND = 0V, −2V ≤ VCM ≤ 28V, and RL = ∞, 10nF
between VS and GND. Boldface limits apply at the temperature extremes.
PARAMETER
MIN (2)
TEST CONDITIONS
TYP (3)
MAX (2)
UNIT
Overall Performance (From –IN (pin 1) and +IN (pin 8) to OUT (pin 5) with pins A1 (pin 3) and A2 (pin 4) connected)
IS
Supply Current
AV
Total Gain
0.3
0.4
0.55
mA
–2V < VCM < 28V
13.93
14
14.07
V/V
–2V < VCM < 40V
13.86
14
14.14
Gain Drift
−40°C ≤ TA ≤ 125°C
±2
±25
SR
Slew Rate
VIN = ±0.2V
0.7
BW
Bandwidth
VOS
Input Offset Voltage
(4)
TCVOS
Input Offset Voltage Drift
en
Input Referred Voltage Noise
−40°C ≤ TA ≤ 125°C
0.1 Hz − 10 Hz, 6–Sigma
±2
mV
±2.5
±15
μV/°C
μVPP
285
nV/√Hz
70
80
dB
−2V ≤ VCM ≤ 40
100
125
kΩ
−2V ≤ VCM ≤ 40
60
85
kΩ
DC,4.5V ≤ VS ≤ 5.5V, VCM = VS/2
Power Supply Rejection Ratio
kHz
±0.25
11
Spectral Density, 1 kHz
PSRR
V/μs
90
VCM = VS / 2
ppm/°C
Preamplifier (From input pins –IN (pin 1) and +IN (pin 8) to A1 (pin 3))
RCM
Input Impedance Common Mode
RDM
Input Impedance Differential Mode
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Drift
DC CMRR
DC Common Mode Rejection Ratio
−2V ≤ VCM ≤ 40V
AC CMRR
AC Common Mode Rejection Ratio
(5)
VCM = VS / 2
(4)
−40°C ≤ TA ≤ 125°C
CMVR
Input Common Mode Voltage Range
A1V
Gain
RF-INT
Output Impedance Filter Resistor
TCRF-INT
Output Impedance Filter Resistor Drift
A1 VOUT
Preamplifier Output Voltage Swing
80
±0.25
±2
mV
±2.5
±15
μV/°C
90
dB
f = 1 kHz
90
dB
f = 10 kHz
85
−2
for 80 dB CMRR
VOL
V
6.93
7.0
7.07
97
100
103
kΩ
20
±100
ppm/°C
4
10
RL = ∞
VOH
40
4.80
4.95
V/V
mV
V
Output Buffer (From A2 (pin 4) to OUT (pin 5))
0V ≤ VCM ≤ VS–1
VOS
Input Offset Voltage
A2V
Gain
IB
Input Bias Current of Output Buffer (6) (5)
A2 VOUT
Output Buffer Output Voltage Swing
1.98
(7) (8)
Output Buffer Output Voltage Swing
(7) (8)
VOL
RL = 100 kΩ
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
mV
2
2.02
V/V
VOL
7
4.80
RL = 10 kΩ
VOH
(1)
±2
±20
VOH
A2 VOUT
±0.25
nA
20
mV
30
mV
4.99
15
4.75
pA
±20
4.95
V
V
The Electrical Characteristics table lists ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Datasheet min/max specification limits are ensured by test, unless otherwise noted.
Typical values represent the most likely parameter norms at TA = +25°C and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Offset voltage drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
Specification is ensured by design and is not tested in production.
Positive current corresponds to current flowing into the device.
For this test input is driven from A1 stage.
For VOL, RL is connected to VS and for VOH, RL is connected to GND.
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5.0V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 5.0V, GND = 0V, −2V ≤ VCM ≤ 28V, and RL = ∞, 10nF
between VS and GND. Boldface limits apply at the temperature extremes.
PARAMETER
ISC
Output Short-Circuit Current
TEST CONDITIONS
(6) (9)
Sourcing, VIN = VS, VOUT = GND
Sinking, VIN = GND, VOUT = VS
(9)
MIN (2)
TYP (3)
MAX (2)
-10
UNIT
mA
10
Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
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Typical Performance Characteristics
Unless otherwise specified, measurements taken at TA = 25°C, VS = 5V, GND = 0V, −2V ≤ VCM ≤ 28V, and RL = ∞, 10nF
between VS and GND.
VOS
vs.
VCM
1.0
1.0
0.8
0.8
0.6
0.6
-40°C
0.4
VOFFSET(mV)
VOFFSET(mV)
VOS
vs.
VS
0.2
25°C
0.0
-0.2
-0.4
-0.6
125°C
0.2
0.0
-0.2
-0.4
25°C
-0.6
125°C
-0.8
-0.8
-1.0
-1.0
-5
0
5 10 15 20 25 30 35 40 45
VCM(V)
4.5
4.7
4.9
5.1
VSUPPLY(V)
5.3
Figure 2.
Figure 3.
A1 Input Bias Current
vs.
VCM
A2 Input Bias Current
vs.
VCM, at 25°C
400
50
350
40
300
5.5
30
250
20
125°C
200
IBIAS(fA)
IBIAS( A)
-40°C
0.4
25°C
150
-40°C
100
10
0
-10
50
-20
0
-30
-50
-40
-100
25°C
-50
-5
0
5 10 15 20 25 30 35 40 45
VCM(V)
0
1
2
3
4
A2 PIN VOLTAGE (V)
Figure 4.
Figure 5.
A2 Input Bias Current
vs.
VCM, at 125°C
Input Referred Voltage Noise
vs.
Frequency
5
0.5
4.0
VOLTAGE NOISE ( V/¥+])
3.5
3.0
IBIAS(nA)
2.5
2.0
1.5
1.0
0.5
0.0
0.3
0.2
0.1
125°C
-0.5
-1.0
0.0
0
1
2
3
4
A2 PIN VOLTAGE (V)
5
Figure 6.
6
0.4
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified, measurements taken at TA = 25°C, VS = 5V, GND = 0V, −2V ≤ VCM ≤ 28V, and RL = ∞, 10nF
between VS and GND.
PSRR
vs.
Frequency
CMRR
vs.
Frequency
120
120
100
100
80
80
CMRR (dB)
60
40
40
20
20
0
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 8.
Figure 9.
Gain
vs.
Frequency, Vout=500mV
Gain
vs.
Frequency, Vout=4.5V
30
30
-40°C
10
25°C
0
125°C
-40°C
20
GAIN (dB)
20
-10
25°C
10
125°C
0
-10
VOUT= 500mV
VOUT= 4.5V
-20
-20
1k
10k
100k
FREQUENCY (Hz)
1M
100
1k
10k
100k
FREQUENCY (Hz)
Figure 11.
Settling Time (Falling Edge)
Settling Time (Rising Edge)
INPUT
OUTPUT
INPUT SIGNAL (100 mV/DIV)
Figure 10.
OUTPUT SIGNAL (1 V/DIV)
100
INPUT SIGNAL (100 mV/DIV)
125°C
0
100
GAIN (dB)
25°C
60
1M
OUTPUT SIGNAL (1 V/DIV)
PSRR (dB)
-40°C
INPUT
OUTPUT
TIME (1 s/DIV)
TIME (1 s/DIV)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified, measurements taken at TA = 25°C, VS = 5V, GND = 0V, −2V ≤ VCM ≤ 28V, and RL = ∞, 10nF
between VS and GND.
Positive Swing
vs.
ILOAD
Step Response
5.00
OUTPUT VOLTAGE (V)
OUTPUT SIGNAL (1 V/DIV)
INPUT SIGNAL (100 mV/DIV)
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.91
INPUT
OUTPUT
4.90
1
10
TIME (10 s/DIV)
Figure 14.
VOS Distribution
40
PERCENTAGE PER 100 µV INTERVAL
100
OUTPUT VOLTAGE (mV)
90
80
70
60
50
40
30
20
10
0
1
10
100
ILOAD( A)
25°C
35
30
25
-40°C
20
15
125°C
10
5
0
-2.0 -1.5 -1.0 -0.5 0.0
1000
0.5
1.0
1.5
2.0
VOS (mV)
Figure 16.
Figure 17.
TCVOS Distribution
CMRR Distribution
35
PERCENTAGE PER 5 dB INTERVAL
20
PERCENTAGE (%)
1000
Figure 15.
Negative Swing
vs.
ILOAD
15
10
5
0
-15 -12 -9 -6 -3
0
3
6
125°C
30
25°C
25
20
-40°C
15
10
9 12 15
5
0
80
90
100
110
120
130
140
CMRR (dB)
TCVOS( V/°C)
Figure 18.
8
100
ILOAD ( A)
Figure 19.
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APPLICATION INFORMATION
GENERAL
The LMP8278 is a fixed gain differential voltage precision amplifier with a gain of 14x and a -2V to +40V input
common mode voltage range when operating from a single 5V supply. The LMP8278 is a member of the LMP™
family and is ideal for unidirectional current sensing applications. Because of its proprietary level-shift input stage
the LMP8278 achieves very low offset, very low thermal offset drift, and very high CMRR. The LMP8278
amplifies and filters small differential signals in the presence of high common mode voltages.
The LMP8278 uses level shift resistors at the inputs. Because of these resistors, the LMP8278 can easily
withstand very large differential input voltages that may exist in fault conditions where some other less protected
current sense amplifiers might sustain permanent damage.
The LMP8278 is available in an 8–Pin VSSOP package. For the VSSOP package, the pitch of the solder pads is
too narrow for reliable use at higher voltages (VCM > 25V). Therefore, it is strongly advised to add a conformal
coating on the PCB assembled with the LMP8278 in VSSOP package.
PERFORMANCE GUARANTIES
To guaranty the high performance of the LMP8278, minimum and maximum values shown in the Electrical
Characteristics of this datasheet are 100% tested and all bold limits are also 100% tested over temperature,
unless otherwise noted.
THEORY OF OPERATION
The schematic shown in Figure 20 gives a schematic representation of the internal operation of the LMP8278.
The signal on the input pins is typically a small differential voltage across a current sensing shunt resistor. The
input signal may appear at a high common mode voltage. The input signals are accessed through two input
resistors. The proprietary level shift circuit brings the common mode voltage behind the input resistors within the
supply rails. Subsequently, the signal is gained up by a factor of 7 and brought out on the A1 pin through a
trimmed 100 kΩ resistor. In the application, additional gain adjustment or filtering components can be added
between the A1 and A2 pins as will be explained in subsequent sections. The signal on the A2 pin is further
amplified by a factor of 2 and brought out on the OUT pin.
LMP8278
Vs
+IN
-IN
+
Proprietary
Level Shift
Circuit
Output Buffer
Gain = 2
Preamplifier
Gain = 7
OUT
-
Internal
Resistor
100 k:
GND
A1
A2
Figure 20. Theory of Operation
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ADDITIONAL SECOND ORDER LOW PASS FILTER
The bandwidth of the output buffer can be reduced by adding a capacitor on the A1 pin to create a first order low
pass filter with a time constant determined by the 100 kΩ internal resistor and the external filter capacitor.
It is also possible to create an additional second order Sallen-Key low pass filter, as illustrated in Figure 21, by
adding external components R2, C1 and C2. Together with the internal 100 kΩ resistor R1, this circuit creates a
second order low-pass filter characteristic.
When the corner frequency of the additional filter is much lower than 90 kHz, the transfer function of the
described amplifier can be written as:
K1 * K2
H(s) =
2
s +s*
1
R1R2C1C2
(1 - K2)
1
1
1
+
+
+
R 1C2 R 2C2
R2C1
R1R2C1C2
where
•
•
K1 equals the gain of the preamplifier
K2 that of the buffer amplifier
(1)
nd
The above equation can be written in the normalized frequency response for a 2
G(jZ) = K1 *
order low pass filter:
K2
2
jZ
(jZ)
+1
2 +
QZo
Zo
(2)
The cutt-off frequency ωo in rad/sec (divide by 2π to get the cut-off frequency in Hz) is given by:
1
Zo =
R 1 R 2C 1 C 2
(3)
And the quality factor of the filter is given by:
Q=
R 1R2C1 C2
R1C1 + R2C1 + (1 - K2) * R1C2
(4)
With K2>1x, the above equation results in:
R 1R 2
Q=
C12
(K-1)
(K-1)R1C2
R1C1 + R2C1 (K-1)
(5)
For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen in a certain
ratio.
C2 =
C1
K-1
(6)
In this case, given the predetermined value of R1 = 100 kΩ (the internal resistor), the quality factor is set solely
by the value of the resistor R2.
10
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R2 can be calculated based on the desired value of Q as the first step of the design procedure with the following
equation:
R2 =
R1
(K - 1) Q2
(7)
For the gain of 2 for the LMP8278 this results in:
R1
R2 =
Q2
(8)
LMP8278
+IN
-IN
8
1
+
K1
K2
Preamplifier
Gain = 7
-
Output Buffer
Gain = 2
Internal
R1
100 k:
3
5
OUT
4
A1
A2
R2
C1
C2
Figure 21. Second Order Low Pass Filter
For instance, the value of Q can be set to 0.5√2 to create a Butterworth response, to 1/√3 to create a Bessel
response, or to 0.5 to create a critically damped response. Once the value of R2 has been found, the second and
last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off
frequency using:
(K-1)Q
C1 =
R1Z0
(9)
Which for the gain=2 will give:
C1 =
Q
R1Z0
(10)
For C2 the value is calculated with:
C2 =
C1
K-1
(11)
Or, for a gain=2, C2=C1
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Note that the frequency response achieved using this procedure will only be accurate if the cut-off frequency of
the second order filter is much smaller than the intrinsic 90 kHz low-pass response. In other words, choose the
frequency response of the circuit such that the internal poles of the LMP8278 do not affect the external second
order filter.
For a desired Q = 0.707 and a cut off frequency = 3 kHz, this will result in rounded values for R2 = 200 kΩ, C1:C2
= 390 pF.
GAIN ADJUSTMENT
The gain of the LMP8278 is 14; however, this gain can be adjusted as the signal path in between the two internal
amplifiers is available on the external pins.
Reduce Gain
Figure 22 shows the configuration that can be used to reduce the gain of the LMP8278.
Rr creates a resistive divider together with the internal 100 kΩ resistor such that the reduced gain Gr becomes:
Gr =
14 Rr
Rr + 100 k:
(12)
Given a desired value of the reduced gain Gr, using this equation the required value for Rr can be calculated
with:
Rr = 100 k: x
Gr
14 - Gr
(13)
Increase Gain
Figure 23 shows the configuration that can be used to increase the gain of the LMP8278.
Ri creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback
increases the gain. The increased gain Gi becomes:
Gi =
14 Ri
Ri - 100 k:
(14)
From this equation, for a desired value of the gain, the required value of Ri can be calculated with:
Ri = 100 k: x
Gi
Gi - 14
(15)
It should be noted from the equation for the gain Gi that for large gains Ri approaches 100 kΩ. In this case, the
denominator in the equation becomes close to zero. In practice, for large gains the denominator will be
determined by tolerances in the values of the external resistor Ri and the internal 100 kΩ resistor. In this case,
the gain becomes very inaccurate. If the denominator becomes equal to zero, the system will even become
unstable. It is recommended to limit the application of this technique to gain values of 35 or smaller.
12
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SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
LMP8278
+IN 8
1
-IN
+
Preamplifier
Gain = 7
-
Output Buffer
Gain = 2
5
OUT
5
OUT
Internal
Resistor
100 k:
3
4
A2
A1
Rr
Figure 22. Reduce Gain
LMP8278
+IN 8
1
-IN
+
Preamplifier
Gain = 7
-
Output Buffer
Gain = 2
Internal
Resistor
100 k:
3
A1
4
A2
Ri
Figure 23. Increase Gain
POWER SUPPLY DECOUPLING
In order to decouple the LMP8278 from AC noise on the power supply, it is recommended to use a 0.1 µF
bypass capacitor between the VS and GND pins. This capacitor should be placed as close as possible to the
supply pins. In some cases an additional 10 µF bypass capacitor may further reduce the supply noise.
DRIVING SWITCHED CAPACITIVE LOADS
Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to
being connected to the signal source. If the LMP8278 is driving such ADCs the sudden current that should be
delivered when the sampling occurs may disturb the output signal. This effect was simulated with the circuit
shown in Figure 24 where the output is connected to a capacitor that is driven by a rail to rail square wave.
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13
LMP8278
SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
www.ti.com
VS
LMP8278
0V
Figure 24. Driving Switched Capacitive Load
This circuit simulates the switched connection of a discharged capacitor to the LMP8278 output. The resulting
VOUT disturbance signal is shown in Figure 25.
The figure can be used to estimate the disturbance that will be caused when driving a switched capacitive load.
To minimize the error signal introduced by the sampling that occurs on the ADC input, an additional RC filter can
be placed in between the LMP8278 and the ADC as illustrated in Figure 26.
The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The
external capacitor should be much larger than the sample and hold capacitor at the input of the ADC and the RC
time constant of the external filter should be such that the speed of the system is not affected.
3.00
2.75
VOUT(V)
2.50
2.25
10 pF
2.00
1.75
20 pF
1.50
1.25
1.00
0
50
100 150 200
TIME (ns)
250
300
Figure 25. Capacitive Load Response
LMP8278
ADC
Figure 26. Reduce Error When Driving ADCs
14
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SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
LOW SIDE CURRENT SENSING APPLICATION
Figure 27 illustrates a low side current sensing application with a low side driver. The power transistor is pulse
width modulated to control the average current flowing through the inductive load which is connected to a
relatively high battery voltage. The current through the load is measured across a shunt resistor RSENSE in series
with the load. When the power transistor is on, current flows from the battery through the inductive load, the
shunt resistor and the power transistor to ground. In this case, the common mode voltage on the shunt is close
to ground. When the power transistor is off, current flows through the inductive load, through the shunt resistor
and through the freewheeling diode. In this case the common mode voltage on the shunt is at least one diode
voltage drop above the battery voltage. Therefore, in this application the common mode voltage on the shunt is
varying between a large positive voltage and a relatively low voltage. Because the large common mode voltage
range of the LMP8278 and because of the high AC common mode rejection ratio, the LMP8278 is very well
suited for this application.
LMP8278
INDUCTIVE
LOAD
+IN 8
RSENSE
0.01Ö
+
24V
1
-IN
+
Output Buffer
Gain = 2
Preamplifier
Gain = 7
-
OUT
Vout = 0.14V/A
-
Internal
Resistor
100 k:
3
4
A2
A1
POWER
SWITCH
5
C1
Figure 27. Low Side Current Sensing Application
HIGH SIDE CURRENT SENSING APPLICATION
Figure 28 illustrates the application of the LMP8278 in a high side sensing application. This application is similar
to the low side sensing discussed above, except in this application the common mode voltage on the shunt drops
below ground when the driver is switched off. Because the common mode voltage range of the LMP8278
extends below the negative rail, the LMP8278 is also very well suited for this application.
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LMP8278
SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
www.ti.com
POWER
SWITCH
LMP8278
+IN
+
RSENSE
-
24V
0.01Ö
8
+
Preamplifier
Gain = 7
1
-
-IN
Output Buffer
Gain = 2
5
OUT
Vout = 0.14V/A
Internal
Resistor
100 k:
INDUCTIVE
LOAD
3
4
A1
A2
C1
Figure 28. High Side Current Sensing Application
RF-PA CONTROL APPLICATION
Figure 29 illustrates how the LMP8278 can be used to monitor current flow in an RF power amplifier control
application. The fact that the LMP8278 can measure small voltages at a high common mode voltage outside its
own supply range makes this part a good choice for such an application. The output signal of the LMP8278 is
used as an input for the PA controller. The PA controller can be used to regulate the output power of the RF-PA
by measuring the output amplifier supply current.
IPA
RSENSE
0.02:
+
24V
-
LMP8278
-IN
1
Preamplifier
Gain = 7
8
+
+IN
Output Buffer
Gain = 2
5
Internal
Resistor
100 k:
OUT
Controller
RF Power Amplifier
Vout = 0.28V/A
3
A1
4
A2
C1
Figure 29. RF Power Amplifier Control Application
16
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SNAS575A – FEBRUARY 2012 – REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP8278QMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AB7A
LMP8278QMME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AB7A
LMP8278QMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AB7A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMP8278QMM/NOPB
VSSOP
DGK
8
LMP8278QMME/NOPB
VSSOP
DGK
LMP8278QMMX/NOPB
VSSOP
DGK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP8278QMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP8278QMME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP8278QMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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