CY7C1360C, CY7C1362C 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description ■ Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply (VDD) ■ 2.5 V/3.3 V I/O operation (VDDQ) ■ Fast clock-to-output times ❐ 3.0 ns (for 200 MHz device) ■ Provide high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Single cycle chip deselect ■ Available in Pb-free 100-pin TQFP package, non Pb-free 119-ball BGA package, and 165-ball FBGA package ■ TQFP available with 3-chip enable and 2-chip enable ■ IEEE 1149.1 JTAG-compatible boundary scan The CY7C1360C/CY7C1362C SRAM integrates 256 K × 36 and 512 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3[1]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at the rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see Pin Definitions on page 8 and Truth Table on page 11 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360C/CY7C1362C operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 200 MHz 166 MHz Unit Maximum access time Description 3.0 3.5 ns Maximum operating current 220 180 mA Maximum CMOS standby current 40 40 mA Note 1. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document Number: 38-05540 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 25, 2012 CY7C1360C, CY7C1362C Logic Block Diagram – CY7C1360C A 0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 ADSP BW D DQ D ,DQP D BYTE WRITE REGISTER DQ D ,DQPD BYTE WRITE DRIVER BW C DQ C ,DQP C BYTE WRITE REGISTER DQ C ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B GW CE 1 CE 2 CE 3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D DQ A ,DQP A BYTE WRITE DRIVER DQ A ,DQP A BYTE WRITE REGISTER BW A BWE MEMORY ARRAY ENABLE REGISTER INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Logic Block Diagram – CY7C1362C A0, A1, A ADDRESS REGISTER 2 MODE A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW B DQ B, DQP B WRITE DRIVER DQ B, DQP B WRITE REGISTER MEMORY ARRAY BW A DQ A, DQP A WRITE DRIVER DQ A, DQP A WRITE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B E BWE GW CE 1 CE2 CE3 ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS OE ZZ SLEEP CONTROL Document Number: 38-05540 Rev. *N Page 2 of 37 CY7C1360C, CY7C1362C Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 8 Functional Overview ........................................................ 9 Single Read Accesses ................................................ 9 Single Write Accesses Initiated by ADSP ................... 9 Single Write Accesses Initiated by ADSC ................. 10 Burst Sequences ....................................................... 10 Sleep Mode ............................................................... 10 Interleaved Burst Address Table ............................... 10 Linear Burst Address Table ....................................... 10 ZZ Mode Electrical Characteristics ............................ 10 Truth Table ...................................................................... 11 Partial Truth Table for Read/Write ................................ 12 Partial Truth Table for Read/Write ................................ 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port (TAP) ............................................. 13 PERFORMING A TAP RESET .................................. 13 TAP REGISTERS ...................................................... 13 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Timing ...................................................................... 16 TAP AC Switching Characteristics ............................... 17 3.3 V TAP AC Test Conditions ....................................... 17 3.3 V TAP AC Output Load Equivalent ......................... 17 2.5 V TAP AC Test Conditions ....................................... 17 2.5 V TAP AC Output Load Equivalent ......................... 17 Document Number: 38-05540 Rev. *N TAP DC Electrical Characteristics and Operating Conditions ..................................................... 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Boundary Scan Order .................................................... 21 Maximum Ratings ........................................................... 22 Operating Range ............................................................. 22 Neutron Soft Error Immunity ......................................... 22 Electrical Characteristics ............................................... 22 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 AC Test Loads and Waveforms ..................................... 24 Switching Characteristics .............................................. 25 Switching Waveforms .................................................... 26 Ordering Information ...................................................... 30 Ordering Code Definitions ......................................... 30 Package Diagrams .......................................................... 31 Acronyms ........................................................................ 34 Document Conventions ................................................. 34 Units of Measure ....................................................... 34 Document History Page ................................................. 35 Sales, Solutions, and Legal Information ...................... 37 Worldwide Sales and Design Support ....................... 37 Products .................................................................... 37 PSoC Solutions ......................................................... 37 Page 3 of 37 CY7C1360C, CY7C1362C Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1360C (256 K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables - A Version) Document Number: 38-05540 Rev. *N Page 4 of 37 CY7C1360C, CY7C1362C Pin Configurations (continued) NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1362C (512 K × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC A A A A A A A CY7C1360C (256 K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (2 Chip Enables - AJ Version) Document Number: 38-05540 Rev. *N A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 5 of 37 CY7C1360C, CY7C1362C Pin Configurations (continued) Figure 3. 119-ball BGA (14 × 22 × 2.4 mm) pinout (2 Chip Enables with JTAG) 1 CY7C1360C (256 K × 36) 3 4 5 A A ADSP A VDDQ 2 A 6 A 7 VDDQ B C NC/288M NC/144M CE2 A A A ADSC VDD A A A A NC/576M NC/1G D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA L DQD DQD NC DQA VDDQ DQD BWA VSS DQA M BWD VSS DQA VDDQ N DQD DQD VSS VSS DQA DQA P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC/72M TMS A TDI A TCK A TDO NC/36M NC ZZ VDDQ Document Number: 38-05540 Rev. *N GW VDD CLK BWE A1 Page 6 of 37 CY7C1360C, CY7C1362C Pin Configurations (continued) Figure 4. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enables with JTAG) CY7C1360C (256 K × 36) 1 A B C D E F G H J K L M N P NC/288M R 2 3 4 5 6 7 8 9 10 11 NC CE1 BWC BWB CE3 BWE ADSC ADV A NC/144M A CE2 BWD BWA CLK GW OE ADSP A DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB DQC VSS DQD DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC/18M VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS TCK A A A A A Document Number: 38-05540 Rev. *N A0 NC/576M Page 7 of 37 CY7C1360C, CY7C1362C Pin Definitions Name I/O Description A0, A1, A InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1:A0 are fed to the two-bit counter. BWA, BWB, BWC, BWD InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled synchronous on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted synchronous LOW to conduct a byte write. CLK Inputclock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3[2] InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA. Where referenced, CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPX I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition. VDD Power supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VSSQ I/O ground Ground for the I/O circuitry. VDDQ I/O power supply Power supply for the I/O circuitry. MODE Inputstatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. Note 2. CE3 is for A version of 100-pin TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. Document Number: 38-05540 Rev. *N Page 8 of 37 CY7C1360C, CY7C1362C Pin Definitions (continued) Name I/O Description TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin should be disconnected. This pin is not available on TQFP packages. output synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. synchronous TMS JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. synchronous TCK JTAGclock Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No connects. Not internally connected to the die NC (18, 36, 72, 144, 288, 576, 1G) – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M, 576M, and 1G densities. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (200 MHz device). The CY7C1360C/CY7C1362C supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3[3]) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3[3] are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock, the data is allowed to propagate through the output register and on the data bus within 3.0 ns (200 MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tristates immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1, CE2, CE3[3] are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1360C/CY7C1362C provides byte write capability that is described in the Write Cycle Descriptions table. Asserting the byte write enable input (BWE) with the selected byte write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1360C/CY7C1362C is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tristates the output drivers. As a safety precaution, DQs are automatically tristated whenever a Write cycle is detected, regardless of the state of OE. Note 3. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. Document Number: 38-05540 Rev. *N Page 9 of 37 CY7C1360C, CY7C1362C Single Write Accesses Initiated by ADSC Sleep Mode ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3[4] are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation ‘sleep’ mode. Two clock cycles are required to enter into or exit from this ‘sleep’ mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the ‘sleep’ mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the ‘sleep’ mode. CE1, CE2, CE3[4], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Because the CY7C1360C/CY7C1362C is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tristates the output drivers. As a safety precaution, DQs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1360C/CY7C1362C provides a two-bit wraparound counter, fed by A1:A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 00 11 10 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 10 01 00 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 00 01 10 Linear Burst Address Table (MODE = GND) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 10 11 00 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ inactive to exit sleep current Test Conditions ZZ > VDD– 0.2 V ZZ > VDD – 0.2 V ZZ < 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 50 2tCYC – 2tCYC – Unit mA ns ns ns ns Note 4. CE3 is for A version of 100-pin TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. Document Number: 38-05540 Rev. *N Page 10 of 37 CY7C1360C, CY7C1362C Truth Table The Truth Table for CY7C1360C and CY7C1362C follows. [5, 6, 7, 8, 9, 10] Operation Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect cycle, power-down None H X X L X L X X X L–H Tri-state Deselect cycle, power-down None L L X L L X X X X L–H Tri-state Deselect cycle, power-down None L X H L L X X X X L–H Tri-state Deselect cycle, power-down None L L X L H L X X X L–H Tri-state Deselect cycle, power-down None L X H L H L X X X L–H Tri-state Sleep mode, power-down None X X X H X X X X X X Tri-state Q READ cycle, begin burst External L H L L L X X X L L–H READ cycle, begin burst External L H L L L X X X H L–H Tri-state WRITE cycle, begin burst External L H L L H L X L X L–H D READ cycle, begin burst External L H L L H L X H L L–H Q READ cycle, begin burst External L H L L H L X H H L–H Tri-state Next X X X L H H L H L L–H READ cycle, continue burst Q READ cycle, continue burst Next X X X L H H L H H L–H Tri-state READ cycle, continue burst Next H X X L X H L H L L–H READ cycle, continue burst Next H X X L X H L H H L–H Tri-state WRITE cycle, continue burst Next X X X L H H L L X L–H WRITE cycle, continue burst Next H X X L X H L L X L–H D READ cycle, suspend burst Current X X X L H H H H L L–H Q Q D READ cycle, suspend burst Current X X X L H H H H H L–H Tri-state READ cycle, suspend burst Current H X X L X H H H L L–H READ cycle, suspend burst Current H X X L X H H H H L–H Tri-state WRITE cycle, suspend burst Current X X X L H H H L X L–H D WRITE cycle, suspend burst Current H X X L X H H L X L–H D Q Notes 5. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 6. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 8. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2. 9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05540 Rev. *N Page 11 of 37 CY7C1360C, CY7C1362C Partial Truth Table for Read/Write The Partial Truth Table for Read/Write for CY7C1360C follows. [11, 12] Function (CY7C1360C) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write byte A – (DQA and DQPA) H L H H H L Write byte B – (DQB and DQPB) H L H H L H Write bytes B, A H L H H L L Write byte C – (DQC and DQPC) H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D – (DQD and DQPD) H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Partial Truth Table for Read/Write The Partial Truth Table for Read/Write for CY7C1362C follows. [11, 12] Function (CY7C1362C) GW BWE BWB BWA Read H H X X Read H L H H Write byte A – (DQA and DQPA) H L H L Write byte B – (DQB and DQPB) H L L H Write bytes B, A H L L L Write all bytes H L L L Write all bytes L X X X Notes 11. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document Number: 38-05540 Rev. *N Page 12 of 37 CY7C1360C, CY7C1362C IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Registers The CY7C1360C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. The CY7C1360C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction Codes on page 19). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. Document Number: 38-05540 Rev. *N Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 16. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order on page 20 and Boundary Scan Order on page 21 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 19. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 19. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail in this section. Page 13 of 37 CY7C1360C, CY7C1362C The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high Z state. Document Number: 38-05540 Rev. *N SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 14 of 37 CY7C1360C, CY7C1362C TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 38-05540 Rev. *N Page 15 of 37 CY7C1360C, CY7C1362C TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Circuitry TDI Selection Circuitry Instruction Register TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TM S TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 38-05540 Rev. *N UNDEFINED Page 16 of 37 CY7C1360C, CY7C1362C TAP AC Switching Characteristics Over the Operating Range Parameter [13, 14] Description Min Max Unit 50 – ns Clock tTCYC TCK clock cycle time tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH time 20 – ns tTL TCK clock LOW time 20 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Output Times Setup Times Hold Times 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input rise and fall times ...................................................1 ns Input pulse levels ............................................... VSS to 2.5 V Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω TDO 50Ω TDO Z O= 50Ω 20pF Z O= 50Ω 20pF Notes 13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 38-05540 Rev. *N Page 17 of 37 CY7C1360C, CY7C1362C TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [15] Min Max Unit VOH1 Output HIGH voltage Description IOH = –4.0 mA Conditions VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V VOH2 Output HIGH voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V VOL1 Output LOW voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V VOL2 Output LOW voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VIH Input HIGH voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VIL Input LOW voltage VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V IX Input load current –5 5 µA GND < VIN < VDDQ Note 15. All voltages referenced to VSS (GND). Document Number: 38-05540 Rev. *N Page 18 of 37 CY7C1360C, CY7C1362C Identification Register Definitions CY7C1360C (256 K × 36) Instruction Field Revision number (31:29) 000 Device depth (28:24) [16] 01011 Description Describes the version number Reserved for internal use Device width (23:18) 119-ball BGA 101000 Defines memory type and architecture Device width (23:18) 165-ball FBGA 000000 Defines memory type and architecture 100110 Defines width and density Cypress device ID (17:12) Cypress JEDEC ID code (11:1) 00000110100 ID register presence indicator (0) 1 Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary scan order (119-ball BGA package) 71 Boundary scan order (165-ball FBGA package) 71 Instruction Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 16. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05540 Rev. *N Page 19 of 37 CY7C1360C, CY7C1362C Boundary Scan Order 165-ball FBGA CY7C1360C (256 K × 36) Bit# Ball ID Signal Name Bit# Ball ID Signal Name 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 3 A7 BWE 39 R4 A 4 B8 OE 40 P4 A 5 A8 ADSC 41 R3 A 6 B9 ADSP 42 P3 A 7 A9 ADV 43 R1 MODE 8 B10 A 44 N1 DQPD 9 A10 A 45 L2 DQD 10 C11 DQPB 46 K2 DQD 11 E10 DQB 47 J2 DQD 12 F10 DQB 48 M2 DQD 13 G10 DQB 49 M1 DQD 14 D10 DQB 50 L1 DQD 15 D11 DQB 51 K1 DQD 16 E11 DQB 52 J1 DQD 17 F11 DQB 53 Internal Internal 18 G11 DQB 54 G2 DQC 19 H11 ZZ 55 F2 DQC 20 J10 DQA 56 E2 DQC 21 K10 DQA 57 D2 DQC 22 L10 DQA 58 G1 DQC 23 M10 DQA 59 F1 DQC 24 J11 DQA 60 E1 DQC 25 K11 DQA 61 D1 DQC 26 L11 DQA 62 C1 DQPC 27 M11 DQA 63 B2 A 28 N11 DQPA 64 A2 A 29 R11 A 65 A3 CE1 30 R10 A 66 B3 CE2 31 P10 A 67 B4 BWD 32 R9 A 68 A4 BWC 33 P9 A 69 A5 BWB 34 R8 A 70 B5 BWA 35 P8 A 71 A6 CE3 36 P11 A Document Number: 38-05540 Rev. *N Page 20 of 37 CY7C1360C, CY7C1362C Boundary Scan Order 119-ball BGA CY7C1360C (256 K × 36) Bit# Ball ID Signal Name Bit# Ball ID Signal Name 1 K4 CLK 37 P4 A0 2 H4 GW 38 N4 A1 3 M4 BWE 39 R6 A 4 F4 OE 40 T5 A 5 B4 ADSC 41 T3 A 6 A4 ADSP 42 R2 A 7 G4 ADV 43 R3 MODE 8 C3 A 44 P2 DQPD 9 B3 A 45 P1 DQD 10 D6 DQPB 46 L2 DQD 11 H7 DQB 47 K1 DQD 12 G6 DQB 48 N2 DQD 13 E6 DQB 49 N1 DQD 14 D7 DQB 50 M2 DQD 15 E7 DQB 51 L1 DQD 16 F6 DQB 52 K2 DQD 17 G7 DQB 53 Internal Internal 18 H6 DQB 54 H1 DQC 19 T7 ZZ 55 G2 DQC 20 K7 DQA 56 E2 DQC 21 L6 DQA 57 D1 DQC 22 N6 DQA 58 H2 DQC 23 P7 DQA 59 G1 DQC 24 N7 DQA 60 F2 DQC 25 M6 DQA 61 E1 DQC 26 L7 DQA 62 D2 DQPC 27 K6 DQA 63 C2 A 28 P6 DQPA 64 A2 A 29 T4 A 65 E4 CE1 30 A3 A 66 B2 CE2 31 C5 A 67 L3 BWD 32 B5 A 68 G3 BWC 33 A5 A 69 G5 BWB 34 C6 A 70 L5 BWA 35 A6 A 71 Internal Internal 36 B6 A Document Number: 38-05540 Rev. *N Page 21 of 37 CY7C1360C, CY7C1362C Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Range Ambient Temperature Storage temperature ................................ –65 °C to +150 °C Commercial 0 °C to +70 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Industrial –40 °C to +85 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current .................................................... > 200 mA VDDQ 3.3 V– 5 % / 2.5 V – 5% to + 10% VDD Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit LSBU Logical single-bit upsets 25 °C 361 394 FIT/ Mb LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/ Mb Single event latch-up 85 °C 0 0.1 FIT/ Dev DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA VDD SEL * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range Parameter [17, 18] Description VDD Power supply voltage VDDQ I/O supply voltage VOH VOL Output HIGH voltage Output LOW voltage Test Conditions Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V 2.0 VDD + 0.3 V V VIH Input HIGH voltage[17] for 3.3 V I/O for 2.5 V I/O 1.7 VDD + 0.3 V V VIL Input LOW voltage[17] for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input leakage current except ZZ GND VI VDDQ and MODE –5 5 A Input current of MODE Input = VSS –30 – A Input = VDD – 5 A Input current of ZZ Input = VSS –5 – A Input = VDD – 30 A Output leakage current GND VI VDDQ, output disabled –5 5 A IX IOZ Notes 17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05540 Rev. *N Page 22 of 37 CY7C1360C, CY7C1362C Electrical Characteristics (continued) Over the Operating Range Parameter [17, 18] Description Test Conditions VDD operating supply current IDD Automatic CE power-down current – TTL inputs ISB1 VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC Min Max Unit 5 ns cycle, 200 MHz – 220 mA 6 ns cycle, 166 MHz – 180 mA 5 ns cycle, 200 MHz – 120 mA 6 ns cycle, 166 MHz – 110 mA ISB2 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, All speeds VIN 0.3 V or VIN > VDDQ – 0.3 V, f=0 – 40 mA ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, or 5 ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 200 MHz f = fMAX = 1/tCYC 6 ns cycle, 166 MHz – 110 mA – 100 mA – 40 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = 0 All speeds Capacitance Parameter [19] Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/output capacitance 100-pin TQFP Max 119-ball BGA Max 165-ball FBGA Max Unit 5 5 5 pF 5 5 5 pF 5 7 7 pF Test Conditions 100-pin TQFP Package 119-ball BGA Package 165-ball FBGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. 29.41 34.1 16.8 °C/W 6.13 14.0 3 °C/W Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V Thermal Resistance Parameter [19] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Note 19. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05540 Rev. *N Page 23 of 37 CY7C1360C, CY7C1362C AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5 V (a) INCLUDING JIG AND SCOPE Z0 = 50 VT = 1.25 V (a) Document Number: 38-05540 Rev. *N R = 351 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE 1 ns (b) GND 5 pF R =1538 (b) 90% 10% 90% 1 ns R = 1667 2.5 V OUTPUT RL = 50 GND 5 pF 2.5 V I/O Test Load OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 24 of 37 CY7C1360C, CY7C1362C Switching Characteristics Over the Operating Range Parameter [20, 21] tPOWER Description VDD(typical) to the first access [22] -200 -166 Min Max Min Max 1 – 1 – Unit ms Clock tCYC Clock cycle time 5.0 – 6.0 – ns tCH Clock HIGH 2.0 – 2.4 – ns tCL Clock LOW 2.0 – 2.4 – ns Output Times tCO Data output valid after CLK rise – 3.0 – 3.5 ns tDOH Data output hold after CLK rise 1.25 – 1.25 – ns tCLZ Clock to low Z [23, 24, 25] 1.25 – 1.25 – ns 1.25 3.0 1.25 3.5 ns [23, 24, 25] tCHZ Clock to high Z tOEV OE LOW to output valid – 3.0 – 3.5 ns tOELZ OE LOW to output low Z [23, 24, 25] 0 – 0 – ns – 3.0 – 3.5 ns tOEHZ OE HIGH to output high Z [23, 24, 25] Set-up Times tAS Address setup before CLK rise 1.5 – 1.5 – ns tADS ADSC, ADSP setup before CLK rise 1.5 – 1.5 – ns tADVS ADV setup before CLK rise 1.5 – 1.5 – ns tWES GW, BWE, BWX setup before CLK rise 1.5 – 1.5 – ns tDS Data input setup before CLK rise 1.5 – 1.5 – ns tCES Chip enable setup before CLK rise 1.5 – 1.5 – ns tAH Address hold after CLK rise 0.5 – 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – 0.5 – ns tADVH ADV hold after CLK rise 0.5 – 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.5 – 0.5 – ns tDH Data input hold after CLK rise 0.5 – 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – 0.5 – ns Hold Times Notes 20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 21. Test conditions shown in (a) of Figure 5 on page 24 unless otherwise noted. 22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 5 on page 24. Transition is measured ± 200 mV from steady-state voltage. 24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 25. This parameter is sampled and not 100% tested. Document Number: 38-05540 Rev. *N Page 25 of 37 CY7C1360C, CY7C1362C Switching Waveforms Figure 6. Read Cycle Timing [26] t CYC CLK t t ADS CH t CL t ADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t WES A3 Burst continued with new base address tWEH GW, BWE, BWx t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05540 Rev. *N Page 26 of 37 CY7C1360C, CY7C1362C Switching Waveforms (continued) Figure 7. Write Cycle Timing [27, 28] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES tWEH GW t CES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE t DS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 38-05540 Rev. *N Page 27 of 37 CY7C1360C, CY7C1362C Switching Waveforms (continued) Figure 8. Read/Write Cycle Timing [29, 30, 31] tCYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO tDH t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A5) D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) D(A6) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 30. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 31. GW is HIGH. Document Number: 38-05540 Rev. *N Page 28 of 37 CY7C1360C, CY7C1362C Switching Waveforms (continued) Figure 9. ZZ Mode Timing [32, 33] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 33. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05540 Rev. *N Page 29 of 37 CY7C1360C, CY7C1362C Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) 166 Package Diagram Ordering Code Part and Package Type CY7C1360C-166AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) CY7C1360C-166AJXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (2 chip enable) Operating Range Commercial CY7C1362C-166AJXC 200 CY7C1360C-166BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) CY7C1360C-166AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) Industrial CY7C1360C-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) Commercial CY7C1360C-200AJXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (2 chip enable) CY7C1360C-200BGC 51-85115 119-ball BGA (14 × 22 × 2.4 mm) Ordering Code Definitions CY 7 C 13XX C - XXX XX X X Temperature range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = A or AJ or BZ or BG A = 100-pin TQFP (3 chip enable) AJ = 100-pin TQFP (2 chip enable) BZ = 165-ball FBGA BG = 119-ball BGA Speed Grade: XXX = 166 MHz or 200 MHz Process Technology: C 90 nm Part Identifier: 13XX = 1360 or 1362 1360 = SCD, 256 K × 36 (9 Mb) 1362 = SCD, 512 K × 18 (9 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05540 Rev. *N Page 30 of 37 CY7C1360C, CY7C1362C Package Diagrams Figure 10. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 38-05540 Rev. *N Page 31 of 37 CY7C1360C, CY7C1362C Package Diagrams (continued) Figure 11. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115 51-85115 *D Document Number: 38-05540 Rev. *N Page 32 of 37 CY7C1360C, CY7C1362C Package Diagrams (continued) Figure 12. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *F Document Number: 38-05540 Rev. *N Page 33 of 37 CY7C1360C, CY7C1362C Acronyms Acronym Document Conventions Description Units of Measure BGA ball grid array CE chip enable °C degree Celsius CMOS complementary metal oxide semiconductor MHz megahertz EIA electronic industries alliance µA microampere FBGA fine-pitch ball grid array mA milliampere I/O input/output mm millimeter JEDEC joint electron devices engineering council ms millisecond JTAG joint test action group mV millivolt LMBU logical multi-bit upsets ns nanosecond LSB least significant bit ohm LSBU logical single-bit upsets % percent MSB most significant bit pF picofarad OE output enable V volt PBGA plastic ball grid array W watt SEL single event latch up SRAM static random access memory TAP test access port TCK test clock TDI test data-in TDO test data-out TMS test mode select TQFP thin quad flat pack TTL transistor-transistor logic Document Number: 38-05540 Rev. *N Symbol Unit of Measure Page 34 of 37 CY7C1360C, CY7C1362C Document History Page Document Title: CY7C1360C/CY7C1362C, 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Document Number: 38-05540 Rev. ECN No. Submission Date Orig. of Change ** 241690 See ECN RKF New data sheet. *A 278130 See ECN RKF Updated Boundary Scan Order (Changed to match the B rev of these devices). Updated Boundary Scan Order (Changed to match the B rev of these devices). Updated Ordering Information (Changed TQFP pkg to Lead-free TQFP in Ordering Information section, added comment of Lead-free BG and BZ packages availability). *B 248929 See ECN VBL Updated Functional Overview (Updated ZZ Mode Electrical Characteristics (Changed maximum value of IDDZZ parameter from 35 mA to 50 mA)). Updated Electrical Characteristics (Changed maximum value of ISB1 and ISB3 parameter as follows: ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA). Updated Ordering Information (Added BG and BZ pkg lead-free part numbers). *C 323636 See ECN PCI Updated Features (Changed frequency from 225 MHz to 250 MHz). Updated Selection Guide (Changed frequency from 225 MHz to 250 MHz). Updated Pin Configurations (Modified address expansion as per JEDEC Standard). Updated Electrical Characteristics (Changed frequency from 225 MHz to 250 MHz). Updated Thermal Resistance (Changed value of JA and JC parameters for 100-pin TQFP Package from 25 C/W and 9 C/W to 29.41 C/W and 6.13 C/W respectively, changed value of JA and JC parameters for 119-ball BGA Package from 25 C/W and 6 C/W to 34.1 C/W and 14.0 C/W respectively, changed value of JA and JC parameters for 165-ball FBGA Package from 27 C/W and 6 C/W to 16.8 C/W and 3.0 C/W respectively). Updated Switching Characteristics (Changed frequency from 225 MHz to 250 MHz, replaced minimum value of tCYC parameter from 4.4 ns to 4.0 ns for 250 MHz frequency). Updated Ordering Information (Removed comment of Lead-free BG and BZ packages availability). *D 332879 See ECN PCI Updated Selection Guide (Unshaded 200 and 166 MHz frequency information). Updated Pin Definitions (Added Address Expansion pins). Updated Identification Register Definitions (Splitted Device Width (23:18) into two rows, retained the same values for 165-ball FBGA, Changed Device Width (23:18) for 119-ball BGA from 000000 to 101000). Updated Electrical Characteristics (Updated Test Conditions of VOH, VOL parameters, unshaded 200 and 166 MHz frequency information). Updated Switching Characteristics (Unshaded 200 and 166 MHz frequency information). Updated Ordering Information (Updated part numbers). *E 357258 See ECN PCI Changed status from Preliminary to Final. Updated Selection Guide (Unshaded 250 MHz frequency information). Updated Electrical Characteristics (Unshaded 250 MHz frequency information, changed maximum value of ISB2 parameter from 30 to 40 mA). Updated Switching Characteristics (Unshaded 250 MHz frequency information) Updated Ordering Information (Updated part numbers). *F 377095 See ECN PCI Updated Electrical Characteristics (Updated Note 18 (Modified test condition from VDDQ < VDD to VDDQ VDD)). Document Number: 38-05540 Rev. *N Description of Change Page 35 of 37 CY7C1360C, CY7C1362C Document History Page (continued) Document Title: CY7C1360C/CY7C1362C, 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Document Number: 38-05540 Rev. ECN No. Submission Date Orig. of Change Description of Change *G 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Changed “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE” in the description of IX parameter). Updated Ordering Information (Updated part numbers, replaced Package Name column with Package Diagram in the Ordering Information table). Replaced three-state with tri-state in all instances across the document. *H 501793 See ECN VKN Updated TAP AC Switching Characteristics (Changed minimum value of tTH, tTL parameters from 25 ns to 20 ns, and maximum value of tTDOV parameter from 5 ns to 10 ns). Updated Maximum Ratings (Added Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *I 2756340 08/26/2009 VKN / AESA *J 3046851 10/04/2010 NJY Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Minor edits and updated in new template. Added Neutron Soft Error Immunity. Updated Ordering Information (By including parts that are available, and modified the disclaimer for the Ordering information). Updated in new template. *K 3052882 10/11/2010 NJY Updated Ordering Information (Removed obsolete parts). *L 3367594 09/09/2011 PRIT Updated Package Diagrams. Updated in new template. *M 3612494 05/09/2012 PRIT Updated Features (Removed 250 MHz frequency related information). Updated Functional Description (Removed the Note “For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.” and its reference). Updated Selection Guide (Removed 250 MHz frequency related information). Updated Pin Configurations (Updated Figure 1 (Removed CY7C1362C related information, updated Figure 3 (Removed CY7C1362C related information), updated Figure 4 (Removed CY7C1362C related information)). Updated Functional Overview (Removed 250 MHz frequency related information). Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1362C related information). Updated Identification Register Definitions (Removed CY7C1362C related information). Updated Scan Register Sizes (Removed “Bit Size (× 18)” column). Updated Boundary Scan Order (Removed CY7C1362C related information). Updated Boundary Scan Order (Removed CY7C1362C related information). Updated Electrical Characteristics (Removed 250 MHz frequency related information). Updated Switching Characteristics (Removed 250 MHz frequency related information). Updated Package Diagrams (spec 51-85180 (changed revision from *C to *E)). *N 3754566 09/25/2012 PRIT Updated Package Diagrams (spec 51-85115 (Changed revision from *C to *D), spec 51-85180 (Changed revision from *E to *F)). Document Number: 38-05540 Rev. *N Page 36 of 37 CY7C1360C, CY7C1362C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05540 Rev. *N Revised September 25, 2012 Page 37 of 37 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.