AMS73CAG01808RA AMS73CAG01808RA HIGH PERFORMANCE 1Gbit DDR3 SDRAM 8 BANKS X 16Mbit X 8 - H7 - I9 DDR3-1066 DDR3-1333 Clock Cycle Time ( tCK6, CWL=5 ) 2.5 ns 2.5 ns Clock Cycle Time ( tCK7, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK8, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK9, CWL=7 ) - 1.5 ns Clock Cycle Time ( tCK10, CWL=7 ) - 1.5 ns 533 MHz 667 MHz System Frequency (fCK max) Specifications - - - - - Features - Density : 1G bits Organization : 16M words x 8 bits x 8 banks Package : - 78-ball FBGA - Lead-free (RoHS compliant) and Halogen-free Power supply : VDD, VDDQ = 1.5V ± 0.075V Data rate : 1333Mbps/1066Mbps (max.) 1KB page size - Row address: A0 to A13 - Column address: A0 to A9 Eight internal banks for concurrent operation Interface : SSTL_15 Burst lengths (BL) : 8 and 4 with Burst Chop (BC) Burst type (BT) : - Sequential (8, 4 with BC) - Interleave (8, 4 with BC) CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 CAS Write Latency (CWL) : 5, 6, 7, 8 Precharge : auto precharge option for each burst access Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω) Refresh : auto-refresh, self-refresh Refresh cycles : - Average refresh period 7.8 μs at 0°C ≤ Tc ≤ +85°C 3.9 μs at +85°C < Tc ≤ +95°C Operating case temperature range - Tc = 0°C to +95°C - - - Double-data-rate architecture; two data transfers per clock cycle The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver DQS is edge-aligned with data for READs; centeraligned with data for WRITEs Differential clock inputs (CK and CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Data mask (DM) for write data Posted CAS by programmable additive latency for better command and data bus efficiency On-Die Termination (ODT) for better signal quality - Synchronous ODT - Dynamic ODT - Asynchronous ODT Multi Purpose Register (MPR) for pre-defined pattern read out ZQ calibration for DQ drive and ODT Programmable Partial Array Self-Refresh (PASR) RESET pin for Power-up sequence and reset function SRT range : Normal/extended Programmable Output driver impedance control Device Usage Chart Operating Temperature Range Package Outline 78-ball FBGA - H7 - I9 Std. L Temperature Mark 0°C ≤ Tc ≤ 95°C • • • • • Blank -40°C ≤ Tc ≤ 95°C • • • • • I AMS73CAG01808RA Rev.1.0 December 2010 Speed 1 Power AMS73CAG01808RA Part Number Information 1 AMS 2 3 4 5 7 3 C A 6 7 8 9 10 11 12 13 14 G 0 1 8 0 8 R A 15 J 16 17 18 19 I 9 ORGANIZATION & REFRESH 256Mx4, 8K : G0140 64Mx16, 8K : G0116 128Mx8, 8K : G0180 512Mx4, 8K : G0240 TEMPERATURE 128Mx16, 8K : G0216 BLANK: 256Mx8, 8K : G0280 I: TYPE 73 : DDR3 CMOS 0 - 95к -40 - 95к H: -40 - 105к E: -40 - 125к SPEED VOLTAGE A: 1.5 V H7 : 533MHz @CL7-7-7 H8 : 533MHz @CL8-8-8 I8 : 667MHz @CL8-8-8 I9 : 667MHz @CL9-9-9 BANKS 8 : 8 BANKS I/O R: SSTL_15 REV CODE SPECIAL FEATURE L : LOW POWER GRADE U : ULTRA LOW POWER GRADE PACKAGE Green PACKAGE DESCRIPTION J FBGA *GREEN: RoHS-compliant and Halogen-Free 1Gb DDR3 SDRAM Addressing Configuration 128Mb x 8 # of Bank 8 Bank Address BA0 ~ BA2 Auto precharge A10/AP Row Address A0 ~ A13 Column Address A0 ~ A9 BC switch on the fly A12/BC Page size AMS73CAG01808RA Rev. 1.0 December 2010 1 KB 2 AMS73CAG01808RA Pin Configurations 78-ball FBGA (x8 configuration) 1 2 3 A VSS VDD B VSS C VDDQ D VSSQ E VREFDQ 4 5 6 7 8 9 NC NU/TDQS VSS VDD A VSSQ DQ0 DM/TDQS VSSQ VDDQ B DQ2 DQS DQ1 DQ3 VSSQ C DQ6 DQS VDD VSS VSSQ D VDDQ DQ4 DQ7 DQ5 VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N VSS RESET A13 NC A8 VSS N 1 Ball Locations (x8) A B C Populated ball D Ball not populated E F G Top view H J (See the balls through the package) K L M N AMS73CAG01808RA Rev. 1.0 December 2010 3 2 3 4 5 6 7 8 9 AMS73CAG01808RA Signal Pin Description Pin Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self -Refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS. The ODT pin will be ignored if the Mode Register (MR1) is pro-grammed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-dent with that input data during a Write access. DM is sampled on both edges of DQS. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. A0 - A13 Input Address Inputs: Provided the row address for Active commands and the column address for Read/ Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below)The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details. RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. DQ0 - DQ7 Input/ Output Data Input/ Output: Bi-directional data bus. DQS, DQS Input/ Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signal DQS to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. AMS73CAG01808RA Rev. 1.0 December 2010 4 AMS73CAG01808RA Pin Type Function TDQS, TDQS Output Termination Data Strobe: When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ power supply: 1.5V +/- 0.075V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5V +/- 0.075V VSS Supply Ground VREFDQ Supply Reference Voltage for DQ VREFCA Supply Reference Voltage for CA ZQ Supply Reference Pin for ZQ calibration NOTE : Input only pins ( BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT and RESET ) do not supply termination. AMS73CAG01808RA Rev. 1.0 December 2010 5 AMS73CAG01808RA Simplified State Diagram CKE L Power applied Power on Reset procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL From any state RESET ZQ calibration MRS SRX REF ZQCL/ZQCS Refreshing Idle PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP READ AP READ Writing READ Reading WRITE READ AP WRITE AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Precharging Reading Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE AMS73CAG01808RA Rev. 1.0 December 2010 PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 6 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION AMS73CAG01808RA Mode Register MR0 The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while controlling the states of address pins according to the table below. BA2 BA1 0*1 0 BA0 0 A 13 A12 0*1 PPD 0 1 A10 A9 WR A8 A7 DLL TM A6 A5 CAS Latency A2 RBT CL A1 A0 Address Field Mode Register 0 BL A7 mode A3 Read Burst Type A1 A0 BL 0 No 0 Normal 0 Nibble Sequential 0 0 8 (Fixed) 1 Yes 1 Test 1 Interleave 0 1 4 or 8(on the fly) Write recovery for autoprecharge 1 0 4 (Fixed) 1 1 Reserved CAS Latency Slow exit (DLL off) A11 A10 A9 WR(cycles) A6 A5 A4 A2 Latency Fast exit (DLL on) 0 0 0 Reserved 0 0 0 0 Reserved 0 0 1 5*2 0 0 1 0 5 0 1 0 *2 0 1 0 0 6 0 1 1 0 7 1 0 0 0 8 1 0 1 0 9 1 1 0 0 10 1 1 1 0 11(Optional for DDR3-1600) 6 BA0 MRS mode 0 1 1 7*2 0 0 MR0 1 0 0 8*2 1 A3 DLL Reset BA1 0 A4 A8 DLL Control for Precharge PD A12 A11 MR1 1 0 MR2 1 1 MR3 1 0 1 10*2 1 1 0 12*2 1 1 1 Reserved *1 : BA2 and A13 are reserved for future use and must be programmed to 0 during MRS. *2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL. AMS73CAG01808RA Rev. 1.0 December 2010 7 AMS73CAG01808RA Mode Register MR1 The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE, high on BA0, low on BA1 and BA2, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A13 A12 A11 A10 A9 0*1 0 1 0*1 Qoff TDQS 0*1 Rtt_Nom A8 A7 0*1 Level A6 Rtt_Nom A5 D.I.C A9 A6 A2 A4 A3 AL A2 Rtt_Nom TDQS enable 0 Disabled 0 0 0 ODT disabled 1 Enabled 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6 1 0 0 RZQ/12*4 Write leveling enable A0 D.I.C DLL Rtt_Nom *3 A11 A7 A1 0 Disabled 1 0 1 RZQ/8*4 1 Enabled 1 1 0 Reserved 1 1 1 Reserved Address Field Mode Register 1 A0 DLL Enable 0 Enable 1 Disable Note : RZQ = 240 ohms Additive Latency A4 A3 0 0 0 (AL disabled) 0 1 CL-1 1 0 CL-2 1 1 Reserved Qoff 0 Output buffer enabled 1 *4: If RTT_Nom is used during Writes, only the values RZQ/2,RZQ/4 and RZQ/6 are allowed. *2 A12 Output buffer disabled *3: In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. A5 A1 *2 *2: Outputs disabled - DQs, DQSs, DQSs. BA1 BA0 Output Driver Impedance Control 0 0 0 1 RZQ/6 RZQ/7 1 0 RZQ/TBD 1 1 RZQ/TBD MRS mode 0 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 Note : RZQ = 240 ohms * 1 : BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS. AMS73CAG01808RA Rev. 1.0 December 2010 8 AMS73CAG01808RA Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below. BA2 BA1 BA 0 0*1 1 0 A 13 A12 A11 0*1 A10 A9 Rtt_WR A8 A7 A6 A5 A4 0*1 SRT ASR A3 A2 Self-refresh temperature range (SRT) 0 Normal operating temperature range 1 Extend temperature self-refresh (Optional) BA1 Address Field Mode Register 2 Partial Array Self Refresh (Optional) 0 0 0 Full Array 0 0 1 HalfArray (BA[2:0]=000,001,010, &011) 0 1 0 Quarter Array (BA[2:0]=000, & 001) 0 1 1 1/8th Array (BA[2:0] = 000) A6 Auto Self-refresh (ASR) 1 0 0 3/4 Array (BA[2:0] = 010,011,100,101,110, & 111) 0 Manual SR Reference (SRT) 1 0 1 HalfArray (BA[2:0] = 100, 101, 110, &111) 1 1 0 Quarter Array (BA[2:0]=110, &111) 1 1 1 1/8th Array (BA[2:0]=111) 1 A10 A9 A0 PASR*2 CWL A2 A1 A0 A7 A1 ASR enable (Optional) Rtt_WR *2 0 0 Dynamic ODT off (Write does not affect Rtt value) 0 1 RZQ/4 A5 A4 A3 CAS write Latency (CWL) 1 0 RZQ/2 0 0 0 5 (tCK(avg) ≥2.5ns) 1 1 Reserved 0 0 1 6 (2.5ns >tCK(avg) ≥1.875ns) 0 1 0 7 (1.875ns>tCK(avg) ≥ 1.5ns) BA0 0 1 1 8 (1.5ns>tCK(avg) ≥1.25ns) MRS mode 1 0 0 Reserved 0 1 Reserved 0 0 MR0 1 0 1 MR1 1 1 0 Reserved 1 0 MR2 1 1 1 Reserved 1 1 MR3 * 1 : BA2, A8, A11 ~ A13 are RFU and must be programmed to 0 during MRS. * 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available. AMS73CAG01808RA Rev. 1.0 December 2010 9 AMS73CAG01808RA Mode Register MR3 The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on CS, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below. BA 2 BA 1 BA0 0*1 1 1 A13 A12 A11 A10 A9 A8 A7 A6 A3 A2 MPR MPR Operation MPR Address BA0 MRS mode 0 0 MR0 A2 Mode Register 3 A0 MPR location 0 Predefined pattern*2 0 1 RFU 1 0 RFU 1 1 RFU 0 Normal operation* 1 0 MR2 1 Dataflow from MPR * 1 : BA2, A3 - A13 are reserved for future use (RFU) and must be programmed to 0 during MRS. * 2 : The predefined pattern will be used for read synchronization. * 3 : When MPR control is set for normal operation, MR3 A[2] = 0, MR3 A[1:0] will be ignored 10 MPR Loc Address Field 0 MR1 AMS73CAG01808RA Rev. 1.0 December 2010 A0 A1 1 MR3 A1 3 MPR 0 1 A4 0*1 BA1 1 A5 AMS73CAG01808RA Command Truth Table (a) Note 1,2,3,4 apply to the entire Command truth table (b) Note 5 applies to all Read/Write commands. [BA=Bank Address, RA=Row Address, CA=Column Address, BC=Burst Chop, X=Don’t care, V=Valid] CKE Function WE BA0 BA2 A13 A15 A12 / BC L L BA L H V V V L L V V H V V V V V H V V V X X X X X L H H H V V V V V Abbreviation Previous Cycle Current Cycle CS Mode Register Set MRS H H L L Refresh REF H H L L Self Refresh Entry SRE H L L Self Refresh Exit Single Bank Precharge Precharge all Banks SRX L H RAS CAS A10 / AP A0 A9,A11 OP Code PRE H H L L H L BA V V L V PREA H H L L H L V V V H V ACT H H L L H H BA Bank Activate Write (Fixed BL8 or BL4) 7,9,12 7,8,9,12 Row Address (RA) WR H H L H L L BA RFU V L CA Write (BL4, on the Fly) WRS4 H H L H L L BA RFU L L CA Write (BL8, on the Fly) WRS8 H H L H L L BA RFU H L CA Write with Auto Precharge (Fixed BL8 or BL4) WRA H H L H L L BA RFU V H CA Write with Auto Precharge (BL4, on the Fly) WRAS4 H H L H L L BA RFU L H CA Write with Auto Precharge (BL8, on the Fly) WRAS8 H H L H L L BA RFU H H CA Read (Fixed BL8 or BL4) Notes RD H H L H L H BA RFU V L CA Read (BL4, on the Fly) RDS4 H H L H L H BA RFU L L CA Read (BL8, on the Fly) RDS8 H H L H L H BA RFU H L CA Read with Auto Precharge (Fixed BL8 or BL4) RDA H H L H L H BA RFU V H CA Read with Auto Precharge (BL4, on the Fly) RDAS4 H H L H L H BA RFU L H CA Read with Auto Precharge (BL8, on the Fly) RDAS8 H H L H L H BA RFU H H CA No Operation NOP H H L H H H V V V V V 10 Device Deselected DES H H H X X X X X X X X 11 ZQ calibration Long ZQCL H H L H H L X X X H X ZQ calibration Short ZQCS H H Power Down Entry PDE H L Power Down Exit PDX L H L H H L X X X L X L H H H V V V V V H V X X X X X X X L H H H V V V V V H X X X X X X X X 6,12 6,12 Note : 1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device density and configuration dependant 2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function. 3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register 4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level” 5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the fly BL will be defined by MRS 6. The Power Down Mode does not perform any refresh operations. 7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 8. Self refresh exit is asynchronous. 9. VREF(Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. 10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 11. The Deselect command performs the same function as a No Operation command. 12. Refer to the CKE Truth Table for more detail with CKE transition AMS73CAG01808RA Rev. 1.0 December 2010 11 AMS73CAG01808RA CKE Truth Table (a) Note 1~7 apply to the entire Command truth table (b) CKE low is allowed only if tMRD and tMOD are satisfied CKE Current State 2 Previous Cycle (N-1) 1 Command (N) Current Cycle (N) 3 1 Action (N) 3 Notes 14, 15 RAS, CAS, WE, CS L L X Maintain Power-Down L H DESELECT or NOP Power Down Exit 11, 14 L L X Maintain Self Refresh 15, 16 L H DESELECT or NOP Self Refresh Exit 8, 12, 16 Bank(s) Active H L DESELECT or NOP Active Power Down Entry 11, 13, 14 Reading H L DESELECT or NOP Power Down Entry 11, 13, 14, 17 Power Down Self Refresh Writing H L DESELECT or NOP Power Down Entry 11, 13, 14, 17 Precharging H L DESELECT or NOP Power Down Entry 11, 13, 14, 17 Refreshing All Banks Idle H L DESELECT or NOP Precharge Power Down Entry 11 H L DESELECT or NOP Precharge Power Down Entry 11,13, 14, 18 H L REFRESH Self Refresh Entry 9, 13, 18 For more details with all signals See “Command Truth Table,” on previous page 10 Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N 3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh 6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH. 7. DESELECT and NOP are defined in the Command truth table 8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied. 9. Self Refresh mode can only be entered from the All Banks Idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. 12. Valid commands for Self Refresh Exit are NOP and DESELECT only. 13. Self Refresh can not be entered while Read or Write operations. See ‘Self-Refresh Operation” and ‘Power-Down Modes” on later section for a detailed list of restrictions. 14. The Power Down does not perform any refresh operations. 15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. It also applies to Address pins 16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. 17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered, otherwise Active Power Down is entered 18. ‘Idle state’ means that all banks are closed(tRP,tDAL,etc. satisfied) and CKE is high and all timings from previous operations are satisfied (tMRD,tMOD,tRFC,tZQinit,tZQoper,tZQCS,etc)as well as all SRF exit and Power Down exit parameters are satisfied (tXS,tXP,tXPDLL,etc) AMS73CAG01808RA Rev. 1.0 December 2010 12 AMS73CAG01808RA Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 °C 1,2 NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Operating Temperature Condition Symbol Parameter Rating Units Notes TC Operating case temperature 0 to +95 °C 1,2,3 NOTE : 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9μs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). Recommended DC Operating Conditions Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply voltage 1.425 1.5 1.575 V 1,2 VDDQ Supply voltage for Output 1.425 1.5 1.575 V 1,2 NOTE : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. AMS73CAG01808RA Rev. 1.0 December 2010 13 AMS73CAG01808RA AC and DC Input Measurement Levels Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter Min. Max. Units Notes VIHCA (DC100) DC input logic high VREF + 0.100 VDD V 1 VILCA (DC100) DC input logic low VSS VREF - 0.100 V 1 VIHCA (AC175) AC input logic high VREF + 0.175 - V 1,2 VILCA (AC175) AC input logic low - VREF - 0.175 V 1,2 VIHCA (AC150) AC input logic high VREF + 0.150 - V 1,2 VILCA (AC150) AC input logic low - VREF - 0.150 V 1,2 VREFCA (DC) Reference voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3,4 NOTE : 1. For input only pins except /RESET : VREF = VREFCA (DC). 2. See Overshoot and Undershoot Specifications section. 3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) by more than ±1% VDD (for reference : approx. ±15 mV). 4. For reference : approx. VDD/2 ±15 mV. Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter Min. Max. Units Notes VIHDQ (DC100) DC input logic high VREF + 0.100 VDD V 1 VILDQ (DC100) DC input logic low VSS VREF - 0.100 V 1 VIHDQ (AC175) AC input logic high VREF + 0.175 - V 1,2 VILDQ (AC175) AC input logic low - VREF - 0.175 V 1,2 VIHDQ (AC150) AC input logic high VREF + 0.150 - V 1,2 VILDQ (AC150) AC input logic low - VREF - 0.150 V 1,2 VREFDQ (DC) Reference voltage for DQ, DM inputs 0.49 * VDD 0.51 * VDD V 3,4 NOTE : 1. For DQ and DM : VREF = VREFDQ (DC). 2. See Overshoot and Undershoot Specifications section. 3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ (DC) by more than ±1% VDD (for reference: approx. ±15 mV). 4. For reference: approx. VDD/2 ±15 mV. AMS73CAG01808RA Rev. 1.0 December 2010 14 AMS73CAG01808RA VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in figure VREF(DC) tolerance and VREF AC-Noise limits. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table of “Single-Ended AC and DC Input Levels for Command and Address”. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD. voltage VDD VSS time VREF(DC) tolerance and VREF AC-Noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in figure above, VREF(DC) tolerance and VREF ACNoise limits. This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings. AMS73CAG01808RA Rev. 1.0 December 2010 15 AMS73CAG01808RA AC and DC Logic Input Levels for Differential Signals Differential signals definition tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK) VIH.DIFF.AC.MIN VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and "time above ac level" tDVAC Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) Differential AC and DC Input Levels Symbol Parameter Min. Max. Units Notes VIHdiff Differential input high +0.2 NOTE 3 V 1 VILdiff Differential input low NOTE 3 -0.2 V 1 VIHdiff(AC) Differential input high AC 2 x (VIH(AC) - VREF) NOTE 3 V 2 VILdiff(AC) Differential input low AC NOTE 3 2 x (VREF - VIL(AC)) V 2 NOTE : 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot specification". AMS73CAG01808RA Rev. 1.0 December 2010 16 AMS73CAG01808RA Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV Min. Max. Min. Max. > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEH min / VSEL max [ approximately equal to the AC-levels ( VIH(AC) / VIL(AC) ) for Address/command signals ] in every half-cycle. DQS, DQS have to reach VSEH min / VSEL max [ approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals ] in every half-cycle proceeding and following a valid transition. Note that the applicable AC-levels for Address/command and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC) / VIL150(AC) is used for Address/command signals, then these AC-levels apply also for the single-ended components of differential CK and CK. AMS73CAG01808RA Rev. 1.0 December 2010 17 AMS73CAG01808RA VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL VSS or VSSQ time Single-ended requirement for differential signals Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. Single-ended levels for CK, DQS, CK, DQS Symbol VSEH VSEL Parameter Min. Max. Units Notes Single-ended high-level for strobes (VDD/2) + 0.175 NOTE 3 V 1,2 Single-ended high-level for CK, CK (VDD/2) + 0.175 NOTE 3 V 1,2 Single-ended low-level for strobes NOTE 3 (VDD/2) - 0.175 V 1,2 Single-ended low-level for CK, CK NOTE 3 (VDD/2) - 0.175 V 1,2 NOTE : 1. For CK, CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on VREFCA; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended components of differential signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot specifications”. AMS73CAG01808RA Rev. 1.0 December 2010 18 AMS73CAG01808RA To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS VIX Definition Cross point voltage for differential input signals ( CK, DQS ) Symbol Parameter VIX Differential Input Cross Point Voltage relative to VDD/2 for CK, CK VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS Min. Max. Units -150 150 mV -175 175 mV -150 150 mV Notes 1 NOTE :1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 +/- 250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to the table of Cross point voltage for differential input signals (CK, DQS) for VSEL and VSEH standard values. Differential input slew rate definition Measured Description Defined by From To Differential input slew rate for rising edge ( CK-CK and DQS-DQS ) VILdiff (max) VIHdiff (min) VIHdiff (min) - VILdiff (max) Delta TRdiff Differential input slew rate for falling edge ( CK-CK and DQS-DQS ) VIHdiff (min) VILdiff (max) VIHdiff (min) - VILdiff (max) Delta TFdiff NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds. VIHdiffmin 0 VILdiffmax delta TRdiff delta TFdiff Differential Input Slew Rate definition for DQS, DQS, and CK, CK AMS73CAG01808RA Rev. 1.0 December 2010 19 AMS73CAG01808RA IDD Specification ( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V ) Conditions Symbol - H7 - I9 Unit Operating One Bank Active-Precharge Current; CKE: High; External clock: On; tCK, nRC, nRAS, CL: see timing used table; BL: 8; AL: 0; CS: High between ACT and PRE; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD0 85 95 mA Operating One Bank Active-Read-Precharge Current; CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see timing used table; BL: 81; AL: 0; CS: High between ACT, RD and PRE; Command, Address, Data IO: partially toggling; DM:stable at 0; Bank Activity: Cycling with one bank active at a time; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD1 100 110 mA Precharge Power-Down Current Slow Exit; CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable IDD2P0 at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit 13 14 mA Precharge Power-Down Current Fast Exit; CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM:stable IDD2P1 at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit 35 40 mA Precharge Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 55 60 mA Precharge Standby ODT Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0; IDD2NT Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: toggling 55 60 mA Precharge Quiet Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD2Q 50 55 mA Active Power-Down Current; CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3P 35 40 mA Active Standby Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: partially toggling; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3N 60 65 mA Operating Burst Read Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: High between RD; Command, Address: par-tially toggling; Data IO: seamless read data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD4R 160 200 mA Operating Burst Write Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: High between WR; Command, Address: par-tially toggling; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks IDD4W open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH 170 210 mA AMS73CAG01808RA Rev. 1.0 December 2010 20 IDD2N AMS73CAG01808RA Conditions Symbol - H7 - I9 Unit Burst Refresh Current; CKE: High; External clock: On; tCK, CL, nRFC: see timing used table; BL: 8; AL: 0; CS: High between REF; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD5B 260 270 mA Self Refresh Current: Normal Temperature Range; TCASE: 0- 85°C; Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normal; CKE: Low; External clock: Off; CK and CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: FLOATING IDD6 10 10 mA 18 18 mA Self Refresh Current: Extended Temperature Range; TCASE: 0- 95°C; Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Extended; CKE: Low; External clock: Off; CK and CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: IDD6ET stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: FLOATING Operating Bank Interleave Read Current; CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see timing used table; BL: 8; AL: CL-1; CS: High between ACT and RDA; Command, Address: partially toggling; Data IO: read data bursts with different data between one burst and the next one; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD7 270 310 mA RESET Low Current; RESET: Low; External clock: off; CK and CK: LOW; CKE: FLOATING; CS, Command, Address, Data IO: FLOATING; ODT Signal : FLOATING IDD8 8 8 mA NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range 6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM 7) Read Burst type : Nibble Sequential, set MR0 A[3]=0B Timing used for IDD and IDDQ Measured - Loop Patterns Speed CL-nRCD-nRP DDR3-1066 7-7-7 tCKmin DDR3-1333 8-8-8 8-8-8 1.875 9-9-9 1.5 Unit ns CL 7 8 8 9 nCK tRCDmin 7 8 8 9 nCK tRCmin 27 28 33 34 nCK tRASmin tRPmin 20 7 20 8 8 nCK 9 nCK tFAW 20 20 nCK tRRD 4 4 nCK tRFC - 1Gb 59 74 nCK AMS73CAG01808RA Rev. 1.0 December 2010 21 AMS73CAG01808RA DDR3-1066 Speed Bins Speed Bin -H7 (DDR3-1066) CL-nRCD-nRP 7-7-7 Parameter Symbol Internal read command to first data Min Max Unit Notes tAA 13.125 20 ns 9 tRCD 13.125 - ns 9 Precharge command period tRP 13.125 - ns 9 Active to active/auto-refresh command time tRC 50.625 - ns 9 Active to read or write delay time Active to precharge command period Average Clock Cycle Time tRAS 37.5 9 * tREFI ns 8 CWL = 5 tCK(avg) 2.5 3.3 ns 1,2,3,6 CWL = 6 tCK(avg) Reserved Reserved ns 1,2,3,4 CL = 7 CWL = 5 tCK(avg) Reserved Reserved ns 4 CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3,4 CL = 8 CWL = 5 tCK(avg) Reserved Reserved ns 4 CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3 CL = 6 Supported CL setting Supported CWL setting 6, 7, 8 nCK 5, 6 nCK DDR3-1333 Speed Bins Speed Bin -I9 (DDR3-1333) CL-nRCD-nRP 9-9-9 Unit Notes 20 ns 9 13.125 - ns 9 tRP 13.125 - ns 9 Active to active/auto-refresh command time tRC 49.125 - ns 9 Active to precharge command period tRAS 36 9 * tREFI ns 8 CWL = 5 tCK(avg) 2.5 3.3 ns 1,2,3,7 CWL = 6 tCK(avg) Reserved Reserved ns 1,2,3,4,7 Parameter Internal read command to first data Active to read or write delay time Precharge command period Average Clock Cycle Time CL = 6 Symbol Min Max tAA 13.125 tRCD CWL = 7 tCK(avg) Reserved Reserved ns 4 CWL = 5 tCK(avg) Reserved Reserved ns 4 CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3,4,7 CWL = 7 tCK(avg) Reserved Reserved ns 1,2,3,4 CWL = 5 tCK(avg) Reserved Reserved ns 4 CWL = 6 tCK(avg) 1.875 < 2.5 ns 1,2,3,7 CWL = 7 tCK(avg) Reserved Reserved ns 1,2,3,4 CL = 9 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4 CWL = 7 tCK(avg) 1.5 < 1.875 ns 1,2,3,4 CL = 10 CWL = 5, 6 tCK(avg) Reserved Reserved ns 4 CWL = 7 tCK(avg) 1.5 < 1.875 ns 1,2,3 CL = 7 CL = 8 Supported CL setting Supported CWL setting AMS73CAG01808RA Rev. 1.0 December 2010 22 6, 7, 8, 9, 10 nCK 5, 6, 7 nCK AMS73CAG01808RA Speed Bin Table Notes NOTE : 1. The CL setting and CWL setting result in tCK(avg) Min and tCK(avg) Max requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(avg) Min limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next "Supported CL". 3. tCK(avg) Max limits: Calculate tCK(avg) = tAA Max / CL Selected and round the resulting tCK(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(avg) Max corresponding to CL selected. 4. "Reserved" settings are not allowed. User must program a different value. 5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 8. tREFI depends on operating case temperature (Tc). 9. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333(CL9) devices supporting down binning to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9). AMS73CAG01808RA Rev. 1.0 December 2010 23 AMS73CAG01808RA AC Characteristics ( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V ) Parameter Symbol -H7 (DDR3-1066) -I9 (DDR3-1333) Min Min Max Max See Speed Bins Table Unit Average clock cycle time tCK(avg) Minimum clock cycle time (DLL-off mode) tCK (DLL-off) 8 - 8 - ns Average CK high level width tCH(avg) 0.47 0.53 0.47 0.53 tCK(avg) Average CK low level width tCL(avg) 0.47 0.53 0.47 0.53 tCK(avg) 7.5 - 6 - ns 4 - 4 - nCK Note ns 6 Active Bank A to Active Bank B command period tRRD Four activate window tFAW 37.5 - 30 - ns Address and Control input hold time (VIH/VIL (DC100) levels) tIH(base) DC100 200 - 140 - ps 16 Address and Control input setup time (VIH/VIL (AC175) levels) tIS(base) AC175 125 - 65 - ps 16 Address and Control input setup time (VIH/VIL (AC150) levels) tIS(base) AC150 125+150 - 65+125 - ps 16,24 DQ and DM input hold time (VIH/VIL (DC) levels) tDH(base) 100 - 65 - ps 17 DQ and DM input setup time (VIH/VIL (AC) levels) tDS(base) 25 - 30 - ps 17 Control and Address Input pulse width for each input tIPW 780 - 620 - ps 25 DQ and DM Input pulse width for each input tDIPW 490 - 400 - ps 25 DQ high impedance time tHZ(DQ) - 300 - 250 ps 13,14 DQ low impedance time tLZ(DQ) -600 300 -500 250 ps 13,14 DQS, DQS high impedance time (RL + BL/2 reference) tHZ(DQS) - 300 - 250 ps 13,14 DQS, DQS low impedance time (RL - 1 reference) tLZ(DQS) -600 300 -500 250 ps 13,14 tDQSQ - 150 - 125 ps 12,13 DQS, DQS to DQ Skew, per group, per access CAS to CAS command delay tCCD 4 - 4 - nCK DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - tCK(avg) 12,13 DQS, DQS rising edge output access time from rising CK, CK tDQSCK -300 300 -255 255 ps 12,13 DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 -0.25 0.25 tCK(avg) DQS falling edge hold time from rising CK tDSH 0.2 - 0.2 - tCK(avg) 29 DQS falling edge setup time to rising CK tDSS 0.2 - 0.2 - tCK(avg) 29 DQS input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK(avg) 27,28 AMS73CAG01808RA Rev. 1.0 December 2010 24 AMS73CAG01808RA -H7 (DDR3-1066) -I9 (DDR3-1333) Symbol Min Max Min Max Unit Note DQS input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK(avg) 26,28 DQS output high time tQSH 0.38 - 0.40 - tCK(avg) 12,13 DQS output low time tQSL 0.38 - 0.40 - tCK(avg) 12,13 Mode register set command cycle time tMRD 4 - 4 - nCK Mode register set command update delay tMOD 15 - 15 - ns 12 - 12 - nCK Read preamble time tRPRE 0.9 - 0.9 - tCK(avg) 13,19 Read postamble time tRPST 0.3 - 0.3 - tCK(avg) 11,13 Write preamble time tWPRE 0.9 - 0.9 - tCK(avg) 1 Write postamble time tWPST 0.3 - 0.3 - tCK(avg) 1 tWR 15 - 15 - ns Parameter Write recovery time Auto precharge write recovery + Precharge time Multi-purpose register recovery time tDAL(min) tMPRR WR + roundup [tRP / tCK(avg)] nCK 1 - 1 - nCK 22 7.5 - 7.5 - ns 18 4 - 4 - nCK 18 7.5 - 7.5 - ns 4 - 4 - nCK tCKE(min) +1nCK - tCKE(min) +1nCK - 10 - 10 - ns 5 - 5 - nCK 10 - 10 - ns 5 - 5 - nCK tRFC(min) +10 - tRFC(min) +10 - 5 - 5 - tXSDLL tDLLK (min) - tDLLK (min) - Auto-refresh to Active/Auto-refresh command time tRFC 110 - 110 - Average Periodic Refresh Interval 0°C < Tc < +85°C tREFI - 7.8 - 7.8 Average Periodic Refresh Interval +85°C < Tc < +95°C tREFI - 3.9 - 3.9 CKE minimum high and low pulse width tCKE 5.625 - 5.625 - ns 3 - 3 - nCK Exit reset from CKE high to a valid command tRFC(min) +10 - tRFC(min) +10 - tXPR 5 - 5 - nCK DLL locking time tDLLK 512 - 512 - nCK Internal write to read command delay Internal read to precharge command delay tWTR tRTP Minimum CKE low width for Self-refresh entry to exit timing tCKESR Valid clock requirement after Selfrefresh entry or Power-down entry tCKSRE Valid clock requirement before Selfrefresh exit or Power-down exit tCKSRX Exit Self-refresh to commands not requiring a locked DLL Exit Self-refresh to commands requiring a locked DLL AMS73CAG01808RA Rev. 1.0 December 2010 tXS 25 ns nCK nCK ns μs μs ns AMS73CAG01808RA -H7 (DDR3-1066) -I9 (DDR3-1333) Symbol Min Max Min Max tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI 24 - 24 - ns 2 10 - 10 - nCK 2 7.5 - 6 - ns 3 - 3 - nCK tCPDED 1 - 1 - nCK Timing of ACT command to Power-down entry tACTPDEN 1 - 1 Timing of PRE command to Power-down entry tPRPDEN 1 - 1 Timing of RD/RDA command to Power-down entry tRDPDEN RL+4+1 - RL+4+1 Timing of WR command to Power-down entry (BL8OTF, BL8MRS, BL4OTF) tWRPDEN (min) WL + 4 + [tWR/tCK(avg)] nCK 9 Timing of WR command to Power-down entry (BC4MRS) tWRPDEN (min) WL + 2 + [tWR/tCK(avg)] nCK 9 nCK 10 nCK 10 nCK 20,21 7 Parameter Power-down entry to exit time Exit precharge power-down with DLL frozen to commands requiring a locked DLL Exit power-down with DLL on to any valid command; Exit precharge power-down with DLL frozen to commands not requiring a locked DLL Command pass disable delay tXPDLL Unit 15 tXP - nCK 20 nCK 20 nCK Timing of WRA command to Power-down tWRAPDEN entry (BL8OTF, BL8MRS, BL4OTF) WL+4 +WR+1 - WL+4 +WR+1 - Timing of WRA command to Power-down tWRAPDEN entry (BC4MRS) WL+2 +WR+1 - WL+2 +WR+1 - 1 - 1 Timing of MRS command to Power-down tMRSPDEN entry tMOD (min) - tMOD (min) - RTT turn-on tAON -300 300 -250 250 ps tAONPD 2 8.5 2 8.5 ns tAOF 0.3 0.7 0.3 0.7 tCK(avg) tAOFPD 2 8.5 2 8.5 ns 4 - 4 6 - 6 Timing of REF command to Power-down entry Asynchronous RTT turn-on delay (Power-down with DLL frozen) RTT_Nom and RTT_WR turn-off time from ODTLoff reference Asynchronous RTT turn-off delay (Power-down with DLL frozen) Note tREFPDEN ODT high time without write command or with write command and BC4 ODTH4 ODT high time with Write command and BL8 ODTH8 - - 8 nCK nCK RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 tCK(avg) Power-up and reset calibration time tZQinit 512 - 512 - nCK Normal operation full calibration time tZQoper 256 - 256 - nCK Normal operation short calibration time tZQCS 64 - 64 - nCK 23 First DQS pulse rising edge after write leveling mode is programmed tWLMRD 40 nCK 3 AMS73CAG01808RA Rev. 1.0 December 2010 26 - 40 - AMS73CAG01808RA -H7 (DDR3-1066) -I9 (DDR3-1333) Symbol Min Min tWLDQSEN 25 Write leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing tWLS 245 Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing tWLH 245 Write leveling output delay tWLO 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns Parameter DQS, DQS delay after write leveling mode is pro-grammed Max - 25 195 195 Max - Unit Note nCK 3 ps ps Absolute clock period tCK(abs) Absolute clock high pulse width tCH(abs) 0.43 - 0.43 - tCK(avg) 30 Absolute clock low pulse width tCL(abs) 0.43 - 0.43 - tCK(avg) 31 Clock period jitter tJIT(per) -90 90 -80 80 ps tJIT(per,lck) -80 80 -70 70 ps tJIT(cc) - 180 - 160 ps Cycle to cycle period jitter during DLL locking period tJIT(cc,lck) - 160 - 140 ps Cumulative error across 2 cycles tERR(2per) -132 132 -118 118 ps Cumulative error across 3 cycles tERR(3per) -157 157 -140 140 ps Cumulative error across 4 cycles tERR(4per) -175 175 -155 155 ps Cumulative error across 5 cycles tERR(5per) -188 188 -168 168 ps Cumulative error across 6 cycles tERR(6per) -200 200 -177 177 ps Cumulative error across 7 cycles tERR(7per) -209 209 -186 186 ps Cumulative error across 8 cycles tERR(8per) -217 217 -193 193 ps Cumulative error across 9 cycles tERR(9per) -224 224 -200 200 ps Cumulative error across 10 cycles tERR(10per) -231 231 -205 205 ps Cumulative error across 11 cycles tERR(11per) -237 237 -210 210 ps Cumulative error across 12 cycles tERR(12per) -242 242 -215 215 ps Cumulative error across n = 13,14,...49,50 cycles tERR(nper) Clock period jitter during DLL locking period Cycle to cycle period jitter AMS73CAG01808RA Rev. 1.0 December 2010 tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max 27 ps ps 32 AMS73CAG01808RA Notes for AC Electrical Characteristics NOTE : 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and READA) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rounded-up to next higher integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon. 8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is when the bus is in high impedance. Both are measured from ODTLoff. 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles as programmed in MR0. 11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. Refer to the section of tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Notes for definition and measurement method. 15. tREFI depends on operating case temperature (Tc). 16. tIS(base) and tIH(base) values are for 1V/ns command/addresss single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section. 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and and Slew Rate Derating section. 18. Start of internal write transaction is defined as follows ; For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL. 19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operation. 21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. AMS73CAG01808RA Rev. 1.0 December 2010 28 AMS73CAG01808RA 24. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns]. 25. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 26. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS, as measured from one falling edge to the next consecutive rising edge. 27. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS, as measured from one rising edge to the next consecutive falling edge. 28. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 29. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 30. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 31. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 32. n = from 13 cycles to 50 cycles. This row defines 38 parameters. AMS73CAG01808RA Rev. 1.0 December 2010 29 AMS73CAG01808RA Package Diagram (x8) 78-Ball Fine Pitch Ball Grid Array Outline AMS73CAG01808RA Rev. 1.0 December 2010 30 AMS73CAG01808RA 31