LTC1857/LTC1858/LTC1859
8-Channel, 12-/14-/16-Bit,
100ksps SoftSpan A/D Converters
with Shutdown
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FEATURES
DESCRIPTIO
■
The LTC®1857/LTC1858/LTC1859 are 8-channel, low
power, 12-/14-/16-bit, 100ksps, analog-to-digital converters (ADCs). These SoftSpanTM ADCs can be softwareprogrammed for 0V to 5V, 0V to 10V, ±5V or ±10V input
spans and operate from a single 5V supply. The 8-channel multiplexer can be programmed for single-ended
inputs or pairs of differential inputs or combinations of
both. In addition, all channels are fault protected to ±25V.
A fault condition on any channel will not affect the
conversion result of the selected channel.
■
■
■
■
■
■
■
■
■
■
■
Sample Rate: 100ksps
8-Channel Multiplexer with ±25V Protection
Single 5V Supply
Software-Programmable Input Ranges:
0V to 5V, 0V to 10V, ±5V or ±10V
Single Ended or Differential
±3LSB INL for the LTC1859, ±1.5LSB INL for the
LTC1858, ±1LSB INL for the LTC1857
Power Dissipation: 40mW (Typ)
SPI/MICROWIRETM Compatible Serial I/O
Power Shutdown: Nap and Sleep
Signal-to-Noise Ratio: 87dB (Typ) for the LTC1859
Operates with Internal or External Reference
Internal Synchronized Clock
28-Pin SSOP Package
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APPLICATIO S
■
■
■
■
An onboard high performance sample-and-hold and precision reference minimize external components. The low
40mW power dissipation is made even more attractive
with two user selectable power shutdown modes. DC specifications include ±3LSB INL for the LTC1859, ±1.5LSB
INL for the LTC1858 and ±1LSB for the LTC1857.
The internal clock is trimmed for 5µs maximum conversion time and the sampling rate is guaranteed at 100ksps.
A separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
Industrial Process Control
Multiplexed Data Acquisition Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
, LTC and LT are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
100kHz, 12-Bit/14-Bit/16-Bit Sampling ADC
2.0
1.5
µP
CONTROL
LINES
1.0
10µF
10µF
3V TO 5V
5V
5V
10µF
INL (LSB)
SOFTWARE-PROGRAMMABLE
SINGLE-ENDED OR
DIFFERENTIAL INPUTS
(0V TO 5V, 0V TO 10V,
±5V OR ±10V)
CONVST
COM
CH0 LTC1857/ RD
CH1 LTC1858/ SCK
CH2 LTC1859 SDI
DGND
CH3
SDO
CH4
BUSY
CH5
OVDD
CH6
DVDD
CH7
AVDD
MUXOUT +
MUXOUT –
AGND3
ADC+
AGND2
ADC–
REFCOMP
AGND1
VREF
LTC1859 Typical INL Curve
0.5
0
– 0.5
–1.0
–1.5
2.5V
1µF
10µF
–2.0
–32768
–16384
0
CODE
16384
32767
1859 TA02
185789f
1
LTC1857/LTC1858/LTC1859
W W
W
AXI U
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ABSOLUTE
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PACKAGE/ORDER I FOR ATIO
RATI GS
(Notes 1, 2)
TOP VIEW
Supply Voltage (OVDD = DVDD = AVDD = VDD) ........... 6V
Ground Voltage Difference
DGND, AGND1, AGND2, AGND3 ...................... ±0.3V
Analog Input Voltage
ADC+, ADC–
(Note 3) ...................(AGND1 – 0.3V) to (AVDD + 0.3V)
CH0-CH7, COM .................................................. ±25V
Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10V
Digital Output Voltage .... (DGND – 0.3V) to (DVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1857C/LTC1858C/LTC1859C ............ 0°C to 70°C
LTC1857I/LTC1858I/LTC1859I .......... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
COM
1
28 CONVST
CH0
2
27 RD
CH1
3
26 SCK
CH2
4
25 SDI
CH3
5
24 DGND
CH4
6
23 SDO
CH5
7
22 BUSY
CH6
8
21 OVDD
CH7
9
20 DVDD
MUXOUT + 10
19 AVDD
MUXOUT – 11
18 AGND3
ADC + 12
17 AGND2
ADC – 13
16 REFCOMP
AGND1 14
ORDER PART
NUMBER
LTC1857CG
LTC1857IG
LTC1858CG
LTC1858IG
LTC1859CG
LTC1859IG
15 VREF
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER A D
ULTIPLEXER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
MUXOUT connected to ADC inputs. (Notes 5, 6)
PARAMETER
Resolution
No Missing Codes
Transition Noise
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
Bipolar Zero Error Drift
Bipolar Zero Error Match
Unipolar Zero Error
Unipolar Zero Error Drift
Unipolar Zero Error Match
Bipolar Full-Scale Error
Bipolar Full-Scale Error Drift
Bipolar Full-Scale Error Match
Unipolar Full-Scale Error
Unipolar Full-Scale Error Drift
Unipolar Full-Scale Error Match
Input Common Mode Range
Input Common Mode Rejection Ratio
CONDITIONS
●
●
MIN
12
12
LTC1857
TYP MAX
MIN
14
14
0.06
(Notes 7, 15)
(Note 15)
(Note 8)
●
●
●
±0.1
(Note 8)
±0.1
±1
External Reference (Note 11) ●
Internal Reference (Note 11)
External Reference
Internal Reference
External Reference (Note 11) ●
Internal Reference (Note 11)
External Reference
Internal Reference
–1
●
●
±1
±2.5
±7
±5
±0.45
±0.75
0 to 10
±10
96
±10
±25
±2
±0.15
±0.40
±8
±0.1
±0.4
±2.5
±7
±10
±0.25
±0.85
±2.5
±7
±5
Unipolar Mode
Bipolar Mode
±0.1
±1
±2.5
±7
±3
4
±28
–2
±6
±15
±1.2
±0.35
±0.45
±2.5
±7
LTC1859
TYP MAX
1
±1.5
1.5
±17
±4
±6
●
MIN
16
15
0.26
±1
1
±9
–1
LTC1858
TYP MAX
±15
±0.20
±0.75
±2.5
±7
±12
0 to 10
±10
96
±15
0 to 10
±10
96
UNITS
Bits
Bits
LSBRMS
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
LSB
%
%
ppm/°C
ppm/°C
LSB
%
%
ppm/°C
ppm/°C
LSB
V
V
dB
185789f
2
LTC1857/LTC1858/LTC1859
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U
A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Analog Input Range
CH0 to CH7, COM
0 to 5, 0 to 10
±5, ±10
V
V
ADC+, ADC– (Note 3)
0 to 2.048
0 to 4.096
ADC – ±1.024
ADC – ±2.048
V
V
V
V
Impedance
MIN
TYP
UNITS
CH0 to CH7, COM
Unipolar
Bipolar
42
31
kΩ
kΩ
MUXOUT+ , MUXOUT–
Unipolar
Bipolar
10
5
kΩ
kΩ
Hi-Z
kΩ
5
pF
0V to 2.048V, ±1.024V
0V to 4.096V, ±2.048V
24
12
pF
pF
Hold Mode ADC+, ADC–
4
pF
ADC+, ADC–
Capacitance
MAX
CH0 to CH7, COM
Sample Mode ADC+, ADC–
Input Leakage Current
ADC+, ADC–, CONVST = Low
●
±1
µA
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. MUXOUT connected to ADC inputs. (Notes 5 and 12)
SYMBOL
PARAMETER
CONDITIONS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal
THD
MIN
LTC1857
TYP MAX
MIN
LTC1858
TYP MAX
MIN
LTC1859
TYP MAX
UNITS
74
83
87
dB
Total Harmonic Distortion
1kHz Input Signal,
First Five Harmonics
–101
–101
–101
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
–103
–103
–103
dB
Channel-to-Channel Isolation
1kHz Input Signal
–120
–120
–120
1
1
1
–70
–70
–70
–3dB Input Bandwidth
Aperture Delay
Aperture Jitter
60
Transient Response
Full-Scale Step
(Note 9)
Overvoltage Recovery
(Note 13)
60
4
150
ns
60
4
150
dB
MHz
ps
4
150
µs
ns
185789f
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LTC1857/LTC1858/LTC1859
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I TER AL REFERE CE CHARACTERISTICS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Temperature Coefficient
IOUT = 0
VREF Output Impedance
–0.1mA ≤ IOUT ≤ 0.1mA
VREFCOMP Output Voltage
IOUT = 0
●
MIN
TYP
MAX
UNITS
2.475
2.50
2.525
V
ppm/°C
±10
8
kΩ
4.096
V
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V, IO = –10µA, OVDD = VDD
VDD = 4.75V, IO = –200µA, OVDD = VDD
●
VDD = 4.75V, IO = 160µA, OVDD = VDD
VDD = 4.75V, IO = 1.6mA, OVDD = VDD
●
●
TYP
MAX
UNITS
2.4
V
0.8
V
±10
µA
5
pF
4.74
V
V
4
0.05
0.10
0.4
V
V
±10
µA
IOZ
Hi-Z Output Leakage
VOUT = 0V to VDD, RD = High
COZ
Hi-Z Output Capacitance
RD = High
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
(Notes 9 and 10)
4.75
5.00
5.25
V
CONVST = 0V or 5V
8.0
5.5
8.0
13
8
15
CONVST = 0V or 5V
40.0
27.5
40.0
Positive Supply Current
Nap Mode
Sleep Mode
Power Dissipation
Nap Mode
Sleep Mode
●
mA
mA
µA
mW
mW
µW
185789f
4
LTC1857/LTC1858/LTC1859
WU
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX) Maximum Sampling Frequency
tCONV
Conversion Time
tACQ
Acquisition Time
CONDITIONS
MIN
Through CH0 to CH7 Inputs
Through ADC+ , ADC– Only
●
TYP
MAX
100
kHz
kHz
166
●
Through CH0 to CH7 Inputs
Through ADC+ , ADC– Only
●
●
4
5
µs
4
µs
µs
20
MHz
1
fSCK
SCK Frequency
(Note 14)
tr
SDO Rise Time
See Test Circuits
tf
SDO Fall Time
See Test Circuits
t1
CONVST High Time
t2
CONVST to BUSY Delay
t3
SCK Period
●
50
ns
t4
SCK High
●
10
ns
t5
SCK Low
●
10
ns
t6
Delay Time, SCK↓ to SDO Valid
CL = 25pF, See Test Circuits
●
t7
Time from Previous SDO Data Remains
Valid After SCK↓
CL = 25pF, See Test Circuits
●
t8
SDO Valid After RD↓
CL = 25pF, See Test Circuits
●
t9
RD↓ to SCK Setup Time
●
20
ns
t10
SDI Setup Time Before SCK↑
●
0
ns
t11
SDI Hold Time After SCK↑
●
7
t12
SDO Valid Before BUSY↑
RD = Low, CL = 25pF, See Test Circuits
●
5
t13
Bus Relinquish Time
See Test Circuits
●
6
ns
6
●
CL = 25pF, See Test Circuits
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
0
UNITS
ns
40
●
ns
15
25
5
30
45
20
11
ns
ns
ns
30
ns
ns
20
10
ns
30
ns
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specifications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 14: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specification is referred to the ±10V input range.
185789f
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LTC1857/LTC1858/LTC1859
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC1859 Typical INL Curve
0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
– 0.5
– 0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–32768
–16384
0
CODE
16384
MAGNITUDE (dB)
2.0
DNL (LSB)
INL (LSB)
2.0
–2.0
–32768
32767
–16384
0
CODE
16384
1859 TA02
84
82
80
78
1.0
–80
–90
–100
76
74
–110
1
100
10
INPUT FREQUENCY (kHz)
1859 G04
BIPOLAR MODE
–0.5
75
UNIPOLAR MODE
–0.5
–25
0
25
50
TEMPERATURE (°C)
75
100
Change in REFCOMP Voltage
vs Load Current
1959 G07
0.04
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
–50
100
1959 G06
CHANGE IN REFCOMP VOLTAGE (V)
UNIPOLAR MODE
INTERNAL REFERENCE VOLTAGE (V)
0.5
0
25
50
TEMPERATURE (°C)
0
–1.0
–50
100
2.520
–25
BIPOLAR MODE
Internal Reference Voltage
vs Temperature
1.0
–1.0
–50
0.5
1859 G05
LTC1859 Channel-to-Channel Gain
Error Matching vs Temperature
0
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
LTC1859 Channel-to-Channel
Offset Error Matching vs
Temperature
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
TOTAL HARMONIC DISTORTION (dB)
86
10
INPUT FREQUENCY (kHz)
5
1869 G03
–70
88
SINAD (dB)
0
32767
LTC1859 Total Harmonic
Distortion vs Input Frequency
90
1
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 86.95dB
THD = –101.42dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
1859 G02
LTC1859 SINAD
vs Input Frequency
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
LTC1859 Nonaveraged
4096-Point FFT Plot
LTC1859 Typical DNL Curve
–25
0
50
25
TEMPERATURE (°C)
75
100
1859 G08
0.02
0
–0.02
–0.04
–50
–40
–30
–20
–10
LOAD CURRENT (mA)
0
10
1859 G09
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LTC1857/LTC1858/LTC1859
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC1859 Power Supply
Feedthrough vs Ripple Frequency
–30
–40
–50
–60
9.0
fSAMPLE = 100kHz
8.5
8.0
7.5
–70
–80
100
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M
Supply Current vs Temperature
POSITIVE SUPPLY CURRENT (mA)
–20
fSAMPLE = 100kHz
VRIPPLE = 60mV
SUPPLY CURRENT (mA)
POWER SUPPLY FEEDTHROUGH (dB)
–10
Supply Current vs Supply Voltage
9.0
7.0
4.5
5
5.25
4.75
SUPPLY VOLTAGE (V)
1859 G10
5.5
fSAMPLE = 100kHz
8.5
8.0
7.5
7.0
–50
–25
1859 G11
0
25
50
TEMPERATURE (°C)
75
100
1859 G12
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PI FU CTIO S
COM (Pin 1): Common Input. This is the reference point
for all single-ended inputs. It must be free of noise and is
usually connected to the analog ground plane.
CH0 (Pin 2): Analog MUX Input.
AGND1 (Pin 14): Analog Ground.
VREF (Pin 15): 2.5V Reference Output. Bypass to analog
ground with a 1µF tantalum capacitor.
CH2 (Pin 4): Analog MUX Input.
REFCOMP (Pin 16): Reference Buffer Output. Bypass to
analog ground with a 10µF tantalum and a 0.1µF ceramic
capacitor. Nominal output voltage is 4.096V.
CH3 (Pin 5): Analog MUX Input.
AGND2 (Pin 17): Analog Ground.
CH4 (Pin 6): Analog MUX Input.
AGND3 (Pin 18): Analog Ground. This is the substrate
connection.
CH1 (Pin 3): Analog MUX Input.
CH5 (Pin 7): Analog MUX Input.
CH6 (Pin 8): Analog MUX Input.
CH7 (Pin 9): Analog MUX Input.
MUXOUT + (Pin 10): Positive MUX Output. Output of the
analog multiplexer. Connect to ADC + for normal operation.
AVDD (Pin 19): 5V Analog Supply. Bypass to analog ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
DVDD (Pin 20): 5V Digital Supply. Bypass to digital ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
MUXOUT – (Pin 11): Negative MUX Output. Output of the
analog multiplexer. Connect to ADC – for normal operation.
OVDD (Pin 21): Positive Supply for the Digital Output
Buffers (3V to 5V). Bypass to digital ground with a 0.1µF
ceramic and a 10µF tantalum capacitor.
ADC + (Pin 12): Positive Analog Input to the Analog-toDigital Converter.
BUSY (Pin 22): Output shows converter status. It is low
when a conversion is in progress.
ADC – (Pin 13): Negative Analog Input to the Analog-toDigital Converter.
SDO (Pin 23): Serial Data Output.
185789f
7
LTC1857/LTC1858/LTC1859
U
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PI FU CTIO S
DGND (Pin 24): Digital Ground.
RD (Pin 27): Read Input. This active low signal enables the
digital output pin SDO.
SDI (Pin 25): Serial Data Input.
CONVST (Pin 28): Conversion Start. This active high
signal starts a conversion on its rising edge.
SCK (Pin 26): Serial Data Clock.
W
FU CTIO AL BLOCK DIAGRA
U
U
AVDD
DVDD
MUX ADDRESS AND RANGE
CH0
CONVST
CONTROL
LOGIC
CH1
INTERNAL
CLOCK
INPUT MUX
AND
RANGE
SELECT
•
•
•
SDI
BUSY
SCK
+
12-/14-/16-BIT
SAMPLING ADC
CH7
–
COM
RD
DATA OUT
SERIAL I/O
OVDD
SDO
4.096V
2.5V
REFERENCE
8k
MUXOUT–
MUXOUT+
ADC+
1.6384X
ADC–
1859 BD
VREF
AGND1
REFCOMP
AGND2 AGND3 DGND
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
DN
1k
DN
1k
25pF
(A) Hi-Z TO VOH AND VOL TO VOH
DN
DN
1k
25pF
(B) Hi-Z TO VOL AND VOH TO VOL
1859 TC01
(A) VOH TO Hi-Z
25pF
25pF
(B) VOL TO Hi-Z
1859 TC02
185789f
8
LTC1857/LTC1858/LTC1859
W
UW
TI I G DIAGRA S
t 2 (CONVST to BUSY Delay)
t2
t1 (For Short Pulse Mode)
CONVST
2.4V
t1
BUSY
50%
50%
CONVST
0.4V
1859 TD02
1859 TD01
t 6 (Delay Time, SCK↓ to SDO Valid)
t7 (Time from Previous Data Remains Valid After SCK↓)
t6
t7
t3, t4, t5 (SCK Timing)
SCK
t4
0.4V
t5
SCK
2.4V
0.4V
SDO
t3
1859 TD03
1859 TD04
t9 (RD↓ to SCK Setup Time)
t8 (SDO Valid After RD↓)
t8
RD
RD
SDO
t9
0.4V
0.4V
Hi-Z
2.4V
0.4V
2.4V
SCK
1959 TD06
1859 TD05
t 10 (SDI Setup Time Before SCK↑)
t11 (SDI Hold Time After SCK↑)
t11
t10
2.4V
SCK
SDI
2.4V
SCK
2.4V
0.4V
2.4V
0.4V
SDI
1859 TD08
1859 TD07
t 12 (SDO Valid Before BUSY↑, RD = 0)
t 13 (BUS Relinquish Time)
t13
t12
2.4V
BUSY
SDO
2.4V
RD
B15
SDO
2.4V
90%
10%
Hi-Z
1859 TD10
1859 TD09
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OVERVIEW
The LTC1857/LTC1858/LTC1859 are innovative, multichannel ADCs that provide software-selectable input ranges
for each of their eight input channels. Using on-chip
resistors and switches, it provides an attenuation and
offset that can be programmed for each channel on the fly.
The precisely trimmed attenuators ensure accurate input
ranges. Because they precede the multiplexer, errors due
to multiplexer on-resistance are eliminated.
The input word that selects the input channel also selects
the desired input range for that channel. The available
ranges are 0V to 5V, 0V to 10V (unipolar), ±5V and ±10V
(bipolar). They are achieved with the ADC running on a
single 5V supply. In addition to the range selection, single
ended or differential inputs may be selected for each
channel or pair of channels. Finally, overrange protection
is provided for unselected channels. An overrange condition on an unused channel will not affect the conversion
result on the selected channel.
CONVERSION DETAILS
The analog signals applied at the MUX input channels are
rescaled by the resistor divider network formed by R1, R2
and R3 as shown below. The rescaled signals appear on
the MUXOUT (Pins 10, 11) which are also connected to the
ADC inputs (Pins 12, 13) under normal operation.
REFCOMP
BIPOLAR
MUX
INPUT
During the conversion, the internal differential 12-/14-/
16-bit capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a high speed comparator.
At the end of a conversion, the DAC output balances the
analog input (ADC + – ADC –). The SAR contents (a 16-bit
data word) which represents the difference of ADC+ and
ADC– are loaded into the 12-/14-/16-bit shift register.
DRIVING THE ANALOG INPUTS
The LTC1857/LTC1858/LTC1859 use a successive approximation algorithm and an internal sample-and-hold circuit
to convert an analog signal to a 12-/14-/16-bit serial output respectively. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
R1
25k
Before starting a conversion, an 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges to
select the MUX address, input range and power down
mode. The ADC enters acquisition mode on the falling
edge of the sixth clock in the 8-bit data word and ends on
the rising edge of the CONVST signal which also starts a
conversion (see Figure 7). A minimum time of 4µs will
provide enough time for the sample-and-hold capacitors
to acquire the analog signal. Once a conversion cycle has
begun, it cannot be restarted.
R3
10k CH SEL
The nominal input ranges for the LTC1857/LTC1858/
LTC1859 are 0V to 5V, 0V to 10V, ±5V and ±10V and the
MUX inputs are overvoltage protected to ±25V. The input
impedance is typically 42kΩ in unipolar mode and 31kΩ
in bipolar mode, therefore, it should be driven with a low
impedance source. Wideband noise coupling into the
input can be minimized by placing a 3000pF capacitor at
the input as shown in Figure 2. An NPO-type capacitor
gives the lowest distortion. Place the capacitor as close to
the device input pin as possible. If an amplifier is to be used
to drive the input, care should be taken to select an
amplifier with adequate accuracy, linearity and noise for
the application. The following list is a summary of the op
amps that are suitable for driving the LTC1857/LTC1858/
LTC1859. More detailed information is available in the
Linear Technology data books and online at
www.linear.com.
MUXOUT
R2
17k
1859 AI03
LT®1007: Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
185789f
10
LTC1857/LTC1858/LTC1859
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APPLICATIO S I FOR ATIO
DVDD
AVDD
MUX ADDRESS AND RANGE
CH0
CONVST
CONTROL
LOGIC
CH1
INPUT MUX
AND
RANGE
SELECT
•
•
•
SDI
INTERNAL
CLOCK
BUSY
SCK
+
12-/14-/16-BIT
SAMPLING ADC
CH7
–
COM
RD
DATA OUT
SERIAL I/O
OVDD
SDO
4.096V
2.5V
REFERENCE
8k
MUXOUT–
MUXOUT+
ADC+
1.6384X
ADC–
1859 BD
VREF
AGND1
REFCOMP
AGND2 AGND3 DGND
Figure 1. LTC1857/LTC1858/LTC1859 Simplified Equivalent Circuit
AIN+
CH0
LT1792: Single, low noise JFET input op amp, ±5V
supplies.
CH1
•
•
•
•
MUXOUT+
LT1793: Single, low noise JFET input op amp, 10pA bias
current, ±5V supplies.
3000pF
AIN–
MUXOUT–
ADC+
ADC–
1859 F02
Figure 2. Analog Input Filtering
LT1227: 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1468/LT1469: Single and dual 90MHz, 16-bit accurate
op amp. Good AC/DC specs.
LT1677: Single, low noise op amp. Rail-to-rail input and
output. Up to ±15V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps. Up to ±15V supplies.
LT1844/LT1885: Dual and quad, 400pA bias current, railto-rail output op amps. Up to ±15V supplies. Faster
response and settling time.
INTERNAL VOLTAGE REFERENCE
The LTC1857/LTC1858/LTC1859 have an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale
range of the LTC1857/LTC1858/LTC1859 is equal to ±5V,
0V to 5V, ±10V or 0V to 10V. The output of the reference
is connected to the input of a gain of 1.6384x buffer
through an 8k resistor (see Figure 3). The input to the
185789f
11
LTC1857/LTC1858/LTC1859
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APPLICATIO S I FOR ATIO
buffer or the output of the reference is available at VREF
(Pin 15). The internal reference can be overdriven with an
external reference if more accuracy is needed. The buffer
output drives the internal DAC and is available at REFCOMP
(Pin 16). The REFCOMP pin can be used to drive a steady
DC load of less than 2mA. Driving an AC load is not
recommended because it can cause the performance of
the converter to degrade.
15 VREF
2.5V
8k
2.5V
REFERENCE
1µF
12-/14-/16-BIT
CAPACITIVE DAC
1.6384X BUFFER
16 REFCOMP
4.096V
0.1µF
1859 F03
10µF
Figure 3. Internal or External Reference Source
For minimum code transition noise the VREF pin and the
REFCOMP pin should each be decoupled with a capacitor
to filter wideband noise from the reference and the buffer.
UNIPOLAR / BIPOLAR OPERATION
Figure 4a shows the ideal input/output characteristics for
the LTC1859. The code transitions occur midway between
1LSB =
111...111
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, … FS – 1.5LSB). The output code is natural binary
with 1LSB = FS/65536. Figure 4b shows the input/output
transfer characteristics for the bipolar mode in two’s
complement format.
FULL SCALE AND OFFSET
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during
a calibration sequence. Offset error must be adjusted
before full-scale error. Zero offset is achieved by adjusting
the offset applied to the “–” input. For single-ended inputs,
this offset should be applied to the COM pin. For differential inputs, the “–” input is dictated by the MUX address.
For unipolar zero offset error, apply 0.5LSB (actual voltage
will vary with input span selected) to the “+” input and
adjust the offset at the “–” input until the output code
flickers between 0000 0000 0000 0000 and 0000 0000
0000 0001 for the LTC1859, between 00 0000 0000 0000
and 00 0000 0000 0001 for the LTC1858 and between
0000 0000 0000 and 0000 0000 0001 for the LTC1857.
For bipolar zero error, apply – 0.5LSB (actual voltage will
vary with input span selected) to the “+” input and adjust
the offset at the “–” input until the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111
1111 for the LTC1859, between 00 0000 0000 0000 and
FS
65536
011...111
111...110
1LSB =
011...110
111...100
OUTPUT CODE
OUTPUT CODE
111...101
UNIPOLAR
ZERO
000...011
FS
65536
BIPOLAR
ZERO
000...001
000...000
111...111
111...110
000...010
100...001
000...001
100...000
000...000
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
1859 F4a
Figure 4a. Unipolar Transfer Characteristics (UNI = 1)
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
1859 F4b
Figure 4b. Bipolar Transfer Characteristics (UNI = 0)
185789f
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LTC1857/LTC1858/LTC1859
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APPLICATIO S I FOR ATIO
1800
11 1111 1111 1111 for the LTC1858 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1857.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111 for the LTC1859,
between 01 1111 1111 1110 and 01 1111 1111 1111 for
the LTC1858 and between 0111 1111 1110 and 0111 1111
1111 for the LTC1857.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifications in the Converter Characteristics table.
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where a
DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution of
output code is shown for a DC input that has been digitized
4096 times. The distribution is Gaussian and the RMS
code transition is about 1LSB for the LTC1859.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4µs. No external adjustments
are required and, with the maximum acquisition time of 4µs,
throughput performance of 100ksps is assured.
1400
1200
COUNT
As mentioned earlier, the internal reference is factory
trimmed to 2.50V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed with an accurate external 2.5V reference applied to VREF. For unipolar inputs, an input voltage of FS – 1.5LSBs should be applied to the “+” input and
the appropriate reference adjusted until the output code
flickers between 1111 1111 1111 1110 and 1111 1111
1111 1111 for the LTC1859, between 11 1111 1111 1110
and 11 1111 1111 1111 for the LTC1858 and between
1111 1111 1110 and 1111 1111 1111 for the LTC1857.
1600
1000
800
600
400
200
0
–4
–3
–2
–1
1
0
CODE
2
3
4
1859 F05
Figure 5. LTC1859 Histogram for 4096 Conversions
3V Input/Output Compatible
The LTC1857/LTC1858/LTC1859 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1857/LTC1858/LTC1859 recognize 3V or
5V inputs. The LTC1857/LTC1858/LTC1859 have a dedicated output supply pin (OVP) that controls the output
swings of the digital output pins (SDO, BUSY) and allows
the part to interface to either 3V or 5V digital systems. The
output is two’s complement binary for bipolar mode and
offset binary for unipolar mode.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CONVST and RD. To start a conversion and
put the sample-and-hold into the hold mode bring CONVST
high for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
Figures 6a and 6b show two different modes of operation
for the LTC1859. For the 12-bit LTC1857 and 14-bit
LTC1858, the last four and two bits of the SDO will output
zeros respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output is
available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
185789f
13
14
Hi-Z
DON’T
CARE
Hi-Z
DON’T
CARE
SGL/
DIFF
t4
1
t10
t3
t4
1
B15 (MSB)
t8
t5
t10
t3
SGL/
DIFF
t8
B15 (MSB)
t9
SELECT
0
4
UNI
5
GAIN
6
B12
B11
B10
B9
NAP
7
B8
SLEEP
8
tACQ
B1
DON’T CARE
15
B0 (LSB)
t7
t6
16
t2
t1
tCONV
t12
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
SELECT
0
4
UNI
5
GAIN
6
NAP
7
SLEEP
SELECT
0
4
UNI
5
GAIN
6
B13
B12
B11
B10
SHIFT CONFIGURATION WORD IN
SELECT
1
3
B9
NAP
7
B8
SLEEP
8
tACQ
B1
DON’T CARE
15
B0 (LSB)
t7
t6
16
t2
Hi-Z
tCONV
t13
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
B13
B12
B11
B10
B9
SELECT
0
4
UNI
5
GAIN
6
NAP
7
SLEEP
8
B8
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
Figure 6a. Mode 1 for the LTC1859*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
B13
SHIFT CONFIGURATION WORD IN
SELECT
1
3
B14
ODD/
SIGN
t11
2
SELECT
0
4
UNI
5
GAIN
6
B13
B12
B11
B10
SHIFT CONFIGURATION WORD IN
SELECT
1
3
B9
NAP
7
B8
SLEEP
8
tACQ
B0 (LSB)
t7
t6
16
t2
Hi-Z
tCONV
t1
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
Figure 7. Operating Sequence for the LTC1859*
B1
DON’T CARE
15
t13
SELECT
0
4
UNI
5
GAIN
6
NAP
7
SLEEP
8
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
Figure 6b. Mode 2 for the LTC1859*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
B14
ODD/
SIGN
t11
2
B14
t12
B15 (MSB)
t11
ODD/
SIGN
t5
t10
2
SGL/
DIFF
t9
DON’T
CARE
t5
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
SDO
SDI
SCK
CONVST = RD
BUSY
CONVST
SDO
SDI
SCK
t3
B1
15
16
B0 (LSB)
DON’T CARE
16
B0 (LSB)
DON’T CARE
16
B0 (LSB)
DON’T CARE
B1
15
B1
15
1859 F07
Hi-Z
1859 F06b
Hi-Z
1859 F06a
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1
APPLICATIO S I FOR ATIO
U
RD = 0
LTC1857/LTC1858/LTC1859
185789f
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three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
SERIAL DATA INPUT (SDI) INTERFACE
The LTC1857/LTC1858/LTC1859 communicate with microprocessors and other external circuitry via a synchronous, full duplex, 3-wire serial interface (see Figure 7).
The shift clock (SCK) synchronizes the data transfer with
each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
An 8-bit input word is shifted into the SDI input which
configures the LTC1857/LTC1858/LTC1859 for the next
conversion. Simultaneously, the result of the previous
conversion is output on the SDO line. At the end of the data
exchange the requested conversion begins by applying a
rising edge on CONVST. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one conversion from the input word requesting it.
SDI
SDI WORD 1
SDO
SDO WORD 0
DATA
TRANSFER
SDI WORD 2
SDI WORD 3
SDO WORD 1
tCONV
A/D
CONVERSION
DATA
TRANSFER
SDO WORD 2
1859 • AI01
tCONV
A/D
CONVERSION
INPUT DATA WORD
The LTC1857/LTC1858/LTC1859 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges.
Further inputs on the SDI pin are then ignored until the next
conversion. The eight bits of the input word are defined as
follows:
INPUT RANGE
SGL/
DIFF
ODD
SIGN
SELECT
1
SELECT
0
UNI
GAIN
SLEEP
NAP
POWER DOWN
SELECTION
MUX ADDRESS
1859 AI02
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
DIFFERENTIAL CHANNEL SELECTION
0
1
+
–
2
3
+
–
+
0,1
{
2,3
{
4,5
{
6,7
{
+ ( –)
– ( +)
+ ( –)
– ( +)
+ ( –)
– ( +)
+ ( –)
– ( +)
5
6
7
–
+
–
–
+
–
+
–
+
–
4 Differential
CHANNEL
4
8 Single-Ended
CHANNEL
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
COM (–)
+
SINGLE-ENDED CHANNEL SELECTION
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
0
1
0,1
{
+
–
2,3
{
–
+
+
+
+
+
4
5
6
7
COM (–)
3
4
5
6
7
+
+
+
+
+
+
+
+
Combinations of
Differential and Single-Ended
CHANNEL
2
COM
–
–
–
–
–
–
–
–
Changing the
MUX Assignment “On the Fly”
4,5
{
6,7
{
+
–
+
–
COM (UNUSED)
1ST CONVERSION
4,5
{
–
+
6
7
+
+
COM (–)
2ND CONVERSION
1859 F08
Figure 8. Examples of Multiplexer Options on the LTC1857/LTC1858/LTC1859
185789f
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MUX ADDRESS
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM. Both the “+” and “–” inputs are sampled simultaneously so common mode noise is rejected.
INPUT RANGE (UNI, GAIN)
The fifth and sixth input bits (UNI, GAIN) determine the
input range for the conversion. When UNI is a logical one,
a unipolar conversion will be performed. When UNI is a
logical zero, a bipolar conversion will result. The GAIN
input bit determines the input span for the conversion.
When GAIN is a logical one, either 0V to 10V or ±10V input
spans will be selected depending on UNI. When GAIN is a
logical zero, either 0V to 5V or ±5V input spans will be
chosen. The input ranges for different UNI and GAIN
inputs are shown in Table 2.
Table 2. Input Range Selection
UNI
GAIN
INPUT RANGE
0
0
±5V
1
0
0V to 5V
0
1
±10V
1
1
0V to 10V
POWER DOWN SELECTION (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) determine the power shutdown mode of the LTC1857/LTC1858/
LTC1859. See Table 3. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the conversion which is indicated by the rising edge of the BUSY
signal. Nap mode lasts until the falling edge of the 2nd SCK
(see Figure 9). Automatic nap will be achieved if Nap = 1
is selected each time an input word is written to the ADC.
Table 3. Power Down Selection
NAP
SLEEP
POWER DOWN MODE
0
0
Power On
1
0
Nap
X
1
Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previous
conversion result can be clocked out and the Sleep mode
will start on the falling edge of the last (16th) SCK. Notice
that the CONVST should stay either high or low in sleep
mode (see Figure 10). To wake up from the sleep mode,
apply a rising edge on the CONVST signal and then apply
Sleep = 0 on the next SDI word and the part will wake up
on the falling edge of the last (16th) SCK (see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10µA)
remain. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 16).
The wake-up time is typically 40ms with the recommended 10µF capacitor connected on the REFCOMP pin.
DYNAMIC PERFORMANCE
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical LTC1859 FFT plot which yields a SINAD of 87dB
and THD of – 101dB.
185789f
16
Hi-Z
DON’T
CARE
tCONV
DON’T
CARE
tCONV
DON’T
CARE
B15 (MSB)
SGL/
DIFF
SGL/
DIFF
1
B15 (MSB)
3
SELECT
0
4
UNI
5
GAIN
6
B13
B14
ODD/
SIGN
2
B14
ODD/
SIGN
2
SELECT
1
3
B11
SELECT
0
4
B10
UNI
5
B9
8
6
B8
B12
B11
B10
A/D RESULT NOT VALID
B9
SELECT
0
4
UNI
5
GAIN
6
B13
B12
B10
SLEEP
tCONV
Hi-Z
NAP
B15 MSB
SGL/
DIFF
1
SELECT
1
B8
SLEEP = 0
8
B14
B0 (LSB)
16
B13
B9
NAP
7
B8
SLEEP = 0
8
B1
DON’T CARE
15
WAKE-UP
TIME
B0 (LSB)
16
READY
tCONV
B15 (MSB)
SGL/
DIFF
1
Figure 10. Sleep Mode Operation for the LTC1859*
B1
DON’T CARE
15
3
SELECT
0
4
UNI
5
GAIN
6
NAP
7
SLEEP
8
15
B14
ODD/
SIGN
2
B12
B13
SELECT
0
4
B10
UNI
5
B9
GAIN
6
B8
NAP
7
8
SLEEP
tACQ
B1
B12
B11
B10
B9
B8
16
B0 (LSB)
DON’T CARE
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
SLEEP
B11
SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN
ODD/
SIGN
2
Figure 11. Wake Up from Sleep Mode for the LTC1859*
A/D RESULT NOT VALID
B11
SHIFT WAKE-UP CONFIGURATION WORD IN
SELECT
1
3
B0 (LSB)
16
Figure 9. Nap Mode Operation for the LTC1859*
tACQ
B1
DON’T CARE
15
CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE
B13
7
NAP
SLEEP = 0
GAIN
NAP = 1
7
SHIFT WAKE-UP CONFIGURATION WORD IN
B12
SHIFT CONFIGURATION WORD IN
SELECT
1
SGL/
DIFF
1
B15 (MSB)
B14
ODD/
SIGN
2
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
CONVST
SDO
SDI
1
16
B1
B0 (LSB)
DON’T CARE
15
1859 F10
1859 F09
Hi-Z
U U
W
SCK
APPLICATIO S I FOR ATIO
1859 F11
U
RD
LTC1857/LTC1858/LTC1859
185789f
17
LTC1857/LTC1858/LTC1859
U
W
U U
APPLICATIO S I FOR ATIO
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows a typical SINAD of 87dB with
a 100kHz sampling rate and a 1kHz input.
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
V22 + V32 + V42 ... + VN2
THD = 20log
V1
MAGNITUDE (dB)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
BOARD LAYOUT, POWER SUPPLIES
AND DECOUPLING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1857/LTC1858/LTC1859, a
printed circuit board is required. Layout for the printed
circuit board should ensure the digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
In applications where the MUX is connected to the ADC, it
is possible to get noise coupling into the ADC from the
trace connecting the MUXOUT to the ADC. Therefore,
reducing the length of the traces connecting the MUXOUT
pins (Pins 10, 11) to the ADC pins (Pins 12, 13) can
minimize the problem. The unused MUX inputs should be
grounded to prevent noise coupling into the inputs.
Figure 13 shows the power supply grounding that will help
obtain the best performance from the 12-bit/14-bit/16-bit
ADCs. Pay particular attention to the design of the analog
and digital ground planes. The DGND pin of the LTC1857/
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 86.95dB
THD = –101.42dB
0
5
10
15
30
20
25
FREQUENCY (kHz)
35
40
45
50
1859 F12
Figure 12. LTC1859 Nonaveraged 4096 Point FFT Plot
185789f
18
LTC1857/LTC1858/LTC1859
U
W
U U
APPLICATIO S I FOR ATIO
LTC1858/LTC1859 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply pins, the reference and reference buffer output
is very important. Low impedance common returns for
these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
+
–
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
LTC1857/
LTC1858/
CH0 LTC1859
10 12
CH1
MUXOUT +
ADC+
CH2
LTC1857/LTC1858/LTC1859
CH3
CH4
ADC–
MUXOUT –
VREF
REFCOMP AGND
AVDD
DVDD
DGND
11 13
CH5
CH6
15
16
14, 17, 18 19
20
24
CH7
10µF
10µF
10µF
1µF
COM
DIGITAL
SYSTEM
OVDD
21
10µF
ANALOG GROUND PLANE
1859 F13
Figure 13. Power Supply Grounding Practice
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
0.65 BSC
2.0
(.079)
MAX
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
7.40 – 8.20
(.291 – .323)
0.65
(.0256)
BSC
0.22 – 0.38
0.05
(.009 – .015)
(.002)
TYP
MIN
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 0204
185789f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1857/LTC1858/LTC1859
U
TYPICAL APPLICATIO
5V
5V
10µF
0.1µF
10µF
19
20
DVDD
AVDD
1 COM
CONVST 28
MUX ADDRESS AND RANGE
2 CH0
SINGLE-ENDED
OR DIFFERENTIAL
CHANNEL
SELECTION
(SEE TABLE 1)
INPUT RANGES:
0V TO 5V
0V TO 10V
±5V AND ±10V
SDI 25
CONTROL
LOGIC
3 CH1
8-BIT SERIAL
DATA INPUT
BUSY 22
INTERNAL
CLOCK
INPUT MUX
AND
RANGE
SELECT
•
•
•
0.1µF
SCK 26
16 SHIFT CLOCK CYCLES
+
9 CH7
12-/14-/16-BIT
SAMPLING ADC
RD 27
DATA OUT
OVDD 21
–
10µF
SERIAL I/O
4.096V
SDO 23
2.5V
REFERENCE
16-BIT SERIAL DATA OUT
1.6384X
8k
AGND1
MUXOUT–
14
11
MUXOUT+
10
ADC+
12
ADC–
VREF
13
15
3V TO 5V
0.1µF
AGND2 AGND3 DGND
REFCOMP
16
1µF
10µF
17
18
1859 TA03
24
0.1µF
RELATED PARTS
PART NUMBER
Sampling ADCs
LTC1417
LTC1418
LTC1604
LTC1605
LTC1606
LTC1608
LTC1609
LTC1850/LTC1851
LTC1852/LTC1853
LTC1864/LTC1865
LTC1864L/LTC1865L
DACs
LTC1588/LTC1589
LTC1592
LTC1595
LTC1596
LTC1597
LTC1650
Op Amps
LT1468/LT1469
DESCRIPTION
COMMENTS
14-Bit, 400ksps Serial ADC
14-Bit, 200ksps, Single 5V or ±5V ADC
16-Bit, 333ksps, ±5V ADC
16-Bit, 100ksps, Single 5V ADC
16-Bit, 250ksps, Single 5V ADC
16-Bit, 500ksps, ±5V ADC
16-Bit, 200ksps Serial ADC
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADC
16-Bit, 1-/2-Channel, 250ksps ADC in MSOP
3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP
5V or ±5V, 20mW, 81dB SINAD and –95dB THD
15mW, Serial/Parallel I/O
90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604
Configurable Unipolar/Bipolar Input, Single 5V Supply
Programmable MUX and Sequencer, Parallel I/O
Single 3V-5V, Programmable MUX and Sequencer, Parallel I/O
Single 5V Supply, 850µA with Autoshutdown
Single 3V Supply, 450µA with Autoshutdown
12-/14-/16-Bit, Serial, SoftSpan IOUT DACs
Software-Selectable Spans, ±1LSB INL/DNL
16-Bit Serial Multiplying IOUT DAC in SO-8
16-Bit Serial Multiplying IOUT DAC
16-Bit Parallel, Multiplying DAC
16-Bit Serial VOUT DAC
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
Low Power, Low Gritch, 4-Quadrant Multiplication
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amp Low Input Offset : 75µV/125µV
185789f
20
Linear Technology Corporation
LT/TP 0904 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004