Cypress CY62148BNSL-70SXI 4-mbit (512k x 8) static ram Datasheet

CY62148BN MoBL®
4-Mbit (512K x 8) Static RAM
Features
Functional Description
• 4.5V–5.5V operation
• Low active power
The CY62148BN is a high performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and tri-state drivers. This device
has an automatic power down feature that reduces power
consumption by more than 99% when deselected.
— Typical active current: 2.5 mA @ f = 1 MHz
•
•
•
•
•
•
— Typical active current:12.5 mA @ f = fmax
Low standby current
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
CMOS for optimum speed and power
Available in standard Pb-free and non Pb-free 32-lead
(450-mil) SOIC and 32-lead TSOP II packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH for
read. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) go into a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE LOW and WE LOW).
Logic Block Diagram
I/O0
INPUT BUFFER
I/O1
512 K x 8
ARRAY
SENSE AMPS
I/O2
ROW DECODER
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
OE
Cypress Semiconductor Corporation
Document #: 001-06517 Rev. *B
A2
A3
A15
A18
A13
A8
A9
A11
A10
WE
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 1, 2007
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CY62148BN MoBL®
Pin Configuration
Top View
SOIC
TSOP II
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
VCC Range
Product
CY62148BNLL
Speed
Min
Typ
Max
4.5 V
5.0V
5.5V
70 ns
Operating ICC (mA)
f = fmax
Typ[1]
Max
12.5
20
Standby ISB2 (µA)
Typ[1]
Max
4
20
Note
1. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed.
Document #: 001-06517 Rev. *B
Page 2 of 9
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CY62148BN MoBL®
DC Input Voltage[2] ................................. –0.5V to VCC +0.5V
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Exceeding the maximum rating may impair the device’s useful
life. User guidelines only and are not tested.
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[2] .....................................–0.5V to VCC +0.5V
Range
Industrial
Ambient
Temperature[3]
VCC
–40°C to +85°C
4.5V–5.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
CY62148BN
Test Conditions
Min
VOH
Output HIGH Voltage
IOH = –1 mA
VOL
Output LOW Voltage
IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
ISB1
Automatic CE Power Down
Current – TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE Power Down
Current – CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f =0
Typ[1]
Unit
Max
2.4
V
0.4
V
2.2
VCC +0.3
V
–0.3
0.8
V
–1
+1
µA
–1
+1
µA
20
mA
IOUT = 0 mA
VCC = Max.,
f = 1 MHz
12.5
2.5
4
mA
1.5
mA
20
µA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC – 5.0V
Max.
Unit
6
pF
8
pF
AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
ALL INPUT PULSES
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
R2
5 pF
990Ω
INCLUDING
JIG AND
SCOPE
(b)
3.0V
R2
990Ω
GND
90%
10%
≤ 3 ns
90%
10%
≤ 3 ns
Equivalent to:
THEVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Notes
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
3. TA is the “instant on” case temperature
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06517 Rev. *B
Page 3 of 9
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CY62148BN MoBL®
Switching Characteristics[5] Over the Operating Range
Parameter
Description
CY62148BN
Min
Max
Unit
READ CYCLE
tRC
Read Cycle Time
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
[6]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
CE LOW to Low
Z[6]
CE HIGH to High
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
WRITE
70
10
ns
ns
5
ns
25
10
Z[6, 7]
tHZCE
ns
ns
ns
25
0
ns
ns
70
ns
CYCLE[8]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Setup to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
55
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold from Write End
0
ns
5
ns
tLZWE
tHZWE
WE HIGH to Low
Z[6]
WE LOW to High
Z[6, 7]
25
ns
Notes
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 001-06517 Rev. *B
Page 4 of 9
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CY62148BN MoBL®
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
tR[9]
Chip Deselect to Data Retention Time
Typ[1]
Min
Max
2.0
No input may exceed
VCC + 0.3V
VCC = VDR
CE > VCC – 0.3V
VIN > VCC – 0.3V or
VIN < 0.3V
Operation Recovery Time
Unit
V
20
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tCDR
tR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ISB
Notes
9. Full Device operation requires linear VCC ramp from VDR to VCC(min) > 100 ms or stable at VCC(min) > 100 ms.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06517 Rev. *B
Page 5 of 9
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CY62148BN MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE
tHZCE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
Notes
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
14. Data I/O is high-impedance if OE = VIH.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06517 Rev. *B
Page 6 of 9
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CY62148BN MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[13, 14]
tWC
ADDRESS
tSCE
CE
tHZCE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 15
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
H
X
X
High Z
I/O0–I/O7
Power Down
Mode
Standby (ISB)
Power
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Diagram
Package Type
CY62148BNSL-70SXI[16]
51-85081
32-lead (450-Mil) Molded SOIC (Pb-Free)
CY62148BNLL-70SXI
51-85081
32-lead (450-Mil) Molded SOIC (Pb-Free)
CY62148BNLL-70ZXI
51-85095
32-lead TSOP II (Pb-Free)
Operating
Range
Industrial
Note
16. CY62148BNSL and CY62148BNLL are identical in specs.
Please contact your local Cypress sales representative for availability of these parts
Document #: 001-06517 Rev. *B
Page 7 of 9
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CY62148BN MoBL®
Package Diagrams
Figure 1. 32-lead (450 Mil) Molded SOIC (51-85081)
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
DIMENSIONS IN INCHES[MM]
MIN.
MAX.
PACKAGE WEIGHT 1.42gms
PART #
S32.45 STANDARD PKG.
SZ32.45 LEAD FREE PKG.
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.050[1.270]
BSC.
0.004[0.102]
MIN.
0.014[0.355]
0.020[0.508]
0.047[1.193]
0.063[1.600]
0.023[0.584]
0.039[0.990]
SEATING PLANE
51-85081-*B
Figure 2. 32-Lead Thin Small Outline Package Type II (51-85095)
51-85095 **
More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06517 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62148BN MoBL®
Document History Page
Document Title: CY62148BN MoBL® 4-Mbit (512K x 8) Static RAM
Document Number: 001-06517
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
426504
See ECN
NXR
New Data Sheet
*A
485639
See ECN
VKN
Corrected the typo in the Array size in the Logic Block Diagram
*B
832320
See ECN
NXR
Removed Commercial Operating Range
Removed 32-lead Reverse TSOP II package from product offering
Corrected the test condition typo error in Electrical Characteristics table
Updated Ordering information table
Document #: 001-06517 Rev. *B
Page 9 of 9
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