IRF IR22141SSPBF Half-bridge gate driver ic Datasheet

Data Sheet No. PD60349 revL
IR21141SSPbF/IR22141SSPbF
HALF-BRIDGE GATE DRIVER IC
Features
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Product Summary
Floating channel up to 600 V or 1200 V
Soft over-current shutdown
Synchronization signal to synchronize shutdown with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
Undervoltage lockout with hysteresis band
Lead free
Description
The IR21141/IR22141 gate driver family is suited to drive a single half bridge
in power switching applications. These drivers provide high gate driving
capability (2 A source, 3 A sink) and require low quiescent current, which
allows the use of bootstrap power supply techniques in medium power
systems. These drivers feature full short circuit protection by means of power
transistor desaturation detection and manage all half-bridge faults by
smoothly turning off the desaturated transistor through the dedicated soft
shutdown pin, therefore preventing over-voltages and reducing
electromagnetic emissions. In multi-phase systems, the IR21141/IR22141
drivers communicate using a dedicated local network (SY_FLT and
FAULT/SD signals) to properly manage phase-to-phase short circuits. The
system controller may force shutdown or read device fault state through the
3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity
from DC-bus noise, the control and power ground use dedicated pins
enabling low-side emitter current sensing as well. Undervoltage conditions in
floating and low voltage circuits are managed independently.
IO+/- (min)
600 V or
1200 V max.
1.0 A / 1.5 A
VOUT
10.4 V – 20 V
VOFFSET
Deadtime matching (max)
75 ns
Deadtime (typ)
330 ns
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
Soft shutdown time (typ)
3 µs
8.0 V
9.25 µs
Package
24-Lead SSOP
Typical connection
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© 2009 International Rectifier
IR21141/IR22141SSPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VS
VB
VHO
VCC
High side offset voltage
IR21141
High side floating supply voltage
IR22141
High side floating output voltage (HOP, HON and SSDH)
VB + 0.3
625
1225
VB + 0.3
-0.3
25
Power ground
VCC - 25
VCC + 0.3
VLO
Low side output voltage (LOP, LON and SSDL)
VCOM -0.3
VCC + 0.3
COM
Low side and logic fixed supply voltage
VB - 25
-0.3
-0.3
VS - 0.3
VIN
Logic input voltage (HIN, LIN and FLT_CLR)
-0.3
VCC + 0.3
VFLT
Fault input/output voltage (FAULT/SD and SY_FLT)
-0.3
VCC + 0.3
VDSH
High side DS input voltage
VS -3
VB + 0.3
Low side DS input voltage
VCOM -3
VCC + 0.3
VDSL
dVs/dt
PD
RthJA
V
Allowable offset voltage slew rate
—
50
Package power dissipation @ TA ≤ 25 °C
—
1.5
W
Thermal resistance, junction to ambient
—
65
°C/W
150
TJ
Junction temperature
—
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
V/ns
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to VSS. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol
VB
Definition
High side floating supply voltage
†
IR21141
IR22141
††
VS
High side floating supply offset voltage
VHO
High side output voltage (HOP, HON and SSDH)
Min.
Max.
VS + 11.5
VSS
VSS
VS
VS + 20
600
1200
VS + 20
VLO
Low side output voltage (LOP, LON and SSDL)
VCOM
VCC
VCC
Low side and logic fixed supply voltage (Note 1)
11.5
20
-5
5
COM
Power ground
VIN
Logic input voltage (HIN, LIN and FLT_CLR)
VSS
VCC
VFLT
Fault input/output voltage (FAULT/SD and SY_FLT)
VSS
VCC
VDSH
High side DS pin input voltage
VS - 2.0
VB
VDSL
Low side DS pin input voltage
VCOM - 2.0
VCC
tPWHIN
High side pulse width for HIN input
TA
†
††
1
Ambient temperature
-40
Units
V
µs
125
°C
While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output
drivers if the UV thresholds are not reached. A minimum supply voltage of 8V is recommended for the driver
to operate safely under switching conditions at VS pin (please refer to the “start-up sequence” in application
section of this document)
Logic operational for VS from VSS-5 V to VSS +600 V or 1200 V. Logic state held for VS from VSS -5 V to VSSVBS. For a negative spike on VB (referenced to VSS) of less than 200ns the IC will withstand a sustained peak
of -40V under normal operation and an isolated event of up to -70V peak spike (please refer to the Design
Tip DT97-3 for more details).
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IR21141/IR22141SSPbF
Static Electrical Characteristics
VCC = 15 V, VSS = COM = 0 V, VS = 600 V or 1200 V and TA = 25 °C unless otherwise specified.
Pins: VCC, VSS, VB, VS (refer to Fig. 1)
Symbol
Definition
Min
Typ
Max Units
VCCUV+
VCC supply undervoltage positive going threshold
9.3
10.2
11.4
VCCUV-
VCC supply undervoltage negative going threshold
8.7
9.3
10.3
VCCUVH
VBSUV+
VCC supply undervoltage lockout hysteresis
(VB-VS) supply undervoltage positive going threshold
—
9.3
0.9
10.2
—
11.4
VBSUVVBSUVH
(VB-VS) supply undervoltage negative going threshold
(VB-VS) supply undervoltage lockout hysteresis
8.7
—
9.3
0.9
10.3
—
Offset supply leakage current
—
—
50
ILK
Test Conditions
V
VS = 0 V, VS = 600 V
or 1200 V
µA
VB = VS = 600 V or
1200 V
VIN = 0 V or 3.3 V
no load
IQBS
Quiescent VBS supply current
—
400
800
IQCC
Quiescent VCC supply current
—
0.7
2.5
mA
Max
Units
Test Conditions
V
VCC = VCCUVto 20 V
Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT (refer to Fig. 2, 3)
Symbol
Definition
Min
Typ
VIH
Logic "1" input voltage
2.0
—
—
VIL
Logic "0" input voltage
—
—
0.8
VIHSS
IIN+
IINRON,FLT
RON,SY
Logic input hysteresis
0.2
0.4
—
Logic “1” input bias current (HIN, LIN, FLTCLR)
—
330
—
Logic “0” input bias current (FAULT/SD, SY_FLT)
0
—
1
Logic “0” input bias current
-1
—
0
Logic “1” input bias current (FAULT/SD, SY_FLT)
-1
—
0
FAULT/SD open drain resistance
SY_FLT open drain resistance
—
60
—
—
60
—
VIN = 3.3 V
µA
VIN = 0 V
Ω
PW≤ 7 µs
Pins: DSL, DSH (refer to Fig. 4)
The active bias is present only the IR21141and IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS
respectively for DSL and DSH.
Symbol
Definition
Min Typ Max Units
Test Conditions
VDESAT+
High desat input threshold voltage
7.2 8.0 8.8
VDESAT-
Low desat input threshold voltage
6.3 7.0 7.7
Desat input voltage hysteresis
—
1.0
—
21
—
VDSTH
IDS+
High DSH or DSL input bias current
—
IDS-
Low DSH or DSL input bias current
DSH or DSL input bias current
(IR21141 and IR22141 only)
— -160 —
IDSB
—
-20
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—
V
µA
mA
See Figs. 4,16
VDESAT = VCC or VBS
VDESAT = 0 V
VDESAT = (VCC or VBS) – 2 V
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IR21141/IR22141SSPbF
Pins: HOP, LOP (refer to Fig. 5)
Symbol
Definition
Min
Typ
Max Units Test Conditions
VOH
High level output voltage, VB – VHOP or VCC –VLOP
—
40
300
IO1+
Output high first stage short circuit pulsed current
1
2
—
mV
IO= 20 mA
VHOP/LOP= 0 V, HIN
or LIN = 1, PW≤
200 ns, resistive
load, see Fig. 8
A
IO2+
Output high second stage short circuit pulsed current
0.5
1
Min
Typ
VHOP/LOP= 0 V, HIN
or LIN= 1,
400 ns ≤PW≤ 10
µs, resistive load,
see Fig. 8
—
Pins: HON, LON, SSDH, SSDL (refer to Fig. 6)
Symbol
VOL
RON,SSD
Definition
Low level output voltage, VHON or VLON
Soft Shutdown on resistance
†
IO-
Output low short circuit pulsed current
†
SSD operation only
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Max Units Test Conditions
—
45
300
mV
IO= 20 mA
—
90
—
Ω
PW≤ 7 µs
1.5
3
—
A
VHOP/LOP = 15 V,
HIN or LIN = 0, PW≤
10 µs
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IR21141/IR22141SSPbF
AC Electrical Characteristics
VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified.
Symbol
Definition
Min.
Typ.
Max. Units
ton
Turn on propagation delay
220
440
660
toff
Turn off propagation delay
220
440
660
Test Conditions
VIN = 0 & 1, VS = 0 V to 600 V
or 1200 V,
HOP shorted to HON, LOP
shorted to LON, Fig. 7
tr
Turn on rise time (CLOAD=1 nF)
—
24
—
tf
Turn off fall time (CLOAD=1 nF)
—
7
—
120
200
280
Fig. 8
tDESAT1
DSH to HO soft shutdown propagation delay at HO
2000
turn on
3300
4600
VHIN= 1 V
tDESAT2
DSH to HO soft shutdown propagation delay after
blanking
1050
—
—
VDESAT = 15 V, Fig. 10
tDESAT3
DSL to LO soft shutdown propagation delay at LO
turn on
2000
3300
4600
VLIN = 1 V
tDESAT4
DSL to LO soft shutdown propagation delay after
blanking
1050
—
—
VDESAT = 15 V, Fig. 10
tDS
Soft shutdown minimum pulse width of desat
1000
—
—
Fig. 9
tSS
Soft shutdown duration period
5700
ton1
tSY_FLT,
Turn on first stage duration time
9250 13500
VDS=15 V, Fig. 9
ns
DSH to SY_FLT propagation delay at HO turn on
—
3600
—
VHIN = 1 V
DSH to SY_FLT propagation delay after blanking
1300
—
—
VDS = 15 V, Fig. 10
DSL to SY_FLT propagation delay at LO turn on
—
3050
—
VLIN = 1 V
DSL to SY_FLT propagation delay after blanking
1050
—
—
VDESAT=15 V, Fig. 10
—
3000
—
VHIN = VLIN = 1 V, VDESAT=15 V,
Fig. 10
Deadtime
—
330
—
Fig. 11
MDT
Deadtime matching, MDT=DTH-DTL
—
—
75
External DT = 0 s, Fig. 11
PDM
Propagation delay matching,
Max (ton, toff) – Min (ton, toff)
—
—
75
External DT > 500 ns, Fig. 7
DESAT1
tSY_FLT,
DESAT2
tSY_FLT,
DESAT3
tSY_FLT,
DESAT4
tBL
DS blanking time at turn on
Deadtime/Delay Matching Characteristics
DT
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IR21141/IR22141SSPbF
schmitt
trigger
comparator
VCC/VB
UV
internal
signal
HIN/LIN/
FLTCLR
internal
signal
10k
VCCUV/VBSUV
VSS/VS
VSS
Figure 1: Undervoltage Diagram
Figure 2: HIN, LIN and FLTCLR Diagram
VCC/VBS
FAULT/SD
SY_FLT
100k
fault/hold
internal signal
active
bias
comparator
schmitt
trigger
DSL/DSH
SSD
RON
VDESAT
VSS
internal
signal
700k
COM/VS
Figure 3: FAULT/SD and SY_FLT Diagram
200ns
oneshot
Figure 4: DSH and DSL Diagram
VCC/VB
LON/HON
VOH
SSDL/SSDH
on/off
internal signal
on/off
internal signal
VOL
LOP/HOP
desat
internal signal
RON,SSD
COM/VS
Figure 5: HOP and LOP Diagram
Figure 6: HON, LON, SSDH and SSDL Diagram
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IR21141/IR22141SSPbF
3.3V
HIN
LIN
50%
t on
50%
PW in
t off
tr
tf
PW out
HO (HOP=HON)
LO (LOP=LON)
90%
90%
10%
10%
Figure 7: Switching Time Waveforms
Ton1
Io1+
Io2+
Figure 8: Output Source Current
3.3V
HIN/LIN
t DS
8V
8V
DSH/DSL
SSD Driver Enable
t DESAT
t SS
HO/LO
Figure 9: Soft Shutdown Timing Waveform
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IR21141/IR22141SSPbF
50%
50%
HIN
50%
LIN
8V
DSH
8V
8V
8V
DSL
t
SY_FLT
50%
50%
t
SY_FLT,DESAT1
50%
50%
SY_FLT,DESAT3
tSY_FLT,DESAT2
tSY_FLT,DESAT4
FAULT/SD
FLTCLR
tDESAT2
tDESAT1
90% SoftShutdown
50%
10%
HON
tBL
Turn_Off propagation Delay
90% SoftShutdown
50%
90%
tBL
tDESAT4
tDESAT3
Turn-On Propagation Delay
10%
LON
90% SoftShutdown
50%
90% SoftShutdown
50%
90%
tBL
tBL
Turn-On Propagation Delay
Figure 10: Desat Timing
LIN
HIN
50%
HO (HOP=HON)
50%
50%
50%
DTH
LO (LOP=LON)
DTL
50%
50%
MDT=DTH-DTL
Figure 11: Internal Deadtime Timing
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IR21141/IR22141SSPbF
Lead Assignments
1
HIN
24
DSH
VB
LIN
FLT_CLR
N.C.
SY_FLT
HOP
FAULT/SD
HON
24-Lead SSOP
VSS
VS
SSOP24
SSDL
SSDH
COM
N.C.
LON
N.C.
LOP
N.C.
VCC
N.C.
12
DSL
13
N.C.
Lead Definitions
Symbol
VCC
Description
Low side gate driver supply
VSS
Logic ground
HIN
Logic input for high side gate driver outputs (HOP/HON)
LIN
Logic input for low side gate driver outputs (LOP/LON)
Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition.
As an input, shuts down the outputs of the gate driver regardless HIN/LIN status.
Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence
is occurring. As an input, an active low signal freezes both output status.
Fault clear active high input. Clears latched fault condition (see Fig. 17)
FAULT/SD
SY_FLT
FLT_CLR
LOP
LON
Low side driver sourcing output
Low side driver sinking output
DSL
SSDL
Low side IGBT desaturation protection input
Low side soft shutdown
COM
VB
Low side driver return
High side gate driver floating supply
HOP
HON
High side driver sourcing output
High side driver sinking output
DSH
High side IGBT desaturation protection input
SSDH
VS
High side soft shutdown
High side floating supply return
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IR21141/IR22141SSPbF
VCC
VB
on/off
SCHMITT
TRIGGER
INPUT
HIN
on/off (HS)
SHOOT
THROUGH
PREVENTION
LIN
INPUT
HOLD
LOGIC
OUTPUT
SHUTDOWN
LOGIC
on/off (LS)
LATCH
on/off
LOCAL DESAT
PROTECTION
LEVEL
SHIFTERS
desat
soft
di/dt control
Driver
HOP
HON
shutdown
SOFT SHUTDOWN
SSDH
UV_VBS DETECT
(DT) Deadtime
internal Hold
Hard ShutDown
DSH
UV_VCC
DETECT
VS
UV_VCC
on/off
DesatHS
SY_FLT
FAULT/SD
SSD
HOLD
FAULT
SD
LOCAL DESAT
PROTECTION
FAULT LOGIC
managemend
(See figure 14)
soft
di/dt control
Driver
LOP
LON
shutdown
SSDL
SOFTSHUTDOWN
DesatLS
FLT_CLR
DSL
COM
VSS
FUNCTIONAL BLOCK DIAGRAM
SY
_
FL
T
Start-Up
Sequence
FL
T_
D
/S
LT
UnderVoltage
VBS
HO=0, LO=LIN
UV_VCC
L
_F
T
_V
UV
CC
LT
/S
D
UV_VBS
FA U
LT/S
D
FA
U
HIN
/LIN
U
SY
Freeze
DS
H/
L
L
H/
DS
FLT
SY_
Soft
ShutDown
FA
S
HO/LO=1
UnderVoltage
VCC
HO=LO=0
VB
V_
UV_V
CC
HI
N
/L
IN
FAU
LT/S
D
U
FAULT
DESAT
EVENT
/SD
ShutDown
HO=LO=0
CL
R
FAULT
STATE DIAGRAM
Stable State
− FAULT
− HO=LO=0 (Normal operation)
− HO/LO=1 (Normal operation)
− UNDERVOLTAGE VCC
− SHUTDOWN (SD)
− UNDERVOLTAGE VBS
− FREEZE
Temporary State
− SOFT SHUTDOWN
− START UP SEQUENCE
System Variable
− FLT_CLR
− HIN/LIN
− UV_VCC
− UV_VBS
− DSH/L
− SY_FLT
− FAULT/SD
NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition.
NOTE 2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event happens in HIN.
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IR21141/IR22141SSPbF
HO/LO Status
0
1
SSD
LO/HO
LOn-1/HOn-1
HOP/LOP
HON/LON
SSDH/SSDL
HiZ
0
HiZ
1
HiZ
HiZ
HiZ
HiZ
0
Output follows inputs (in=1->out=1, in=0->out=0)
Output keeps previous status
Logic Table: Output Drivers Status Description
INPUTS
Operation
Shutdown
Fault Clear
Fault Cleared
Normal
Operation
Anti Shoot
Through
Soft
Shutdown
(entering)
INPUT/OUTPUT
Hin
Lin
FLT_CLR
X
X
X
HIN
Undervoltage
Yes: V< UV
threshold
No : V> UV
threshold
X: don’t care
LIN
OUTPUTS
______
SY_FLT
SSD: desat (out)
HOLD: freezing
(in)
_________
FAULT/SD
SD: shutdown (in)
FAULT: diagnostic
(out)
VCC
VBS
HO
LO
X
0 (SD)
X
X
0
0
No
No
HO
LO
No
No
HO
LO
X
(FAULT)
†
1
††
HIN
LIN
1
X
1
0
0
1
1
No
No
1
0
0
1
0
1
1
No
No
0
1
0
0
0
1
1
No
No
0
0
1
1
0
1
1
No
No
0
0
1
No
No
SSD
0
1
0
0
(SSD)
0
1
0
(SSD)
1
No
No
0
SSD
0
(SSD)
(FAULT)
No
No
0
0
(SSD)
(FAULT)
No
No
0
0
Soft
Shutdown
(finishing)
X
X
X
0
Freeze
X
X
X
0 (HOLD)
1
No
No
HOn-1
LOn-1
X
LIN
X
1
1
No
Yes
0
LO
X
X
X
1
0 (FAULT)
Yes
X
0
0
Undervoltage
†
††
X
SY_FLT automatically resets after the SSD event is over, without requiring FLT_CLR to be asserted. To
avoid FLT_CLR conflicting with the SSD sequence of operations, in the event of a SSD during normal
operation it is recommended not to apply FLT_CLR while SY_FLT is active. At power supply start-up
instead, it is recommended to keep FLT_CLR active to prevent spurious diagnostic signals being
generated, as described in section 1.1 Start-Up Sequence and in section 1.4.5 Fault Management at
Start-up.
Holding FLT_CLR high all time will not allow the gate driver to latch the FAULT status and migth
compromise power system protection.
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IR21141/IR22141SSPbF
1.4 Fault Management
The IR21141/IR22141 is able to manage supply failure
(undervoltage lockout) and transistor desaturation (on
both the low and high side switches).
1 Features Description
1.1 Start-Up Sequence
At power supply start-up, it is recommended to keep the
FLT_CLR pin active until the supply voltages are
properly established. This prevents spurious diagnostic
signals being generated.
When the bootstrap supply topology is used for
supplying the floating high side stage, the following startup sequence is recommended (see also Fig. 12):
1.
2.
3.
4.
5.
Set VCC,
Set FLT_CLR pin to HIGH level,
Set LIN pin to HIGH level and charge the
bootstrap capacitor,
Release LIN pin to LOW level,
Release FLT_CLR pin to LOW level.
VCC
1.4.1 Undervoltage (UV)
The undervoltage protection function disables the
driver’s output stage which prevents the power device
from being driven when the input voltage is less than the
undervoltage threshold. Both the low side (VCC supplied)
and the floating side (VBS supplied) are controlled by a
dedicate undervoltage function.
An undervoltage event on the VCC pin (when
VCC < UVVCC-) generates a diagnostic signal by forcing
the FAULT/SD pin low (see FAULT/SD section and Fig.
14). This event disables both the low side and floating
drivers and the diagnostic signal holds until the
undervoltage condition is over. The fault condition is not
latched and the FAULT/SD pin is released once VCC
becomes higher than UVVCC+.
The VBS undervoltage protection works by disabling only
the floating driver. Undervoltage on VBS does not prevent
the low side driver from activating its output nor does it
generate diagnostic signals. The VBS undervoltage
condition (VBS < UVVBS-) latches the high side output
stage in the low state. VBS must exceed the UVVBS+
threshold to return the device to its normal operating
mode. To turn on the floating driver, HIN must be reasserted high (rising edge event on HIN is required).
FLT_CLR
LIN
LO
Figure 12 Start-Up Sequence
A minimum 15 µs LIN and FLT-CLR pulse is required.
A minimum supply voltage of 8V is recommended for the
driver to operate safely under switching conditions at VS
pin. At lower supply the gate driving capability decreases
and might become not sufficient to counteract switching
charge injected to the outputs.
1.2 Normal Operation Mode
After the start-up sequence has completed, the device
becomes fully operative (see grey blocks in the State
Diagram).
HIN and LIN produce driver outputs to switch
accordingly, while the input logic monitors the input
signals and deadtime (DT) prevent shoot-through events
from occurring.
1.3 Shutdown
The system controller can asynchronously command the
Hard Shutdown (HSD) through the 3.3 V compatible
CMOS I/O FAULT/SD pin. This event is not latched.
In a multi-phase system, FAULT/SD signals are or-ed so
the controller or one of the gate drivers can force the
simultaneous shutdown of the other gate drivers through
the same pin.
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1.4.2 Power Devices Desaturation
Different causes can generate a power inverter failure
(phase and/or rail supply short-circuit, overload
conditions induced by the load, etc.). In all of these fault
conditions, a large increase in current results in the
IGBT.
The IR21141/IR22141 fault detection circuit monitors the
IGBT emitter to collector voltage (VCE) (an external high
voltage diode is connected between the IGBT’s collector
and the ICs DSH or DSL pins). A high current in the
IGBT may cause the transistor to desaturate; this
condition results in an increase of VCE.
Once in desaturation, the current in the power transistor
can be as high as 10 times the nominal current.
Whenever the transistor is switched off, this high current
generates relevant voltage transients in the power stage
that need to be smoothed out in order to avoid
destruction (by over-voltage). The gate driver is able to
control the transient condition by smoothly turning off the
desaturated transistor with its integrated soft shutdown
(SSD) protection.
1.4.3 Desaturation Detection: DSH/L Function
Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This configuration is
the same for both the high and low side output stages.
© 2009 International Rectifier
12
RDSH/L
Ron,ss
IR21141/IR22141SSPbF
Figure 13: High and Low Side Output Stage
internal
HOLD
internal FAULT
(hard shutdown)
SY_FLT
(external
hold)
FAULT/SD
(external hard
shutdown)
Q
Q
SET
CLR
S
DesatHS
R
DesatLS
UVCC
FLTCLR
Figure 14: Fault Management Diagram
The external sensing diode should have breakdown
voltage greater than 600 V (IR21141) or 1200 V
(IR22141), and low stray capacitance (in order to
minimize noise coupling and switching delays). The
diode is biased by an internal pull-up resistor RDSH/L
(equal to VCC/IDS- or VBS/IDS-) or by a dedicated circuit
(see the active-bias section). To limit the current flowing
through DSH and DSL in case of desaturation an
external Schottky diode is required, as shown in Fig. 13.
When VCE increases, the voltage at the DSH or DSL pin
increases too. Being internally biased to the local supply,
the DSH/DSL voltage is automatically clamped. When
DSH/DSL exceeds the VDESAT+ threshold, the
comparator triggers (see Fig. 13). The comparator’s
output is filtered in order to avoid false desaturation
detection by externally induced noise; pulses shorter
than tDS are filtered out. To avoid detecting a false
desaturation event during IGBT turn on, the desaturation
circuit is disabled by a blanking signal (TBL, see blanking
block in Fig. 13). This time is the estimated maximum
IGBT turn on time and must be not exceeded by proper
gate resistance sizing. When the IGBT is not completely
saturated after TBL, desaturation is detected and the
driver will turn off.
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (tSS). Once
the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).
Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).
It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.
1.4.4 Fault Management in Multi-Phase Systems
In a system with two or more gate drivers the
IR21141/IR22141 devices must be connected as shown
in Fig. 15.
Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
turn off the IGBT through the SSDH/SSDL pin. The
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© 2009 International Rectifier
13
IR21141/IR22141SSPbF
FAULT
VCC
VB
VCC
VB
VCC
VB
HOP
LIN
HOP
HIN
FLT_CLR
HON
SSH
HIN
FLT_CLR
HON
SSH
SY_FLT
FAULT/SD
DSH
SY_FLT
VS
LOP
LON
FAULT/SD
SSL
COM
phase U
SY_FLT
VS
LOP
LON
FAULT/SD
SSL
DSL
VSS
DSH
IR2214
LIN
HON
SSH
IR2214
HOP
HIN
FLT_CLR
IR2214
LIN
COM
phase V
VS
LOP
LON
SSL
DSL
VSS
DSH
DSL
VSS
COM
phase W
Figure 15: IR22141 used in a 3 phase application
SY_FLT: The bi-directional SY_FLT pins communicate
each other through a local network. The logic signal is
active low. The device that detects the IGBT
desaturation activates the SY_FLT, which is then read
by the other gate drivers. When SY_FLT is active all the
drivers hold their output state regardless of the input
signals (HIN, LIN) they receive from the controller (freeze
state). This feature is particularly important in phase-tophase short circuit where two IGBTs are involved; in
fact, while one is softly shutting-down, the other must be
prevented from hard shutdown to avoid exiting SSD. In
the freeze state, the frozen drivers are not completely
inactive because desaturation detection still takes the
highest priority. SY_FLT communication has been
designed for creating a local network between the
drivers.
FAULT/SD:
The bi-directional FAULT/SD pins
communicate with each other and with the system
controller. The logic signal is active low. When low, the
FAULT/SD signal commands the outputs to go off by
hard shutdown. There are three events that can force
FAULT/SD low:
1.
2.
3.
Desaturation detection event: the FAULT/SD
pin is latched low when SSD is over, and only a
FLT_CLR signal can reset it;
Undervoltage on VCC: the FAULT/SD pin is
forced low and held until the undervoltage is
active. This event is not latched;
FAULT/SD is externally driven low either from
the controller or from another IR21141/IR22141
device. This event is not latched; therefore the
FLT_CLR cannot disable it. Only when
FAULT/SD becomes high the device returns to
its normal operating mode.
1.4.5 Fault Management at Start-up
When the bootstrap supply topology is used for
supplying the floating high side and the recommended
power supply start-up sequence is followed, FLT_CLR
pin must be kept active to prevent spurious diagnostic
signals being generated.
In the event of power inverter failure already present or
occurring during start-up (phase and/or rail supply shortcircuit, overload conditions induced by the load, etc.),
keeping the FLT_CLR pin active will also prevent the
real fault condition to be detected with the FAULT/SD
pin. In such a condition a large current increase in the
IGBT will desaturate the transistor, allowing the gate
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driver to detect and turn-off the desaturated transistor
with the integrated soft shutdown (SSD) protection.
As with a normal SSD sequence, during SSD the
SY_FLT output pin (active low, see Fig. 14) will report
the gate driver status. But now, being the FLT_CLR pin
already active, the gate driver will not generate a FAULT
signal by activating the FAULT/SD pin and it will not
enter hard shutdown.
To prevent the driver to resume charging the bootstrap
capacitor, therefore re-establishing the condition that will
determine again the occurrence of the large current
increase in the IGBT, it is recommended to monitor the
SY_FLT output pin. Should the SY_FLT output pin go
low during the start-up sequence, the controller must
interpret a power inverter failure is present, and stop the
start-up sequence.
1.5 Active Bias
For the purpose of sensing the power transistor
desaturation, the collector voltage is monitored (an
external high voltage diode is connected between the
IGBT’s collector and the IC’s DSH or DSL pin). The
diode is normally biased by an internal pull up resistor
connected to the local supply line (VB or VCC). When the
transistor is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by the
internal pull up resistor value.
In the high side circuit, the desaturation biasing current
may become relevant for dimensioning the bootstrap
capacitor (see Fig. 19). In fact, a pull up resistor with a
low resistance may result in a high current that
significantly discharges the bootstrap capacitor. For that
reason, the internal pull up resistor typical value is of the
order of 100 kΩ.
While the impedance of the DSH/DSL pins is very low
when the transistor is on (low impedance path through
the external diode down to the power transistor), the
impedance is only controlled by the pull up resistor when
the transistor is off. In that case, relevant dV/dt applied
by the power transistor during the commutation at the
output results in a considerable current injected through
the stray capacitance of the diode into the desaturation
detection pin (DSH/DSL). This coupled noise may be
easily reduced by using an active bias structure for the
sensing diode.
In IR21141/IR22141 the DSH/DSL pins integrate an
active pull-up structure respectively to VB/VCC, and a pulldown structure to VS/COM.
The dedicated biasing circuit reduces the impedance on
the DSH/DSL pin when the voltage exceeds the VDESAT
threshold (see Fig. 16). This low impedance helps
rejecting the noise current injected by the parasitic
capacitance. When the power transistor is fully on, the
sensing diode is forward biased and the voltage at the
DSH/DSL pin decreases. At this point the biasing circuit
deactivates, to reduce the bias current of the diode as
shown in Fig. 16.
In certain switching conditions (short pulses, high
temperature) the recovery current of the external desaturation sensing diode might reach levels beyond the
capability of the active bias circuit. In order to avoid
malfunctions and damage for the IC an external Schottky
© 2009 International Rectifier
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IR21141/IR22141SSPbF
while an additional stage is maintained in the active state
for a limited time (ton1). This feature boosts the total
driving capability in order to accommodate both a fast
gate charge to the plateau voltage and dV/dt control in
switching.
diode is required between DSH and VB and between
DSL and Vcc, as shown in Fig 13. A diode similar to the
1N5818 is good enough to protect DSH and DSL.
RDSH/L
100K ohm
At turn off, a single n-channel sinks up to 3 A (IO-) and
offers a low impedance path to prevent the self-turn on
due to the parasitic Miller capacitance in the power
switch.
100 ohm
1.7 Timing and Logic State Diagrams Description
The following figures show the input/output logic
diagram. Figure 17 shows the SY_FLT and FAULT/SD
signals as outputs, whereas Fig. 18 shows them as
inputs.
VDESAT+
VDESAT-
VDSH/L
Figure 16: RDSH/L Active Biasing
1.6 Output Stage
The structure is shown in Fig. 13 and consists of two
turn on stages and one turn off stage. When the driver
turns on the IGBT (see Fig. 8), a first stage is activated
A
B
C
D
E
F
G
HIN
LIN
DSH
DSL
SY_FLT
FAULT/SD
FLT_CLR
HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output
A B
C
D
E
F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
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Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input
© 2009 International Rectifier
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IR21141/IR22141SSPbF
Referred to the timing diagram of Fig. 17:
A. When the input signals are on together the
outputs go off (anti-shoot through),
B. The HO signal is on and the high side IGBT
desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if LIN
goes up, LO does not change (freeze),
C. When FAULT/SD is latched low (see
FAULT/SD section) FLT_CLR can disable it
and the outputs go back to follow the inputs,
D. The DSH goes high but this is not read
because HO is off,
E. The LO signal is on and the low side IGBT
desaturates, the low side behaviour is the
same as described in point B,
F. The DSL goes high but this is not read as LO
is off,
G. As point A (anti-shoot through).
Referred to the timing diagram Fig. 18:
A. The device is in the hold state, regardless of
input variations. The hold state results as
SY_FLT is forced low externally,
B. The device outputs go off by hard shutdown,
externally commanded. A through B is the
same sequence adopted by another IR2x14x
device in SSD procedure.
C. Externally driven low FAULT/SD (shutdown
state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section),
D. The FAULT/SD is released and the outputs go
back to follow the inputs,
E. Externally driven low FAULT/SD: outputs go
off by hard shutdown (like point B),
F. As point A and B but for the low side output.
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© 2009 International Rectifier
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IR21141/IR22141SSPbF
− Charge required by the internal level shifters
(QLS); typical 20 nC,
− Bootstrap capacitor leakage current (ILK_CAP),
− High side on time (THON).
2 Sizing Tips
2.1 Bootstrap Supply
The VBS voltage provides the supply to the high side
driver circuitry of the gate driver. This supply sits on top
of the VS voltage and so it must be floating. The
bootstrap method is used to generate the VBS supply
and can be used with any of the IR211(4,41)/
IR221(4,41) drivers. The bootstrap supply is formed by
a diode and a capacitor as connected in Fig. 19.
bootstrap
resistor
bootstrap
diode
Rboot
VCC
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using at
least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
Then we have:
DC+
VF
QTOT = QG + Q LS + ( I LK _ GE + I QBS +
VB
VCC
+ I LK + I LK _ DIODE + I LK _ CAP + I DS − ) ⋅ THON
HOP
IR2214
VBS
bootstrap
capacitor
VGE
HON
The minimum size of bootstrap capacitor is:
ILOAD
motor
VS
SSDH
C BOOT min =
VCEon
VFP
QTOT
∆V BS
An example follows using IR2214SS or IR22141SS:
COM
a) using a 25 A @ 125 °C 1200 V IGBT
(IRGP30B120KD):
Figure 19: Bootstrap Supply Schematic
This method has the advantage of being simple and low
cost but may force some limitations on duty-cycle and
on-time since they are limited by the requirement to
refresh the charge in the bootstrap capacitor. Proper
capacitor choice can reduce drastically these
limitations.
•
•
•
•
•
•
•
•
•
2.2 Bootstrap Capacitor Sizing
To size the bootstrap capacitor, the first step is to
establish the minimum voltage drop (∆VBS) that we
have to guarantee when the high side IGBT is on.
IQBS = 800 µA
(datasheet IR2214);
ILK = 50 µA (see Static Electrical Characteristics);
QLS = 20 nC
QG = 160 nC
(datasheet IRGP30B120KD);
ILK_GE = 100 nA
(datasheet IRGP30B120KD);
ILK_DIODE = 100 µA
(reverse recovery <100 ns);
ILK_CAP = 0
(neglected for ceramic capacitor);
IDS- = 150 µA (see Static Electrical Characteristics);
THON = 100 µs.
And:
If VGEmin is the minimum gate emitter voltage we want
to maintain, the voltage drop must be:
•
•
•
•
∆VBS ≤ VCC − VF − VGE min − VCEon
under the condition,
VCC = 15 V
VF = 1 V
VCEonmax = 3.1 V
VGEmin = 10.5 V
the maximum voltage drop ∆VBS becomes
VGE min > VBSUV −
∆VBS ≤ VCC − VF − VGEmin − VCEon =
where VCC is the IC voltage supply, VF is bootstrap
diode forward voltage, VCEon is emitter-collector voltage
of low side IGBT, and VBSUV- is the high-side supply
undervoltage negative going threshold.
Now we must consider the
contributing VBS to decrease:
influencing
And the bootstrap capacitor is:
factors
CBOOT ≥
− IGBT turn on required gate charge (QG),
− IGBT gate-source leakage current (ILK_GE),
− Floating section quiescent current (IQBS),
− Floating section leakage current (ILK),
− Bootstrap diode leakage current (ILK_DIODE),
− Desat diode bias when on (IDS),
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290 nC
= 725 nF
0. 4 V
NOTICE: VCC has been chosen to be 15 V. Some
IGBTs may require a higher supply to work correctly
with the bootstrap technique. Also VCC variations
must be accounted in the above formulas.
© 2009 International Rectifier
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IR21141/IR22141SSPbF
minimize the amount of charge fed back from the
bootstrap capacitor to VCC supply.
2.3 Some Important Considerations
Voltage Ripple: There are three different cases to
consider (refer to Fig. 19).
2.4 Gate Resistances
The switching speed of the output transistor can be
controlled by properly sizing the resistors controlling the
turn-on and turn-off gate currents. The following section
provides some basic rules for sizing the resistors to
obtain the desired switching time and speed by
introducing the equivalent output resistance of the gate
driver (RDRp and RDRn).
ILOAD < 0 A; the load current flows in the low side
IGBT (resulting in VCEon).
VBS = VCC − VF − VCEon
In this case we have the lowest value for VBS. This
represents the worst case for the bootstrap capacitor
sizing. When the IGBT is turned off, the Vs node is
pushed up by the load current until the high side
freewheeling diode is forwarded biased.
The example shown uses IGBT power transistors and
Figure 20 shows the nomenclature used in the following
paragraphs. In addition, Vge* indicates the plateau
voltage, Qgc and Qge indicate the gate to collector and
gate to emitter charge respectively.
ILOAD = 0 A; the IGBT is not loaded while being on
and VCE can be neglected
IC
CRES
V BS = VCC − VF
VGE
ILOAD > 0 A; the load current flows through the
freewheeling diode
t1,QGE
V BS = VCC − VF + VFP
t2,QGC
VCE
dV/dt
In this case we have the highest value for VBS. Turning
on the high side IGBT, ILOAD flows into it and VS is
pulled up. To minimize the risk of undervoltage, the
bootstrap capacitor should be sized according to the
ILOAD< 0 A case.
IC
90%
CRESon
CRES
VGE
Vge*
CRESoff
10%
Bootstrap Resistor: A resistor (Rboot) is placed in series
with the bootstrap diode (see Fig. 19) in order to limit
the current when the bootstrap capacitor is initially
charged. We suggest not exceeding 10 Ω to avoid
increasing the VBS time-constant. The minimum on time
for charging the bootstrap capacitor or for refreshing its
charge must be verified against this time-constant.
10%
t,Q
tSW
tDon
tR
Figure 20: Nomenclature
Bootstrap Capacitor: For high tHON designs where an
electrolytic capacitor is used, its ESR must be
considered. This parasitic resistance forms a voltage
divider with Rboot, which generats a voltage step on VBS
at the first charge of bootstrap capacitor. The voltage
step and the related speed (dVBS/dt) should be limited.
As a general rule, ESR should meet the following
constraint.
2.5 Sizing The Turn-On Gate Resistor
Switching-Time: For the matters of the calculation
included hereafter, the switching time tsw is defined
as the time spent to reach the end of the plateau
voltage (a total Qgc+Qge has been provided to the
IGBT gate). To obtain the desired switching time the
gate resistance can be sized starting from Qge and
Qgc, Vcc, Vge* (see Fig. 21):
A parallel combination of a small ceramic capacitor and
a large electrolytic capacitor is normally the best
compromise, the first capacitor posses a fast time
constant and limits the dVBS/dt by reducing the
equivalent resistance. The second capacitor provides a
large capacitance to maintain the VBS voltage drop
within the desired ∆VBS.
I avg =
Qgc + Qge
t sw
and
RTOT =
Bootstrap Diode: The diode must have a BV > 600 V or
1200 V and a fast recovery time (trr < 100 ns) to
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Vcc − V ge*
I avg
© 2009 International Rectifier
18
IR21141/IR22141SSPbF
flowing in RGoff and RDRn (see Fig. 22). If the voltage
drop at the gate exceeds the threshold voltage of the
IGBT, the device may self turn on, causing large
oscillation and relevant cross conduction.
Iavg
Vcc/Vb
CRES
RDRp
RGon
dV/dt
HS Turning ON
COM/Vs
CRESoff
Figure 21: RGon Sizing
RGoff
OFF
where
ON
RTOT = RDRp + RGon
RDRn
C IES
RGon = gate on-resistor
RDRp = driver equivalent on-resistance
Figure 22: RGoff Sizing: Current Path When Low Side is
Off and High Side Turns On
RDRp is approximately given by
RDRp
Vcc t SW Vcc t SW − ton1
 I t + I
t SW
o 2+
=  o1+ on1
Vcc


I o1+
(IO1+ ,IO2+
and
Characteristics”).
ton1
from
for t SW > ton1
for t SW ≤ t on1
“Static
The transfer function between the IGBT collector and
the IGBT gate then becomes:
Vge
Vde
=
s ⋅ ( RGoff + RDRn ) ⋅ CRESoff
1 + s ⋅ ( RGoff + RDRn ) ⋅ (CRESoff + CIES )
Electrical
which yields to a high pass filter with a pole at:
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using typical
datasheet values and assuming VCC= 15 V).
1/τ =
Output Voltage Slope: The turn-on gate resistor
RGon can be sized to control the output slope
(dVOUT/dt). While the output voltage has a nonlinear behaviour, the maximum output slope can be
approximated by:
( RGoff
1
+ RDRn ) ⋅ (CRESoff + CIES )
As a result, when τ is faster than the collector rise time
(to be verified after calculation) the transfer function can
be approximated by:
Vge
I avg
dVout
=
dt
C RESoff
Vde
= s ⋅ ( RGoff + RDRn ) ⋅ CRESoff
so that
inserting the expression yielding Iavg and rearranging:
Vge = ( RGoff + RDRn ) ⋅ CRESoff ⋅
*
RTOT =
Vcc − Vge
dV
C RESoff ⋅ out
dt
dVde
dt
in the time domain. Then the condition:
Vth > Vge = (RGoff + RDRn ) ⋅ CRESoff
As an example, table 2 shows the sizing of gate
resistance to get dVout/dt= 5 V/ns when using two
popular IGBTs (typical datasheet values are used and
VCC= 15 V is assumed).
dVout
dt
must be verified to avoid spurious turn on.
Rearranging the equation yields:
NOTICE: Turn on time must be lower than TBL to avoid
improper desaturation detection and SSD triggering.
RGoff <
Vth
CRESoff
2.6 Sizing the Turn-Off Gate Resistor
The worst case in sizing the turn-off resistor RGoff is
when the collector of the IGBT in the off state is forced
to commutate by an external event (e.g., the turn-on of
the companion IGBT). In this case the dV/dt of the
output node induces a parasitic current through CRESoff
dV
⋅
dt
− RDRn
RDRn is approximately given by
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© 2009 International Rectifier
19
IR21141/IR22141SSPbF
RDRn =
which is driven only by IGBT characteristics.
Vcc
I o−
As an example, table 3 reports RGoff (calculated with the
above mentioned disequation) for two popular IGBTs to
withstand dVout/dt = 5 V/ns.
In any case, the worst condition for unwanted turn on is
with very fast steps on the IGBT collector.
In that case, the collector to gate transfer function can
be approximated with the capacitor divider:
Vge = Vde ⋅
NOTICE: The above-described equations are intended
to approximate a way to size the gate resistance. A
more accurate sizing may provide more precise device
and PCB (parasitic) modelling.
CRESoff
(CRESoff + CIES )
IGBT
Qge
Qgc
IRGP30B120K(D)
IRG4PH30K(D)
19 nC
10 nC
82 nC
20 nC
IGBT
Qge
IRGP30B120K(D)
IRG4PH30K(D)
19 nC
10 nc
Qgc
Vge*
tsw
Iavg
Rtot
RGon → std commercial value
9V
400 ns 0.25 A 24 Ω RTOT - RDRp = 12.7 Ω → 10 Ω
9V
200 ns 0.15 A 40 Ω RTOT - RDRp = 32.5 Ω → 33 Ω
Table 1: tsw Driven RGon Sizing
Vge*
CRESoff
Rtot
RGon → std commercial value
82 nC
9V
85 pF
14 Ω
RTOT - RDRp = 6.5 Ω → 8.2 Ω
20 nC
9V
14 pF
RTOT - RDRp = 78 Ω → 82 Ω
85 Ω
Table 2: dVOUT/dt Driven RGon Sizing
IGBT
IRGP30B120K(D)
IRG4PH30K(D)
Vth(min)
4
CRESoff
85 pF
3
14 pF
Table 3: RGoff Sizing
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Tsw
→420 ns
→202 ns
dVout/dt
→4.5 V/ns
→5 V/ns
RGoff
RGoff ≤ 4 Ω
RGoff ≤ 35 Ω
© 2009 International Rectifier
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IR21141/IR22141SSPbF
3 PCB Layout Tips
3.5 Routing and Placement Example
3.1 Distance from High to Low Voltage
Figure 24 shows one of the possible layout solutions
using a 3 layer PCB. This example takes into account
all the previous considerations. Placement and routing
for supply capacitors and gate resistances in the high
and low voltage side minimize the supply path loop and
the gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible to
the bootstrap capacitor and the anode far from high
voltage and close to VCC.
The IR2x14x pinout maximizes the distance between
floating (from DC- to DC+) and low voltage pins. It’s
strongly recommended to place components tied to
floating voltage on the high voltage side of device (VB,
VS side) while the other components are placed on the
opposite side.
3.2 Ground Plane
To minimize noise coupling, the ground plane must not
be placed under or near the high voltage floating side.
R2
3.3 Gate Drive Loops
VGH
Current loops behave like antennas and are able to
receive and transmit EM noise. In order to reduce the
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
much as possible. Figure 23 shows the high and low
side gate loops.
D3
Phase
IR2214
VGL
R5
R6
C2
R7
a)
Top Layer
C1
D1
VEH
VCC
R1
VEL
IGC
gate
resistance
DC+
R4
Moreover, current can be injected inside the gate drive
loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate
loop contributes to developing a voltage across the
gate-emitter, increasing the possibility of self turn-on.
For this reason, it is strongly recommended to place the
three gate resistances close together and to minimize
the loop area (see Fig. 23).
VB/ VCC
D2
R3
b) Bottom Layer
CGC
H/LOP
H/LON
SSDH/L
Gate Drive
Loop
VGE
VS/COM
Figure 23: gate drive loop
3.4 Supply Capacitors
c) Ground Plane
The IR2x14x output stages are able to quickly turn on
an IGBT, with up to 2 A of output current. The supply
capacitors must be placed as close as possible to the
device pins (VCC and VSS for the ground tied supply, VB
and VS for the floating supply) in order to minimize
parasitic inductance/resistance.
Figure 24: layout example
Information below refers to Fig. 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
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© 2009 International Rectifier
21
IR21141/IR22141SSPbF
VCCUV- Threshold (V)
VCCUV+ Threshold (V)
Figures 25-83 provide information on the experimental performance of the IR21141/IR22141SSPbF HVIC. The line
plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots
were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood trend. The individual data points on the curve were determined by
calculating the averaged experimental value of the parameter (for a given temperature).
10.30
10.25
10.20
10.15
10.10
10.05
9.60
9.55
9.50
9.45
9.40
9.35
9.30
9.25
Exp.
10.00
Exp.
9.20
9.95
9.15
-50
-25
0
25
50
75
100
125
-50
-25
0
o
V BSUV- ThresholdThreshold (V)
VBSUV+ Threshold Threshold (V)
100
125
Figure 26. VCCUV- Threshold vs. Temperature
10.45
10.40
10.35
10.30
10.25
10.20
Exp.
10.05
9.70
9.65
9.60
9.55
9.50
9.45
9.40
9.35
Exp.
9.30
9.25
10.00
-50
-25
0
25
50
75
100
-50
125
-25
0
VCC Quiescent Current (mA)
500
400
Exp.
200
100
0
0
25
50
75
75
100
125
Figure 28. VBSUV- Threshold vs. Temperature
600
-25
50
Temperature ( C)
Figure 27. V BSUV+ Threshold vs. Temperature
-50
25
o
Temperature (oC)
VBS Quiescent Current (uA)
75
Temperature ( C)
Figure 25. VCCUV+ Threshold vs. Temperature
300
50
o
Temperature ( C)
10.15
10.10
25
100
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
Exp.
-50
125
-25
0
25
50
75
100
125
o
o
Temperature ( C)
Temperature ( C)
Figure 30. V CC Quiescent Current vs. Temperature
Figure 29. VBS Quiescent Current vs. Temperature
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© 2009 International Rectifier
22
V IL Logic Input Voltage (V)
V IH Logic Input Voltage (V)
IR21141/IR22141SSPbF
2.70
2.30
1.90
Exp.
1.50
1.10
2.10
1.80
1.50
1.20
Exp.
0.90
-50
-25
0
25
50
75
100
125
-50
-25
0
o
100
125
Figure 32. VIL Logic Input Voltage vs. Temperature
LIN Logic "1" Input Voltage (V)
VIHSS HIN Logic Input Hysteresis (V)
75
Temperature ( C)
Figure 31. VIH Logic Input Voltage vs. Temperature
0.60
Exp.
0.40
0.30
0.20
0.10
2.20
1.90
Exp.
1.60
1.30
1.00
0.00
-50
-25
0
25
50
75
100
-50
125
-25
0
VIHSS LIN Logic Input Hysteresis (V)
1.90
1.60
1.30
Exp.
1.00
0.70
0
25
50
75
100
125
Figure 34. LIN Logic "1" Input Voltage vs. Temperature
Figure 33. VIHSS HIN Logic Input Hysteresis vs.
Temperature
-25
50
Temperature ( C)
Temperature ( C)
-50
25
o
o
LIN Logic "0" Input Voltage (V)
50
o
Temperature ( C)
0.50
25
75
100
125
o
0.90
0.70
Exp.
0.50
0.30
0.10
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Figure 35. LIN Logic "0" Input Voltage vs. Temperature
Figure 36. VIHSS LIN Logic Input Hysteresis vs.
Temperature
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© 2009 International Rectifier
23
2.30
2.00
Exp.
1.70
1.40
1.10
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
VIL FLTCLR Logic Input Hysteresis (V)
VIH FLTCLR Logic Input Voltage (V)
IR21141/IR22141SSPbF
Exp.
1.10
0.80
-50
-25
0
0.60
Exp.
0.40
0.30
75
100
125
o
2.10
1.70
Exp.
1.30
0.90
-50
-25
0
25
50
75
100
-50
125
-25
0
1.70
Exp.
0.90
0.50
25
50
75
100
125
VIHSS SD Logic Input Hysteresis (V)
2.10
0
75
100
125
Figure 40. VIH SD Logic Input Voltage vs. Temperature
Figure 39. VIHSS FLTCLR Logic Input Hysteresis vs.
Temperature
-25
50
Temperature ( C)
Temperature ( C)
-50
25
o
o
VIL SD Logic Input Voltage (V)
50
0.50
0.20
1.30
25
Figure 38. VIL FLTCLR Logic Input Voltage vs.
Temperature
V IH SD Logic Input Voltage (V)
VIHSS FLTCLR Logic Input Hysteresis (V)
1.40
Temperature ( C)
Figure 37. VIH FLTCLR Logic Input Voltage vs.
Temperature
0.50
1.70
0.60
0.50
Exp.
0.40
0.30
0.20
-50
-25
0
25
50
75
100
125
o
o
Temperature ( C)
Temperature ( C)
Figure 42. VIHSS SD Logic Input Hysteresis vs. Temperature
Figure 41. VIL SD Logic Input Voltage vs. Temperature
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© 2009 International Rectifier
24
V IL SYFLT Logic Input Voltage (V)
V IH SYFLT Logic Input Voltage (V)
IR21141/IR22141SSPbF
2.40
2.00
Exp.
1.60
1.20
0.80
-50
-25
0
25
50
75
100
125
2.40
2.00
1.60
Exp.
1.20
0.80
-50
-25
0
o
100
125
Figure 44. VIL SYFLT Logic Input Voltage vs. Temperature
60
0.60
0.50
50
Exp.
VOL LO (mV)
VIHSS SYFLT Logic Input Hysteresis (V)
75
Temperature ( C)
Figure 43. VIH SYFLT Logic Input Voltage vs. Temperature
0.40
0.30
0.20
40
Exp.
30
20
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
100
125
o
Temperature ( C)
Figure 45. VIHSS SYFLT Logic Input Hysteresis vs.
Temperature
Figure 46. VOL LO vs. Temperature
900
65
725
55
V OL HO (mV)
VOH LO (mV)
50
o
Temperature ( C)
550
375
25
Exp.
45
Exp.
35
25
200
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
Temperature (oC)
Temperature (oC)
Figure 48. VOL HO vs. Temperature
Figure 47. VOH LO vs. Temperature
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© 2009 International Rectifier
25
VDSH+ DSH Input Voltage (V)
IR21141/IR22141SSPbF
900
VOH HO (mV)
725
550
Exp.
375
200
-50
-25
0
25
50
75
100
125
9
Exp.
8
7
6
5
-50
-25
0
25
VDSH- DSH Input Voltage (V)
VDSL+ DSL Input Voltage (V)
9
9
8
Exp.
8
25
50
75
100
7.60
Exp.
6.90
6.20
125
-25
0
7.50
Exp.
6.50
6.00
0
25
50
75
100
125
FAULT/SD Open Drain Resistance (Ω)
VDSL- DSL Input Voltage (V)
8.00
-25
50
75
100
125
Figure 52. VDSH- DSH Input Voltage vs. Temperature
Figure 51. VDSL+ DSL Input Voltage vs. Temperature
-50
25
Temperature (oC)
Temperature (oC)
7.00
125
8.30
5.50
-50
7
0
100
Figure 50. VDSH+ DSH Input Voltage vs. Temperature
Figure 49. VOH HO vs. Temperature
-25
75
Temperature ( C)
Temperature ( C)
-50
50
o
o
90
75
60
45
Exp.
30
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 54. FAULT/SD Open Drain Resistance vs.
Temperature
Figure 53. VDSL- DSL Input Voltage vs. Temperature
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© 2009 International Rectifier
26
130
DTL Off Deadtime (ns)
SY_FLT Open Drain Resistance (Ω)
IR21141/IR22141SSPbF
105
80
55
Exp.
30
-50
-25
0
25
50
75
100
490
430
370
Exp.
310
250
-50
125
-25
0
Temperature (oC)
75
100
125
Temperature ( C)
Figure 56. DTL Off Deadtime vs. Temperature
TonH Propagation Delay (ns)
DTH Off Deadtime (ns)
50
o
Figure 55. SY_FLT Open Drain Resistance vs. Temperature
490
430
Exp.
370
310
780
660
540
Exp.
420
300
250
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
o
o
Temperature ( C)
Temperature ( C)
Figure 58. TonH Propagation Delay vs. Temperature
Figure 57. DTH Off Deadtime vs. Temperature
32
780
TrH Turn On Rise Time (ns)
ToffH Propagation Delay (ns)
25
660
540
420
Exp.
28
24
20
Exp.
16
12
300
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
o
Temperature ( C)
o
Temperature ( C)
Figure 60. TrH Turn On Rise Time vs. Temperature
Figure 59. ToffH Propagation Delay vs. Temperature
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© 2009 International Rectifier
27
TonL Propagation Delay (ns)
TfH Turn Off Fall Time (ns) )
IR21141/IR22141SSPbF
18
15
12
Exp.
9
780
660
540
Exp.
420
300
6
-50
-25
0
25
50
75
100
-50
125
-25
0
75
100
125
Figure 62. TonL Propagation Delay vs. Temperature
780
TrL Turn On Rise Time (ns)
ToffL Propagation Delay (ns)
50
Temperature ( C)
Temperature ( C)
Figure 61. TfH Turn Off Fall Time vs. Temperature
660
540
Exp.
420
300
40
33
26
Exp.
19
12
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
o
Temperature ( C)
Figure 63. ToffL Propagation Delay vs. Temperature
Figure 64. TrL Turn On Rise Time vs. Temperature
20
6
16
5
tDSAT1 (us)
TfL Turn Off Fall Time (ns)
25
o
o
12
Exp.
Exp.
4
3
8
4
2
-50
-25
0
25
50
75
100
125
Temperature (oC)
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Figure 65. TfL Turn Off Fall Time vs. Temperature
Figure 66. tDSAT1 vs. Temperature
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© 2009 International Rectifier
28
3
6
3
5
t DSAT3 (us)
tDSAT2 (us)
IR21141/IR22141SSPbF
2
Exp.
2
1
Exp.
4
3
2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
o
Figure 67. tDSAT2 vs. Temperature
100
125
Figure 68. tDSAT3 vs. Temperature
4.50
17
3.50
14
t SSH (us)
t DSAT4 (us)
75
Temperature (oC)
Temperature ( C)
2.50
Exp.
1.50
Exp.
11
8
0.50
5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
o
50
75
100
125
100
125
o
Temperature ( C)
Temperature ( C)
Figure 69. tDSAT4 vs. Temperature
IO2+H SC Pulsed Current (A)
Figure 70. tSSH vs. Temperature
17
14
tSSL (us)
50
Exp.
11
8
1.80
1.45
1.10
Exp.
0.75
0.40
5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
o
o
Temperature ( C)
Temperature ( C)
Figure 72. IO2+H SC Pulsed Current vs. Temperature
Figure 71. tSSL vs. Temperature
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© 2009 International Rectifier
29
IO-H SC Pulsed Current (A)
IR21141/IR22141SSPbF
IO2+L SC Pulsed Current (A)
1.80
1.45
Exp.
1.10
0.75
0.40
-50
-25
0
25
50
75
100
3.25
2.80
Exp.
2.35
1.90
1.45
-50
125
-25
0
Temperature (oC)
75
100
125
Figure 74. IO-H SC Pulsed Current vs. Temperature
3.50
900
3.05
700
Exp.
2.60
t ON1H (ns)
IO-L SC Pulsed Current (A)
50
Temperature (oC)
Figure 73. IO2+L SC Pulsed Current vs. Temperature
2.15
Exp.
500
300
1.70
1.25
100
-50
-25
0
25
50
75
100
125
-50
-25
0
o
50
75
100
125
100
125
Temperature ( C)
Figure 75. IO-L SC Pulsed Current vs. Temperature
IO1+H SC Pulsed Current (A)
Figure 76. tON1H vs. Temperature
500
400
Exp.
300
25
o
Temperature ( C)
tON1L (ns)
25
200
3.00
2.50
2.00
Exp.
1.50
1.00
100
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
o
Temperature (oC)
Temperature ( C)
Figure 78. IO1+H SC Pulsed Current vs. Temperature
Figure 77. tON1L vs. Temperature
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© 2009 International Rectifier
30
IHIN+ Logic "1" Input Bias Current (uA)
IO1+L SC Pulsed Current (ns)
IR21141/IR22141SSPbF
4
3
Exp.
2
1
0
-50
-25
0
25
50
75
100
125
900
700
500
300
Exp.
100
-50
-25
0
0.02
Exp.
-0.08
-0.13
-0.18
-0.23
-0.28
-25
0
25
50
100
125
75
100
125
900
700
500
300
Exp.
100
-50
-25
o
0
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Figure 81. IHIN- Logic "0" Input Bias Currentvs.
Temperature
ILIN- Logic "0" Input Bias Current (uA)
75
Figure 80. IHIN+ Logic "1" Input Bias Current vs.
Temperature
ILIN+ Logic "1" Input Bias Current (uA)
IHIN- Logic "0" Input Bias Current (uA)
Figure 79. IO1+L SC Pulsed Current vs. Temperature
-50
50
Temperature ( C)
Temperature ( C)
-0.03
25
o
o
Figure 82. ILIN+ Logic "1" Input Bias Current vs.
Temperature
0.02
-0.03
Exp.
-0.08
-0.13
-0.18
-0.23
-0.28
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Figure 83. ILIN- Logic "0" Input Bias Current vs.
Temperature
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© 2009 International Rectifier
31
IR21141/IR22141SSPbF
Case Outline
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© 2009 International Rectifier
32
IR21141/IR22141SSPbF
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR 24SSOP:2000 units per reel
Metric
Min
Max
11.90
12.10
3.90
4.10
15.70
16.30
7.40
7.60
8.30
8.50
8.50
8.70
1.50
n/a
1.50
1.60
Code
A
B
C
D
E
F
G
H
Imperial
Min
Max
0.468
0.476
0.153
0.161
0.618
0.641
0.291
0.299
0.326
0.334
0.334
0.342
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 24SSOP
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
22.40
G
18.50
21.10
H
16.40
18.40
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.881
0.728
0.830
0.645
0.724
© 2009 International Rectifier
33
IR21141/IR22141SSPbF
ORDER INFORMATION
24-Lead SSOP IR21141SSPbF
24-Lead SSOP IR22141SSPbF
24-Lead SSOP Tape & Reel IR21141SSPbF
24-Lead SSOP Tape & Reel IR22141SSPbF
WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105
This part has been qualified per industrial level
http://www.irf.com Data and specifications subject to change without notice. 5/18/2006
www.irf.com
© 2009 International Rectifier
34
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