IDT IDT71T7570285BG Synchronous zbt sram Datasheet

512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
Features
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IDT71T75702
IDT71T75902
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
W (READ/WRITE) control pin
Single R/W
4-word burst capability (Interleaved or linear)
BW 1 - BW 4) control (May tie active)
Individual byte write (BW
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
Pin Description Summary
A0-A 19
Address Inputs
Input
Synchronous
CE1, CE 2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/LD
Advance Burst Address/Load New Address
Input
Synchronous
LBO
Linear/Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
N/A
TDI
Test Data Input
Input
N/A
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
N/A
TRST
JTAG Reset (Optional)
Input
Asynchronous
Input
Synchronous
I/O
Synchronous
ZZ
Sleep Mode
I/O0-I/O31 , I/OP1-I/OP4
Data Input/Output
VDD, V DDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5319 tbl 01
APRIL 2004
FEBRUARY
2009
1
©2004 Integrated Device Technology, Inc.
DSC-5319/08
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A19
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/ LD low, CEN lo w, and true chip enables.
ADV/ LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the
chip deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
ADV/LD is sampled high.
R/W
Read / Write
I
N/A
R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
CEN
Clock Enable
I
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/ W is sampled high. The appropriate byte(s) of data are written into the device one cycle
later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71T75702/902
(CE1 or CE2 sampled high or CE 2 sampled low) and ADV/ LD low at the rising edge of clock, initiates a
deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after
deselect is initiated.
CE2
Chip Enable
I
HIGH Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE 2 has
inverted polarity but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71T75702/902. Except for OE, all timing refe rences for the device are
made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW Burst ord er selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is
low the Linear burst sequence is selected. LBO is a static input, and it must not change during device
operation.
OE
Output Enable
I
LOW Asynchronous output enable. OE must be low to read data from the IDT71T75702/902. When OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be active ly controlled for read and
write cycles. In normal operation, OE can be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active d epending on the state of
the TAP controller.
TRST
JTAG Reset
(Optional)
I
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
HIGH IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
This pin has an internal pulldown.
VDD
Power Supply
N/A
N/A
2.5V core power supply.
VDDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
NOTE:
5319 tbl 02
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram — 512K x 36
LBO
Address A [0:18]
512K x 36 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
CE1, CE2 CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
DO
Control Logic
Q
Clk
Mux
Clock
Gate
OE
TMS
TDI
TCK
TRST
(optional)
Sel
Data I/O [0:31], I/O P[1:4]
JTAG
5319 drw 01
TDO
6.42
3
,
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram — 1M x 18
LBO
1M x 18 BIT
MEMORY ARRAY
Address A [0:19]
D
Q
Address
D
Q
Control
CE1, CE2 CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Clock
Gate
OE
TMS
TDI
TCK
TRST
Data I/O [0:15], I/O P[1:2]
TDO
JTAG
(optional)
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDQ
I/O Supply Voltage
2.375
2.5
2.625
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage — Inputs
1.7
____
VDD +0.3
V
VIH
Input High Voltage — I/O
1.7
____
VDDQ +0.3(2)
V
____
0.7
VIL
Input Low Voltage
Sel
-0.3
(1)
V
5319 tbl 03
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC /2, once per cycle.
6.42
4
5319 drw 01a
,
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(1)
VSS
VDD
VDDQ
Commerical
0 °C to +70 °C
OV
2.5V ± 5%
2.5V ± 5%
Industrial
-40 °C to +85 °C
OV
2.5V ± 5%
2.5V ± 5%
5319 tbl 05
A8
A9
A18
A17
BW3
BW2
BW1
CE2
CE2
BW4
A7
CE1
A6
Pin Configuration — 512K x 36
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
VDD(2)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
4
77
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
28
53
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VSS(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A16
A10
A11
A12
A13
A14
A15
NC / TDO(3)
NC / TCK(3,4)
NC / TMS(3)
NC / TDI(3)
VSS
VDD
LBO
A5
A4
A3
A2
A1
A0
5319 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
2. Pin 16 does not have to be connected directly to V DD as long as the input voltage is ≥ VIH.
3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation,
several settings are possible. Pins 38, 39 and 43 could be tied to VDD or V SS and pin 42 should be left unconnected. Or all JTAG inputs (TMS,
TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
6.42
5
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
A19
A18
A8
A9
NC
BW2
BW1
CE2
CE2
NC
A6
A7
CE1
Pin Configuration — 1M x 18
Commercial
Industrial
VTERM(2)
Symbol
Terminal Voltage with
Respect to GND
-0.5 to +3.6
-0.5 to +3.6
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDD +0.5
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
-0.5 to VDDQ +0.5
TA(7)
Operating Ambient
Temperature
0 to +70
-40 to +85
o
C
C
C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
78
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
VDD(2)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
19
63
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
53
28
29
52
30
51
5319 drw 02a
A11
A12
A13
A14
A15
A16
A17
A5
A4
A3
A2
A1
A0
NC / TMS(3)
NC / TDI(3)
VSS
VDD
NC / TDO(3)
NC / TCK(3,4)
LBO
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VSS(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to V SS as long as the
input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.
3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will
remain disabled from power up.
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
5
pF
VOUT = 3dV
7
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
V
Temperature Under Bias
-55 to +125
-55 to +125
-55 to +125
-55 to +125
o
PT
Power Dissipation
2.0
2.0
W
IOUT
DC Output Current
50
50
mA
5319 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
, maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. During production testing, the case temperature equals T A.
fBGA Capacitance
(TA = +25°° C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
5319 tbl 07b
pF
Conditions
V
Storage Temperature
(TA = +25°° C, f = 1.0MHz)
Symbol
V
TSTG
5319 tbl 07
BGA Capacitance
V
TBIAS
(TA = +25°° C, f = 1.0MHz)
Parameter(1)
Unit
o
TQFP Capacitance
Symbol
Rating
pF
5319 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 512K x 36, 119 BGA (1,2,3,4)
1
2
3
4
5
6
7
A
VDDQ
A6
A4
A18
A8
A16
VDDQ
B
NC
CE2
A3
ADV/ LD
A9
CE2
NC
C
NC
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
CE1
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW3
A17
BW2
I/O11
I/O10
H
I/O22
I/O23
VSS
R/W
VSS
I/O9
I/O8
J
VDDQ
VDD
VDD(2)
VDD
VSS (1)
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M
VDDQ
I/O28
VSS
CEN
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/OP1
I/O0
R
NC
A5
LBO
VDD
VSS (1)
A13
NC
T
U
NC
NC
VDDQ
NC/TMS (3)
A10
A11
(3)
NC/TDI
(4)
A14
NC/TCK (3)
NC/TDO
NC
(3)
ZZ
NC/ TRST(3,5)
VDDQ
5319 tbl 25
Top View
Pin Configurations — 1M x 18, 119 BGA(1,2,3,4)
1
2
3
4
5
6
7
A
VDDQ
A6
A4
A 19
A8
A16
V DDQ
B
NC
CE 2
A3
ADV/LD
A9
CE2
NC
C
NC
A7
A2
V DD
A 13
A17
NC
D
I/O8
NC
VSS
NC
V SS
I/OP1
NC
E
NC
I/O9
VSS
CE1
V SS
NC
I/O7
F
VDDQ
NC
VSS
OE
V SS
I/O6
V DDQ
G
NC
I/O10
BW2
A 18
V SS
NC
I/O5
H
I/O11
NC
VSS
R/W
V SS
I/O4
NC
J
VDDQ
V DD
V DD(2)
V DD
VSS (1)
VDD
V DDQ
K
NC
I/O12
VSS
CLK
V SS
NC
I/O3
L
I/O13
NC
VSS
NC
BW1
I/O2
NC
M
VDDQ
I/O14
VSS
CEN
V SS
NC
V DDQ
N
I/O15
NC
VSS
A1
V SS
I/O1
NC
P
NC
I/OP2
VSS
A0
V SS
NC
I/O0
R
NC
A5
LBO
V DD
VSS (1)
A12
NC
T
NC
A 10
A15
NC(4)
A 14
A 11
U
VDDQ
NC/TMS
(3)
(3)
NC/TDI
NC/TCK
(3)
(3)
NC/TDO
ZZ
NC/TRST
(3,5)
V DDQ
5319 tbl 25a
Top View
NOTES:
1. Pins R5 and J5 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin J3 does not have to be connected directly to V DD as long as the input voltage is > VIH.
3. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several
settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST)
U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
4. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
5. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
CEN
R/W
CE1, CE2(5)
ADV/ LD
BW x
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
L
L
L
Valid
External
X
LOAD WRITE
D(7)
L
H
L
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)(2)
Q(7)
L
X
H
L
X
X
X
DESELECT or STOP (3)
HIZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HIZ
H
X
X
X
X
X
X
SUSPEND(4)
Previous Value
5319 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
R/W
BW 1
BW 2
BW 3(3)
BW 4(3)
H
X
X
X
X
L
L
L
L
L
WRITE BYTE 1 (I/O[0:7], I/OP1)
L
L
H
H
H
WRITE BYTE 2 (I/O[8:15], I/OP2)(2)
L
H
L
H
H
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3)
L
H
H
L
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
L
H
H
H
L
NO WRITE
L
H
H
H
H
OPERATION
READ
WRITE ALL BYTES
(2)
5319 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
Interleaved Burst Sequence Table (LBO=V DD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42
8
5319 tbl 10
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=V SS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
0
0
0
1
1
0
5319 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
CLOCK
(2)
ADDRESS
(A0 - A18)
CONTROL
(2)
(R/W, ADV/LD, BWx)
DATA
(2)
I/O [0:31], I/O P[1:4]
5319 drw 03
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
9
,
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
Cycle
Address
R/ W
ADV/LD
CE1(1)
CEN
BW x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
D1
Load read
n+1
X
X
H
X
L
X
L
Q0
Burst read
n+2
A1
H
L
L
L
X
L
Q0+1
Load read
n+3
X
X
L
H
L
X
L
Q1
Deselect or STOP
n+4
X
X
H
X
L
X
X
Z
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
L
Q2
Burst read
n+7
X
X
L
H
L
X
L
Q2+1
n+8
A3
L
L
L
L
L
X
Z
Load write
n+9
X
X
H
X
L
L
X
D3
Burst write
n+10
A4
L
L
L
L
L
X
D3+1
Load write
n+11
X
X
L
H
L
X
X
D4
Deselect or STOP
n+12
X
X
H
X
L
X
X
Z
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
D5
Load read
n+15
A7
L
L
L
L
L
L
Q6
Load write
n+16
X
X
H
X
L
L
X
D7
Burst write
n+17
A8
H
L
L
L
X
X
D7+1
Load read
n+18
X
X
H
X
L
X
L
Q8
Burst read
n+19
A9
L
L
L
L
L
L
Q8+1
Load write
Deselect or STOP
5319 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.42
10
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation(1)
Cycle
Address
R/W
ADV/ LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5319 tbl 13
Burst Read Operation(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+2
X
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+5
A1
H
L
L
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+6
X
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+7
A2
H
L
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5319 tbl 14
Write Operation(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
D0
Write to Address A0
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5319 tbl 15
Burst Write Operation(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+2
X
X
H
X
L
L
X
D0+1
Address A0+1 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+2
Address A0+2 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+3
Address A0+3 Write, Load A1
n+5
A1
L
L
L
L
L
X
D0
Address A0 Write, Inc. Count
n+6
X
X
H
X
L
L
X
D1
Address A1 Write, Inc. Count
n+7
A2
L
L
L
L
L
X
D1+1
Address A1+1 Write, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
11
5319 tbl 16
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address A0 and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
L
Q0
Address A0 Read out, Load A1
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q1
Address A1 Read out, Load A 2
n+6
A3
H
L
L
L
X
L
Q2
Address A2 Read out, Load A 3
n+7
A4
H
L
L
L
X
L
Q3
Address A3 Read out, Load A 4
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5319 tbl 17
Write Operation with Clock Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address A0 and Control meet setup.
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored.
n+2
A1
L
L
L
L
L
X
D0
Write data D0, Load A1.
n+3
X
X
X
X
H
X
X
X
Clock Ignored.
n+4
X
X
X
X
H
X
X
X
Clock Ignored.
n+5
A2
L
L
L
L
L
X
D1
Write Data D1, Load A2
n+6
A3
L
L
L
L
L
X
D2
Write Data D2, Load A3
n+7
A4
L
L
L
L
L
X
D3
Write Data D3, Load A4
5319 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
12
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE1(2)
CEN
BW x
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A0
H
L
L
L
X
X
Z
Address A0 and Control meet setup.
n+3
X
X
L
H
L
X
L
Q0
Address A0 read out, Deselected.
n+4
A1
H
L
L
L
X
X
Z
Address A1 and Control meet setup.
n+5
X
X
L
H
L
X
L
Q1
Address A1 read out, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A2
H
L
L
L
X
X
Z
Address A2 and Control meet setup.
n+8
X
X
L
H
L
X
L
Q2
Address A2 read out, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
5319 tbl 19
Write Operation with Chip Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BW x
OE
I/O
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A0
L
L
L
L
L
X
Z
Address A0 and Control meet setup
n+3
X
X
L
H
L
X
X
D0
Data D0 Write In, Deselected.
n+4
A1
L
L
L
L
L
X
Z
Address A1 and Control meet setup
n+5
X
X
L
H
L
X
X
D1
Data D1 Write In, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A2
L
L
L
L
L
X
Z
Address A2 and Control meet setup
n+8
X
X
L
H
L
X
X
D2
Data D2 Write In, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
5319 tbl 20
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
5
µA
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
|ILI|
LBO, JTAG and ZZ Input Leakage Current(1)
VDD = Max., VIN = 0V to V DD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to V CC
___
5
µA
VOL
Output Low Voltage
IOL = +6mA, VDD = Min.
___
0.4
V
2.0
___
V
Output High Voltage
VOH
IOH = -6mA, VDD = Min.
5319 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
7.5n s
S ym b ol
P aram eter
8ns
8.5n s
Test Co nd itio ns
Unit
Co m 'l
Ind
Co m 'l
Ind
Co m 'l
Ind
IDD
O p e rating P o we r
S up p ly Cu rre nt
De v ic e S e le c te d , O utp uts O p e n,
A DV /LD = X, V DD = M ax .,
V IN > V IH o r < V IL, f = fMA X (2)
275
295
250
270
225
245
mA
IS B 1
CM O S S tand b y P o we r
S up p ly Cu rre nt
De v ic e De s e le c te d , O utp uts O p e n ,
V DD = M a x ., V IN > V HD o r < V LD ,
f = 0 (2,3)
40
60
40
60
40
60
mA
IS B 2
Clo c k Running P o we r
S up p ly Cu rre nt
De v ic e De s e le c te d , O utp uts O p e n ,
V DD = M a x ., V IN > V HD o r < V LD ,
f = fMA X (2,3)
105
125
100
120
95
115
mA
IS B 3
Id le P o we r
S up p ly Cu rre nt
De v ic e S e le c te d , O utp uts O p e n,
CEN > V IH , V DD = M ax .,
V IN > V HD o r < V LD , f = f MA X (2,3)
60
80
60
80
60
80
mA
IZZ
Fu ll S le e p M o d e
S up p ly Cu rre nt
De v ic e S e le c te d , O utp uts O p e n,
CEN < V IH , V DD = M ax ., ZZ > V HD
V IN > V HD o r < V LD , f = f MA X (2,3)
40
60
40
60
40
60
mA
5319 tb l 2 2
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Load
AC Test Conditions
VDDQ/2
Input Pulse Levels
50Ω
I/O
Input Rise/Fall Times
Z0 = 50Ω
5319 drw 04
,
Figure 1. AC Test Load
6
5
∆tCD 3
(Typical, ns)
2
1
•
•
20 30 50
• •
80 100
Capacitance (pF)
200
5319 drw 05
2ns
Input Timing Reference Levels
(V DDQ/2)
Output Reference Levels
(V DDQ/2)
Output Load
Figure 1
5319 tbl 23
•
4
0 to 2.5V
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
14
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 2.5V±5%, Commercial and Industrial Temperature Ranges)
7.5ns
Symbol
Parameter
8ns
8.5ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
10
____
10.5
____
11
____
ns
tCH(1)
Clock High Pulse Width
2.5
____
2.7
____
3.0
____
ns
tCL(1)
Clock Low Pulse Width
2.5
____
2.7
____
3.0
____
ns
____
7.5
____
8
____
8.5
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
2
____
2
____
2
____
ns
tCLZ(2,3,4)
Clock High to Output Active
3
____
3
____
3
____
ns
tCHZ(2,3,4)
Clock High to Data High-Z
____
5
____
5
____
5
ns
tOE
Output Enable Access Time
____
5
____
5
____
5
ns
tOLZ(2,3)
Output Enable Low to Data Active
0
____
0
____
0
____
ns
tOHZ(2,3)
Output Enable High to Data High-Z
____
5
____
5
____
5
ns
2.0
____
2.0
____
2.0
____
ns
2.0
____
2.0
____
ns
Set Up Times
tSE
Clock Enable Setup Time
tSA
Address Setup Time
2.0
____
tSD
Data In Setup Time
2.0
____
2.0
____
2.0
____
ns
tSW
Read/Write (R/W) Setup Time
2.0
____
2.0
____
2.0
____
ns
tSADV
Advance/Load (ADV/ LD) Setup Time
2.0
____
2.0
____
2.0
____
ns
2.0
____
2.0
____
2.0
____
ns
2.0
____
2.0
____
ns
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
ns
tSC
Chip Enable/Select Setup Time
tSB
Byte Write Enable (BWx) Setup Time
2.0
____
Clock Enable Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
Hold Times
tHE
tHA
Address Hold Time
tHD
Data In Hold Time
tHW
Read/Write (R/W) Hold Time
0.5
____
tHADV
Advance/Load (ADV/ LD) Hold Time
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
0.5
____
0.5
____
ns
5319 tbl 24
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 2.375V).
6.42
15
6.42
16
tCLZ
A1
tSC
tS A
tHA
tHW
tHE
tCD
tHC
A2
tSW
Q(A1 )
Read
tSADV
tSE
Read
Q(A2 )
tHADV
tCDC
tCH
Q(A2+1 )
tCD
tCL
Burst Read
Q(A2+2 )
Q(A2+3 )
(CEN high, eliminates
current L-H clock edge)
tCDC
Q(A2+3 )
Q(A2 )
(Burst Wraps around
to initial state)
tCHZ
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
DATAO UT
OE
BW1 - BW4
CE1 , CE2 (2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
5319 drw 06
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
.
6.42
17
B(A1)
A1
Write
tSADV
tHW
tHE
tHC
D(A1)
tSD
tHD
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tSE
Write
D(A2)
B(A2+1)
tHADV
tCH
tHD
D(A2+1)
tSD
B(A2+2)
tCL
(CEN high, eliminates
current L-H clock edge)
Burst Write
D(A2+2)
B(A2+3)
D(A2+3)
(Burst Wraps around
to initial state)
B(A2)
D(A2)
5319 drw 07
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
,
6.42
18
A1
tCD
tHW
tHE
tHC
tCHZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
Q(A1)
Read
tSADV
tSE
Write
A3
tCLZ
D(A2)
tSD tHD
tHADV
tCH
Read
Q(A3)
tCDC
B(A4)
A4
tCL
Write
D(A4)
B(A5)
A5
Write
D(A5)
A6
Read
Q(A6)
A7
Read
Q(A7)
B(A8)
A8
D(A8)
A9
5319 drw 08
Write
NOTES:
1. Q (A1) represents the first output from the external address A 1. D (A 2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
6.42
19
tCD
tCLZ
A1
Q(A1)
tSE
tSADV
tHE
tHW
tHC
Q(A1)
tCDC
tCHZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tCH
tHADV
tCL
tCD
D(A2)
tSD tHD
A3
Q(A3)
tCDC
A4
NOTES:
1. Q (A1) represents the first output from the external address A 1. D (A 2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur.
All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
5319 drw 09
Q(A4)
A5
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
6.42
20
tCD
tCLZ
A1
tSADV
tSC
Q(A1)
tHW
tHE
tHC
tHA
A2
tSA
tSW
tSE
tCHZ
tCDC
Q(A2)
tHADV
tCH
tHB
B(A3)
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A4)
A5
Q(A5)
,,
NOTES:
5319 drw 10
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the
deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST(3)
x
M5319 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
5(1)
ns
tJF
JTAG Clock Fall Time
____
5(1)
ns
JTAG Identification (JIDR)
tJRST
JTAG Reset
50
____
ns
Boundary Scan (BSR)
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
20
ns
tJDC
JTAG Data Output Hold
0
____
ns
ns
ns
tJS
JTAG Setup
25
____
tJH
JTAG Hold
25
____
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
32
Note (1)
I5319 tbl 03
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
I5319 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
21
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x2
IDT Device ID (27:12)
0x221, 0x223
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number.
Defines IDT part number 71T75702 and 71T75902, respectively.
Allows unique identification of device vendor as IDT.
1
Indicates the presence of an ID register.
I5319 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
(1)
EXTEST
Forces contents of the boundary scan cells onto the device outputs .
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
RESERVED
RESERVED
0100
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
RESERVED
CLAMP
0101
0110
0111
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
RESERVED
1000
1001
RESERVED
1010
Same as above.
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5319tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
22
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100 Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
23
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
24
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
Q
DATAOUT
Q
,
5319 drw 11
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
XXXX
S
XX
XX
Device
Type
Power
Speed
Package
X
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BG
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
75
80
85
Access time (tCD) in tenths of nanoseconds
IDT71T75702
IDT71T75902
512Kx36 Flow-Through ZBT SRAM
1Mx18 Flow-Through ZBT SRAM
5319 drw 12
6.42
25
,
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev
0
1
Date
05/25/00
08/24/01
2
3
4
5
10/16/01
12/21/01
05/29/02
06/07/02
6
7
11/19/02
05/23/03
8
04/01/04
02/20/09
Pages
Description
Created Advance Information Datasheet
p. 1, 25
Removed reference of BQ165 package
p. 8
Removed page of the 165 BGA pin configuration
p. 24
Removed page of the 165 BGA package diagram outline
p. 7
Corrected 3.3V to 2.5V in Note 3
p. 5-7
Added clarification to JTAG pins, allow for NC. Added 36M address pin locations
p. 21
Corrected 100-pin TQFP package drawing
p. 1-4,7,14,21,22 Added complete JTAG functionality.
p. 2,14
Added notes for ZZ pin internal pulldown and ZZ leakage current.
p. 14
Updated ISB3 power supply current from 40 to 60mA for all speeds.
p.1-26
Changed datasheet from Advanced information to final release.
p.5,6,14,15,25 Added I-temp to the datasheet.
p.6
Updated 165 BGA table.
p.1
Updated logo with new design.
p.5,6
Clarified ambient and case operating temperatures.
p.7
Updated I/O pin number order for the 119 BGA.
p.24
Updated 119BGA Package Diagram Drawing.
p.25
Removed "IDT" from orderable parts number.
CORPORATE HEADQUARTERS
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for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
26
for Tech Support:
[email protected]
800-345-7015 or
408/284-4555