MICRF005 Micrel MICRF005 115kbps, 800MHz - 1GHz UHF Receiver Final Information General Description Features The MICRF005 QwikRadio™ UHF receiver is a single-chip OOK (on-off keyed) receiver IC for remote wireless applications. This device is a true single-chip, “antenna-in, data-out” device. All RF and IF tuning is accomplished automatically within the IC which eliminates manual tuning production costs and results in a highly reliable, extremely low-cost solution for high-volume wireless applications. The MICRF005 provides two additional key features: (1) A transmit standby mode, and (2) a shutdown mode which may be used for duty-cycle operation. These features make the MICRF005 ideal for low power applications in both one-way and bi-directional wireless links. All IF and post-detection (demodulator) data filtering is provided on the MICRF005, no external filters are required. Nominal filter bandwidth is fixed a 300kHz allowing a data throughput at rates up to 115kbps. • • • • • • • • • 800MHz to 1000MHz frequency range Data rates up to 115kbps No filters or inductors required Low 10mA operating supply current at 868MHz Shutdown mode for >10:1 duty-cycle operation Very low RF antenna re-radiation CMOS logic interface for standard ICs Extremely low external part count Transmit standby mode for bi-directional link control Applications • Wireless game controllers • Security systems • Medium-rate data modems Ordering Information Part Number Junction Temp. Range Package MICRF005BM –40°C to +85°C 14-Lead SOIC Typical Application MICRF005 T/R Control +5V SEL0 T/R REFOSC VSSRF NC VSSRF CAGC ANT VDDRF NC SHUT VDDBB DO CTH Y1 14.3359MHz C1(CAGC) 4.7µF Data Output VSSBB C4(CTH) 0.047µF 915MHz, 115kbps OOK ISM Band Receiver QwikRadio is a trademark of Micrel Semiconductor. The QwikRadio ICs were developed under a partnership agreement with AIT of Orlando, Florida. Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com October 2001 1 MICRF005 MICRF005 Micrel Pin Configuration MICRF005BM 1 SEL0 14 REFOSC VSSRF 2 13 N/C VSSRF 3 12 CAGC T/R ANT 4 11 N/C VDDRF 5 10 SHUT VDDBB 6 9 DO CTH 7 8 VSBB Standard 14-Pin SOP (M) Package Pin Description Pin Number Pin Name 1 T/R 2, 3 VSSRF This pin is the ground return for the RF section of the IC. The bypass capacitor connected from the VDDRF to VSSRF should have the shortest possible lead length. For best performance, connect VSSRF to VSSBB at the power supply only (i.e. keep VSSBB currents from flowing through VSSRF return paths). 4 ANT This is the receive RF input, internally ac-coupled. Connect this pin to the receive antenna. For applications located in high ambient noise environments, a fixed value band-pass network may be connected between the ANT pin and VSSRF to provide additional receive selectivity and input overload protection. 5 VDDRF This pin is the positive supply input for the RF section of the IC. VDDBB and VDDRF should be connected together directly at the IC pins. 6 VDDBB This pin is the positive supply input for the baseband section of the IC. VDDBB and VDDRF should be connected together at the IC pins. 7 CTH 8 VSSBB 9 DO 10 SHUT 11 NC 12 CAGC 13 NC 14 REFOSC MICRF005 Pin Function Transmit/Receive control switch. Pull low to enable receiver function. This capacitor extracts the (DC) average value from the demodulated waveform which becomes the reference for the internal data slicing comparator. Treat as a low-pass RC filter with source impedance of nominally 30kΩ. A standard ±20% X7R ceramic capacitor is generally sufficient. This is the ground return for the baseband section of the IC. The bypass and output capacitors connected to VSSBB should have the shortest possible leads lengths. For best performance, connect VSSRF to VSSBB at the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path). CMOS-level compatible data output signal. Shutdown-mode logic-level control input. Pull low to enable the receiver. This pin is internally pulled-up to VDDRF. No connection Intergrating capacitor for on-chip AGC (Automatic Gain Control). The Decay/ Attack time-constant (TC) ratio is nominally set as 10:1. Use of 0.47µF or greater is strongly recommended for best range performance. Use lowleakage type capacitors for duty-cycle operation (Dip Tantalum, Ceramic, Polyester). No connection This is the timing reference for on-chip tuning and alignment. Connect crystal between this pin and VSSBB, or drive the input with an AC coupled 0.5VPP input clock. 2 October 2001 MICRF005 Micrel Absolute Maximum Ratings (Note 1) Operating Ratings (Note 2) Supply Voltage (VDDRF, VDDBB) .................................... +7V Reference Oscillator Input Voltage (VREFOSC).......... VDDBB Input/Output Voltage (VI/O) ................. VSS–0.3 to VDD+0.3 Junction Temperature (TJ) ...................................... +150°C Storage Temperature Range (TS) ............ –65°C to +150°C Lead Temperature (soldering, 10 sec.) ................... +260°C ESD Rating, Note 3 Supply Voltage (VDDRF, VDDBB) ................ +4.75V to +5.5V Ambient Temperature (TA) ......................... –40°C to +85°C Electrical Characteristics VDDRF = VDDBB = VDD where 4.75V ≤ VDD ≤ 5.5V, VSS = 0V; VT/R = VSHUT = 0V; CAGC = 0.47µF, CTH = 4.7nF, 115kbps data-rate (Manchester encoded); fREFOSC = 14.3359MHz (fRF = 915MHz); TA = 25°C, bold values indicate –40°C ≤ TA ≤ +85°C; current flow into device pins is positive; unless noted. Symbol Parameter Condition IOP Operating Current ISTBY Standby Current Min Typ Max Units continuous operation 10 13.5 18.5 mA 10:1 duty cycle 1 mA VT/R = VSHUT = VDD 11 µA –84 dBm RF Section, IF Section Receiver Sensitivity Notes 4, 6 fIF IF Center Frequency Note 7 2.496 MHz fBW IF 3dB Bandwidth Notes 7 1.2 MHz fANT –81 Maximum Receive Data Rate 115 kb/s RF Input Range 800 1000 MHz Receive Modulation Duty-Cycle 20 80 % Maximum Receiver Input RS = 50Ω –10 dBm Spurious Reverse Isolation ANT pin, RSC = 50Ω, Note 5 30 µVrms AGC Attack to Decay Ratio tATTACK ÷ tDECAY, Note 9 0.1 AGC Leakage Current TA = +85°C, VSHUT = VDD or VT/R = VDD, Note 9 ±200 nA 1.2 ms 300 kΩ Reference Oscillator Synthesizer Stabilization Time ZREFOSC to 1% of final value Reference Oscillator Input Impedance OSC Input Voltage 300 mVp-p Demodulator ZCTH CTH Source Impedance Note 8, 9 26 kΩ ∆ZCTH CTH Source Impedance Variation Note 9 ±15 % Demodulator Filter Bandwidth Notes 7 300 kHz October 2001 3 MICRF005 MICRF005 Symbol Micrel Parameter Condition Min Typ Max Units Digital/Control Section IIN(pu) VSHUT Pull-Up Current VSHUT = VSS 8.5 µA IIN(pd) VT/R Pull-Down Current VT/R = VDD 12 µA VIN(high) VT/R, VSHUT, Input-High Voltage VIN(low) VT/R, VSHUT, Input-Low Voltage IOUT Output Current DO, push-pull VOUT(high) Output-High Voltage DO, IOUT = –5µA VOUT(low) Output-Low Voltage DO, IOUT = 5µA tR, tF Output Rise and Fall Times DO, CLOAD = 10pF VDD–0.5 V 0.5 V µA 90 0.9VDD V 0.1VDD tbd V µs Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handling precautions recommended. Note 4: Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded data). The RF input is assumed to be matched into 50Ω. Note 5: Spurious reverse isolation represents the spurious components which appear on the RF input pin (ANT) measured into 50Ω with an input RF matching network. Parameter guaranteed by device characterization, not production tested. Note 6: Sensitivity, a commonly specified receiver parameter, provides an indication of the receiver’s input referred noise, generally input thermal noise. However, it is possible for a more sensitive receiver to exhibit range performance no better than that of a less sensitive receiver if the background noise is appreciably higher than the thermal noise. Background noise refers to other interfering signals, such as FM radio stations, pagers, etc. A better indicator of achievable receiver range performance is usually given by its selectivity, often stated as intermediate frequency (IF) or radio frequency (RF) bandwidth, depending on receiver topology. Selectivity is a measure of the rejection by the receiver of “ether” noise. More selective receivers will almost invariably provide better range. Only when the receiver selectivity is so high that most of the noise on the receiver input is actually thermal will the receiver demonstrate sensitivity-limited performance. Note 7: Parameter scales linearly with reference oscillator frequency fT. For any reference oscillator frequency other than 14.3359MHz, compute new parameter value as the ratio: fREFOSCMHz × (parameter value at 14.3359MHz) 14.3359 Note 8: Parameter scales inversely with reference oscillator frequency fT. For any reference oscillator frequency other than 14.3359MHz, compute new parameter value as the ratio: 14.3359 × (parameter value at 14.3359MHz) fREFOSCMHz Note 9: Parameter guaranteed by design (not tested). Typical Characteristics Supply Current vs. Temperature 16 12 14 10 CURRENT (mA) CURRENT (mA) Supply Current vs. Frequency 14 8 6 4 10 8 6 4 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1000 960 980 920 940 2 880 900 860 800 0 820 840 TA = 25°C 2 V = 5V DD f = 915MHz VDD = 5V 12 FREQUENCY (MHz) MICRF005 4 October 2001 MICRF005 Micrel Functional Diagram T/R CAGC AGC Control CAGC 2nd Order Low-Pass Filter 5th Order Band-Pass Filter ANT RF Amp fRX fIF IF Amp IF Amp SwitchedCapacitor Resistor Peak Detector RSC fLO Comparator DO CTH VDD Programmable Synthesizer VSS CTH UHF Downconverter Control Logic SHUT OOK Demodulator REFOSC fT Reference Oscillator Reference and Control Crystal MICRF005 MICRF005 Block Diagram MΩ resistor from the CTH pin to either VSS or VDD, depending on the desired offset polarity. Since the MICRF005 has receiver AGC, noise at the internal comparator input is always the same, set by the AGC. The squelch offset requirement does not change as the local noise strength changes from installation to installation. Introducing squelch will reduce range modestly. Only introduce an amount of offset sufficient to quiet the output. Automatic Gain Control The signal path has AGC (automatic gain control) to increase input dynamic range. An external capacitor, CAGC, must be connected to the CAGC pin of the device. The ratio of decayto-attack time-constant is fixed at 10:1 (that is, the attack time constant is 1/10th of the decay time constant). However, the attack time constant is set externally by choosing a value for CAGC. By adding resistance from the CAGC pin to VDDBB or VSSBB in parallel with the AGC capacitor, the ratio of decay-to-attack time constant may be varied, although the value of such adjustments must be studied on a per-application basis. Generally the design value of 10:1 is adequate for the vast majority of applications. To maximize system range, it is important to keep the AGC control voltage ripple low, preferably under 10mVpp once the control voltage has attained its quiescent value. For this reason capacitor values of at least 0.47µF are recommended. The AGC control voltage is carefully managed on-chip to allow duty-cycle operation of the MICRF005 in excess of 10:1. When the device is placed into shutdown mode (SHUT pin pulled high), the AGC capacitor floats, to retain the voltage. When operation is resumed, only the voltage droop on the capacitor due to leakage must be replenished, therefore a relatively low-leakage capacitor is recommended for Functional Description Refer to “MICRF005 Block Diagram”. Identified in the block diagram are the three sections of the IC: UHF Downconverter, OOK Demodulator and Reference and Control. Also shown in the figure are two capacitors (CTH, CAGC) and one timing component (CR), usually a crystal. With the exception of a supply decoupling capacitor, these are the only external components needed by the MICRF005 to construct a complete UHF receiver. Two control inputs are shown in the block diagram: T/R and SHUT. Through these logic inputs, the user can control the operation of the IC. These inputs are CMOS compatible, and are pulled-up on the IC. IF Bandpass Filter Rolloff response of the IF Filter is 7th order, while the demodulator data filter exhibits a 2nd order response. Slicing Level Extraction of the dc value of the demodulated signal for purposes of logic-level data slicing is accomplished using the external threshold capacitor CTH and the on-chip switchedcapacitor “resistor” RSC, shown in the block diagram. The effective resistance of RSC is 30kΩ. Slicing level time constant values vary somewhat with decoder type, data pattern, and data rate, but typical values range from 5ms to 50ms. Optimization of the value of CTH is required to maximize range. Squelch During quiet periods (no signal) the data output (DO pin) transitions randomly with noise, presenting problems for some decoders. A simple solution is to introduce a small offset, or squelch voltage, on the CTH pin so that noise does not trigger the internal comparator. Usually 20mV to 30mV is sufficient, and may be introduced by connecting a severalOctober 2001 5 MICRF005 MICRF005 Micrel CTH Pin duty-cycled operation. The actual tolerable leakage will be application dependent. Clearly, leakage performance is less critical when the device off-time is low (milliseconds) and more critical when the off-time is high (seconds). To further enhance duty-cycled operation of the IC, the AGC push and pull currents are increased for a fixed time immediately after the device is taken out of shutdown mode (turnedon). This compensates for AGC capacitor voltage droop while the IC is in shutdown mode, reduces the time to restore the correct AGC voltage, and therefore extends maximum achievable duty ratios. Push-pull currents are increased by 45 times their nominal values. The fixed time period is based on the reference oscillator frequency fT, [tbd]ms for fT = 14.3359MHz, and varies inversely as fT varies. Transmit / Standby Function The transmit/receive function is controlled by the logic state of T/R. T/R is internally tied to VSS. When T/R is open circuit or in the low state, the MICRF005 functions in its normal receive operating mode. The T/R pin may be pulled high to Vdd, this will place the receiver in a “stand-by” operating mode. This mode is intended for use during transmit cycles in transceiver applications where the receiver is co-located with a transmitter. In this “transmit” mode, the receiver oscillator remains active but the AGC function is disabled and the CAGC pin is high impedance to hold the AGC capacitor voltage. This function enables the MICRF005 to immediately resume receive operation after a transmit cycle. Shutdown Function The shutdown function is controlled by a logic state applied to the SHUT pin. When VSHUT is high, the device goes into low-power standby mode, consuming less than 1µA. This pin is pulled high internally. It must be externally pulled low to enable the receiver. Reference Oscillator All timing and tuning operations on the MICRF005 are derived from the internal Colpitts reference oscillator. Timing and tuning is controlled through the REFOSC pin in one of two ways: 1. Connect a crystal 2. Drive this pin with an external timing signal The second approach is attractive for lowering system cost further if an accurate reference signal exists elsewhere in the system, for example, a reference clock from a crystal-controlled microprocessor. An externally applied signal should be ac-coupled and resistively-attenuated, or otherwise limited, to approximately 0.5Vpp. The specific reference frequency required is related to the system transmit frequency. I/O Pin Interface Circuitry Interface circuitry for the various I/O pins of the MICRF005 are diagrammed in Figures 1 through 6. The ESD protection diodes at all input and output pins are not shown. Integrated into an actual design application with the best results possible. MICRF005 VDDBB PHI2B Demodulator Signal 2.85Vdc PHI1B CTH VSSBB PHI2 6.9pF PHI1 VSSBB Figure 2. CTH Pin Figure 2 illustrates the CTH-pin interface circuit. The CTH pin is driven from a P-channel MOSFET source-follower with approximately 10µA of bias. Transmission gates TG1 and TG2 isolate the 6.9pF capacitor. Internal control signals PHI1/PHI2 are related in a manner such that the impedance across the transmission gates looks like a “resistance” of approximately 100kΩ. The dc potential at the CTH pin is approximately 1.6V CAGC Pin VDDBB 1.5µA 67.5µA Comparator CAGC Timout 15µA 675µA VSSBB Figure 3. CAGC Pin Figure 3 illustrates the CAGC pin interface circuit. The AGC control voltage is developed as an integrated current into a capacitor CAGC. The attack current is nominally 15µA, while the decay current is a 1/10th scaling of this, nominally 1.5µA, making the attack/decay timeconstant ratio a fixed 10:1. Signal gain of the RF/IF strip inside the IC diminishes as the voltage at CAGC decreases. Modification of the attack/decay ratio is possible by adding resistance from the CAGC pin to either VDDBB or VSSBB, as desired. Both the push and pull current sources are disabled during shutdown, which maintains the voltage across CAGC, and improves recovery time in duty-cycled applications. To further improve duty-cycle recovery, both push and pull currents are increased by 45 times for approximately 10ms after release of the SHUT pin. This allows rapid recovery of any voltage droop on CAGC while in shutdown. 6 October 2001 MICRF005 Micrel DO Pin pullup to VDDBB. Typical pullup current is 8.5µA, leading to an impedance to the VDDBB supply of typically 1MΩ. VDDBB T/R Pin 80µA VDDBB Comparator Q1 DO Q2 VDDBB 80µA Q3 VSSBB Figure 4. DO Pin VSSBB The output stage for DO (digital output) is shown in Figure 4. The output is a 90µA push and 90µA pull switched-current stage. This output stage is capable of driving CMOS loads. An external buffer-driver is recommended for driving highcapacitance loads. Figure 7. T/R Pin The transmit/receive function is controlled by the logic state of T/R. T/R is internally tied to VSS. When T/R is open circuit or in the low state, the MICRF005 functions in its normal receive operating mode. The T/R pin may be pulled high to Vdd, this will place the receiver in a “stand-by” operating mode. This mode is intended for use during transmit cycles in transceiver applications where the receiver is co-located with a transmitter. In this “transmit” mode, the receiver oscillator remains active but the AGC function is disabled and the CAGC pin is tri-stated to hold the AGC capacitor voltage. This function enables the MICRF005 to quickly resume receive operation after a transmit cycle. REFOSC Pin VDDBB Active Bias 200k REFOSC 250Ω 15pF 7.5pF 30µA VSSBB VSSBB Figure 5. REFOSC Pin The REFOSC input circuit is shown in Figure 5. Input impedance is high (300kΩ). This is a Colpitts oscillator with internal capacitors. The nominal dc bias voltage on this pin is 1.4V. SHUT Pin VDDBB Q1 Q2 to Internal Circuits VSSBB SHUT Q3 VSSBB Figure 6. SHUT Pin Control input circuitry is shown in Figures 6. The standard input is a logic inverter constructed with minimum geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large channel length device which functions essentially as a “weak” October 2001 7 MICRF005 MICRF005 Micrel place accuracy on the frequency is generally adequate. The following table identifies fT for some common transmit frequencies when the MICRF005 is operated. Application Information Bypass and Output Capacitors The bypass and output capacitors connected to VSSBB should have the shortest possible lead lengths. For best performance, connect VSSRF to VSSBB at the power supply only (that is, keep VSSBB currents from flowing through the VSSRF return path). VDDRF and VDDBB should be connected directly together at the IC pins. A 10Ω resistor in series with the supply line plus three decoupling capacitors is recommended. The suggested capacitor values are 1nF, 10nF and 100nF. 5V 13.6050MHz 915MHz 14.3359MHz 916.5MHz 14.3594MHz C3 1nF The first step in the process is selection of a data-slicing-level time constant. This selection is strongly dependent on system issues including system decode response time and data code structure (that is, existence of data preamble, etc.). This issue is covered in more detail in “Application Note 22.” Source impedance of the CTH pin is given by equation (3), where fT is in MHz: To MICRF005 VSS Figure 8. Supply Bypassing External Timing Signals Externally applied signals should be ac-coupled and the amplitude must be limited to approximately 0.5Vpp. Optional BandPass Filter For applications located in high ambient noise environments, a fixed value band-pass network may be connected between the ANT pin and VSSRF to provide additional receive selectivity and input overload protection. Frequency and Capacitor Selection Selection of the reference oscillator frequency fT, slicing level capacitor (CTH), and AGC capacitor (CAGC) are briefly summarized in this section. (3) RSC = 30Ω 14.3359 fT Assuming that a slicing level time constant τ has been established, capacitor CTH may be computed using equation (4). (4) C TH = τ RSC A standard ±20% X7R ceramic capacitor is generally sufficient. Selecting CAGC Capacitor in Continuous Mode Selecting Reference Oscillator Frequency fT Selection of CAGC is dictated by minimizing the ripple on the AGC control voltage by using a sufficiently large capacitor. Factory experience suggests that CAGC should be in the vicinity of 0.47µF to 4.7µF. Large capacitor values should be carefully considered as this determines the time required for the AGC control voltage to settle from a completely discharged condition. AGC settling time from a completely discharged (zero-volt) state is given approximately by equation (5): As with any superheterodyne receiver, the difference between the internal LO (local oscillator) frequency fLO and the incoming transmit frequency fTX ideally must equal the IF center frequency. Equation 1 may be used to compute the appropriate fLO for a given fTX: f fLO = fTX ± 2.496 TX 915 Frequencies fTX and fLO are in MHz. Note that two values of fLO exist for any given fTX, distinguished as “high-side mixing” and “low-side mixing,” and there is generally no preference of one over the other. After choosing one of the two acceptable values of fLO, use Equation 2 to compute the reference oscillator frequency fT: (5) ∆t = 1.333C AGC − 0.44 where: CAGC is in µF, and ∆t is in seconds. Selecting CAGC Capacitor in Duty-Cycle Mode Generally, droop of the AGC control voltage during shutdown should be replenished as quickly as possible after the IC is “turned-on”. As described in the functional description, for about [tbd]ms after the IC is turned on, the AGC push-pull currents are increased to 45 times their normal values. Consideration should be given to selecting a value for CAGC and a shutdown time period such that the droop can be replenished within this [tbd]ms period. fLO 64 Equations (1) and (2) can be simplified to: fT = fT = 63.8258 fTX Frequency fT is in MHz. Connect a series-mode crystal of frequency fT to REFOSC on the MICRF005. Four-decimal- MICRF005 868.35MHz Selecting Capacitor CTH VDD C1 C2 100nF 10nF (2) Reference Oscillator Frequency (fT) Table 2. Common Transmitter Frequencies R1 10R (1) Transmit Frequency (fTX) 8 October 2001 MICRF005 Micrel For example, if user desires ∆t = 10ms and chooses a 4.7µF CAGC, then the allowable droop is about 144mV. Using the same equation with 200nA worst case pin leakage and assuming 1µA of capacitor leakage in the same direction, the maximum allowable ∆t (shutdown time) is about 0.56s for droop recovery in 10ms. Polarity of the droop is unknown, meaning the AGC voltage could droop up or down. Worst-case from a recovery standpoint is downward droop, since the AGC pullup current is 1/10th magnitude of the pulldown current. The downward droop is replenished according to the Equation (6): I (6) C AGC = ∆V ∆t where: I = AGC pullup current for the initial [tbd]ms (67.5µA) CAGC = AGC capacitor value ∆t = droop recovery time ∆V = droop voltage October 2001 9 MICRF005 MICRF005 Micrel Typical Applications Figure 9 below illustrates a typical application for the MICRF005 UHF receiver IC. Operation in this example is at 916.5MHz ANTENNA 50Ω Y1 14.3359MHz MICRF005 T/R Control L1 Z1 L2 Z2 +5V Ground SEL0 T/R NC VSSRF CAGC ANT VDDRF NC SHUT VDDBB DO CTH C1 4.7µF C2 0.1µF REFOSC VSSRF C1(CAGC) 0.47µF Data Output VSSBB C3 CTH Bill of Materials Item Part Number U1 MICRF005 Manufacturer Description UHF Receiver 1 C1, C4 Panasonic 4.7µF Ceramic Cap 1 C2 Panasonic 0.47µF Ceramic Cap 1 C3 Panasonic 0.1µF Ceramic Cap 1 [tbd]nH, Wire wound SMT inductors 1 13.3594MHz crystal 1 L1, L2 Micrel Qty Coilcraft Y1 MICRF005 10 October 2001 MICRF005 Micrel Package Information PIN 1 DIMENSIONS: INCHES (MM) 0.154 (3.90) 0.026 (0.65) MAX) 0.193 (4.90) 0.050 (1.27) 0.016 (0.40) TYP TYP 45° 0.006 (0.15) 0.057 (1.45) 0.049 (1.25) 0.344 (8.75) 0.337 (8.55) 3°–6° 0.244 (6.20) 0.228 (5.80) SEATING PLANE 14-Lead SOIC (M) MICREL INC. 1849 FORTUNE DRIVE TEL + 1 (408) 944-0800 FAX SAN JOSE, CA 95131 + 1 (408) 944-0970 WEB USA http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2001 Micrel Incorporated October 2001 11 MICRF005