MCP6001/2/4 1 MHz, Low-Power Op Amp Features Description • • • • • • • The Microchip Technology Inc. MCP6001/2/4 family of operational amplifiers (op amps) is specifically designed for general-purpose applications. This family has a 1 MHz Gain Bandwidth Product (GBWP) and 90° phase margin (typ.). It also maintains 45° phase margin (typ.) with a 500 pF capacitive load. This family operates from a single supply voltage as low as 1.8V, while drawing 100 µA (typ.) quiescent current. Additionally, the MCP6001/2/4 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS – 300 mV. This family of op amps is designed with Microchip’s advanced CMOS process. Available in SC-70-5 and SOT-23-5 packages Gain Bandwidth Product: 1 MHz (typ.) Rail-to-Rail Input/Output Supply Voltage: 1.8V to 5.5V Supply Current: IQ = 100 µA (typ.) Phase Margin: 90° (typ.) Temperature Range: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C • Available in Single, Dual and Quad Packages Applications • • • • • • The MCP6001/2/4 family is available in the industrial and extended temperature ranges, with a power supply range of 1.8V to 5.5V. Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Package Types MCP6001 MCP6002 SC-70-5, SOT-23-5 PDIP, SOIC, MSOP 5 VDD VOUT 1 Available Tools FilterLab® Software (at www.microchip.com) + SPICE Macro Models (at www.microchip.com) VSS 2 VINA– 2 - 4 VIN– VIN+ 3 VOUTA 1 VINA+ 3 8 VDD 7 VOUTB - + + - VSS 4 6 VINB– 5 VINB+ Typical Application MCP6001R VDD VIN SOT-23-5 5 VSS VOUT 1 + VDD 2 + VOUT MCP6001 – VOUTA 1 - VIN+ 3 MCP6004 PDIP, SOIC, TSSOP 4 VIN– VSS 14 VOUTD VINA– 2 - + + - 13 VIND– VINA+ 3 12 VIND+ VDD 4 MCP6001U R1 VREF SOT-23-5 R1 Gain = 1 + -----R2 Non-Inverting Amplifier © 2005 Microchip Technology Inc. VSS 2 VINB– 6 5 VDD VIN+ 1 VINB+ 5 VOUTB 7 10 VINC+ - + + - 9 VINC– 8 VOUTC + R2 11 VSS - VIN– 3 4 VOUT DS21733F-page 1 MCP6001/2/4 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD – VSS ........................................................................7.0V All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Difference Input Voltage ...................................... |VDD – VSS| Output Short-Circuit Current .................................continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±30 mA Storage Temperature.....................................-65°C to +150°C Maximum Junction Temperature (TJ) .......................... +150°C ESD Protection On All Pins (HBM;MM) ............... ≥ 4 kV; 200V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to VDD/2 and VOUT ≈ VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Ratio VOS -4.5 — +4.5 ΔVOS/ΔTA — ±2.0 — PSRR — 86 — dB IB — ±1.0 — pA IB — 19 — pA TA = +85°C IB — 1100 — pA TA = +125°C IOS — ±1.0 — pA mV VCM = VSS (Note 1) µV/°C TA= -40°C to +125°C, VCM = VSS VCM = VSS Input Bias Current and Impedance Input Bias Current: Industrial Temperature Extended Temperature Input Offset Current Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Common Mode Input Range VCMR VSS − 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 60 76 — dB VCM = -0.3V to 5.3V, VDD = 5V AOL 88 112 — dB VOUT = 0.3V to VDD – 0.3V, VCM = VSS — VDD – 25 mV VDD = 5.5V — ±6 — mA VDD = 1.8V — ±23 — mA VDD = 5.5V VDD 1.8 — 5.5 V IQ 50 100 170 µA Common Mode Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short-Circuit Current VOL, VOH VSS + 25 ISC Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: IO = 0, VDD = 5.5V, VCM = 5V MCP6001/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV minimum/ maximum limits. DS21733F-page 2 © 2005 Microchip Technology Inc. MCP6001/2/4 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions GBWP — 1.0 — MHz Phase Margin PM — 90 — ° Slew Rate SR — 0.6 — V/µs Input Noise Voltage Eni — 6.1 — µVp-p f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 28 — nV/√Hz f = 1 kHz Input Noise Current Density ini — 0.6 — fA/√Hz f = 1 kHz AC Response Gain Bandwidth Product G = +1 Noise TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Industrial Temperature Range TA -40 — +85 °C Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SC70 θJA — 331 — °C/W Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC (150 mil) θJA — 163 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W °C/W Conditions Temperature Ranges Note Thermal Package Resistances Thermal Resistance, 14L-PDIP θJA — 70 — Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Note: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. © 2005 Microchip Technology Inc. DS21733F-page 3 MCP6001/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 100 PSRR, CMRR (dB) 64,695 Samples VCM = VSS 95 90 PSRR (VCM = VSS) 85 80 CMRR (VCM = -0.3V to +5.3V) 75 -25 CMRR 40 30 100 1.E+02 14% 12% 10% 100k 1.E+05 PSRR, CMRR vs. 40 8% 6% 4% 2% -150 0 -180 VCM = VSS -20 -210 1k 10k 0.1 1.E 1 1.E 10 100 1M 10M 1.E1.E 1.E 1.E 100k 1.E 1.E 1.E 01 +00 +01 Frequency +02 +03 +04 (Hz) +05 +06 +07 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 30 27 24 21 18 15 12 9 6 3 Input Bias Current (pA) FIGURE 2-3: DS21733F-page 4 Input Bias Current at +85°C. Open-Loop Gain, Phase vs. 605 Samples VDD = 5.5V VCM = VDD TA = +125°C 0 0% -120 Gain 20 FIGURE 2-5: Frequency. 1230 Samples VDD = 5.5V VCM = VDD TA = +85°C 0 Percentage of Occurrences FIGURE 2-2: Frequency. 1k 10k 1.E+03 1.E+04 Frequency (Hz) Percentage of Occurrences 20 10 1.E+01 -90 1500 50 -60 Phase 60 1350 PSRR+ 80 1200 60 -30 1050 PSRR– 100 450 70 0 900 80 120 750 Open-Loop Gain (dB) VCM = VSS 90 125 CMRR, PSRR vs. Ambient 300 100 PSRR, CMRR (dB) FIGURE 2-4: Temperature. Input Offset Voltage. 150 FIGURE 2-1: 0 25 50 75 100 Ambient Temperature (°C) Open-Loop Phase (°) -50 Input Offset Voltage (mV) 600 5 4 3 2 1 0 -1 -2 -3 70 -4 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 5 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Input Bias Current (pA) FIGURE 2-6: Input Bias Current at +125°C. © 2005 Microchip Technology Inc. MCP6001/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. FIGURE 2-7: vs. Frequency. Input Noise Voltage Density FIGURE 2-10: Input Offset Voltage (µV) Input Offset Voltage (µV) -300 -400 TA = -40°C TA = +25°C TA = +85°C TA = +125°C -500 -600 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -700 12 10 8 6 4 2 0 -2 100 50 VDD = 5.5V 0 VDD = 1.8V -50 -100 -150 VCM = VSS -200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-11: Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. Input Offset Voltage vs. 30 VDD = 5.5V Short Circuit Current Magnitude (mA) Input Offset Voltage (µV) -4 150 Common Mode Input Voltage (V) -100 Input Offset Voltage Drift. 200 VDD = 1.8V -200 0 -6 Input Offset Voltage Drift (µV/°C) 0 -100 8% 6% 4% 2% 0% -12 10 0.1 1.E+0 1 10 1.E+0 100 1.E+0 1k 1.E+0 10k 1.E+0 100k 1.E-01 1.E+0 0 Frequency 1 2 (Hz) 3 4 5 1225 Samples TA = -40°C to +125°C VCM = VSS -8 100 18% 16% 14% 12% 10% -10 Percentage of Occurrences Input Noise Voltage Density (nV/Hz) 1,000 -200 -300 -400 TA = -40°C TA = +25°C TA = +85°C TA = +125°C -500 -600 Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. © 2005 Microchip Technology Inc. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -700 25 20 15 TA = -40°C TA = +25°C TA = +85°C TA = +125°C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-12: Output Short-Circuit Current vs. Power Supply Voltage. DS21733F-page 5 MCP6001/2/4 0.08 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 G = +1 V/V Falling Edge, VDD = 5.5V Falling Edge, VDD = 1.8V Rising Edge, VDD = 5.5V Rising Edge, VDD = 1.8V -50 -25 0 25 50 75 100 Output Voltage (20 mV/div) Slew Rate (V/µs) Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. 125 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 FIGURE 2-13: Temperature. Slew Rate vs. Ambient FIGURE 2-16: Pulse Response. Output Voltage Headroom (mV) 1,000 6.E-06 7.E-06 8.E-06 10 Output Voltage (V) VDD – VOH VOL – VSS G = +1 V/V VDD = 5.0V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 100µ 1m 1.E-04 1.E-03 Output Current Magnitude (A) 10m 1.E-02 0.0 0.E+00 180 Quiescent Current per amplifier (µA) 160 VDD = 5.5V 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04 VDD = 1.8V Large-Signal, Non-Inverting VCM = VDD - 0.5V 140 120 100 80 60 40 20 DS21733F-page 6 2.E-05 FIGURE 2-17: Pulse Response. 10 FIGURE 2-15: Frequency. 1.E-05 Time (10 µs/div) FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. 0.1 1k 1.E+03 1.E-05 5.0 100 1 9.E-06 Small-Signal, Non-Inverting 4.5 1 10µ 1.E-05 Output Voltage Swing (V P-P) 5.E-06 Time (1 µs/div) Ambient Temperature (°C) TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 Output Voltage Swing vs. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. © 2005 Microchip Technology Inc. MCP6001/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP6001 3.1 PIN FUNCTION TABLE MCP6001R MCP6001U MCP6002 Symbol Description 1 1 4 1 1 VOUT, VOUTA Analog Output (op amp A) 4 4 3 2 2 VIN–, VINA– Inverting Input (op amp A) 3 3 1 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 5 2 5 8 4 VDD Non-inverting Input (op amp B) Positive Power Supply — — — 5 5 VINB+ — — — 6 6 VINB– Inverting Input (op amp B) — — — 7 7 VOUTB Analog Output (op amp B) — — — — 8 VOUTC Analog Output (op amp C) — — — — 9 VINC– Inverting Input (op amp C) — — — — 10 VINC+ Non-inverting Input (op amp C) 2 5 2 4 11 VSS — — — — 12 VIND+ Non-inverting Input (op amp D) — — — — 13 VIND– Inverting Input (op amp D) — — — — 14 VOUTD Analog Output (op amp D) Analog Outputs The output pins are low-impedance voltage sources. 3.2 MCP6004 Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. © 2005 Microchip Technology Inc. 3.3 Negative Power Supply Power Supply (VSS and VDD) The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 µF to 0.1 µF) within 2 mm of the VDD pin. These parts can share a bulk capacitor with analog parts (typically 2.2 µF to 10 µF) within 100 mm of the VDD pin. DS21733F-page 7 MCP6001/2/4 4.0 APPLICATION INFORMATION – The MCP6001/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6001/2/4 ideal for battery-powered applications. This device has high phase margin, which makes it stable for larger capacitive load applications. 4.1 RIN VIN VOUT ( Maximum expected VIN ) – V DD RIN ≥ ------------------------------------------------------------------------------2 mA V SS – ( Minimum expected V IN ) R IN ≥ ---------------------------------------------------------------------------2 mA Rail-to-Rail Input The MCP6001/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. FIGURE 4-2: Resistor (RIN). 4.2 6 Input, Output Voltages (V) MCP600X + VIN VOUT Rail-to-Rail Output The output voltage range of the MCP6001/2/4 op amps is VDD – 25 mV (min.) and VSS + 25 mV (max.) when RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. VDD = 5.0V G = +2 V/V 5 Input Current Limiting 4 3 4.3 2 1 0 -1 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04 Time (10 µs/div) FIGURE 4-1: Phase Reversal. The MCP6001/2/4 Show No The input stage of the MCP6001/2/4 op amps use two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS – 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS – 0.3V to VDD + 0.3V at 25°C) can cause excessive current to flow into or out of the input pins, while current beyond ±2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-2. Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load. – VIN MCP600X + RISO VOUT CL FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. DS21733F-page 8 © 2005 Microchip Technology Inc. MCP6001/2/4 Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). Recommended RISO (:) 1000 100 VDD = 5.0V RL = 100 k: GN = 1 GN t 2 4.5 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow; which is greater than the MCP6001/2/4 family’s bias current at 25°C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-5. VIN- 10 100p 1n 10n 10p 10n 1.E-11 1.E-10 1.E-09 1.E-08 Normalized Load Capacitance; CL/GN (F) VIN+ VSS FIGURE 4-4: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6001/2/4 SPICE macro model are very helpful. 4.4 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. © 2005 Microchip Technology Inc. Guard Ring FIGURE 4-5: for Inverting Gain. 1. 2. Example Guard Ring Layout Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. DS21733F-page 9 MCP6001/2/4 4.6 4.6.1 Application Circuits 100 pF UNITY-GAIN BUFFER The rail-to-rail input and output capability of the MCP6001/2/4 op amp is ideal for unity-gain buffer applications. The low quiescent current and wide bandwidth makes the device suitable for a buffer configuration in an instrumentation amplifier circuit, as shown in Figure 4-6. – 1/2 MCP6002 VIN1 + MCP6001 VOUT + 1/2 MCP6002 VIN2 R2 + R1 R1 = 20 kΩ R2 = 10 kΩ VREF R1 V OUT = ( VIN2 – VIN1 ) • ------ + V REF R2 FIGURE 4-6: Instrumentation Amplifier with Unity-Gain Buffer Inputs. 4.6.2 33 pF 4.6.3 – – + MCP6002 FIGURE 4-7: Low- Pass Filter. R1 R2 VIN 14.3 kΩ 53.6 kΩ ACTIVE LOW-PASS FILTER The MCP6001/2/4 op amp’s low input bias current makes it possible for the designer to use larger resistors and smaller capacitors for active low-pass filter applications. However, as the resistance increases, the noise generated also increases. Parasitic capacitances and the large value resistors could also modify the frequency response. These trade-offs need to be considered when selecting circuit elements. Usually, the op amp bandwidth is 100X the filter cutoff frequency (or higher) for good performance. It is possible to have the op amp bandwidth 10X higher than the cutoff frequency, thus having a design that is more sensitive to component tolerances. Figure 4-7 shows a second-order Butterworth filter with 100 kHz cutoff frequency and a gain of +1 V/V; the op amp bandwidth is only 10X higher than the cutoff frequency. The component values were selected using Microchip’s FilterLab® software. – VOUT Active Second-Order PEAK DETECTOR The MCP6001/2/4 op amp has a high input impedance, rail-to-rail input/output and low input bias current, which makes this device suitable for peak detector applications. Figure 4-8 shows a peak detector circuit with clear and sample switches. The peak-detection cycle uses a clock (CLK), as shown in Figure 4-8. At the rising edge of CLK, Sample Switch closes to begin sampling. The peak voltage stored on C1 is sampled to C2 for a sample time defined by tSAMP. At the end of the sample time (falling edge of Sample Signal), Clear Signal goes high and closes the Clear Switch. When the Clear Switch closes, C1 discharges through R1 for a time defined by tCLEAR. At the end of the clear time (falling edge of Clear Signal), op amp A begins to store the peak value of VIN on C1 for a time defined by tDETECT. In order to define tSAMP and tCLEAR, it is necessary to determine the capacitor charging and discharging period. The capacitor charging time is limited by the amplifier source current, while the discharging time (τ) is defined using R1 (τ = R1C1). tDETECT is the time that the input signal is sampled on C1 and is dependent on the input voltage change frequency. The op amp output current limit, and the size of the storage capacitors (both C1 and C2), could create slewing limitations as the input voltage (VIN) increases. Current through a capacitor is dependent on the size of the capacitor and the rate of voltage change. From this relationship, the rate of voltage change or the slew rate can be determined. For example, with an op amp shortcircuit current of ISC = 25 mA and a load capacitor of C1 = 0.1 µF, then: EQUATION 4-1: dV C1 I SC = C 1 ------------dt dV C1 I SC ------------- = -------dt C1 25mA = --------------0.1μF dVC1 ------------ = 250mV ⁄ μs dt DS21733F-page 10 © 2005 Microchip Technology Inc. MCP6001/2/4 This voltage rate of change is less than the MCP6001/2/4 slew rate of 0.6 V/µs. When the input voltage swings below the voltage across C1, D1 becomes reversebiased. This opens the feedback loop and rails the amplifier. When the input voltage increases, the amplifier recovers at its slew rate. Based on the rate of voltage change shown in the above equation, it takes an extended period of time to charge a 0.1 µF capacitor. The capacitors need to be selected so that the circuit is not limited by the amplifier slew rate. Therefore, the capacitors should be less than 40 µF and a stabilizing resistor (RISO) needs to be properly selected. (Refer to Section 4.3 “Capacitive Loads”). VIN + 1/2 MCP6002 – D1 RISO VC1 Op Amp A C1 R1 RISO VC2 + 1/2 MCP6002 – C2 Op Amp B + MCP6001 – VOUT Op Amp C Sample Switch Clear Switch tSAMP Sample Signal tCLEAR Clear Signal tDETECT CLK FIGURE 4-8: Peak Detector with Clear and Sample CMOS Analog Switches. © 2005 Microchip Technology Inc. DS21733F-page 11 MCP6001/2/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6001/2/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6001/2/4 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from our web site at www.microchip.com, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21733F-page 12 © 2005 Microchip Technology Inc. MCP6001/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC-70 (MCP6001) XXN (Front) YWW (Back) Example: (I-Temp) Device MCP6001 I-Temp Code E-Temp Code AAN CDN AA7 (Front) 432 (Back) Note: Applies to 5-Lead SC-70. OR OR XXNN Device I-Temp Code E-Temp Code MCP6001 AANN CDNN AA74 Note: Applies to 5-Lead SC-70. Example: (E-Temp) 5-Lead SOT-23 (MCP6001/1R/1U) 4 5 XXNN 1 2 I-Temp Code E-Temp Code MCP6001 AANN CDNN MCP6001R ADNN CENN MCP6001U AFNN CFNN Device 3 4 5 CD25 1 2 3 Note: Applies to 5-Lead SOT-23. 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Legend: Note: * XX...X YY WW NNN Example: MCP6002 I/P256 0432 Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. © 2005 Microchip Technology Inc. DS21733F-page 13 MCP6001/2/4 Package Marking Information (Continued) 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP Example: MCP6002 I/SN0432 256 Example: XXXXXX 6002I YWWNNN 432256 14-Lead PDIP (300 mil) (MCP6004) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6004) Example: MCP6004-I/P 0432256 Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6004) DS21733F-page 14 MCP6004ISL 0432256 Example: XXXXXX YYWW 6004ST 0432 NNN 256 © 2005 Microchip Technology Inc. MCP6001/2/4 5-Lead Plastic Package (SC-70) E E1 D p B n 1 Q1 A2 c A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Top of Molded Pkg to Lead Shoulder Lead Thickness Lead Width A A2 A1 E E1 D L Q1 c B MIN .031 .031 .000 .071 .045 .071 .004 .004 .004 .006 INCHES NOM 5 .026 (BSC) MAX .043 .039 .004 .094 .053 .087 .012 .016 .007 .012 MILLIMETERS* NOM 5 0.65 (BSC) 0.80 0.80 0.00 1.80 1.15 1.80 0.10 0.10 0.10 0.15 MIN MAX 1.10 1.00 0.10 2.40 1.35 2.20 0.30 0.40 0.18 0.30 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70 Drawing No. C04-061 © 2005 Microchip Technology Inc. DS21733F-page 15 MCP6001/2/4 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 n D 1 α c A Units Dimension Limits n Number of Pins p Pitch p1 Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic φ L β A A2 A1 E E1 D L φ c B α β MIN .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 DS21733F-page 16 © 2005 Microchip Technology Inc. MCP6001/2/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2005 Microchip Technology Inc. DS21733F-page 17 MCP6001/2/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21733F-page 18 © 2005 Microchip Technology Inc. MCP6001/2/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM 8 .026 BSC .033 .193 TYP. .118 BSC .118 BSC .024 .037 REF .006 .012 - MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN Number of Pins Pitch A .043 Overall Height A2 .030 .037 Molded Package Thickness .000 .006 A1 Standoff E Overall Width E1 Molded Package Width D Overall Length L .016 .031 Foot Length Footprint (Reference) F φ Foot Angle 0° 8° c Lead Thickness .003 .009 Lead Width B .009 .016 α Mold Draft Angle Top 5° 15° β 5° 15° Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8° 0.23 0.40 15° 15° JEDEC Equivalent: MO-187 Drawing No. C04-111 © 2005 Microchip Technology Inc. DS21733F-page 19 MCP6001/2/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21733F-page 20 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 © 2005 Microchip Technology Inc. MCP6001/2/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 © 2005 Microchip Technology Inc. DS21733F-page 21 MCP6001/2/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B1 α β MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21733F-page 22 © 2005 Microchip Technology Inc. MCP6001/2/4 APPENDIX A: REVISION HISTORY Revision F (March 2005) Updated 6.0 “Packaging Information” to include old and new packaging examples. Revision E (December 2004) The following is the list of modifications: 1. 2. 3. VOS specification reduced to ±4.5 mV from ±7.0 mV for parts starting with date code YYWW = 0449 Corrected package markings in Section 6.0 “Packaging Information” Added Appendix A: Revision History. Revision D (May 2003) Revision C (December 2002) Revision B (October 2002) Revision A (June 2002) Original data sheet release. © 2005 Microchip Technology Inc. DS21733E-page 23 MCP6001/2/4 NOTES: DS21733E-page 24 © 2005 Microchip Technology Inc. MCP6001/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device: MCP6001T: MCP6001RT: MCP6001UT: MCP6002: MCP6002T: MCP6004: MCP6004T: Single Op Amp (Tape and Reel) (SC-70, SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC, MSOP) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, MSOP) Temperature Range: I E = -40°C to +85°C = -40°C to +125°C Package: LT = Plastic Package (SC-70), 5-lead (MCP6001 only) OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6001, MCP6001R, MCP6001U) MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4mm Body), 14-lead c) d) MCP6001T-I/LT: Tape and Reel, Industrial Temperature, 5LD SC-70 package MCP6001T-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT-23 package. MCP6001RT-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT-23 package. MCP6001UT-E/OT: Tape and Reel, Extended Temperature, 5LD SOT-23 package. a) MCP6002-I/MS: b) MCP6002-I/P: c) MCP6002-E/P: d) MCP6002-I/SN: e) MCP6002T-I/MS: a) MCP6004-I/P: b) MCP6004-I/SL: c) MCP6004-E/SL: d) MCP6004-I/ST: e) MCP6004T-I/SL: f) MCP6004T-I/ST: Industrial Temperature, 8LD MSOP package. Industrial Temperature, 8LD PDIP package. Extended Temperature, 8LD PDIP package. Industrial Temperature, 8LD SOIC package. Tape and Reel, Industrial Temperature, 8LD MSOP package. Industrial Temperature, 14LD PDIP package. Industrial Temperature,, 14LD SOIC package. Extended Temperature,, 14LD SOIC package. Industrial Temperature, 14LD TSSOP package. Tape and Reel, Industrial Temperature, 14LD SOIC package. Tape and Reel, Industrial Temperature, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com) to receive the most current information on our products. © 2005 Microchip Technology Inc. DS21733E-page 25 MCP6001/2/4 NOTES: DS21733E-page 26 © 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. DS21733E-page 27 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 10/20/04 DS21733E-page 28 © 2005 Microchip Technology Inc.