Lattice ISPLSI1032E125LTN In-system programmable high density pld Datasheet

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Package
Options
Available!
ispLSI 1032E
®
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
D7 D6 D5 D4 D3 D2 D1 D0
C7
A0
— High Speed Global Interconnect
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
A2
A3
D Q
A5
C4
C2
C1
A6
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
— Electrically Erasable and Reprogrammable
C0
CLK
EW
Output Routing Pool
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
0139A(A1)-isp
N
Description
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
R
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-volatile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
FO
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
03
2E
A
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
GLB
D
— TTL Compatible Inputs and Outputs
D Q
C3
A4
A7
C5
D Q
Logic
Array
Output Routing Pool
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
C6
ES
IG
N
Output Routing Pool
D Q
A1
S
— 192 Registers
— Four Dedicated Clock Input Pins
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
I1
— Synchronous and Asynchronous Clocks
pL
S
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
SE
is
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032e_09
1
August 2006
Specifications ispLSI 1032E
Functional Block Diagram
IN 7
IN 6
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 59
I/O 58
I/O 57
I/O 56
I/O 63
I/O 62
I/O 61
I/O 60
Figure 1. ispLSI 1032E Functional Block Diagram
S
RESET
Input Bus
Generic
Logic Blocks
(GLBs)
D7
D6
D5
D4
D3
D2
D1
ES
IG
N
Output Routing Pool (ORP)
GOE 1/IN 5
GOE 0/IN 4
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
EW
A4
C3
C2
A5
R
A6
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
B0
B1
B2
FO
A7
B3
B4
B5
B6
C1
Clock
Distribution
Network
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
C0
B7
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
A
Megablock
D
C4
Global
Routing
Pool
(GRP)
A3
lnput Bus
A2
Output Routing Pool (ORP)
C5
N
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
C6
A1
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to minimize overall output switching noise.
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
03
SDO/IN 2
SCLK/IN 3
2E
Input Bus
ispEN
Y0
Y1
Y2
Y3
I/O 0
I/O 1
I/O 2
I/O 3
LS
I1
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
SE
is
p
Clocks in the ispLSI 1032E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032E device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
U
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1032E device contains four Megablocks.
2
Specifications ispLSI 1032E
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
S
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
ES
IG
N
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
EW
D
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
VIL
VIH
Input Low Voltage
UNITS
4.75
5.25
V
Industrial
TA = -40°C to + 85°C
4.5
5.5
V
0
0.8
V
2.0
Vcc+1
V
Table 2-0005/1032E
A
2E
SYMBOL
MAX.
TA = 0°C to + 70°C
Input High Voltage
Capacitance (TA=25oC, f=1.0 MHz)
MIN.
Commercial
R
Supply Voltage
FO
VCC
N
PARAMETER
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
8
pf
VCC = 5.0V, VPIN = 2.0V
C2
Y0 Clock Capacitance
15
pf
VCC = 5.0V, VPIN = 2.0V
I1
03
C1
Table 2-0006/1032E
LS
Data Retention Specifications
PARAMETER
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
is
p
Data Retention
MINIMUM
Erase/Reprogram Cycles
U
SE
Table 2-0008/1032E
3
Specifications ispLSI 1032E
Switching Test Conditions
Figure 2. Test Load
GND to 3.0V
-125
≤ 2 ns
Others
≤ 3 ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
R1
Device
Output
See Figure 2
Table 2-0003/1032E
3-state levels are measured 0.5V from
steady-state active level.
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
B
C
*CL includes Test Fixture and Probe Capacitance.
0213a
R
A
D
CL
EW
R2
N
R1
Test
Point
CL*
R2
Output Load Conditions (see Figure 2)
TEST CONDITION
S
Input Rise and Fall Time
10% to 90%
ES
IG
N
Input Pulse Levels
FO
Table 2-0004/1032E
DC Electrical Characteristics
SYMBOL
2E
A
Over Recommended Operating Conditions
PARAMETER
Output Low Voltage
ICC2, 4
Operating Power Supply Current
Output High Voltage
03
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
3
MIN.
TYP.
MAX. UNITS
IOL= 8 mA
–
–
0.4
V
IOH = -4 mA
2.4
–
–
V
–
–
-10
μA
3.5V ≤ VIN ≤ VCC
–
–
10
μA
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
VIL = 0.5V, VIH = 3.0V
Commercial
–
190
–
mA
fCLOCK = 1 MHz
Industrial
–
190
–
mA
LS
I1
0V ≤ VIN ≤ VIL (Max.)
Input or I/O High Leakage Current
is
p
Input or I/O Low Leakage Current
CONDITION
Table 2-0007/1032E
U
SE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .
4
Specifications ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
4
-100
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
A
2
Data Propagation Delay, Worst Case Path
–
10.0
–
12.5
3
1
MIN. MAX. MIN. MAX.
3
Clock Frequency with Internal Feedback
UNITS
1
tsu2 + tco1
)
ns
S
DESCRIPTION
ES
IG
N
A
2
ns
125
–
100
91.0
–
71.0
–
MHz
167
–
125
–
MHz
5.0
–
7.0
–
ns
–
MHz
–
4
Clock Frequency with External Feedback (
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
5.0
–
6.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
6.0
–
8.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
6.0
–
7.0
ns
–
11 GLB Reg. Hold Time after Clock
0.0
–
0.0
–
ns
ns
EW
D
( twh 1+ tw1 )
10.0
–
5.0
–
6.5
–
ns
–
12.0
–
15.0
ns
–
12.0
–
15.0
ns
–
7.0
–
9.0
ns
–
7.0
–
9.0
ns
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
4.0
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
3.0
–
3.5
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
–
0.0
–
ns
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
B
14 Input to Output Enable
C
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
A
FO
R
A
N
–
13.5
2E
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
p
LS
1.
2.
3.
4.
-125
TEST
COND.
03
PARAMETER
5
Table 2-0030A/1032E
Specifications ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
4
TEST
COND.
DESCRIPTION
-70
-80
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
10.0
–
12.0
–
15.0
A
2
Data Propagation Delay, Worst Case Path
–
12.5
–
15.0
–
17.5
A
3
Clock Frequency with Internal Feedback 3
90.0
–
80.0
–
70.0
–
MHz
69.0
–
61.0
–
56.0
–
MHz
125
–
111
–
100
–
MHz
7.5
–
8.5
–
9.0
–
ns
Clock Frequency with External Feedback (
(
1
twh + tw1
)
)
S
ES
IG
N
4
1
tsu2 + tco1
ns
ns
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
6.0
–
6.5
–
7.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
8.5
D
–
–
10 GLB Reg. Clock to Output Delay
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
14 Input to Output Enable
C
15 Input to Output Disable
0.0
10.0
–
11.0
–
ns
–
7.0
–
7.5
–
8.0
ns
0.0
–
0.0
–
0.0
–
ns
–
13.5
–
14.0
–
15.0
ns
6.5
–
8.0
–
10.0
–
ns
–
15.0
–
16.5
–
18.0
ns
–
15.0
–
16.5
–
18.0
ns
–
9.0
–
10.0
–
12.0
ns
–
9.0
–
10.0
–
12.0
ns
–
EW
N
13 Ext. Reset Pulse Duration
FO
R
–
B
16 Global OE Output Enable
17 Global OE Output Disable
–
18 External Synchronous Clock Pulse Duration, High
4.0
–
4.5
–
5.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
4.0
–
4.5
–
5.0
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5
–
3.5
–
4.0
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
0.0
–
0.0
–
ns
A
B
C
0.0
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
p
LS
1.
2.
3.
4.
-90
1
2
2E
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
#
03
PARAMETER
6
Table 2-0030B/1032E
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM. #
2
-125
DESCRIPTION
-100
MIN. MAX. MIN. MAX.
UNITS
Inputs
–
0.3
–
0.3
ns
23 I/O Latch Delay
–
1.9
–
2.3
ns
24 I/O Register Setup Time before Clock
3.0
–
3.5
–
ns
25 I/O Register Hold Time after Clock
0.0
–
0.0
–
ns
26 I/O Register Clock to Out Delay
–
4.6
–
5.0
ns
27 I/O Register Reset to Out Delay
–
4.6
–
5.0
ns
28 Dedicated Input Delay
–
2.3
–
2.7
ns
–
1.8
–
1.9
ns
–
2.0
–
2.4
ns
–
2.3
–
2.4
ns
–
ES
IG
N
GRP
EW
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
2.8
–
3.0
ns
–
3.8
–
4.2
ns
34 4 Prod.Term Bypass Path Delay (Combinatorial)
–
3.9
–
5.3
ns
35 4 Prod. Term Bypass Path Delay (Registered)
–
4.0
–
5.3
ns
36 1 Prod.Term/XOR Path Delay
–
3.6
–
4.6
ns
–
5.0
–
5.8
ns
–
5.0
–
6.3
ns
–
0.4
–
1.0
ns
40 GLB Register Setup Time before Clock
0.1
–
0.5
–
ns
41 GLB Register Hold Time after Clock
4.5
–
5.8
–
ns
42 GLB Register Clock to Output Delay
–
2.3
–
2.5
ns
43 GLB Register Reset to Output Delay
–
4.9
–
6.2
ns
3.9
–
4.5
ns
N
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
R
tgrp1
tgrp4
tgrp8
tgrp16
tgrp32
A
2E
LS
I1
03
39 GLB Register Bypass Delay
–
–
5.4
–
7.2
ns
46 GLB Prod. Term Clock Delay
2.9
4.0
3.5
4.7
ns
–
1.0
–
1.0
ns
0.0
–
0.0
ns
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
47 ORP Delay
SE
torp
torpbp
38 XOR Adjacent Path Delay 3
is
p
ORP
37 20 Prod. Term/XOR Path Delay
FO
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
S
22 I/O Register Bypass
D
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
48 ORP Bypass Delay
–
U
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/1032E
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM. #
2
-80
-90
DESCRIPTION
-70
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
–
0.3
–
0.3
–
0.3
ns
23 I/O Latch Delay
–
2.3
–
2.7
–
3.3
24 I/O Register Setup Time before Clock
3.5
–
3.5
–
4.0
–
ns
25 I/O Register Hold Time after Clock
–
0.0
–
ns
0.0
–
0.0
–
5.0
–
5.4
–
6.1
ns
27 I/O Register Reset to Out Delay
–
5.0
–
5.4
–
6.0
ns
28 Dedicated Input Delay
–
2.6
–
2.8
–
2.8
ns
29 GRP Delay, 1 GLB Load
–
2.1
–
2.2
–
2.5
ns
–
2.3
–
2.5
–
2.5
ns
–
2.6
–
2.8
–
3.2
ns
–
3.2
–
3.5
–
4.0
ns
–
4.4
–
4.8
–
5.6
ns
34 4 Prod.Term Bypass Path Delay (Combinatorial)
–
5.7
–
7.1
–
8.8
ns
35 4 Prod. Term Bypass Path Delay (Registered)
–
6.1
–
6.7
–
7.2
ns
36 1 Prod.Term/XOR Path Delay
–
5.6
–
6.6
–
8.3
ns
–
6.8
–
7.8
–
8.7
ns
–
7.1
–
8.2
–
9.2
ns
–
0.4
–
1.3
–
1.6
ns
40 GLB Register Setup Time before Clock
0.2
–
0.5
–
0.5
–
ns
41 GLB Register Hold Time after Clock
6.8
–
7.9
–
8.8
–
ns
42 GLB Register Clock to Output Delay
–
2.9
–
2.9
–
2.9
ns
43 GLB Register Reset to Output Delay
–
6.3
–
6.4
–
6.8
ns
44 GLB Prod.Term Reset to Register Delay
–
5.1
–
5.5
–
5.8
ns
EW
GRP
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
R
tgrp1
tgrp4
tgrp8
tgrp16
tgrp32
A
LS
I1
03
39 GLB Register Bypass Delay
2E
38 XOR Adjacent Path Delay
3
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
47 ORP Delay
SE
torp
torpbp
37 20 Prod. Term/XOR Path Delay
is
p
ORP
FO
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
D
ns
26 I/O Register Clock to Out Delay
ES
IG
N
22 I/O Register Bypass
N
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
S
Inputs
48 ORP Bypass Delay
U
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
–
7.1
–
8.0
–
9.0
ns
4.1
5.3
4.5
5.8
4.8
6.2
ns
–
1.0
–
1.0
–
1.0
ns
–
0.0
–
0.0
–
0.0
ns
Table 2-0036B/1032E
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM.
#
-125
DESCRIPTION
-100
MIN. MAX. MIN. MAX.
UNITS
–
1.3
–
2.0
ns
50 Output Buffer Delay, Slew Limited Adder
–
9.9
–
10.0
ns
51 I/O Cell OE to Output Enabled
–
4.3
–
5.1
ns
52 I/O Cell OE to Output Disabled
–
4.3
–
5.1
ns
53 Global OE
–
2.7
–
3.9
ns
1.4
1.4
1.5
1.5
ns
1.4
1.4
1.5
1.5
ns
0.8
1.8
0.8
1.8
ns
0.0
0.0
0.0
0.0
ns
0.8
1.8
0.8
1.8
ns
–
2.8
–
4.3
ns
Clocks
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
EW
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
N
Global Reset
59 Global Reset to GLB and I/O Registers
R
tgr
U
SE
is
p
LS
I1
03
2E
A
FO
1. Internal Timing Parameters are not tested and are for reference only.
9
S
49 Output Buffer Delay
ES
IG
N
tob
tsl
toen
todis
tgoe
D
Outputs
Table 2-0037A/1032E
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM.
#
-80
-90
DESCRIPTION
-70
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
–
1.7
–
2.1
–
2.6
ns
50 Output Buffer Delay, Slew Limited Adder
–
10.0
–
10.0
–
10.0
ns
51 I/O Cell OE to Output Enabled
–
5.3
–
5.7
–
6.2
ns
52 I/O Cell OE to Output Disabled
–
5.3
–
5.7
–
6.2
ns
53 Global OE
–
3.7
–
4.3
–
5.8
ns
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.4
1.4
1.5
1.5
1.5
1.5
ns
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.4
2.9
2.6
3.1
1.5
1.5
ns
56 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
0.8
1.8
0.8
1.8
ns
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.0
0.0
0.0
0.0
0.0
0.0
ns
0.8
1.8
0.8
1.8
0.8
1.8
ns
4.5
–
4.5
–
4.6
ns
N
Global Reset
59 Global Reset to GLB and I/O Registers
–
R
tgr
EW
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
U
SE
is
p
LS
I1
03
2E
A
FO
1. Internal Timing Parameters are not tested and are for reference only.
10
S
49 Output Buffer Delay
ES
IG
N
tob
tsl
toen
todis
tgoe
D
Outputs
Table 2-0037B/1032E
Specifications ispLSI 1032E
ispLSI 1032E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#34
#28
GLB Reg Bypass
ORP Bypass
#30
#35
#39
#48
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#59
#29, 31 - 33
#36 - 38
GRP4
Reg 4 PT Bypass
D
Q
Clock
Distribution
EW
#55 - 58
D
Y1,2,3
#40 - 43
Control RE
PTs
OE
#44 - 46 CK
#54
Y0
#53
N
GOE 0,1
R
Derivations of tsu, th and tco from the Product Term Clock 1
=
=
=
2.2 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th
=
=
=
3.5 ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
A
2E
03
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
I1
=
=
=
10.9 ns =
LS
tco
FO
tsu
Derivations of tsu, th and tco from the Clock GLB 1
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
is
p
=
=
=
2.9 ns =
SE
tsu
=
=
=
2.7 ns =
Clock (max) + Reg h - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco
=
=
=
5.5 ns =
Clock (max) + Reg co + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
U
th
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
Table 2-0042a/1032E
11
#51, 52
#47
RST
#59
Reset
#49, 50
ES
IG
N
I/O Pin
(Input)
Comb 4 PT Bypass
#22
I/O Reg Bypass
0491
I/O Pin
(Output)
S
Ded. In
Specifications ispLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI 1032E-80
ispLSI 1032E-90/100
4.0
ispLSI 1032E-125
3.0
D
2.0
1
4
8
16
32
EW
1.0
S
5.0
ES
IG
N
GRP Delay (ns)
ispLSI 1032E-70
GLB Load
GRP/GLB/1032E
N
Power Consumption
3 shows the relationship between power and operating
speed.
FO
R
Power consumption in the ispLSI 1032E device depends
on two primary factors: the speed at which the device is
operating, and the number of product terms used. Figure
A
Figure 3. Typical Device Power Consumption vs fmax
2E
350
03
ispLSI 1032E
250
I1
ICC (mA)
300
200
LS
150
SE
is
p
100
0
20
40
60
80
fmax (MHz)
100
125
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
I CC can be estimated for the ispLSI 1032E using the following equation:
U
I CC (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating
conditions and the program in the device, the actual I CC should be verified.
12
0127/1032E
Specifications ispLSI 1032E
Pin Description
PLCC PIN
NUMBERS
NAME
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
TQFP PIN
NUMBERS
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
DESCRIPTION
20, Input/Output Pins - These are the general purpose I/O pins used by the logic
28, array.
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
GOE 0/IN 43
67
66
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
GOE 1/IN 53
84
87
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
IN 6, IN 7
2,
ispEN
23
14
SDI/IN 02
25
16
MODE/IN 12
42
37
SDO/IN 22
44
39
SCLK/IN 32
61
60
RESET
24
Y0
20
Y1
66
U
GND
VCC
NC1
ES
IG
N
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
N
EW
D
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,
Dedicated input pins to the device.
10
2E
A
FO
R
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
I1
03
Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
15
11
LS
SE
Y3
89,
65
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
63
62
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
62
61
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
13, 38, 63, 88
Ground (GND)
12, 64
Vcc
is
p
Y2
19
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
S
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
1,
22, 43, 64
21, 65
1,
26,
51,
76,
2,
27,
52,
77,
24,
49,
74,
99,
25, No connect.
50,
75,
100
1. NC pins are not to be connected to any active signals, Vcc or GND.
2. Pins have dual function capability.
3. Pins have dual function capability which is software selectable.
13
Table 2-0002A/1032E
Specifications ispLSI 1032E
Pin Configurations
I/O 60
15
I/O 61
16
I/O 62
17
I/O 63
18
IN 7
19
Y0
20
ispLSI 1032E
ispEN
23
Top View
RESET
24
29
I/O 4
30
I/O 5
31
I/O 6
32
S
I/O 39
I/O 40
A
I/O 3
2E
28
03
I/O 2
I1
27
LS
26
I/O 1
FO
22
I/O 0
I/O 41
1 84 83 82 81 80 79 78 77 76 75
21
25
I/O 42
2
VCC
0
I/O 43
GND
3
GND
1SDI/IN
I/O 44
IN 6
I/O 45
I/O 48
I/O 46
I/O 49
I/O 47
I/O 50
GOE 1/IN 52
I/O 51
4
ES
IG
N
14
5
D
I/O 59
6
EW
13
7
N
12
I/O 58
8
R
I/O 57
I/O 52
11 10 9
I/O 53
I/O 54
I/O 55
I/O 56
ispLSI 1032E 84-Pin PLCC Pinout Diagram
74
I/O 38
73
I/O 37
72
I/O 36
71
I/O 35
70
I/O 34
69
I/O 33
68
I/O 32
67
GOE 0/IN 42
66
Y1
65
VCC
64
GND
63
Y2
62
Y3
61
SCLK/IN 31
60
I/O 31
59
I/O 30
58
I/O 29
57
I/O 28
56
I/O 27
55
I/O 26
54
I/O 25
U
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
2
GND
1SDO/IN
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 9
I/O 8
1MODE/IN
SE
I/O 7
is
p
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1. Pins have dual function capability.
3. Pins have dual function capability which is software selectable.
0123-32-isp
14
Specifications ispLSI 1032E
Pin Configurations
N
EW
S
ES
IG
N
D
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
R
ispLSI 1032E
A
FO
Top View
NC3
NC3
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0/IN 42
Y1
VCC
GND
Y2
Y3
SCLK/IN 31
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
NC3
NC3
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
1MODE/IN1
GND
1SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
3NC
3NC
3NC
is
p
U
SE
3NC
LS
I1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
Y0
VCC
GND
ispEN
RESET
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
3NC
3NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2E
3NC
03
3NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC3
NC3
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
GND
GOE 1/IN 52
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
NC3
NC3
ispLSI 1032E 100-Pin TQFP Pinout Diagram
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
3. NC pins are not to be connected to any active signal, VCC or GND.
15
0766A-32E-isp
Specifications ispLSI 1032E
Part Number Description
ispLSI 1032E – XXX
X
X
X
Device Family
S
Grade
Blank = Commercial
I = Industrial
Device Number
ES
IG
N
Package
J = PLCC
T = TQFP
JN = Lead-Free PLCC
TN = Lead-Free TQFP
Speed
125 = 125 MHz fmax
100 = 100 MHz fmax
90 = 90 MHz fmax
80 = 80 MHz fmax
70 = 70 MHz fmax
EW
D
Power
L = Low
N
ispLSI 1032E Ordering Information
Conventional Packaging
ispLSI
125
7.5
125
7.5
100
10
100
10
90
10
10
03
90
80
70
LS
70
12
PACKAGE
ispLSI 1032E-125LJ
84-Pin PLCC
ispLSI 1032E-125LT
100-Pin TQFP
ispLSI 1032E-100LJ
84-Pin PLCC
ispLSI 1032E-100LT
100-Pin TQFP
ispLSI 1032E-90LJ1
84-Pin PLCC
1
100-Pin TQFP
1
84-Pin PLCC
1
100-Pin TQFP
ispLSI 1032E-90LT
ispLSI 1032E-80LJ
12
ispLSI 1032E-80LT
15
ispLSI 1032E-70LJ
84-Pin PLCC
15
ispLSI 1032E-70LT
100-Pin TQFP
I1
80
ORDERING NUMBER
FO
tpd (ns)
A
fmax (MHz)
2E
FAMILY
R
COMMERCIAL
FAMILY
INDUSTRIAL
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
70
15
ispLSI 1032E-70LJI
84-Pin PLCC
70
15
ispLSI 1032E-70LTI
100-Pin TQFP
U
SE
ispLSI
is
p
1. Converted to -100 speed grade per PCN# 001-97.
16
Specifications ispLSI 1032E
ispLSI 1032E Ordering Information (Cont.)
Lead-Free Packaging
COMMERCIAL
tpd (ns)
ORDERING NUMBER
PACKAGE
125
7.5
ispLSI 1032E-125LJN
Lead-Free 84-Pin PLCC1
125
7.5
ispLSI 1032E-125LTN
Lead-Free 100-Pin TQFP
100
10
ispLSI 1032E-100LJN
100
10
ispLSI 1032E-100LTN
70
15
ispLSI 1032E-70LJN
70
15
ispLSI 1032E-70LTN
ispLSI
S
fmax (MHz)
ES
IG
N
FAMILY
Lead-Free 84-Pin PLCC1
Lead-Free 100-Pin TQFP
Lead-Free 84-Pin PLCC1
Lead-Free 100-Pin TQFP
D
1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com.
INDUSTRIAL
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
70
15
ispLSI 1032E-70LJNI
Lead-Free 84-Pin PLCC1
70
15
ispLSI 1032E-70LTNI
Lead-Free 100-Pin TQFP
ispLSI
EW
FAMILY
N
1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com.
FO
Date
R
Revision History
Version
Change Summary
08
August 2006
09
Updated for lead-free package options.
U
SE
is
p
LS
I1
03
2E
A
—
Previous Lattice release.
17