IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: DESCRIPTION: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.3V VDD • tpd Phase Error at 133MHz: < ±150ps • Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz • Spread Spectrum Compatible • Operating frequency 25MHz to 140MHz • Available in 24-Pin TSSOP package The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CSP2510C operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSP2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground. The CSP2510C is specified for operation from 0°C to +85°C. This device is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details. APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations FUNCTIONAL BLOCK DIAGRAM 11 G 3 Y0 4 Y1 5 Y2 8 Y3 9 Y4 15 Y5 16 Y6 17 CLK 24 Y7 PLL 20 13 Y8 FBIN 21 AV DD Y9 23 12 FBOUT The IDT logo is a registered trademark of Integrated Device Technology, Inc. 0ººC TO 85ººC TEMPERATURE RANGE OCTOBER 2000 1 c 1999 Integrated Device Technology, Inc. DSC-5180/2 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) AGND 1 24 CLK VDD 2 23 AVDD Y0 3 22 VDD Y1 4 21 Y9 Symbol Rating Max VDD Supply Voltage Range –0.5 to +4.6 V VI(1) VO(1,2) Input Voltage Range Voltage range applied to any –0.5 to +6.5 –0.5 to VDD + 0.5 V V IIK output in the high or low state Input clamp current –50 mA (VI <0) IOK Terminal Voltage with Respect ±50 mA ±50 mA ±100 – 65 to +150 mA °C +150 °C Y2 5 20 Y8 (VO <0 or VO > VDD) GND 6 19 GND Continuous Output Current IO (VO = 0 to VDD) GND 7 18 GND Y3 8 17 Y7 VDD or GND TSTG Continuous Current Storage Temperature Range TJ Junction Temperature Y4 9 16 Y6 VDD 10 15 Y5 G 11 14 VDD FBOUT 12 13 FBIN Unit to GND (inputs VIH 2.5, VIL 2.5) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. TSSOP TOP VIEW CAPACITANCE Parameter CIN Description Input Capacitance Min. Typ. Max. Unit 5 pF 6 pF 30 pF VI = VDD or GND CO Output Capacitance VO = VDD or GND CL Load Capacitance NOTE: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. RECOMMENDED OPERATING CONDITIONS Symbol VDD, AVDD TA Min. Max. Unit Power Supply Voltage Description 3 3.6 V Operating Free-Air Temperature 0 +85 °C 2 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PIN DESCRIPTION Terminal Name No. Type Description CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CSP2510C clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Y (0:9) 3, 4, 5, 8, 9, O 15, 16, 17, Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control input. 20, 21 AVDD 23 Power Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VDD 2, 10, 14, 22 Power Power supply GND 6, 7, 18, 19 Ground Ground STATIC FUNCTION TABLE (AVDD = 0V) Inputs DYNAMIC FUNCTION TABLE (AVDD = 3.3V) Outputs Inputs Outputs G CLK Y (0:9) FBOUT G L L L L X L L L L H L H L running L running in H H H H H L L L L H L H H running running running H running running in running in phase with CLK phase with CLK H H H H CLK Y (0:9) FBOUT phase with CLK 3 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERATURE RANGE(1) Symbol Description Test Conditions VDD Min. VIK Input Clamp Voltage II = -18mA 3V VIH Input HIGH Level 2 VIL Input LOW Level VOH VOL II IDD HIGH Level Output Voltage LOW Level Output Voltage (2) Typ. Max. Unit – 1.2 V V V 0.8 IOH = -100µA Min. to Max. VDD – 0.2 IOH = -12mA 3V 2.1 IOH = -6mA 3V 2.4 IOL = 100µA Min. to Max. 0.2 IOL = 12mA 3V 0.8 IOL = 6mA 3V 0.55 V V Input Current VI = VDD or GND 3.6V ±5 µA Supply Current VI = VDD or GND, AVDD = GND, 3.6V 10 µA 3.3V to 3.6V 500 µA 3.6V 10 14 pF AVDD = 3.3V 10 mA IO = 0, Outputs: LOW or HIGH ∆IDD Change in Supply Current CPD Power Dissipation Capacitance (3) IDDA One input at VDD - 0.6V, other inputs at VDD or GND AVDD Power Supply Current NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. 2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 3. For IDD of AVDD, see TYPICAL CHARACTERISTICS. TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE(1) Min. Max. Unit 25 140 MHz Input clock duty cycle 40% 60% Stabilization time(2) 1 Clock frequency fCLOCK ms NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. 2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. 4 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF(1) VDD = 3.3V ± 0.3V Parameter (2) tPHASE error tPHASE error – jitter(3) tSK(o) (4) Jitter (cycle-cycle) From (Input) To (Output) Min. Typ. Max. Unit 150 ps 50 ps 150 ps 75 ps 100MHz < CLK↑ < 133MHz FBIN↑ – 150 CLK↑ = 133MHz FBIN↑ – 50 Any Y (133MHz) Any Y CLK = 133MHz Any Y or FBOUT – 75 CLK = 133MHz (peak-to-peak) Duty cycle reference (5) Any Y or FBOUT 45 tR Any Y or FBOUT 0.8 tF Any Y or FBOUT 0.8 NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION. 2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 3. Phase error does not include jitter. 4. The tSK(O) specification is only valid for equal loading of all outputs. 5. See TYPICAL CHARACTERISTICS. 5 55 % 2.1 ns 2.7 ns IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION(1) From Output Under Test 3V 50% V DD 0V Input C L =30pF (2) 500 Ω tPHASE ER ROR 2V Output or FBIN 50% V DD 0.4V tR tF CLK CLK C L = 30pF (2) F BIN CF tP HASE ERROR Y CSP2510C 500 Ω on each Y output FBOUT F BOUT Any Y t SK(o) PCB TRACE Any Y Any Y tS K(o) Phase ERROR and Skew Calculations (3,4) NOTES: 1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF≤ 1.2 ns. 2. CL includes probe and jig capacitance. 3. The outputs are measured one at a time with one transition per measurement. 4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN ≅ 6pF. 6 0.4V V OL Load Circuit and Voltage Waveforms FBIN V OH 2V IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE TYPICAL CHARACTERISTICS Phase Error vs Clock Frequency AVDD and VDD = 3.3V Ta = 25C 200 150 100 Time (ps) 50 0 25 50 66 100 133 150 -50 -100 -150 -200 Clock Frequency (MHz) Analog Supply Current vs. Clock Frequency AVDD and VDD = 3.3V Ta = 25C 16 14 Analog Current (mA) 12 10 8 6 4 2 0 25 50 66 100 Clock Frequency (MHz) 7 133 150 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE TYPICAL CHARACTERISTICS (CONT.) Output Duty Cycle vs Clock Frequency AVDD and VDD = 3.3V Ta = 25C 55 Duty Cycle (%) 53 51 49 47 45 25 50 66 100 133 150 Clock Frequency (MHz) Jitter vs Clock Frequency Avcc and Vcc = 3.3V Ta = 25C 100 90 80 70 Jitter (ps) 60 50 Peak to Peak 40 30 20 10 Cycle to Cycle 0 50 66 100 133 Clock Frequency (MHz) 8 140 150 IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE ORDERING INFORMATION IDTCSP XXXXX Device Type XX Package X Process Blank I 0°C to +85°C (standard) -40°C to +85°C (Industrial) PG PGG Thin Shrink Small Outline Package TSSOP - Green 2510C Phase-Lock Loop Clock Driver CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: [email protected] (408) 654-6459