FUNCTIONAL BLOCK DIAGRAM FEATURES Yaw rate gyro with digital range scaling ±80°/sec, ±160°/sec, and ±320°/sec settings 14-bit digital gyroscope sensor outputs 12-bit digital temperature sensor output Calibrated sensitivity and bias Extended temperature range In-system, auto-zero for bias drift calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with rate/threshold limits Embedded integration for short-term angle estimates Digitally activated self-test Digitally activated low power mode Interrupt-driven wake-up SPI®-compatible serial interface 52 Hz Sensor Bandwidth Auxiliary 12-bit ADC input and 12-bit DAC output Auxiliary digital input/output Single-supply operation: 4.75 V to 5.25 V 2000 g powered shock survivability AUX ADC AUX DAC VREF ADIS16250 TEMPERATURE SENSOR GYROSCOPE SENSOR RATE FILT SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING CS SPI PORT SCLK DIN DIGITAL CONTROL SELF-TEST VCC POWER MANAGEMENT ALARM DOUT AUXILIARY I/O COM RST DIO0 DIO1 06070-001 Preliminary Technical Data Programmable Low Power Gyroscope with Temperature Compensation ADIS16255 Figure 1. APPLICATIONS Instrumentation control Platform control and stabilization Motion control and analysis Avionics instrumentation Navigation Image stabilization Robotics GENERAL DESCRIPTION The ADIS16255 is a complete, angular rate measurement system available in a single compact package enabled by Analog Devices iSensor™ integration. By enhancing Analog Devices iMEMS® sensor technology with an embedded signal processing solution, the ADIS16255 provides factory calibrated and tunable digital sensor data in a convenient format that can be accessed using a simple SPI serial interface. The ADIS16255 provides calibration over an extended temperature range. The SPI interface provides access to measurements for the gyroscope, temperature, power supply, and one auxiliary analog input. Easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. The device range can be digitally selected from three different settings: ±80°/sec, ±160°/sec, and ±320°/sec. Unique characteristics of the end system are accommodated easily through several built-in features, including a single-command auto-zero recalibration function, as well as configurable sample rate and frequency response. Additional features can be used to further reduce system complexity, including: • • • • Configurable alarm function Auxiliary 12-bit ADC and DAC Two configurable digital I/O ports Digital self-test function. System power dissipation can be optimized via the ADIS16255 power management features, including an interrupt-driven wake-up. The ADIS16255 is available in an 11 mm × 11 mm × 5.5 mm, laminate-based land grid array (LGA) package with a temperature range of −40°C to +85°C. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADIS16255 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Temperature Sensor ......................................................................9 Applications....................................................................................... 1 Auxiliary ADC FunctIon..............................................................9 Functional Block Diagram .............................................................. 1 Basic Operation .............................................................................. 10 General Description ......................................................................... 1 Serial Peripheral Interface (SPI)............................................... 10 Specifications..................................................................................... 3 Data Output Register Access .................................................... 11 Timing Specifications .................................................................. 5 Programming and Control............................................................ 13 Absolute Maximum Ratings............................................................ 6 Control Register Overview ....................................................... 13 ESD Caution.................................................................................. 6 Control Register Access............................................................. 13 Pin Configuration and Function Descriptions............................. 7 Calibration................................................................................... 13 Recommended Layout ..................................................................... 7 Global Commands ..................................................................... 14 Typical Performance Characteristics ............................................. 8 Operational Control................................................................... 15 Theory of Operation ........................................................................ 9 Status and Diagnostics............................................................... 16 Overview........................................................................................ 9 Outline Dimensions ....................................................................... 19 Relative Angle Estimate ............................................................... 9 Ordering Guide .......................................................................... 19 REVISION HISTORY 10/06—Revision PrA: Pre-release Rev. PrA | Page 2 of 20 Preliminary Technical Data ADIS16255 SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, angular rate = 0°/sec, ±1 g, ±320°/sec range setting, unless otherwise noted. Table 1. Parameter SENSITIVITY Initial Tolerance Nonlinearity BIAS In Run Bias Stability Turn on—Turn on Bias Stability Angular Random Walk Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Output Noise Rate Noise Density FREQUENCY RESPONSE 3 dB Bandwidth Sensor Resonant Frequency Turn-on Time SELF-TEST STATE Change for positive stimulus Change for negative stimulus TEMPERATURE SENSOR Output at 25°C Scale Factor ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance Conditions Clockwise rotation is positive output 25°C, dynamic range = ±320°/sec1 25°C, dynamic range = ±160°/sec 25°C, dynamic range = ±80°/sec 25°C, dynamic range = ±320°/sec Best fit straight line Min Typ Max 0.07326 0.03663 0.01832 −1 +1 0.1 25°C, 1 σ 25°C, 1 σ 25°C, 1 σ Any axis VCC = 4.75 V to 5.25 V 0.016 0.035 3.6 0.2 1.0 Unit degrees/sec/LSB degrees/sec/LSB degrees/sec/LSB % % of FS degrees/sec degrees/sec o /√hr degrees/sec /g degrees/sec/V At 25°C, ±320°/sec dynamic range, no filtering At 25°C, ±160°/sec dynamic range, minimum four tap filter setting At 25°C, ±80°/sec dynamic range, minimum 16 tap filter setting At 25°C, f = 25 Hz, no average TBD TBD degrees/sec rms degrees/sec rms TBD degrees/sec rms 0.05 degrees/sec/√Hz rms See Analog Bandwidth section for adjustment 52 14 TBD Hz kHz ms Power on from SLEEP mode to ±2 degrees/sec of final, no averaging, minimum sample period Relative to output prior to self test Relative to output prior to self test 439 −439 721 −721 LSB LSB/°C 12 ±2 ±1 ±4 ±2 ±40 Bits LSB LSB LSB LSB V pF V mV ppm/oK 70 Ω 2.5 20 2.5 At 25°C −10 Rev. PrA | Page 3 of 20 LSB LSB 0 6.88 0 During acquisition 1092 −1092 +10 ADIS16255 DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Logic 0 Output Current (RST )2 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period3 FLASH MEMORY Endurance4 Data Retention5 CONVERSION RATE Minimum Conversion Time Maximum Conversion Time Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range VCC Power Supply Current Preliminary Technical Data 5 kΩ/100 pF to GND 12 4 1 ±5 ±0.5 0 to 2.5 2 10 For Code 101 to Code 4095 Bits LSB LSB mV % V Ω μs 2.0 For CS signal when used to wake up from SLEEP mode VIH = 3.3 V VIL = 0 V ISOURCE = 1.6 mA ISINK = 1.6 mA ±0.2 40 1 10 0.8 V V 0.55 V ±10 60 μA μA mA pF 2.4 0.5 0.4 V V 128 Sec 20,000 20 TJ = 55°C Cycles Years 3.906 7.75 256 0.129 4.75 Normal mode at 25°C Fast mode at 25°C Sleep mode at 25°C 1 5.0 15 41 500 ms Sec SPS SPS 5.25 19 48 750 V mA mA μA The sensor is capable of +600 °/sec but the specifications herein are for +320°/sec only. The RST pin has an internal pull-up 3 Guaranteed by design. 4 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 5 Retention lifetime equivalent at junction temperature (TJ) 55°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. 2 Rev. PrA | Page 4 of 20 Preliminary Technical Data ADIS16255 TIMING SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted. Table 2. Parameter fSCLK Min1 0.01 0.01 40 100 48.8 Description Fast mode2 Normal mode2 Chip select period, fast mode3 Chip select period, normal mode3 Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge tDATARATE tDATARATE tcs tDAV tDSU tDHD tDF tDR tSFS Max1 2.5 1.0 Typ Unit MHz MHz μs μs ns ns ns ns ns min ns min ns typ 100 24.4 48.8 5 5 12.5 12.5 5 1 Guaranteed by design, typical specifications are not tested or guaranteed. Based upon sample rate selection. 3 This number can be used to calculate tSTALL number in Figure 2 2 tDATA RATE tSTALL CS 06070-002 SCLK Figure 2. SPI Chip Select Timing CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV MSB DB14 DB13 tDSU DIN W/R DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) Rev. PrA | Page 5 of 20 D1 LSB 06070-003 DOUT ADIS16255 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) VCC to COM Digital Input/Output Voltage to COM Analog Inputs to COM Operating Temperature Range1 Storage Temperature Range1 1 Rating 2000 g 2000 g −0.3 V to +6.0 V −0.3 V to +5.5 V −0.3 V to +3.5 V −40°C to +125°C −65°C to +150°C Extended exposure to temperatures outside of the specified temperature range of −40°C to +85°C can adversely affect the accuracy of the factory calibration. For best accuracy, store the parts within the specified operating range of −40°C to +85°C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RATEOUT RATE AXIS +8.91 LSB LONGITUDINAL AXIS CLOCK-WISE ROTATION 10 5 6 1 –8.91 LSB LATERAL AXIS RATE IN 06070-011 Table 3. Figure 4. RATE OUT Level Increase with Clockwise Rotation Increase ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 6 of 20 Preliminary Technical Data ADIS16255 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREF COM COM VCC VCC 20 19 18 17 16 1 15 FILT 14 RATE 13 AUX ADC 12 AUX DAC DNC = DO NOT CONNECT 11 9 10 7 8 DNC ADIS16250 DOUT 2 DIN 3 CS 4 DIO0 5 TOP VIEW (Not To Scale) POSITIVE OUTPUT ROTATIONAL DIRECTION 6 DIO1 RST DNC DNC DNC 06070-004 SCLK Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5, 6 7 8, 9, 10, 11 12 13 14 15 Mnemonic SCLK DOUT DIN CS DIO0, DIO1 RST DNC AUX DAC AUX ADC RATE FILT Type1 I O I I I/O I – O I O I 16, 17 18, 19 20 VCC COM VREF S S O 1 Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select, Active Low. Multifunction Digital Input/Output Pin. Reset, Active Low. This resets the sensor signal conditioning circuit and initiates a start-up sequence. Do Not Connect. Auxiliary DAC Analog Output Voltage. Auxiliary ADC Analog Input Voltage. Analog Rate Signal Output (uncalibrated). Analog Amplifier Summing Junction. This is used for setting the analog bandwidth. See Analog Bandwidth section for more details. 5.0 V Power Supply. Common. Reference point for all circuitry in the ADIS16255. Precision Reference Output. S = supply; O = output; I = input. RECOMMENDED LAYOUT 9.673 BSC 20× 0.973 BSC 4× Figure 6. Recommended Pad Layout Rev. PrA | Page 7 of 20 07060-010 0.973 BSC 4× 1.127 BSC 20× 0.773 BSC 16× 0.500 BSC 2× ADIS16255 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Figure 10. Figure 8. Figure 11. Figure 9. Figure 12. . Rev. PrA | Page 8 of 20 Preliminary Technical Data ADIS16255 THEORY OF OPERATION OVERVIEW AUXILIARY ADC FUNCTION The core angular rate sensor integrated inside the ADIS16255 is based on Analog Devices iMEMS technology. This sensor operates on the principle of a resonator gyro. Two polysilicon sensing structures each contain a dither frame, which is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force during rotation. At two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers that are placed between fixed fingers to form a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The auxiliary ADC function integrates a standard 12-bit ADC into the ADIS16255 to digitize other system-level analog signals. The output of the ADC can be monitored through the AUX_ADC control register, as defined in Table 6. The ADC is a 12-bit successive approximation converter. The output data is presented in straight binary format with the full-scale range extending from 0 V to VREF. A high precision, low drift, factory calibrated 2.5 V reference is also provided. The calibrated gyro data (GYRO_OUT) is made available through output data registers along with temperature, power supply, auxiliary ADC, and relative angle output calculations. VDD RELATIVE ANGLE ESTIMATE D The ANGL_OUT register offers the integration of the GYRO_OUT data. In order for this information to be useful, the reference angle must be known. This can be accomplished by reading the register contents at the initial time, before starting the monitoring, or by setting its contents to zero. This number is reset to zero when the NULL command is used, after a RESET command is used, and during power-up. This function can be used to estimate change in angle over a period. The user is cautioned to fully understand the stability requirements and the time period over which to use this estimated relative angle position. TEMPERATURE SENSOR An internal temperature sensor monitors the sensor’s junction temperature. The TEMP_OUT data register provides a digital representation of this measurement. This sensor provides a convenient temperature measurement for system-level characterization and calibration feedback. C1 D R1 C2 06070-005 The base sensor output signal is sampled using an ADC, and then the digital data is fed into a proprietary digital calibration circuit. This circuit contains calibration coefficients from the factory calibration, along with user-defined calibration registers that can be used to calibrate system-level errors. Figure 13 shows the equivalent circuit of the analog input structure of the ADC. The input capacitor, C1, is typically 4 pF and can be attributed to parasitic package capacitance. The two diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward-biased and start conducting. They can handle 10 mA without causing irreversible damage. The resistor is a lumped component that represents the on resistance of the switches. The value of this resistance is typically 100 Ω. Capacitor C2 represents the ADC sampling capacitor and is typically 16 pF. Figure 13. Equivalent Analog Input Circuit Conversion Phase: Switch Open Track Phase: Switch Closed For ac applications, removing high frequency components from the analog input signal is recommended by the use of a low-pass filter on the analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. When no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. Rev. PrA | Page 9 of 20 ADIS16255 Preliminary Technical Data BASIC OPERATION The ADIS16255 is designed for simple integration into industrial system designs, requiring only a 5.0 V power supply and a 4-wire, industry standard serial peripheral interface (SPI). All outputs and user-programmable functions are handled by a simple register structure. Each register is 16 bits in length and has its own unique bit map. The 16 bits in each register consist of an upper (D8 to D15) and lower (D0 to D7) byte, each of which has its own 6-bit address. Writing to Registers SERIAL PERIPHERAL INTERFACE (SPI) Reading the contents of a register requires a modification to the sequence in Figure 14. In this case, the first two bits in the DIN sequence are 0, followed by the address of the register. Each register has two addresses (upper, lower), but either one can be used to access its entire 16 bits of data. The final 8 bits of the DIN sequence are irrelevant and can be counted as “don’t cares” during a read command. Then, during the next data frame, the DOUT sequence contains the register’s 16-bit data, as shown in Figure 15. Even though a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling. Figure 14 displays a typical data frame for writing a command to a control register. In this case, the first bit of the DIN sequence is a 1, followed by a 0, then the 6-bit address and the 8-bit data command. Because each write command covers a single byte of data, two data frames are required when writing the entire 16-bit space of a register. Reading from Registers The purpose of this section is to provide a basic description of SPI operation in the ADIS16255. Please refer to Table 2, Figure 2, and Figure 3 for detailed timing and operation of this port. The ADIS16255 SPI port includes four signals: chip select (CS), serial clock (SCLK), data input (DIN), and data output (DOUT). The CS line enables the ADIS16255 SPI port and, in effect, frames each SPI event. When this signal is high, the DOUT lines are in a high impedance state, and the signals on DIN and SCLK have no impact on operation. A complete data frame contains 16 clock cycles. Because the SPI port operates in full duplex mode, it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT) functions during the same data frame. DATA FRAME CS SCLK W/R A5 A4 A3 A2 A1 A0 REGISTER ADDRESS WRITE = 1 READ = 0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DATA FOR WRITE COMMANDS DON’T CARE FOR READ COMMANDS DC0 06070-006 DIN Figure 14. DIN Bit Sequence CS DATA FRAME DATA FRAME SCLK W/R BIT DOUT ADDRESS DON’T CARE NEXT COMMAND ZERO BASED ON PREVIOUS COMMAND 16-BIT REGISTER CONTENTS Figure 15. SPI Sequence for Read Commands Rev. PrA | Page 10 of 20 06070-007 DIN Preliminary Technical Data ADIS16255 DATA OUTPUT REGISTER ACCESS The ADIS16255 provides access to calibrated rotation measurements, relative angle estimates, power supply measurements, temperature measurements, and an auxiliary 12-bit ADC channel. This output data is continuously updating internally, regardless of user read rates. The following bit map describes the structure of all output data registers in the ADIS16255. The MSB holds the new data (ND) indicator. When the output registers are updated with new data, the ND bit goes to a 1 state. After the output data is read, it returns to a 0 state. The EA bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range. See the Status and Diagnostics section for more details. The output data is either 12 bits or 14 bits in length. For all of the 12-bit output data, the D13 bit and the D12 bit are assigned “don’t care” status. Table 5. Register Bit Map The output data register map is located in MSB LSB ND EA D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 6 and provides all of the necessary details for accessing each register’s data. Table 7 displays the output coding for the GYRO_OUT register. Figure 16 provides an example SPI read cycle for this register. Table 6. Data Output Register Information Name ENDURANCE SUPPLY_OUT GYRO_OUT AUX_ADC TEMP_OUT ANGL_OUT Function Flash Memory Write Counter Power Supply Data Gyroscope Data Auxiliary Analog Input Data Sensor Temperature Data Angle Output Address 0x01, 0x00 0×03, 0×02 0×05, 0×04 0×0B, 0×0A 0×0D, 0×0C 0×0F, 0×0E Resolution (Bits) 16 12 14 12 12 14 Data Format Binary Binary Twos Complement Binary Twos Complement Binary Scale Factor (per LSB) N/A 1.832 mV 0.07326°/sec1 0.61 mV +0.1453°C 0.03663° Table 7. Output Coding Example, GYRO_OUT2, 3 ±320°/sec Range 600°/sec 320°/sec 80°/sec 40°/sec 0.07326°/sec 0°/sec −0.07326°/sec −40°/sec −80°/sec −320°/sec −600°/sec 1 2 3 Rate of Rotation ±160°/sec Range 300°/sec 160°/sec 40°/sec 20°/sec 0.03663°/sec 0°/sec −0.03663°/sec −20°/sec −40°/sec −160°/sec −300°/sec ±80°/sec Range 150°/sec 80°/sec 20°/sec 10°/sec 0.018315°/sec 0°/sec −0.018315°/sec −10°/sec −20°/sec −80°/sec −150°/sec Assumes that the scaling is set to 320°/sec. Two MSBs have been masked off and are not considered in the coding. Nominal sensitivity and zero offset null performance are assumed. Rev. PrA | Page 11 of 20 Binary Output 01 1111 1111 1111 01 0001 0001 0001 00 0100 0100 0100 00 0010 0010 0010 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1101 1101 1110 11 1011 1011 1100 10 1110 1111 0000 10 0000 0000 0000 HEX Output 0x1FFF 0x1110 0x0444 0x0222 0x0001 0x0000 0x3FFF 0x3DDE 0x3BBC 0x2EF0 0x2000 Decimal 8191 4368 1092 546 1 0 −1 −546 −1092 −4368 −8192 ADIS16255 Preliminary Technical Data CS SCLK DIN ADDRESS = 000101 DOUT DATA = 1011 1101 1101 1110 NEW DATA, NO ALARM, GYRO_OUT = –40°/SECOND Figure 16. Example Read Cycle Rev. PrA | Page 12 of 20 07060-008 W/R BIT = 0 Preliminary Technical Data ADIS16255 PROGRAMMING AND CONTROL CONTROL REGISTER OVERVIEW CONTROL REGISTER ACCESS The ADIS16255 offers many programmable features that are controlled by writing commands to the appropriate control registers using the SPI. The following sections describe these controls and specify each function and corresponding register configuration. A list of features available for configuration in this register space follows: Table 8 displays the control register map for the ADIS16255, including address, volatile status, basic function, and accessibility (read/write). The following sections contain detailed descriptions and configurations for each of these registers. • Calibration • Global commands • Operational Control • Sample rate • Power management • Digital filtering • Dynamic range • DAC output • Digital I/O • Operational Status and Diagnostics • Self test • Status conditions • Alarms The ADIS16255 is a flash-based device with the nonvolatile functional registers implemented as flash registers. Take into account the endurance limitation of 20,000 writes when considering the system-level integration of these devices. The ENDURANCE register (see Table 30) maintains a flash memory write count, which provides a tool for keeping track of this limit. The nonvolatile column in Table 8 indicates the registers that are recovered on power-up. The user must use a manual flash update command (using the command register) to store the nonvolatile data registers once they are configured properly. When performing a manual flash update command, the user needs to ensure that the power supply remains within limits for a minimum of 50 ms after the start of the update. This ensures a successful write of the nonvolatile data. Table 8. Control Register Mapping Register Name Type Volatility GYRO_OFF GYRO_SCALE R/W R/W Nonvolatile Nonvolatile ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL R/W R/W R/W R/W R/W Nonvolatile Nonvolatile Nonvolatile Nonvolatile Nonvolatile AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS/AVG R/W R/W R/W R/W R/W SLP_CNT STATUS COMMAND 1 Volatile Volatile Nonvolatile1 Nonvolatile Nonvolatile Address 0x10 0x14 0x16 0x18 to to 0x1F 0x20 0x22 0x24 0x26 0x28 0x2A to 0x2F 0x30 0x32 0x34 0x36 0x38 Bytes 4 2 2 8 2 2 2 2 2 6 2 2 2 2 2 R/W Volatile 0x3A 2 R W Volatile N/A 0x3C 0x3E 2 2 Function Reserved Gyroscope bias offset factor Gyroscope scale factor Reserved Alarm 1 amplitude threshold Alarm 2 amplitude threshold Alarm 1 sample period Alarm 2 sample period Alarm source control register Reserved Auxiliary DAC data Auxiliary digital I/O control register Miscellaneous control register ADC sample period control Defines the dynamic range (sensitivity setting) and the number of taps for the digital filter Counter used to determine length of powerdown mode System status register System command register The contents of the upper byte are non-volatile and the contents of the lower byte are volatile Rev. PrA | Page 13 of 20 Reference Table Table 9, Table 10 Table 11, Table 12 Table 31, Table 32 Table 35, Table 36 Table 33, Table 34 Table 25, Table 26 Table 37, Table 38 Table 21, Table 22 Table 23, Table 24 Table 26, Table 27 Table 15, Table 16 Table 19, Table 20 Table 17, Table 18 Table 28, Table 29 Table 13, Table 14 ADIS16255 Preliminary Technical Data CALIBRATION GLOBAL COMMANDS The ADIS16255 is factory-calibrated for sensitivity and bias. It also provides several user calibration functions for simplifying field-level corrections. The calibration factors are stored in nonvolatile memory and are applied using the following linear calibration equation: The ADIS16255 provides global commands for common operations, such as auto null, factory calibration restore, manual FLASH update, auxiliary DAC latch, and software reset. Each of these global commands have a unique control bit assigned to them in the COMMAND register and are initiated by writing a 1 to its assigned bit. y = mx + b Where : y = Calibrated output data x = Pre - calibration data m = Sensitivity scale factor b = Offset scale factor There are three options for system-level calibrations of the bias in the ADIS16255: auto null, factory calibration restore, and manual calibration updates. The auto null and factory reset options are described in the Global Commands section. Optional field-level calibrations use the above equation and require two steps: (1) characterize the behavior of the ADIS16255 at predefined critical operating conditions, and (2) use this characterization data to calculate and load the appropriate adjustment factors into the GYRO_OFF (“b”). The GYRO_SCALE (“m”) register can also be adjusted to implement corrections in the sensitivity scale factor through the system calibration process. The GYRO_OFF provides a calibration range of ±37.5°/sec, and its contents are nonvolatile. The GYRO_SCALE register provides a calibration range of 0 to 1.9995, and its contents are nonvolatile as well. Table 9. GYRO_OFF Register Definition Scale1 0.018315°/sec Address 0x11, 0x10 1 Default 0x0000 Format Twos complement Access R/W Scale is the weight of each LSB. 1 Default2 0x0800 Format Binary Access R/W Scale is the weight of each LSB. 2 Equates to a scale factor of one.. Table 12. GYRO_SCALE Bit Designations Bit 15:12 11:0 Default N/A Format N/A Table 14. COMMAND Bit Descriptions Table 11. GYRO_SCALE Register Definition Scale1 0.0488% The DAC latch command loads the contents of AUX_DAC into the DAC latches. Since the AUX_DAC contents must be updated one byte at a time, this command ensures a stable DAC output voltage during updates. Finally, the software reset command sends the ADIS16255’s digital processor into a restart sequence, effectively doing the same thing as the RST line. Address 0x3F, 0x3E Description Not used Data bits Address 0x13, 0x12 The “factory calibration restore” command sets the contents of GYRO_OFF to 0x0000 and GYRO_SCALE to 0x0800, erasing any field-level calibration contents. The manual FLASH update writes the contents of each nonvolatile register into FLASH memory for storage. This process takes approximately 50 ms and requires the power supply voltage to be within specification for the duration of the event. It is worth noting that this operation also automatically follows the auto null and factory reset commands. Table 13. COMMAND Register Definition Table 10. GYRO_OFF Bit Designations Bit 15:12 11:0 The auto null function does two different things: it resets the contents of the ANGL_OUT register to zero and it adjusts the GYRO_OUT register to zero. This automated adjustment takes twos steps: (1) read GYRO_OUT and (2) write the opposite of this value into the GRYO_OFF register. Sensor noise influences the accuracy of this step. For optimal calibration accuracy, set the number of filtering taps to its maximum, wait for the appropriate number of samples to process through the filter, and then exercise this option. Description Not used Data bits Bit 15:8 7 6:4 3 2 1 0 Refer to AN-879 for a detailed description of calibrating the ADIS16255, and other MEMS gyroscopes. Rev. PrA | Page 14 of 20 Description Not used Software reset command Not used Manual FLASH update command Auxiliary DAC data latch Factory Calibration Restore command Auto null command Access Write only Preliminary Technical Data ADIS16255 OPERATIONAL CONTROL Internal Sample Rate The internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the SPI port. The SMPL_PRD register controls the ADIS16255 internal sample rate and has two parts: a selectable time base and a multiplier. The sample period can be calculated using the following equation: T = Time base N = Increment setting B S T = Sample period S T = T × N +1 S B S Table 17. SLP_CNT Register Definition Address 0x3B, 0x3A 1 ) Scale1 0.5sec Table 15. SMPL_PRD Register Definition Analog Bandwidth Format N/A Access R/W Description Not used Time base, 0 = 1.953 ms, 1 = 60.54 ms Multiplier fOUT = 1/(2 × π × (COUT + 0.068 μF)) ROUT = 45.22 kΩ COUT = External capacitance Here is an example calculation of the sample period for the ADIS16255. If SMPL _ PRD = 0 x 0007, Description Not used Data bits The analog bandwidth of the ADIS16255 is 52 Hz. This bandwidth can be reduced by placing an external capacitor across the RATE and FILT pins. In this case, the analog bandwidth can be calculated using the following equation: Table 16. SMPL_PRD Bit Descriptions Bit 15:8 7 6:0 Access R/W Table 18. SLP_CNT Bit Designations Bit 15:8 7:0 Default 0x0001 Format Binary Scale is the weight of each LSB. The default value is the maximum 256 samples per second, and the contents of this register are nonvolatile. Address 0x37, 0x36 Default 0x0000 Digital Filtering B 7 − B 0 = 00000111 B 7 = 0 ⇒ TB = 1.953ms B 6...B 0 = 0000111 ⇒ N S = 7 TS = TB × (N S + 1) = 1.953ms × (7 + 1) = 15.624ms f S = 1 = 64SPS TS The sample rate setting has a direct impact on the SPI data rate capability. For sample rates of 64 SPS and above, the SPI SCLK can run at a rate up to 2.5 MHz. For sample rates below 64 SPS, the SPI SCLK can run at a rate up to 1 MHz. The ADIS16255 GYRO_OUT signal path has a nominal analog bandwidth of 52 Hz. The ADIS16255 provides a Bartlett Window FIR filter for additional noise reduction on all of the output data registers. The SENS/AVG register stores the number of taps in this filter in seven, power of two-step sizes (i.e. –2M = 1, 2, 4, 16, 32, 64, and 128). Filter setup requires one simple step: write the appropriate M factor to the assigned bits in the SENS/AVG register. The bit assignments are listed in Table 20. The following equation offers a frequency response relationship for this filter. H B ( f ) = H A2 ( f ) ⇒ H A ( f ) = The sample rate setting also affects the power dissipation. When the sample rate is set below 64 SPS, the power dissipation reduces by a factor of 60%. The two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. In addition to offering two different performance modes for power optimization, the ADIS16255 offers a programmable shutdown period. Writing the appropriate sleep time to the SLP_CNT register shuts the device down for the specified time. The following example provides an illustration of this relationship: 0 N=2 N=4 –20 N = 16 –40 MAGNITUDE (dB) Power Management sin (π × N × f × t s ) N × sin (π × f × t s ) –60 N = 128 –80 –100 –120 –140 –160 0.001 B7 … B0 = 00000110 07060-009 ( After completing this sleep period, the ADIS16255 returns to normal operation. If measurements are required before sleep period completion, the ADIS16255 can be awakened by putting the CS line in a zero logic state. Otherwise, the CS line must be kept high to maintain sleep mode. 0.01 0.1 FREQUENCY (f/fs) Sleep period = 3 seconds Figure 17. Bartlett Window FIR Frequency Response Rev. PrA | Page 15 of 20 1 ADIS16255 Preliminary Technical Data Dynamic Range General Purpose I/O The ADIS16255 provides three dynamic range settings: ±80°/sec, ±160°/sec, and ±320°/sec. The lower dynamic range settings (80, 160) limit the minimum filter tap sizes in order to maintain the resolution as the maximum rate measurements decrease. The recommended order for programming the SENS/AVG register is (1) dynamic range and then (2) filtering response. The contents of the SENS/AVG register are nonvolatile. The ADIS16255 provides two general-purpose pins that enable digital I/O control using the SPI. The GPIO_CTRL control register establishes the configuration of these pins and handles the SPI-to-pin controls. Each pin provides the flexibility of both input (read) and output (write) operations. For example, writing a 0x0202 to this register establishes Line 0 as an output and set its level as a one. Writing 0x0000 to this register establishes both lines as inputs, and their status can be read through Bit 0 and Bit 1 of this register. Table 19. SENS/AVG Register Definition Address 0x39, 0x38 Default 0x0402 Format Binary Access R/W The digital I/O lines are also available for data ready and alarm/error indications. In the event of conflict, the following priority structure governs the digital I/O configuration: Table 20. SENS/AVG Bit Description Bit 15:11 10:8 Value 100 010 001 7:4 3:0 Description Not used Sensitivity selection bits 320°/sec (default condition) 160°/sec, filter taps ≥ 4 (bit 3:0 ≥ 0x02) 80°/sec, filter taps ≥16 (bit 3:0 ≥ 0x04) Not used Filter tap setting, M = binary number (number of taps, N = 2M) 1. GPIO_CTRL 2. MSC_CTRL 3. ALM_CTRL Table 23. GPIO_CTRL Register Definition Address 0x33, 0x32 Default 0x0000 Format N/A Access R/W Table 24. GPIO_CTRL Bit Descriptions Auxiliary DAC The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of this feature. It offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V. The DAC can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches ground, the linearity begins to degrade (100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC output latch function, contained in the COMMAND register, provides continuous operation while writing each byte of this register. The contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. Table 21. AUX_DAC Register Definition Address 0x31, 0x30 Default 0x0000 Format Binary Table 22. AUX_DAC Bit Descriptions Bit 15:12 11:0 Description Not used Data bits Access R/W Bit 15:10 9 8 7:2 1 0 Description Not used General purpose I/O line 0, data direction control 1 = output, 0 = input General purpose I/O line 1, data direction control 1 = output, 0 = input Not used General purpose I/O line 0 polarity 1 = high, 0 = low General purpose I/O line 1 polarity 1 = high, 0 = low STATUS AND DIAGNOSTICS The ADIS16255 provides a number of status and diagnostic functions. Table 25 provides a summary of these functions, along with their appropriate control registers. Table 25. Status and Diagnostic Functions Function Data ready I/O indicator Self test, mechanical check for MEMS sensor Status Check for predefined output conditions Flash memory endurance Alarms Configure and check for user-specific conditions Rev. PrA | Page 16 of 20 Register MSC_CTRL MSC_CTRL STATUS ENDURANCE ALM_MAG1/2 ALM_SMPL1/2 ALM_CTRL Preliminary Technical Data ADIS16255 Table 28. STATUS Register Definition Data-Ready I/O Indicator The data-ready function provides an indication of updated output data. The MSC_CTRL control register provides the opportunity to configure either of the general-purpose I/O pins (DIO0 and DIO1) as a data-ready indicator signal. Table 26. MSC_CTRL Register Definition Address 0x35, 0x34 Default 0x0000 Format N/A Access R/W Table 27. MSC_CTRL Bit Descriptions Bit 15:11 10 9 8 7:3 2 1 0 Description Not used Internal self-test enable: 1 = enabled, 0 = disabled. External negative rotation self-test enable 1 = enabled, 0 = disabled. External positive rotation self-test enable 1 = enabled, 0 = disabled. Not used Data-ready enable: 1 = enabled, 0 = disabled Data-ready polarity: 1 = active high, 0 = active low Data-ready line select:1 = DIO1, 0 = DIO0 Address 0x3D, 0x3C Default 0x0000 Format N/A Access Read only Table 29. STATUS Bit Descriptions Bit 15:10 9 8 7:6 5 4 3 2 1 0 Description Not used Alarm 2 status: 1 = active, 0 = inactive Alarm 1 status: 1 = active, 0 = inactive Not used Self-test diagnostic error flag 1 = error condition, 0 = normal operation Angular rate over range 1 = error condition, 0 = normal operation SPI communications failure 1 = error condition, 0 = normal operation Control register update failed 1 = error condition, 0 = normal operation Power supply in range above 5.25 V 1 = above 5.25 V, 0 = below 5.25V (normal) Power supply below 4.75 V 1 = below 4.75 V, 0 = above 4.75V (normal) Flash Memory Endurance Self Test The MSC_CTRL register also provides a self-test function, which verifies the MEMS sensor’s mechanical integrity. There are two different self-test options: (1) internal self-test and (2) external self-test. The internal test provides a simple, two-step process for checking the MEMS sensor: (1) start the process by writing a 1 to Bit 10 in the MSC_CTRL register and (2) check the result by reading Bit 5 of the STATUS register. The external self-test is a static condition that can be enabled and disabled. In this test, both positive and negative MEMS sensor movements are available. After writing to the appropriate control bit, the GYRO_OUT register reflects the changes after a delay that reflects the sensor signal chain response time. For example, the standard 52 Hz bandwidth reflects an exponential response with a time constant of 2 ms. The appropriate bit definitions for self-test are listed in Table 26 and Table 27. Status Conditions The STATUS register contains the following error-condition flags: Alarm conditions, self-test status, angular rate over range, SPI communication failure, control register update failure, and power supply out of range. See Table 28 and Table 29 for the appropriate register access and bit assignment for each flag. The bits assigned for checking power supply range and angular rate over range automatically reset to zero when the error condition no longer exists. The remaining error-flag bits in the STATUS register require a read in order to return them to zero. Note that a STATUS register read clears all of the bits to 0. The ENDURANCE register maintains a running count of writes to the Flash memory. Table 30. ENDURANCE Register Definition Address 0x01, 0x00 Default N/A Format Binary Access R Alarms The ADIS16255 provides two independent alarm options for event detection. Event detections occur when output register data meets the configured conditions. Configuration options are: • • • • • All output data registers are available for monitoring as the source data The source data can be filtered or unfiltered Comparisons can be static or dynamic (rate of change) The threshold levels and times are configurable Comparison can be greater than or less than The ALM_MAG1 register and ALM_MAG2 register establish the threshold level for detecting events. They take on the format of the source data and provide a bit for establishing the greater than/less than comparison direction. When making dynamic comparisons, the ALM_SMPL1 register and the ALM_SMPL2 register establish the number of averages taken for the source data as a reference for comparison. In this configuration, each subsequent source data sample is subtracted from the previous one, establishing an instantaneous delta. Rev. PrA | Page 17 of 20 ADIS16255 Preliminary Technical Data The ALM_CTRL register controls the source data selection, static/dynamic selection, filtering selection and digital I/O usage for the alarms. Rate of Change Calculation Table 37. ALM_SMPL2 Register Definition Address 0x27, 0x26 Default 0x0000 Format Binary N DS = Number of samples in ALM_SMPL1/2 Table 38. ALM_SMPL2 Bit Designations y(n) = Sampled Output Data Bit 15:8 7:0 M C = Magnitude for comparison in ALM_MAG1/2 YC = Factor to be compared with M C Description Not used Data bits N DS Table 39. ALM_CTRL Register Definition n =1 Rate of ChangeAlarm ⇒ Address 0x29, 0x28 Compare YC with M C according to ALM_MAG1/2 MSB (> or < ?) Table 40. ALM_CTRL Bit Designations YC = 1 N DS ∑ y (n + 1) −y (n) Bit 15 Table 31. ALM_MAG1 Register Definition Address 0x21, 0x20 Default 0x0000 Format N/A Access R/W 000 001 010 011 100 101 110 111 Table 32. ALM_MAG1 Bit Designations Bit 15 14 13:0 Description Comparison polarity: 1 = greater than, 0 = less than Not used Data bits: format matches source data format 11 Table 33. ALM_SMPL1 Register Definition Address 0x25, 0x24 Default 0x0000 Format Binary Access R/W 10:8 000 001 010 011 100 101 110 111 Table 34. ALM_SMPL1 Bit Designations Bit 15:8 7:0 Description Not used Data bits Table 35. ALM_MAG2 Register Definition Address 0x23, 0x22 Default 0x0000 Format N/A Access R/W Table 36. ALM_MAG2 Bit Designations Bit 15 14 13:0 Value 14:12 The ALM_MAG1 register contains the threshold level for Alarm 1. The contents of this register are nonvolatile. Description Comparison polarity: 1 = greater than, 0 = less than Not used Data bits: format matches source data format 7:5 4 3 2 1 0 Rev. PrA | Page 18 of 20 Access R/W Default 0x0000 Format N/A Access R/W Description Rate of change (ROC) enable for alarm 2 1 = rate of change, 0 = static level Alarm 2 source selection Disable Power supply output Gyroscope output Inactive Inactive Auxiliary ADC output Temperature sensor output Inactive Rate of change (ROC) enable for alarm 1 1 = rate of change, 0 = static level Alarm 1 source selection Disable Power supply output Gyroscope output Inactive Inactive Auxiliary ADC output Temperature sensor output Inactive Not used Filtered data comparison 1 = filtered data, 0 = unfiltered data Not used Alarm output enable 1 = enabled, 0 = disabled Alarm output polarity 1 = active high, 0 = active low Alarm output line select 1 = DIO1, 0 = DIO0 Preliminary Technical Data ADIS16255 OUTLINE DIMENSIONS 11.127 MAX. 16 1.200 BSC 11.00 TYP. 0.900 BSC 16 PLACES 0.373 BSC 20 PLACES 20 19 18 17 15 2 14 10.173 BSC 13 2 PLACES 12 11 6 7 8 9 1.000 BSC 20 PLACES 20 1 13 3 12 4 11 5 9 8 7 6 BOTTOM VIEW 1 5 19 2 16 4 18 14 10 3 17 15 TOP VIEW PIN 1 INDICATOR 1.000 BSC 20 PLACES PIN 1 INDICATOR 1.200 BSC 0.900 BSC 16 PLACES 0.373 BSC 20 PLACES 7.0 TYP. 5.5 MAX. 11.127 MAX. 10 LAYOUT VIEW (LOOKING THRU PART) SIDE VIEW ALL DIMENSIONS IN MM Figure 18. 20-Terminal Land Grid Array [LGA] (CC-20-5) Dimensions shown in millimeters ORDERING GUIDE Model ADIS16255ACCZ ADIS16255/PCBZ Temperature Range −40°C to +85°C Package Description 20-Terminal Land Grid Array [LGA] Evaluation Board Rev. PrA | Page 19 of 20 Package Option CC-20-5 ADIS16255 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06462-0-10/06(PrA) Preliminary Technical Data