FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch Features Description Space Saving MicroPak™ (1.6 x 2.1mm) 0.3Ω Maximum RON Flatness for +5V Supply The FSUSB11 is a high-performance, dual Single-Pole Double-Throw (SPDT) switch designed for switching USB 1.1 signals. The device features ultra-low on resistance (RON) of 1.15Ω maximum at 4.5V VCC and 4.3Ω at 2.7V supply. High bandwidth and ultra low (RON) make this switch able to pass both USB low- and fullspeed signal with minimum signal distortion. The device is fabricated with sub-micron CMOS technology to achieve fast switching speeds and designed for breakbefore-make operation. The select input is TTL-level compatible. USB 1.1 Signal Switching Compliant 3db Bandwidth: >350MHz Maximum 1.15Ω RON at 4.5V VCC and 4Ω for 2.7V Supply Broad VCC Operating Range: 1.65V to 5.5V Fast Turn-On and Turn-Off Time Break-Before-Make Enable Circuitry Over-Voltage Tolerant, TTL-Compatible Control Input Applications Cell Phones, PDAs, Digital Cameras, Notebook Computers Ordering Information Operating Part Number Temperature Range FSUSB11L10X FSUSB11MTCX -40 to +85°C -40 to +85°C Package Packing Method RoHS 10-Lead, MicroPak™, JEDEC MO255,1.6 X 2.1mm Tape and Reel RoHS 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Tape and Reel Eco Status For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Figure 1. Block Diagram MicroPak™ is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch November 2009 Figure 2. TSSOP Pin Assignment (Top View) Figure 3. Micropak™ Pin Assignment (Top View) Analog Symbol FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch Pin Configuration Figure 4. Analog Symbol Pin Descriptions TSSOP Pin # MicroPak™ Pin # Pin Names Description 1, 3, 4, 6, 9, 12 1, 3, 4, 6, 7, 9 D+, D1+, D-, D1-, D2-, D2+ Data Ports 2, 5 10 GND Ground NC No Connect 7, 8 10, 13 2, 8 S1, S2 Control Input 11, 14 5 VCC Supply Voltage Truth Table Control Inputs Function Low Logic Level D1 Connected to D+/D- High Logic Level D2 Connected to D+/D- © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 6.0 V VS Switch Voltage -0.5 VCC + 0.5 V VIN Input Voltage (1) -0.5 6.0 IIK Input Diode Current ISW Switch Current 200 mA Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) 400 mA +150 °C ISWPEAK TSTG -50 Storage Temperature Range -65 V mA TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C 8 kV ESD Human Body Model, JESD22-A114 Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC Parameter Power Supply VIN Control Input Voltage VSW Switch Input Voltage TA (2) Operating Temperature Min. Max. Unit 1.65 5.50 V 0 VCC VCC 0 VCC VCC -40 +85 °C Note: 2. Unused inputs must be held HIGH or LOW. They may not float. © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 3 Unless otherwise specified, typical values are at +25°C. Symbol Parameter Conditions TA=+25°C VCC (V) TA=-40 to +85°C Units Min. Typ. Max. Min. Max. 2.7 to 3.6 2.0 4.5 to 5.5 4.0 VIH Input Voltage High VIL Input Voltage Low IIN Control Input Leakage VIN=0V to VCC Off-Leakage Current of Port D1 and D2 A=1V, 4.5V, B0 or B1=1V, 4.5V 5.5 -50 50 -100 100 nA On-Leakage Current of Port D A=1V, 4.5V, B0 or B1=1V, 4.5V or Floating 5.5 50 50 -100 100 nA IOUT= 100mA, D1 or D2=1.5V 2.7 2.60 4.00 4.30 IOUT= 100mA, D1 or D2=3.5V 4.5 0.95 1.15 1.30 IOUT= 100mA, D1 or D2=1.5V 2.7 2.80 4.50 IOUT= 100mA, D1 or D2=3.5V 4.5 1.50 3.00 Micropak On Resistance IOUT= 100mA, Matching Between D1 or D2=3.5V (4) TSSOP Channel 4.5 INO(OFF), INO(OFF) IA(ON) 2.7 to 3.6 Switch On (3) Resistance TSSOP ΔRON RFLAT(ON) On Resistance Flatness ICC V 4.5 to 5.5 Micropak RON V (5) Quiescent Supply Current 2.7 to 3.6 µA 4.5 to 5.5 Ω 0.06 0.12 0.07 0.15 2.7 1.4 IOUT=100mA, B0 or B1=0V, 1V, 2V 4.5 0.2 0.3 0.4 3.6 0.1 0.5 1.0 5.5 0.1 0.5 1.0 VIN=0V or VCC, IOUT=0 Ω 0.30 IOUT=100mA, D1 or D2=0V, 0.75V, 1.5V FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch DC Electrical Characteristics Ω µA Notes: 3. On resistance is determined by the voltage drop between D and Dn pins at the indicated current through the switch. 4. ΔRON = RONmax - RONmin measured at identical VCC, temperature, and voltage. 5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 4 Unless otherwise specified, typical values are at +25°C. Symbol Parameter Conditions Min. D1 or D2=1.5V, RL=50Ω, CL=35pF tON tOFF tBBM 2.7 to 3.6 Max. Min. 50 35 30 D1 or D2=1.5V, RL=50Ω, CL=35pF 2.7 to 3.6 20 20 Turn-off Time S-to-Bus B 4.5 to 5.5 D1 or D2=1.5V, RL=50Ω, CL=35pF 2.7 to 3.6 CL=1.0nF, VGEN=0V, RGEN=0Ω Off Isolation f=1MHz, RL=50Ω XTALK Non-Adjacent Channel Crosstalk f=1MHz, RL=50Ω -3dB Bandwidth RL=50Ω ns Figure 5 ns Figure 5 ns Figure 6 pC Figure 8 dB Figure 7 dB Figure 7 MHz Figure 10 Units Figure ns Figure 11 ps Figure 12 ps Figure 12 15 1 Break-Before-Make Time Charge Injection Figure 60 4.5 to 5.5 D1 or D2=3.0V, RL=50Ω, CL=35pF Units Max. D1 or D2=3.0V, RL=50Ω, CL=35pF OIRR BW Typ. Turn-on Time S-to-Bus B D1 or D2=3.0V, RL=50Ω, CL=35pF Q TA=-40 to +85°C TA=+25°C VCC(V) 4.5 to 5.5 20 2.7 to 3.6 20 4.5 to 5.5 10 2.7 to 3.6 -70 4.5 to 5.5 -70 2.7 to 3.6 -75 4.5 to 5.5 -75 2.7 to 3.6 350 4.5 to 5.5 350 1 FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch AC Electrical Characteristics USB Related AC Electrical Characteristics Unless otherwise specified, typical values are at 25°C. Symbol Parameter Conditions VCC (V) tSK(O) Skew RS=39, CL=50pF, tR=tF=12ns at 12Mbps tSK(P) Rising/Fall Time Mismatch (Duty Cycle=50%) Total Jitter RS=39, CL=50pF, tR=tF=12ns at 12Mbps (PRBS=215 1) TJ TA=+25°C Min. Typ. 2.7 to 3.6 0.15 4.5 to 5.5 0.15 2.7 to 3.6 30 4.5 to 5.5 20 2.7 to 3.6 1.7 4.5 to 5.5 1.6 Max. Capacitance Symbol CIN Parameter Control Pin Input Capacitance Conditions VCC (V) f=1MHz 0.0 TA=+25°C Min. Typ. 3.5 Max. Units Figure pF Figure 9 COFF Dn Port Off Capacitance f=1MHz 4.5 12.0 pF Figure 9 CON D Port On Capacitance f=1MHz 4.5 40.0 pF Figure 9 © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 5 Note: 6. CL includes fixture and stray capacitance. Note: 7. Logic input waveforms inverted for switches that have the opposite logic sense. Figure 5. Turn On/ Turn Off Timing FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch AC Loadings and Waveforms Note: 8. CL includes fixture and stray capacitance. Figure 6. Break-Before-Make Timing Figure 7. Off Isolation and Crosstalk © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 6 FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch AC Loadings and Waveforms (Continued) Note: 9. Q=(ΔVOUT) (CL). Figure 8. Charge Injection Figure 9. On/Off Capacitance Measurement Setup Figure 10. Figure 11. Figure 12. © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 Bandwidth Skew Test Rise/Fall Time Mismatch Test www.fairchildsemi.com 7 0.10 C 2.10 2X A 1.62 B KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED (0.11) PIN1 IDENT IS 2X LONGER THAN OTHER LINES 0.56 1.12 1.60 0.10 C 2X TOP VIEW (0.35) 10X (0.25) 10X 0.50 RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C 0.05 0.00 C (0.20) 0.35 0.25 SIDE VIEW D 0.65 0.55 DETAIL A 0.35 0.25 1 4 0.35 0.25 DETAIL A 2X SCALE 0.56 10 (0.29) (0.15) (0.36) 5 6 9 0.50 0.25 9X 0.15 1.62 0.35 9X 0.25 0.10 0.05 C A B C ALL FEATURES BOTTOM VIEW Figure 13. FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch Physical Dimensions NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. 10-Lead, MicroPak™, JEDEC MO255,1.6 X 2.1mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L10X © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 0.65 0.43 TYP 1.65 6.10 0.45 12.00°TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch Physical Dimensions R0.09min Figure 14. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 9 FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch © 2005 Fairchild Semiconductor Corporation FSUSB11 • Rev. 1.0.4 www.fairchildsemi.com 10