AD ADUM5402WCRWZ-1 Quad-channel isolators with integrated dc-to-dc converter Datasheet

FUNCTIONAL BLOCK DIAGRAMS
isoPower integrated, isolated dc-to-dc converter
Qualified for automotive applications
Regulated 5 V or 3.3 V output
Up to 500 mW output power
Quad dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC package with 7.6 mm creepage
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1
VIORM = 565 V peak
OSC
VDD1 1
RECT
REG
VIA 3
VIB/VOB 4
VIC/VOC 5
16 VISO
15 GNDISO
GND1 2
14 VOA
4 CHANNEL iCOUPLER CORE
ADuM5401W/ADuM5402W/
ADuM5403W
13 VOB/VIB
12 VOC/VIC
11 VID
VOD 6
10 VSEL
RCOUT 7
GND1 8
9
GNDISO
08758-001
FEATURES
Figure 1. ADuM5401W/ADuM5402W/ADuM5403W Block Diagram
VIA
VIB
APPLICATIONS
VIC
VOD
Hybrid electric battery management
3
14
ADuM5401W
4
13
5
12
6
11
VOA
VOB
VOC
VID
08758-002
Data Sheet
Quad-Channel Isolators with
Integrated DC-to-DC Converter
ADuM5401W/ADuM5402W/ADuM5403W
Figure 2. ADuM5401W
GENERAL DESCRIPTION
isoPower uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. See the AN-0971 Application Note for board layout
recommendations.
1
VOC
VOD
3
14
ADuM5402W
4
13
5
12
6
11
VOA
VOB
VIC
VID
Figure 3. ADuM5402W
VIA
VOB
VOC
VOD
3
14
ADuM5403W
4
13
5
12
6
11
VOA
VIB
VIC
VID
08758-004
The ADuM5401W-1/ADuM5402W-1/ADuM5403W-1
versions of the isolators provide an upgraded voltage reference
to ensure proper startup under all load conditions (see the
Ordering Guide for more information).
VIA
VIB
08758-003
The ADuM5401W/ADuM5402W/ADuM5403W1 devices are
quad-channel digital isolators with isoPower®, an integrated,
isolated dc-to-dc converter. Based on the Analog Devices, Inc.,
iCoupler® technology, the dc-to-dc converter provides up to
500 mW of regulated, isolated power at 5.0 V (see Table 1).
These devices eliminate the need for a separate, isolated dc-todc converter in low power, isolated designs. The iCoupler chip
scale transformer technology is used to isolate the logic signals
and for the magnetic components of the dc-to-dc converter.
The result is a small form factor, total isolation solution.
Figure 4. ADuM5403W
Table 1. Power Levels
Input Voltage (V)
5.0
5.0
3.3
Output Voltage (V)
5.0
3.3
3.3
Output Power (mW)
500
330
200
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
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ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Truth Table .................................................................................. 14
Applications ....................................................................................... 1
Typical Performance Characteristics ........................................... 15
General Description ......................................................................... 1
Terminology .................................................................................... 18
Functional Block Diagrams ............................................................. 1
Applications Information .............................................................. 19
Revision History ............................................................................... 2
Theory of Operation .................................................................. 19
Specifications..................................................................................... 3
PCB Layout ................................................................................. 19
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 3
Thermal Analysis ....................................................................... 19
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 5
Start-Up Behavior....................................................................... 20
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 7
DC Correctness and Magnetic Field Immunity ..................... 20
Propagation Delay Related Parameters ................................... 20
EMI Considerations ................................................................... 20
Package Characteristics ............................................................... 9
Power Consumption .................................................................. 21
Regulatory Approvals................................................................... 9
Power Considerations ................................................................ 22
Insulation and Safety-Related Specifications ............................ 9
Insulation Lifetime ..................................................................... 22
DIN EN 69747-5-2 (VDE 0884 Teil 2) Insulation
Characteristics ............................................................................ 10
VISO Start-Up Issues .................................................................... 23
Outline Dimensions ....................................................................... 24
Recommended Operating Conditions .................................... 10
Ordering Guide .......................................................................... 24
Absolute Maximum Ratings.......................................................... 11
Automotive Products ................................................................. 24
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
REVISION HISTORY
4/13—Rev. C to Rev. D
Added Figure 17 and Figure 18; Renumbered Sequentially ..... 16
Added Start-Up Behavior Section ................................................ 20
Change to DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 20
Changes to Ordering Guide .......................................................... 24
11/12—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 23
6/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Added Table 1; Renumbered Sequentially .................................... 1
Changes to Table 2, Table 3, and Table 4 ....................................... 3
Changes to Endnote 3 in Table 5 .................................................... 4
Change to Table 6 ............................................................................. 5
Changes to Table 9 ............................................................................ 6
Change to Table 10 ........................................................................... 7
Changes to Table 13 .......................................................................... 8
Change to Table 16 ........................................................................... 9
Change to Table 18 ......................................................................... 10
Changes to Table 21 ........................................................................ 12
Changes to Table 22 ........................................................................ 13
Changes to Table 23 and Table 24 ................................................ 14
Changes to Theory of Operation Section.................................... 18
Changes to EMI Considerations Section .................................... 19
4/12—Rev. 0 to Rev. A
Changes to General Description and Features Sections ..............1
Changed DIN V VDE 0884-10 (VDE V 0884-10):2006-12 to
DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1 Throughout ........1
Added Electrical Characteristics—3.3 V Primary Input
Supply/3.3 V Secondary Isolated Supply Section ..........................5
Added Table 5, Table 6, and Table 7; Renumbered
Sequentially ........................................................................................5
Added Table 8 ....................................................................................6
Added Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply Section .......................................7
Added Table 9, Table 10, and Table 11............................................7
Added Table 12 ..................................................................................8
Changes to Table 14 and Table 15 ...................................................9
Changes to Table 16 ....................................................................... 10
Changes to Typical Performance Characteristics Section ........ 16
Changes to VISO Start-Up Issues Section ..................................... 23
Changes to Ordering Guide .......................................................... 24
Added Automotive Products Section .......................................... 24
1/10—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range, which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
4.7
5.0
1
1
75
200
180
625
5.4
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
Unit
Test Conditions/Comments
68
71
75
mA
mA
mA
No VISO load
No VISO load
No VISO load
87
85
83
mA
mA
mA
5
100
34
20
290
IDD1 (Q)
IDD1 (MAX)
35
VISO > 4.5 V
IISO = 100 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401W
ADuM5402W
ADuM5403W
Available to Load
ADuM5401W
ADuM5402W
ADuM5403W
Symbol
25 Mbps—C Grade
Min Typ Max
IDD1
IISO (LOAD)
Table 4. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
Typ
Max
Unit
Test Conditions/Comments
45
25
60
6
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
15
Mbps
ns
ns
ps/°C
ns
ns
6
15
ns
ns
5
PW
tPSK
tPSKCD
tPSKOD
40
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
1
Rev. D | Page 3 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
Table 5. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold 1
Logic Low Input Threshold1
Symbol
Min
VIH
VIL
0.7 × VISO or 0.7 × VDD1
Logic High Output Voltages 2
VOH
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
Logic Low Output Voltages2
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents Per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 3
Refresh Rate
Typ
Max
0.3 × VISO or
0.3 × VDD1
5.0
4.8
0.0
0.2
Unit
V
V
0.1
0.4
V
V
V
V
+20
V
V
V
µA
UVLO
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/µs
1.0
Mbps
fr
Test Conditions/Comments
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
0 V ≤ VIx ≤ VDD1 or VISO
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VSEL is a nonstandard input that has a logic threshold of approximately 0.9 V.
RCOUT is a nonstandard output intended to interface with other isoPower parts. It is not recommended for standard digital loads.
3
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. D | Page 4 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range, which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 54 mA
CBO = 0.1 µF||10 µF, IISO = 54 mA
Unit
Test Conditions/Comments
44
46
47
mA
mA
mA
No VISO load
No VISO load
No VISO load
52
51
49
mA
mA
mA
5
60
33
14
175
IDD1 (Q)
IDD1 (MAX)
22
VISO > 3 V
IISO = 60 mA
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401W
ADuM5402W
ADuM5403W
Available to Load
ADuM5401W
ADuM5402W
ADuM5403W
Symbol
25 Mbps—C Grade
Min
Typ
Max
IDD1
IISO (LOAD)
Table 8. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
Typ
Max
Unit
Test Conditions/Comments
45
25
60
6
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
45
Mbps
ns
ns
ps/°C
ns
ns
6
15
ns
ns
5
PW
tPSK
tPSKCD
tPSKOD
40
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
1
Rev. D | Page 5 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
Table 9. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold 1
Logic Low Input Threshold1
Symbol
Min
VIH
VIL
0.7 × VISO or 0.7 × VDD1
Logic High Output Voltages 2
VOH
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
Logic Low Output Voltages2
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 3
Refresh Rate
Typ
Max
0.3 × VISO or
0.3 × VDD1
3.3
3.1
0.0
0.0
Unit
V
V
0.1
0.4
V
V
V
V
+10
V
V
V
µA
UVLO
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/µs
1.0
Mbps
fr
Test Conditions/Comments
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
0 V ≤ VIx ≤ VDD1 or VISO
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VSEL is a nonstandard input that has a logic threshold of approximately 0.9 V.
RCOUT is a nonstandard output intended to interface with other isoPower parts. It is not recommended for standard digital loads.
3
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. D | Page 6 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the
entire recommended operation range, which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise
noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
3.0
3.3
1
1
50
3.6
V
mV/V
%
mV p-p
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF,
IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
5
130
180
625
100
30
14
230
IDD1 (Q)
IDD1 (MAX)
22
mV p-p
MHz
kHz
mA
%
mA
mA
VISO > 3 V
IISO = 90 mA
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401W
ADuM5402W
ADuM5403W
Available to Load
ADuM5401W
ADuM5402W
ADuM5403W
Symbol
Min
25 Mbps—C Grade
Typ
Max
Unit
Test Conditions/Comments
44
45
46
mA
mA
mA
No VISO load
No VISO load
No VISO load
92
91
89
mA
mA
mA
IDD1
IISO (LOAD)
Table 12. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
Typ
Max
Unit
Test Conditions/Comments
45
25
60
6
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
15
Mbps
ns
ns
ps/°C
ns
ns
6
15
ns
ns
5
PW
tPSK
tPSKCD
tPSKOD
40
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
1
Rev. D | Page 7 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
Table 13. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold 1
Symbol
Min
VIH
0.7 × VISO or
0.7 × VDD1
Logic Low Input Threshold1
VIL
Logic High Output Voltages 2
VOH
Logic Low Output Voltages2
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 3
Refresh Rate
Typ
Max
VOL
V
VDD1 or VISO
V
IOx = −20 µA, VIx = VIxH
VDD1 − 0.2 or
VISO − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
+10
V
V
V
µA
UVLO
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/µs
1.0
Mbps
fr
Test Conditions/Comments
V
0.3 × VISO or
0.3 × VDD1
VDD1 − 0.2 or
VISO − 0.2
VDD1 − 0.5 or
VISO − 0.5
Unit
0 V ≤ VIx ≤ VDD1 or VISO
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VSEL is a nonstandard input that has a logic threshold of approximately 0.9 V.
RCOUT is a nonstandard output intended to interface with other isoPower parts. It is not recommended for standard digital loads.
3
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. D | Page 8 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
PACKAGE CHARACTERISTICS
Table 14. Thermal and Isolation Characteristics
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.2
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3
The device is considered a 2-terminal device; Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
1
2
REGULATORY APPROVALS
Table 15.
UL 1
Recognized under 1577 component
recognition program1
Single protection, 2500 V rms
isolation voltage
File E214100
CSA
Approved under CSA Component
Acceptance Notice #5A
Basic insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File 205078
VDE 2
Certified according to DIN EN 69747-5-2
(VDE 0884 Teil 2):2003-1
Reinforced insulation, 565 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM5401W/ADuM5402W/ADuM5403W is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current
leakage detection limit = 10 µA).
2
In accordance with DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1, each ADuM5401W/ADuM5402W/ADuM5403W is proof tested by applying an insulation test voltage ≥
1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1
approval.
1
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
2500
>8.0
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
7.6
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>175
IIIa
mm
V
Rev. D | Page 9 of 24
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals
in the seating plane of the PCB, shortest distance
through air
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
DIN EN 69747-5-2 (VDE 0884 TEIL 2) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking on packages denotes DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1 approval.
Table 17. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
565
1059
V peak
V peak
904
678
V peak
V peak
VTR
4000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 5)
Case Temperature
Side 1 IDD1 Current
Insulation Resistance at TS
VIO = 500 V
500
400
300
200
100
0
08758-005
SAFE OPERATING VDD1 CURRENT (mA)
600
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter
Operating Temperature 1
Supply Voltages 2
1
2
Symbol
TA
VDD1
Min
−40
3.0
Operation at 105°C requires reduction of the maximum load current, as specified in Table 19.
Each voltage is relative to its respective ground.
Rev. D | Page 10 of 24
Max
+105
5.5
Unit
°C
V
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 20. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Table 19.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages (VDD1, VISO)1
VISO Supply Current2
TA = −40°C to +85°C
TA = −40°C to +105°C
Input Voltage (VIA, VIB, VIC, VID)1, 3
Output Voltage (RCOUT, VOA, VOB,
VOC, VOD)1, 3
Average Output Current Per Data
Output Pin4
Maximum Cumulative AC HiPot
Maximum Cumulative DC HiPot
Common-Mode Transients5
Rating
−55°C to +150°C
−40°C to +105°C
Parameter
AC Voltage
Bipolar Waveform
Unit
424
V peak
Basic Insulation
560
V peak
Unipolar Waveform
Basic Insulation
560
V peak
Working voltage
per IEC 60950-1
560
V peak
Working voltage
per IEC 60950-1
−0.5 V to +7.0 V
100 mA
60 mA
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
DC Voltage
Basic Insulation
−10 mA to +10 mA
5 min at 2500 V rms
5 min at 3500 VDC
−100 kV/µs to +100 kV/µs
All voltages are relative to their respective grounds.
VISO provides current for dc and dynamic loads on the VISO I/O channels. This
current must be included when determining the total VISO supply current. For
ambient temperatures from 85°C to 105°C, the maximum allowed current is
reduced.
3
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
4
See Figure 5 for the maximum rated current values for various temperatures.
5
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
1
1
Applicable
Certification
Max
All certifications,
50-year operation
Working voltage
per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 11 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIC 5
ADuM5401W
13 VOB
TOP VIEW
(Not to Scale) 12 VOC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
08758-006
VIB 4
Figure 6. ADuM5401W Pin Configuration
Table 21. ADuM5401W Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
6
7
VIA
VIB
VIC
VOD
RCOUT
9, 15
GNDISO
10
11
12
13
14
16
VSEL
VID
VOC
VOB
VOA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it
is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5401W
to control the regulation of the slave device.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
Rev. D | Page 12 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VOC 5
ADuM5402W
13 VOB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
08758-007
VIB 4
Figure 7. ADuM5402W Pin Configuration
Table 22. ADuM5402W Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
6
7
VIA
VIB
VOC
VOD
RCOUT
9, 15
GNDISO
10
11
12
13
14
16
VSEL
VID
VIC
VOB
VOA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it
is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5402W
to control the regulation of the slave device.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
Rev. D | Page 13 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VOC 5
ADuM5403W
13 VIB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
08758-008
VOB 4
Figure 8. ADuM5403W Pin Configuration
Table 23. ADuM5403W Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
6
7
VIA
VOB
VOC
VOD
RCOUT
9, 15
GNDISO
10
11
12
13
14
16
VSEL
VID
VIC
VIB
VOA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it
is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Output B.
Logic Output C.
Logic Output D.
Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5403W
to control the regulation of the slave device.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
Logic Input D.
Logic Input C.
Logic Input B.
Logic Output A.
Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
TRUTH TABLE
Table 24. Truth Table (Positive Logic)
VSEL
High
Low
Low
High
1
RCOUT 1
PWM
PWM
PWM
PWM
VDD1 (V)
5
5
3.3
3.3
VISO (V)
5
3.3
3.3
5
Notes
Master mode, normal operation
Master mode, normal operation
Master mode, normal operation
This supply configuration is not recommended due to extremely poor efficiency
PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices.
Rev. D | Page 14 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
4.0
40
4.0
35
3.5
30
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
25
20
15
1.0
1.0
10
0.02
0.04
0.06
0.08
OUTPUT CURRENT (A)
0.10
0.12
0.5
0.5
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
6.5
08758-012
0
IDD1
08758-009
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
5
0
3.5
POWER
INPUT SUPPLY VOLTAGE (V)
Figure 9. Typical Power Supply Efficiency at 5 V Input/5 V Output
and 3.3 V Input/3.3 V Output
Figure 12. Typical Short-Circuit Input Current and Power
vs. VDD1 Supply Voltage
OUTPUT VOLTAGE
(500mV/DIV)
1.0
0.9
0.7
0.6
0.5
90% LOAD
10% LOAD
0.4
0.3
0.2
0
0
0.02
0.04
0.06
IISO (A)
0.08
0.10
0.12
(100µs/DIV)
08758-010
VDD1 = 5V, V ISO = 5V
VDD1 = 5V, V ISO = 3.3V
VDD1 = 3.3V, V ISO = 3.3V
08758-013
DYNAMIC LOAD
POWER DISSIPATION (W)
0.8
0.1
Figure 10. Typical Total Power Dissipation vs. Isolated Output Supply Current
in All Supported Power Configurations
Figure 13. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
OUTPUT VOLTAGE
(500mV/DIV)
0.12
0.08
0.04
0
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0
0.05
0.10
0.15
0.20
INPUT CURRENT (A)
0.25
0.30
0.35
10% LOAD
90% LOAD
08758-014
DYNAMIC LOAD
0.06
08758-011
OUTPUT CURRENT (A)
0.10
0.02
POWER (W)
INPUT CURRENT (A)
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
(100µs/DIV)
Figure 14. Typical VISO Transient Load Response, 3.3 V Output,
10% to 90% Load Step
Figure 11. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
Rev. D | Page 15 of 24
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
5V OUTPUT RIPPLE (10mV/DIV)
5
VISO (V)
4
10% LOAD
3
90% LOAD
2
0
–1.0
BW = 20MHz (400ns/DIV)
–0.5
0
0.5
1.0
1.5
TIME (ms)
2.0
2.5
3.0
08758-031
08758-015
1
Figure 18. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V
Figure 15. Typical VISO = 5 V Output Voltage Ripple at 90% Load
20
DATA RATE (Mbps)
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
SUPPLY CURRENT (mA)
3.3V OUTPUT RIPPLE (10mV/DIV)
16
12
8
BW = 20MHz (400ns/DIV)
0
Figure 16. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
0
5
10
15
DATA RATE (Mbps)
20
25
08758-017
08758-016
4
Figure 19. Typical ICH Supply Current per Forward Data Channel
(15 pF Output Load)
7
20
10% LOAD
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
6
SUPPLY CURRENT (mA)
16
4
90% LOAD
3
2
12
8
4
0
–1
0
1
TIME (ms)
2
3
0
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 20. Typical ICH Supply Current per Reverse Data Channel
(15 pF Output Load)
Figure 17. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 5 V
Rev. D | Page 16 of 24
08758-120
1
08758-030
VISO (V)
5
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
3.0
5
2.5
SUPPLY CURRENT (mA)
3
5V
2
2.0
1.5
5V
1.0
3.3V
3.3V
1
0
0
0
5
10
15
20
DATA RATE (Mbps)
25
Figure 21. Typical IISO (D) Dynamic Supply Current per Input
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 22. Typical IISO (D) Dynamic Supply Current per Output
(15 pF Output Load)
Rev. D | Page 17 of 24
08758-122
0.5
08758-121
SUPPLY CURRENT (mA)
4
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
TERMINOLOGY
IDD1 (Q)
IDD1 (Q) is the minimum operating current drawn at the VDD1 pin
when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current. IDD1 (Q) reflects the minimum current operating condition.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
IISO (LOAD)
IISO (LOAD) is the current available to an external VISO load.
tPHL Propagation Delay
tPHL propagation delay is measured from the 50% level of the
falling edge of the VIx signal to the 50% level of the falling edge
of the VOx signal.
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the rising
edge of the VIx signal to the 50% level of the rising edge of the
VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
Channel-to-Channel Matching (tPSKCD/tPSKOD)
Channel-to-channel matching is the absolute value of the difference
in propagation delays between the two channels when operated
with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. D | Page 18 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5401W/
ADuM5402W/ADuM5403W works on principles that are
common to most modern power supplies. It is a secondary side
controller architecture with isolated pulse-width modulation
(PWM) feedback. VDD1 power is supplied to an oscillating circuit
that switches current into a chip scale air core transformer.
Power transferred to the secondary side is rectified and regulated
to either 3.3 V or 5 V. The secondary (VISO) side controller
regulates the output by creating a PWM control signal that is
sent to the primary (VDD1) side by a dedicated iCoupler data
channel. The PWM modulates the oscillator circuit to control
the power being sent to the secondary side. Feedback allows for
significantly higher power and efficiency.
The ADuM5401W/ADuM5402W/ADuM5403W implement
undervoltage lockout (UVLO) with hysteresis on the VDD1 power
input. This feature ensures that the converter does not enter
oscillation due to noisy input power or slow power-on ramp rates.
In the original ADuM540xW devices, a minimum load current
of 10 mA is recommended to ensure optimum load regulation.
Smaller loads can generate excess noise on chip due to short or
erratic PWM pulses. Excess noise generated in this way can cause
data corruption in some circumstances. This requirement has
been removed in the newer ADuM540xW-1 devices, which are
recommended for new designs.
PCB LAYOUT
The ADuM5401W/ADuM5402W/ADuM5403W digital isolators
with 0.5 W isoPower integrated dc-to-dc converters require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 23). Note that a low ESR bypass capacitor is required
between Pin 1 and Pin 2 as well as between Pin 15 and Pin 16,
as close to the chip pads as possible.
The power supply section of the ADuM5401W/ADuM5402W/
ADuM5403W uses a 180 MHz oscillator frequency to efficiently
pass power through its chip scale transformers. In addition,
normal operation of the data section of the iCoupler introduces
switching transients on the power supply pins. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor; ripple
suppression and proper regulation require a large value capacitor.
These are most conveniently connected between Pin 1 and Pin 2
for VDD1 and between Pin 15 and Pin 16 for VISO. To suppress
noise and reduce ripple, a parallel combination of at least two
capacitors is required. The recommended capacitor values are
0.1 µF and 10 µF for VDD1 and VISO. A 10 nF capacitor should
be used for optimum EMI emissions performance. The smaller
capacitors must have a low ESR; for example, use of an NPO
ceramic capacitor is advised.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. A bypass between Pin 1
and Pin 8 and between Pin 9 and Pin 16 should also be considered
unless both common ground pins are connected together close
to the package.
BYPASS < 2mm
VDD1
GND1
VIA
VISO
GNDISO
VOA
VIB/VOB
VOB/VIB
VIC/VOC
VOC/VIC
VOD
RCOUT
GND1
VID
VSEL
GNDISO
08758-020
THEORY OF OPERATION
Figure 23. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between pins,
exceeding the absolute maximum ratings specified in Table 19,
thereby leading to latch-up and/or permanent damage.
The ADuM5401W/ADuM5402W/ADuM5403W are power
devices that dissipate about 1 W of power when fully loaded and
running at maximum speed. Because it is not possible to apply a
heat sink to an isolation device, the devices primarily depend
on heat dissipation into the PCB through the ground pins. If the
devices are used at high ambient temperatures, provide a thermal
path from the ground pins to the PCB ground plane. The board
layout in Figure 23 shows enlarged pads for Pin 8 and Pin 9. Large
diameter vias should be implemented from the pad to the ground,
and power planes should be used to reduce inductance. Multiple
vias in the thermal pads can significantly reduce temperatures
inside the chip. The dimensions of the expanded pads are left to
the discretion of the designer and the available board space.
THERMAL ANALYSIS
The ADuM5401W/ADuM5402W/ADuM5403W parts consist
of four internal die attached to a split lead frame with two die
attach paddles. For the purposes of thermal analysis, the die is
treated as a thermal unit, with the highest junction temperature
reflected in the θJA value from Table 14. The value of θJA is based
on measurements taken with the parts mounted on a JEDEC
standard, 4-layer board with fine width traces and still air. Under
normal operating conditions, the ADuM5401W/ADuM5402W/
ADuM5403W devices operate at full load across the full temperature range without derating the output current. However,
following the recommendations in the PCB Layout section
decreases thermal resistance to the PCB, allowing increased
thermal margins in high ambient temperatures.
Rev. D | Page 19 of 24
ADuM5401W/ADuM5402W/ADuM5403W
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 24).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
08758-021
tPLH
50%
Figure 24. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5401W/ADuM5402W/ADuM5403W component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5401W/
ADuM5402W/ADuM5403W components operating under
the same conditions.
Data Sheet
As a result, the ADuM5401W/ADuM5402W/ADuM5403W
devices can draw large amounts of current at low voltage for
extended periods of time.
The output voltage of the ADuM5401W/ADuM5402W/
ADuM5403W devices exhibits VISO overshoot during startup.
If this overshoot could potentially damage components attached
to VISO, a voltage-limiting device such as a Zener diode can be
used to clamp the voltage. Typical behavior is shown in Figure 17
and Figure 18.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5401W/ADuM5402W/
ADuM5403W components must, of necessity, operate at a very
high frequency to allow efficient power transfer through the small
transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge and dipole radiation. Grounded enclosures are recommended for applications that use these devices. If grounded
enclosures are not possible, follow good RF design practices in
the layout of the PCB. See the AN-0971 Application Note for
board layout recommendations.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
START-UP BEHAVIOR
The ADuM5401W/ADuM5402W/ADuM5403W do not
contain a soft start circuit. Therefore, the start-up current and
voltage behavior must be taken into account when designing
with these devices.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the VDD1 slew rate.
With a fast VDD1 slew rate (200 μs or less), the peak current draws
up to 100 mA/V of VDD1. The input voltage goes high faster than
the output can turn on; therefore, the peak current is proportional to the maximum input voltage.
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM5401W/ADuM5402W/ADuM5403W devices may
not be able to drive the output to the regulation point if a
current-limiting device clamps the VDD1 voltage during startup.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 μs, periodic sets of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 μs, the input side
is assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default low state by the watchdog
timer circuit. This situation should occur only during power-up
and power-down operations.
The limitation on the magnetic field immunity of the
ADuM5401W/ADuM5402W/ADuM5403W is set by the
condition in which induced voltage in the receiving coil of the
transformer is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM5401W/
ADuM5402W/ADuM5403W, and an imposed requirement that
Rev. D | Page 20 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
the induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 25.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
POWER CONSUMPTION
10
1
0.1
08758-022
0.01
0.001
1k
Note that, in combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
1M
10k
100k
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
The VDD1 power supply input provides power to the iCoupler data
channels, as well as to the power converter. For this reason, the
quiescent currents drawn by the power converter and the primary
and secondary I/O channels cannot be determined separately.
All of these quiescent power demands have been combined into
the IDD1 (Q) current, as shown in Figure 27. The total IDD1 supply
current is equal to the sum of the quiescent operating current;
the dynamic current, IDD1 (D), demanded by the I/O channels;
and any external IISO load.
IDD1(Q)
Figure 25. Maximum Allowable External Magnetic Flux Density
IDD1(D)
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of
0.25 V at the receiving coil. This voltage is approximately 50% of
the sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5401W/
ADuM5402W/ADuM5403W transformers. Figure 26 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown in Figure 26, the ADuM5401W/
ADuM5402W/ADuM5403W are extremely immune and can be
affected only by extremely large currents operated at high frequency
very close to the component. For the 1 MHz example, a 0.5 kA
current placed 5 mm away from the ADuM5401W/ADuM5402W/
ADuM5403W is required to affect component operation.
IDDP(D)
DISTANCE = 100mm
DISTANCE = 5mm
0.1
0.01
100k
SECONDARY
DATA
INPUT/OUTPUT
4-CHANNEL
Figure 27. Power Consumption Within the
ADuM5401W/ADuM5402W/ADuM5403W
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of fr. The dynamic current
of each channel is determined by its data rate. Figure 19 shows the
current for a channel in the forward direction, meaning that the
input is on the VDD1 side of the part; Figure 20 shows the current
for a channel in the reverse direction, meaning that the input is on
the VISO side of the part. Both figures assume a typical 15 pF load.
The following relationship allows the total IDD1 current to be
calculated:
(1)
where:
IDD1 is the total supply input current.
ICHn is the current drawn by a single channel determined from
Figure 19 or Figure 20, depending on channel direction.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at 100 mA load from Figure 9 at
the VISO and VDD1 condition of interest.
1
10k
IISO(D)
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4
10
1k
CONVERTER
SECONDARY
08758-024
PRIMARY
DATA
INPUT/OUTPUT
4-CHANNEL
DISTANCE = 1m
100
08758-023
MAXIMUM ALLOWABLE CURRENT (kA)
1k
IISO
CONVERTER
PRIMARY
1M
10M
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 26. Maximum Allowable Current for Various
Current-to-ADuM5401W/ADuM5402W/ADuM5403W Spacings
(2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
Rev. D | Page 21 of 24
ADuM5401W/ADuM5402W/ADuM5403W
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 21 and Figure 22.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
The ADuM5401W/ADuM5402W/ADuM5403W power input,
data input channels on the primary side, and data channels on
the secondary side are all protected from premature operation
by UVLO circuitry. Below the minimum operating voltage, the
power converter holds its oscillator inactive and all input channel
drivers and refresh circuits are idle. Outputs remain in a high
impedance state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because
no data comes from the secondary side inputs until secondary
power is established.
The primary side oscillator also begins to operate, transferring
power to the secondary power circuits. The secondary VISO
voltage is below its UVLO limit at this point; the regulation
control signal from the secondary is not being generated. The
primary side power oscillator is allowed to free run in this
circumstance, supplying the maximum amount of power to the
secondary side, until the secondary voltage rises to its regulation
setpoint. This creates a large inrush current transient at VDD1.
When the regulation point is reached, the regulation control
circuit produces the regulation control signal that modulates
the oscillator on the primary side. The VDD1 current is reduced
and is then proportional to the load current. The inrush current
is less than the short-circuit current shown in Figure 12. The
duration of the inrush current depends on the VISO loading
conditions and the current available at the VDD1 pin.
As the secondary side converter begins to accept power from
the primary, the VISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the corresponding primary side input. It can take up to 1 µs after the secondary
side is initialized for the state of the output to correlate with the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 µs after the secondary
side becomes active.
Data Sheet
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care with the design to allow the
converter sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge. The
outputs on the secondary side hold the last state that they received
from the primary side. Either the UVLO level is reached and the
outputs are placed in their high impedance state, or the outputs
detect a lack of activity from the primary side inputs and the
outputs are set to their default low value before the secondary
power reaches UVLO.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM5401W/ADuM5402W/
ADuM5403W.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest.
The values shown in Table 20 summarize the peak voltages for
50 years of service life in several operating conditions. In many
cases, the working voltage approved by agency testing is higher
than the 50-year service life voltage. Operation at working
voltages higher than the service life voltage listed leads to
premature insulation failure.
The insulation lifetime of the ADuM5401W/ADuM5402W/
ADuM5403W depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates, depending on whether the waveform is
bipolar ac, unipolar ac, or dc. Figure 28, Figure 29, and Figure 30
illustrate these different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines the
maximum working voltage recommended by Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms to
either the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 29 or Figure 30
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 20.
Rev. D | Page 22 of 24
Data Sheet
ADuM5401W/ADuM5402W/ADuM5403W
Symptom
08758-025
RATED PEAK VOLTAGE
The VISO output voltage restarts to an incorrect voltage between
3.4 V and 4.7 V when power is removed at VDD1 and then reapplied
between 250 ms and 3 sec later. The error occurs only on restart; it
does not occur at initial power-up. If the part initializes incorrectly,
power must be removed for an extended time to allow internal
nodes to discharge and reset. The amount of time required can
be several minutes at low temperature; therefore, it is critical to
avoid allowing the device to initialize improperly.
Figure 28. Bipolar AC Waveform
08758-026
RATED PEAK VOLTAGE
Figure 29. DC Waveform
Cause
The secondary side band gap reference does not initialize to the
proper voltage due to a slow slew rate on VISO after the internal
nodes are precharged during the previous power cycle. The
secondary side band gap sets the output voltage of the regulator.
RATED PEAK VOLTAGE
0V
Solution
08758-027
NOTES
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE
VOLTAGE CANNOT CROSS 0V.
Figure 30. Unipolar AC Waveform
VISO START-UP ISSUES
An issue with reliable startup was identified in the ADuM5401W/
ADuM5402W/ADuM5403W components. This issue has been
addressed in the ADuM5401W-1/ADuM5402W-1/ADuM5403W1 for the current silicon. The ADuM5401W-1/ADuM5402W-1/
ADuM5403W-1 devices are recommended for all new designs.
The following description applies only to the original released
version of these devices. Production of the original release of
the devices is being continued for existing customers, but it is
not recommended for new designs.
The slew rate of VISO is determined by the resistive and capacitive
load present on the output. Designs that attempt to reduce ripple
by adding capacitance to the VISO output can slow the slew rate
enough to cause start-up errors. Choose values for bulk capacitance
based on the effective dc load. Calculate the dc load as the resistive
equivalent to the current drawn from the VISO line. Determine
the range of allowable capacitance for the VISO output from
Figure 31. Choose the bulk capacitance for VISO to achieve the
application required ripple, unless the value is in the disallowed
combinations area; then the value must be reduced to avoid
restart issues.
The start-up issue in the original release of the ADuM5401W/
ADuM5402W/ADuM5403W is related to initialization of the
band gap voltage references on the primary (power input) and
secondary (power output) sides of the isoPower device and are
being addressed in future revisions of the silicon. For current
versions of the silicon, the user must follow these design guidelines to guarantee proper operation of the device.
The band gap voltage references are vulnerable to slow power-up
slew rate. The susceptibility to power-up errors is process sensitive;
therefore, not all devices display these behaviors. These recommendations should be implemented for all designs until the corrections
are made to the silicon. The symptoms and corrective actions
required for issues with the primary and secondary side startup
are different.
Rev. D | Page 23 of 24
100k
10k
DISALLOWED
COMBINATIONS
1k
100
10
08758-028
0V
RVISO (Ω)
0V
1
1
10
100
CVISO (µF)
Figure 31. Maximum Capacitive Load for Proper Restart
1k
ADuM5401W/ADuM5402W/ADuM5403W
Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Figure 32. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1, 2, 3
ADuM5401WCRWZ-1
ADuM5402WCRWZ-1
ADuM5403WCRWZ-1
ADuM5401WCRWZ
ADuM5402WCRWZ
ADuM5403WCRWZ
Notes
4
4
4
Number
of Inputs,
VDD1 Side
3
2
1
3
2
1
Number
of Inputs,
VISO Side
1
2
3
1
2
3
Maximum
Data Rate
(Mbps)
25
25
25
25
25
25
Maximum
Propagation
Delay, 5 V (ns)
60
60
60
60
60
60
Maximum
Pulse Width
Distortion (ns)
6
6
6
6
6
6
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Package
Option
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.
4
This device is not recommended for new designs.
1
2
3
AUTOMOTIVE PRODUCTS
The ADuM5401W/ADuM5402W/ADuM5403W models are available with controlled manufacturing to support the quality and
reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the
commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade
products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific
product ordering information and to obtain the specific Automotive Reliability reports for these models.
©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08758-0-4/13(D)
Rev. D | Page 24 of 24