HANBit HMD16M32M8G 64Mbyte(16Mx32) 72-pin FP Mode 4K Ref. SIMM Design 5V Part No. HMD16M32M8G GENERAL DESCRIPTION The HMD16M32M8G is a 16Mbit x 32 dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 4bit DRAMs in 32-pin TSOPII packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a Single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible. PIN ASSIGNMENT FEATURES PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL wHMD16M32M8G: 1 Vss 19 A10 37 NC 55 DQ11 4K Cycles/64ms Refresh Gold 2 DQ0 20 DQ4 38 NC 56 DQ27 w Access times : 50, 60ns 3 DQ16 21 DQ20 39 Vss 57 DQ12 w High-density 64MByte design 4 DQ1 22 DQ5 40 /CAS0 58 DQ28 w Single + 5V ±0.5V power supply 5 DQ17 23 DQ21 41 /CAS2 59 Vcc w JEDEC standard pinout 6 DQ2 24 DQ6 42 /CAS3 60 DQ29 w FP(Fast Page) mode operation 7 DQ18 25 DQ22 43 /CAS1 61 DQ13 w TTL compatible inputs and outputs 8 DQ3 26 DQ7 44 /RAS0 62 DQ30 w FR4-PCB design 9 DQ19 27 DQ23 45 NC 63 DQ14 10 Vcc 28 A7 46 NC 64 DQ31 11 NC 29 A11 47 /W 65 DQ15 12 A0 30 Vcc 48 NC 66 NC 13 A1 31 A8 49 DQ8 67 PD1 14 A2 32 A9 50 DQ24 68 PD2 15 A3 33 NC 51 DQ9 69 PD3 16 A4 34 /RAS2 52 DQ25 70 PD4 17 A5 35 NC 53 DQ10 71 NC 18 A6 36 NC 54 DQ26 72 Vss OPTIONS MARKING w Timing 50ns access 60ns access -5 -6 w Packages 72-pin SIMM M PERFORMANCE RANGE SPEED tRAC tCAC tRC -5 50ns 13ns 90ns -6 60ns 15ns 110ns wPART IDENTIFICATION PRESENCE DETECT PINS 50ns 60ns PD1 Vss Vss PD2 NC NC PD3 Vss NC PD4 Vss NC URL: www.hbe.co.kr REV. 1.0 (August. 2002) 1 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G FUNCTIONAL BLOCK DIAGRAM /CAS0 /RAS0 U0 CAS RAS OE W A0-A11 U1 CAS RAS OE W /CAS1 A0-A11 U2 CAS RAS OE W A0-A11 U3 CAS RAS OE W /CAS2 /RAS2 A0-A11 U4 CAS RAS OE W A0-A11 U5 CAS RAS OE W /CAS3 A0-A11 U6 CAS RAS OE W A0-A11 U7 CAS RAS OE W A0-A11 DQ0 DQ1 DQ2 DQ3 DQ0-DQ3 DQ0 DQ1 DQ2 DQ3 DQ4-DQ7 DQ0 DQ1 DQ2 DQ3 DQ8-DQ11 DQ0 DQ1 DQ2 DQ3 DQ12-DQ15 DQ0 DQ1 DQ2 DQ3 DQ16-DQ19 DQ0 DQ1 DQ2 DQ3 DQ20-DQ23 DQ0 DQ1 DQ2 DQ3 DQ24-DQ27 DQ0 DQ1 DQ2 DQ3 DQ28-DQ31 /W A0-A11 Vcc 0.1uF or 0.22uF Capacitor for each DRAM To all DRAMs Vss URL: www.hbe.co.kr REV. 1.0 (August. 2002) 2 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 6W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 880 MA -6 - 800 MA - 16 MA -5 - 880 MA -6 - 800 MA -5 - 720 MA -6 - 560 MA - 8 MA -5 - 880 MA -6 - 800 MA Il(L) -60 5 µA IO(L) -5 5 µA ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 VOH 2.4 - V VOL - 0.4 V URL: www.hbe.co.kr REV. 1.0 (August. 2002) 3 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. o CAPACITANCE ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A11) CIN1 - 40 pF Input Capacitance (/W) C IN2 - 56 pF Input Capacitance (/RAS0) CIN3 - 58 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 54 pF Input/Output Capacitance (DQ0-31) CDQ1 - 57 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 PARAMETER -6 SYMBOL UNIT MIN MAX MAX Random read or write cycle time tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 0 Output buffer turn-off delay tOFF 0 13 0 15 ns Transition time (rise and fall) tT 3 50 3 50 ns /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 50 60 ns /CAS pulse width tCAS 13 10K 15 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns URL: www.hbe.co.kr REV. 1.0 (August. 2002) 4 90 MIN 110 ns 0 ns 40 10K 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 10 10 ns Column address hold referenced to /RAS tAR 50 55 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 10 10 ns Write command hold referenced to /RAS tWCR 50 55 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 13 15 ns Write command to /CAS lead time tCWL 13 15 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 10 10 ns Data-in hold referenced to /RAS tDHR 50 55 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 10 10 ns /CAS hold time (C-B-R refresh) tCHR 15 15 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA Fast page mode cycle time tPC 40 45 ns /CAS precharge time (Fast page) tCP 10 10 ns /RAS pulse width (Fast page ) tRASP 60 /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns /CAS precharge(C-B-R counter test) tCPT 20 30 ns 16 16 35 100K 40 70 100K ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD ≥ tRCD(max) URL: www.hbe.co.kr REV. 1.0 (August. 2002) 5 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. Timing Diagrams TIMING WAVEFORM OF READ CYCLE URL: www.hbe.co.kr REV. 1.0 (August. 2002) 6 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) URL: www.hbe.co.kr REV. 1.0 (August. 2002) 7 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G WRITE CYCLE (/OE CONTROLLED WRITE) Note: Dout=open URL: www.hbe.co.kr REV. 1.0 (August. 2002) 8 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G /CAS-BEFORE-/RAS REFRESH COUNTER TEST CYCLE URL: www.hbe.co.kr REV. 1.0 (August. 2002) 9 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8G PACKAGING INFORMATION SIMM Design 107.95 mm 3.38 mm R 1.57 mm 101.19 3.18mmDIA 0.51mm 20.00 mm 10.16 mm 6.35 1 72 2.03 6.35 mm 1.02 mm 6.35 mm 1.27 mm 3.34 mm 95.25 mm 2.54 mm 0.25mm MIN 1.27±10% Gold : 1.04±0.10 mm Solder:0.914±0.10mm 1.27 ORDERING INFORMATION Part Number Density Org. Package HMD16M32M8G-5 64Byte x 32 72 Pin-SIMM HMD16M32M8G-6 64Byte x 32 72 Pin-SIMM URL: www.hbe.co.kr REV. 1.0 (August. 2002) 10 Component Vcc MODE SPEED 8EA 5V FPM 50ns 8EA 5V FPM 60ns Number HANBit Electronics Co.,Ltd.