L2330 L2330 DEVICES INCORPORATED Coordinate Transformer Coordinate Transformer DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Rectangular-to-Polar or Polar-toRectangular at 50 MHz ❑ Performs Direct Digital Synthesis (DDS) functions along with PM and FM Modulation ❑ 24-Bit Polar Phase Angle Accuracy ❑ Replaces Fairchild TMC2330A ❑ 120-pin PQFP The L2330 is a coordinate transformer that converts bidirectionally between Rectangular and Polar coordinates. seen at the output after 22 clock cycles and will continue upon every clock cycle thereafter. When in Rectangular-to-Polar mode, the L2330 is able to retrieve phase and magnitude information or backward map from a rectangular raster display to a radial data set. When in Rectangular-to-Polar mode, the user inputs a 16-bit Rectangular coordinate and the output generates a Polar transformation with 16-bit magnitude and 16-bit phase. The user may select the data format to be either two’s complement or sign-andmagnitude Cartesian data format. Polar Magnitude data is always in magnitude format only. Polar Phase Angle data is modulo 2π so it may be regarded as either unsigned or two’s complement format. When in Polar-to-Rectangular mode, the L2330 is able to execute direct digital waveform synthesis and modulation. Real-time image-space conversions are achieved from radially-generated images, such as RADAR, SONAR, and ultrasound to raster display formats. Functional Description The L2330 converts bidirectionally between Rectangular (Cartesian) and Polar (Phase and Magnitude) coordinates. The user selects the numeric format. A valid transformed result is When in Polar-to-Rectangular mode, the user inputs 16-bit Polar Magnitude and 32-bit Phase data and the output generates a 16-bit Rectangular coordinate. The use may select the data format to be either two’s complement or sign-and-magnitude Cartesian data format. L2330 BLOCK DIAGRAM OERX ENXR XRIN 15-0 ENYP 1-0 YPIN 31-0 16 2 POLAR 16 RXOUT 15-0 32 OEPY ACC 1-0 2 RECTANGULAR 16 PYOUT 15-0 TCXY RTP OVF CLK Special Arithmetic Functions 1 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer Outputs L2330 FUNCTIONAL BLOCK DIAGRAM XRIN15-0 ENXR 16 ENYP1-0 YPIN31-0 32 RXOUT15-0 — x-coordinate/Magnitude Data Output ACC0 RXOUT15-0 is the 16-bit Cartesian x-coordinate/Polar Magnitude Data output port. When OERX is HIGH, RXOUT15-0 is forced into the highimpedance state. 2 32 M ACC1 C AM 32 PM FM PYOUT15-0 — y-coordinate/Phase Angle Data Output 32 PYOUT15-0 is the 16-bit Cartesian y-coordinate/Polar Phase Angle Data output port. When OEPY is HIGH, PYOUT15-0 is forced into the highimpedance state. 32 **n 16 16 TCXY RTP Controls **n ENXR — x-coordinate/Magnitude Data Input Enable * TRANSFORM PROCESSOR 16 16 16 16 OERX When ENXR is HIGH, XRIN is latched into the input register on the rising edge of clock. When ENXR is LOW, the value stored in the register is unchanged. OEPY RXOUT15-0 OVF ENYP1-0 — y-coordinate/Phase Angle Data Input Control PYOUT15-0 * REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED ** WHEN RTP IS HIGH ’n’ IS 16-BITS, WHEN RTP IS LOW ’n’ IS 24-BITS ENYP1-0 is the 2-bit y-coordinate/ Phase Angle Data Input Control that determines four modes as shown in SIGNAL DEFINITIONS Inputs Power XRIN15-0 — x-coordinate/Magnitude Data Input VCC and GND +5V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. TABLE 1. REGISTER OPERATION XRIN15-0 is the 16-bit Cartesian x-coordinate/Polar Magnitude Data input port. XRIN15-0 is latched on the rising edge of CLK. ENYP1-0 M C 00 Hold Hold 01 Load Hold 10 Hold Load 11 Clear Load YPIN31-0 — y-coordinate/Phase Angle Data Input YPIN31-0 is the 32-bit Cartesian y-coordinate/Polar Phase Angle Data input port. When RTP is HIGH, the input accumulators should not be used. When ACC is LOW, the upper 16 bits of YPIN are the input port and the lower 16 bits become “don’t cares”. YPIN31-0 is latched on the rising edge of CLK. TABLE 2. ACCUMULATOR CONTROL ACC1-0 Configuration 00 No accumulation (normal operation) 01 PM accumulator path enabled 10 FM accumulator path enabled 11 Logical OR of PM and FM (Nonsensical) Special Arithmetic Functions 2 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer Table 1. ‘M’ is the Modulation Register and ‘C’ is the Carrier Register as shown in the Functional Block Diagram. RTP — Rectangular-to-Polar When RTP is HIGH, Rectangular-toPolar conversion mode is selected. When RTP is LOW, Polar-to-Rectangular conversion mode is selected. FIGURE 1A. ACC1-0 — Accumulator Control ACC1-0 is the 2-bit accumulator control that determines four modes as shown in Table 2. Changing of the internal phase Accumulator structure is very useful when RTP is LOW allowing for waveform synthesis and modulation. ACC1-0 set to ‘00’ is most commonly used when RTP is HIGH unless performing backward mapping from Cartesian to Polar coordinates. TCXY — Data Input/Output Format Select When TCXY is HIGH, two’s complement format is selected. When TCXY is LOW, sign-and-magnitude format is selected. INPUT FORMATS XRIN YPIN Integer Unsigned Magnitude 15 14 13 215 214 213 (RTP = 0) Fract. Unsigned Mag./Two's Comp. 2 1 0 22 21 20 31 30 29 *±20 2–1 2–2 2 1 0 2–29 2–30 2–31 Integer Signed Magnitude (RTP = 1, TCXY = 0) 15 14 13 NS 214 213 2 1 0 22 21 20 31 30 29 NS 214 213 18 17 16 22 21 20 Integer Two's Complement (RTP = 1, TCXY = 1) 15 14 13 –215 214 213 2 1 0 22 21 20 31 30 29 –215 214 213 18 17 16 22 21 20 (RTP = 0) Fractional Unsigned Magnitude Fract. Unsigned Mag./Two's Comp. 15 14 13 20 2–1 2–2 2 1 0 2–13 2–14 2–15 31 30 29 *±20 2–1 2–2 2 1 0 2–29 2–30 2–31 Fractional Signed Magnitude (RTP = 1, TCXY = 0) 15 14 13 NS 2–1 2–2 2 1 0 2–13 2–14 2–15 31 30 29 NS 2–1 2–2 18 17 16 2–13 2–14 2–15 Fractional Two's Complement (RTP = 1, TCXY = 1) 15 14 13 –20 2–1 2–2 2 1 0 2–13 2–14 2–15 31 30 29 –20 2–1 2–2 18 17 16 2–13 2–14 2–15 *±20 denotes two's complement sign or highest magnitude bit. Since phase angles are modulo 2π and phase accumulator is modulo 232, this bit may be regarded as ±π. NS denotes negative sign. (i.e. '1' negates the number) Special Arithmetic Functions 3 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer OVF — Overflow Flag OVF will go HIGH on the clock the magnitude of either of the current Cartesian coordinate outputs exceed the maximum range. OVF will return LOW on the clock that the Cartesian output value(s) return within range. An overflow condition can only occur when RTP is LOW. FIGURE 1B. OERX — x-coordinate/Magnitude Data Output Enable OEPY — y-coordinate/Phase Angle Data Output Enable When OERX is LOW, RXOUT15-0 is enabled for output. When OERX is HIGH, RXOUT15-0 is placed in a high-impedance state. When OEPY is LOW, PYOUT15-0 is enabled for output. When OEPY is HIGH, PYOUT15-0 is placed in a high-impedance state. OUTPUT FORMATS RXOUT PYOUT Integer Signed Magnitude (RTP = 0, TCXY = 0) 15 14 13 NS 214 213 2 1 0 22 21 20 15 14 13 NS 214 213 2 1 0 22 21 20 Integer Two's Complement (RTP = 0, TCXY = 1) 15 14 13 –215 214 213 2 1 0 22 21 20 15 14 13 –215 214 213 Integer Unsigned Magnitude 15 14 13 215 214 213 2 1 0 22 21 20 (RTP = 1) Fract. Unsigned Mag./Two's Comp. 2 1 0 22 21 20 15 14 13 *±20 2–1 2–2 2 1 0 2–13 2–14 2–15 Fractional Signed Magnitude (RTP = 0, TCXY = 0) 15 14 13 NS 2–1 2–2 2 1 0 2–13 2–14 2–15 15 14 13 NS 2–1 2–2 2 1 0 2–13 2–14 2–15 Fractional Two's Complement (RTP = 0, TCXY = 1) 15 14 13 –20 2–1 2–2 2 1 0 2–13 2–14 2–15 15 14 13 –20 2–1 2–2 2 1 0 2–13 2–14 2–15 (RTP = 1) Fractional Unsigned Magnitude Fract. Unsigned Mag./Two's Comp. 15 14 13 20 2–1 2–2 2 1 0 2–13 2–14 2–15 15 14 13 *±20 2–1 2–2 2 1 0 2–13 2–14 2–15 *±20 denotes two's complement sign or highest magnitude bit. Since phase angles are modulo 2π 32 and phase accumulator is modulo 2 , this bit may be regarded as ±π. NS denotes negative sign. (i.e. '1' negates the number) Special Arithmetic Functions 4 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Conversion Ranges The L2330 supports 16-bit unsigned radii and 16-bit signed Cartesian coordinates. Since the 16-bit rectangular coordinate space does not completely cover the polar space defined by 16-bit radii, certain values of “r” will not map correctly. This condition is indicated by the overflow (OVF) flag. In Polar-to-Rectangular conversions, no overflow occurs for r ≤ 32767 (7FFFH). Overflow will always occur when r > 46341 (B505H). Note that in signed magnitude mode r = 46340 (B504H) will also cause an overflow. For 32767 ≤ r ≤ 46340, overflow may occur depending on the exact values of r and θ. Figure 2 shows, for the first quadrant, these three regions: A = no overflow (correct conversion), B = possible overflow, C = overflow. The other quadrants are mapped in a similar manner. When in signed magnitude mode, the overflows on the other three quadrants are the same as in the first. This occurs because the signed magnitude number system is symmetric about zero. For example, if a given r and angle θ cause an overflow, the same r will cause an overflow for the angles -θ, π+θ , π-θ. Coordinate Transformer complement number system is not symmetric about zero. For example, if the X or Y component of the input is –32768 (8000H), no overflow occurs. But if the X or Y component of the input is +32768, overflow does occur. FIGURE 2. 65535 When converting from Rectangular-toPolar, if both inputs are zero the radius is zero but the angle is not defined. The L2330 will output 4707H in this case. Since the angle is not defined for a zero length vector, this is not an error. CONVERSION RANGES π/2 C 32767 B A y r θ However, when in two’s complement mode, the overflows aren’t quite the same. This occurs because the two’s x 32767 65535 Special Arithmetic Functions 5 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Internal Precision When performing a coordinate transformation, inaccuracies are introduced by a combination of quantization and approximation errors. The accuracy of a coordinate transformer is dependent on the word length used for the input variables, the word length used for internal calculations, as well as the number of iterations or steps performed. Truncation errors are due to the finite word length, and approximation errors are due to the finite number of iterations. For example, in the case of performing a polar-to-rectangular transformation, the accuracy of the rotation will be determined by how closely the input rotation angle was approximated by the summation of sub-rotation angles. In this study, we examine the effectiveness of 16-bit internal precision versus 24-bit internal precision. 10,000 random Rectangular coordinates were converted to Polar and back to Rectangular. The resulting Rectangular coordinates from this double conversion were then compared to the original Coordinate Transformer Rectangular coordinates input to the device. These vectors, with maximum word width of 16-bits, were sent through a 16-bit internal processor versus a 24-bit internal processor. The Rectangular coordinates were limited to the following conditions: –32769<x<32768 –32769<y<32768 Using the 16-bit internal processor, the resulting Rectangular coordinates were compared to the original Rectangular coordinates (see Table 3). Using the 24bit internal processor, the resulting TABLE 3. Rectangular coordinates were compared to the original Rectangular coordinates (see Table 3). By way of comparison between the 16-bit internal processor and the 24-bit internal processor, we find that the 24-bit internal processor is significantly more accurate. This accuracy is due to internal word length. During coordinate transformation, the number of bits truncated within a 24-bit internal processor are much smaller than in a 16-bit internal processor resulting in smaller error. DOUBLE CONVERSION ERROR Error Mean Error (X) Mean Error (Y) Mean Absolute Error (X) Mean Absolute Error (Y) Root Mean Square Error (X) Root Mean Square Error (Y) Max Error (X) Max Error (Y) Standard Deviation of Error (X) Standard Deviation of Error (Y) Internal 16-bit Internal 24-bit 0.0216 –0.0036 1.5736 1.0756 2.0168 1.4356 6.0/–7.0 5.0/–5.0 2.0168 1.4357 –0.0118 –0.0028 0.5116 0.5160 0.7664 0.7738 3.0/–3.0 3.0/–3.0 0.7664 0.7739 Special Arithmetic Functions 6 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Circle Test When performing a polar-to-rectangular transformation, a 24-bit internal processor proves to be significantly more accurate than a 16-bit internal processor. In this study, we compare how accurately a coordinate transformer with a 16-bit internal processor versus a 24-bit internal processor can calculate all the coordinates of a circle. By setting the radius to 7FFFH (maximum before overflow), θ is incremented using the accumulator of the L2330 in steps of 0000 4000H until all the points of a full circle are calculated into rectangular coordinates. The resulting rectangular coordinates were plotted and graphed. A graphical representation of the resulting vectors for both 16-bit and 24-bit internal processors are compared near 45°. Theoretically, a perfect circle is the desired output but when the resulting vectors from a coordinate transformer with 16-bit internal processor are graphed and displayed as shown in Figure 3, we see significant errors due to the inherent properties of a digital coordinate transformation system. In comparison, the 24-bit internal processor proves to be significantly more accurate than a 16-bit internal processor due to minimization of truncation errors. In many applications, this margin of error is of great significance especially when being used in applications such as medical ultrasound or modulation techniques. Data values for Figure 3 and Figure 4 are shown in Table 4. By looking at these values, we observe the step resolution on a 16-bit internal processor is not 1 unit in the x and y. In most cases, the minimum step resolution is 2 units in the x and y. On the other hand, Coordinate Transformer step resolution on a 24-bit internal processor is 1 unit in the x and y thus resulting in greater accuracy. 0.00549° and will not be able to properly calculate the theoretical minimum angle resolution. On the other hand, a 24-bit internal processor can produce a minimum angle resolution of 0.00002° and could therefore properly calculate the theoretical minimum angle resolution. The minimum theoretical angle resolution that could be produced is 0.00175° when x = 7FFFH and y = 1H. A 16-bit internal processor can produce a minimum angle resolution of only FIGURE 3. CIRCLE TEST RESULT NEAR 45° (16-BIT INTERNAL PROCESSOR) 23200 23190 23180 Y 23170 23160 23150 23140 23140 23150 23160 23170 23180 23190 23200 X FIGURE 4. CIRCLE TEST RESULT NEAR 45° (24-BIT INTERNAL PROCESSOR) 23200 23190 23180 Y 23170 23160 23150 23140 23140 23150 23160 23170 23180 23190 23200 X Special Arithmetic Functions 7 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED TABLE 4. Coordinate Transformer RESULTANT DATA VALUES OF CIRCLE TEST NEAR 45° 16-bit Internal Processor x 23201 23199 23199 23199 23199 23197 23197 23197 23197 23195 23195 23195 23195 23192 23192 23192 23192 23190 23190 23190 23190 23187 23187 23187 23187 23185 23185 23185 23185 23183 x (HEX) 5AA1 5A9F 5A9F 5A9F 5A9F 5A9D 5A9D 5A9D 5A9D 5A9B 5A9B 5A9B 5A9B 5A98 5A98 5A98 5A98 5A96 5A96 5A96 5A96 5A93 5A93 5A93 5A93 5A91 5A91 5A91 5A91 5A8F y 23139 23141 23141 23141 23141 23143 23143 23143 23143 23145 23145 23145 23145 23148 03148 23148 23148 23150 23150 23150 23150 23152 23152 23152 23152 23154 23154 23154 23154 23156 y (HEX) 5A63 5A65 5A65 5A65 5A65 5A67 5A67 5A67 5A67 5A69 5A69 5A69 5A69 5A6C 5A6C 5A6C 5A6C 5A6E 5A6E 5A6E 5A6E 5A70 5A70 5A70 5A70 5A72 5A72 5A72 5A72 5A74 24-bit Internal Processor x 23199 23198 23198 23197 23197 23196 23196 23195 23194 23194 23194 23193 23192 23191 23191 23191 23190 23189 23189 23189 23188 23187 23186 23186 23186 23185 23184 23184 23184 23183 x (HEX) 5A9F 5A9E 5A9E 5A9D 5A9D 5A9C 5A9C 5A9B 5A9A 5A9A 5A9A 5A99 5A98 5A97 5A97 5A97 5A96 5A95 5A95 5A95 5A94 5A93 5A92 5A92 5A92 5A91 5A90 5A90 5A90 5A8F y 23140 23141 23141 23142 23142 23143 23143 23144 23145 23145 23145 23146 23147 23148 23148 23148 23149 23150 23150 23150 23151 23152 23153 23153 23153 23154 23155 23155 23155 23156 y (HEX) 5A64 5A65 5A65 5A66 5A66 5A67 5A67 5A68 5A69 5A69 5A69 5A6A 5A6B 5A6C 5A6C 5A6C 5A6D 5A6E 5A6E 5A6E 5A6F 5A70 5A71 5A71 5A71 5A72 5A73 5A73 5A73 5A74 Special Arithmetic Functions 8 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 4.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.4 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 95 mA ICC2 VCC Current, Quiescent (Note 7) 5 mA CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF Special Arithmetic Functions 9 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol L2330– 1234567890123456 1234567890123456 1234567890123456 * 50 25 1234567890123456 1234567890123456 1234567890123456 Min Max Min Max 1234567890123456 1234567890123456 50 25 1234567890123456 1234567890123456 1234567890123456 1234567890123456 10 8 1234567890123456 1234567890123456 1234567890123456 8 7 1234567890123456 1234567890123456 1234567890123456 12 7 1234567890123456 1234567890123456 1234567890123456 1 0 1234567890123456 1234567890123456 1234567890123456 22 18 1234567890123456 1234567890123456 1234567890123456 1234567890123456 13 13 1234567890123456 1234567890123456 1234567890123456 13 13 1234567890123456 Parameter tCYC Cycle Time tPWL Clock Pulse Width Low tPWH Clock Pulse Width High tS Input Setup Time tH Input Hold Time tD Output Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 20 Min Max 20 7 6 6 0 16 13 13 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol 1234567890123456789012345678901212345678901234 L2330– 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 50* 25* 20* 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Min Max Min Max Min Max 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 50 25 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 11 9 7 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 8 7 6 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 13 7 6 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 2 2 1 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 25 20 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 14 13 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 14 13 1234567890123456789012345678901212345678901234 Parameter tCYC Cycle Time tPWL Clock Pulse Width Low tPWH Clock Pulse Width High tS Input Setup Time tH Input Hold Time tD Output Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Special Arithmetic Functions 10 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer SWITCHING WAVEFORMS: NO ACCUMULATION 0 1 2 3 22 23 24 CLK tH tS RTP TCXY tPWL tPWH tCYC ACC1-0 00 00 00 ENXR ENYP1-0 EN EN EN XRIN15-0 YPIN31-0 A B C tD RXOUT15-0 PYOUT15-0 f(A) SWITCHING WAVEFORMS: f(B) PHASE MODULATION 0 1 2 3 4 22 24 23 25 CLK RTP, TCXY ACC1-0 00 01 01 01 01 ENXR XRIN15-0 R ENYP1-0 10 01 01 01 01 YPIN31-0 C I J K L RXOUT15-0 PYOUT15-0 C+I 2C + J 3C + K 4C + L Special Arithmetic Functions 11 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot and overshoot. measures are recommended: Input levels below ground or above VCC will be clamped beginning at – a. A 0.1 µF ceramic capacitor should be 0.6 V and VCC + 0.6 V. The device can installed between VCC and Ground withstand indefinite operation with in- leads as close to the Device Under Test puts in the range of –0.5 V to +7.0 V. (DUT) as possible. Similar capacitors Device operation will not be adversely should be installed between device VCC affected, however, input current levels and the tester common, and device ground and tester common. will be well in excess of 100 mA. 4. Actual test conditions may vary b. Ground and VCC supply planes from those designated but operation is must be brought directly to the DUT guaranteed as specified. socket or contactor fingers. 5. Supply current for a given application c. Input voltages should be adjusted to can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. Special Arithmetic Functions 12 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer ORDERING INFORMATION 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 PYOUT5 PYOUT6 GND PYOUT7 PYOUT8 PYOUT9 GND PYOUT10 PYOUT11 PYOUT12 VCC PYOUT13 PYOUT14 PYOUT15 GND OVF RXOUT0 RXOUT1 VCC RXOUT2 RXOUT3 RXOUT4 GND RXOUT5 RXOUT6 RXOUT7 GND RXOUT8 RXOUT9 VCC 120-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Top View RXOUT10 RXOUT11 GND RXOUT12 RXOUT13 RXOUT14 VCC RXOUT15 GND OERX VCC XRIN15 XRIN14 XRIN13 GND XRIN12 XRIN11 XRIN10 XRIN9 XRIN8 XRIN7 XRIN6 GND XRIN5 XRIN4 XRIN3 GND XRIN2 XRIN1 VCC GND YPIN9 YPIN10 VCC YPIN11 YPIN12 YPIN13 YPIN14 YPIN15 YPIN16 YPIN17 VCC YPIN18 YPIN19 YPIN20 GND YPIN21 YPIN22 YPIN23 VCC YPIN24 YPIN25 YPIN26 YPIN27 YPIN28 YPIN29 YPIN30 YPIN31 ENXR XRIN0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VCC PYOUT4 PYOUT3 GND PYOUT2 PYOUT1 PYOUT0 VCC OEPY GND RTP CLK GND TCXY ENYP0 GND ENYP1 ACC0 ACC1 VCC YPIN0 YPIN1 YPIN2 YPIN3 YPIN4 YPIN5 YPIN6 GND YPIN7 YPIN8 Plastic Quad Flatpack (Q1) Speed 0°C to +70°C — COMMERCIAL SCREENING 25 ns 20 ns L2330QC25 L2330QC20 Special Arithmetic Functions 13 09/27/2001–LDS.2330-E L2330 DEVICES INCORPORATED Coordinate Transformer ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 2 3 4 5 6 7 8 9 10 11 12 13 120-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 PYO5 PYO7 PYO8 PYO10 PYO12 PYO14 PYO15 RXO0 RXO2 RXO4 RXO6 RXO8 RXO10 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 B 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 PYO3 PYO4 PYO6 PYO9 PYO11 PYO13 OVF RXO1 RXO3 RXO5 RXO7 RXO9 RXO12 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 PYO1 PYO2 VCC GND GND VCC GND VCC GND GND VCC RXO11 RXO13 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND RXO14 RXO15 OEPY PYO0 GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 KEY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 E 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 VCC GND OERX RTP GND VCC 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top View VCC XRI15 XRI14 TCXY GND CLK 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Through Package G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND XRI12 XRI13 ENYP1 ENYP0 GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 XRI9 XRI10 XRI11 ACC0 ACC1 VCC 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND XRI7 XRI8 YPI0 YPI1 YPI3 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND XRI5 XRI6 YPI2 YPI4 GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 YPI5 YPI7 GND VCC YPI14 VCC GND VCC YPI27 YPI31 VCC XRI3 XRI4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 M 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 YPI6 YPI9 YPI11 YPI13 YPI16 YPI18 YPI20 YPI23 YPI25 YPI28 ENXR XRI1 XRI2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 N 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 YPI8 YPI10 YPI12 YPI15 YPI17 YPI19 YPI21 YPI22 YPI24 YPI26 YPI29 YPI30 XRI0 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G4) Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Special Arithmetic Functions 14 09/27/2001–LDS.2330-E