Maxim MAX1091 250ksps, 3v, 8-/4-channel, 10-bit adcs with 2.5v reference and parallel interface Datasheet

19-1638; Rev 2; 12/02
KIT
ATION
EVALU
E
L
B
AVAILA
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
The MAX1091/MAX1093 tri-states INT when CS goes
high. Refer to MAX1061/MAX1063 if tri-stating INT is not
desired.
The MAX1091 is available in a 28-pin QSOP package,
while the MAX1093 is available in a 24-pin QSOP. For
pin-compatible +5V, 10-bit versions, refer to the
MAX1090/MAX1092 data sheet.
Applications
Features
♦ 10-Bit Resolution, ±0.5 LSB Linearity
♦ +3V Single-Supply Operation
♦ User-Adjustable Logic Level (+1.8V to +3.6V)
♦ Internal +2.5V Reference
♦ Software-Configurable, Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1091)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1093)
♦ Software-Configurable, Unipolar/Bipolar Inputs
♦ Low Power
1.9mA (250ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
♦ Internal 3MHz Full-Power Bandwidth Track/Hold
♦ Byte-Wide Parallel (8 + 2) Interface
♦ Small Footprint: 28-Pin QSOP (MAX1091)
24-Pin QSOP (MAX1093)
Pin Configurations
TOP VIEW
HBEN 1
24 VLOGIC
D7 2
23 VDD
D6 3
22 REF
D5 4
21 REFADJ
D4 5
20 GND
Industrial Control Systems
Data Logging
D3 6
Energy Management
Patient Monitoring
D2 7
18 CH0
Data-Acquisition Systems
Touch Screens
D1/D9 8
17 CH1
D0/D8 9
16 CH2
INT 10
15 CH3
RD 11
14 CS
WR 12
13 CLK
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
INL
(LSB)
MAX1091ACEI
0°C to +70°C
28 QSOP
±0.5
MAX1091BCEI
0°C to +70°C
28 QSOP
±1
MAX1091AEEI
-40°C to +85°C
28 QSOP
±0.5
MAX1091BEEI
-40°C to +85°C
28 QSOP
Ordering Information continued at end of data sheet.
±1
MAX1093
19 COM
QSOP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1091/MAX1093
General Description
The MAX1091/MAX1093 low-power, 10-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a VLOGIC
pin that allows them to interface directly with a +1.8V to
+3.6V digital supply.
Power consumption is only 5.7mW (VDD = VLOGIC) at the
maximum sampling rate of 250ksps. Two software-selectable power-down modes enable the MAX1091/
MAX1093 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can cut
supply current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1091 has
eight input channels and the MAX1093 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, combined with ease of use and small package size, make
these converters ideal for battery-powered and dataacquisition applications or for other circuits with demanding power consumption and space requirements.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VLOGIC to GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V)
REF, REFADJ to GND ................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D9, INT) to GND.....-0.3V to (VLOGIC + 0.3V)
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C) ...........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C) .........667mW
Operating Temperature Ranges
MAX1091_C_ _/MAX1093_C_ _ ...........................0°C to +70°C
MAX1091_E_ _/MAX1093_E_ _ ........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
RES
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
10
Bits
MAX109_A
±0.5
MAX109_B
±1
No missing codes over temperature
±1
LSB
Offset Error
±2
LSB
Gain Error (Note 3)
±2
LSB
LSB
Gain Temperature Coefficient
±2.0
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
DYNAMIC SPECIFICATIONS (fIN(sine wave) = 50kHz, VIN = 2.5VP-P, 250ksps, external fCLK = 4.8MHz, bipolar input mode)
Signal-to-Noise Plus Distortion
SINAD
60
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-72
dB
Spurious-Free Dynamic Range
SFDR
72
dB
fIN1 = 49kHz, fIN2 = 52kHz
76
dB
Channel-to-Channel Crosstalk
fIN = 125kHz, VIN = 2.5VP-P (Note 4)
-78
dB
Full-Linear Bandwidth
SINAD > 56dB
250
kHz
Full-Power Bandwidth
-3dB rolloff
3
MHz
Intermodulation Distortion
IMD
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
tCONV
External clock mode
3.3
External acquisition/internal clock mode
2.5
3.0
3.5
Internal acquisition/internal clock mode
3.2
3.6
4.1
tACQ
625
µs
ns
Aperture Delay
External acquisition or external clock mode
50
ns
Aperture Jitter
External acquisition or external clock mode
Internal acquisition/internal clock mode
<50
<200
ps
External Clock Frequency
Duty Cycle
2
fCLK
0.1
4.8
MHz
30
70
%
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Analog Input Voltage Range
Single-Ended and Differential
(Note 6)
VIN
Unipolar, VCOM = 0
Bipolar, VCOM = VREF / 2
Multiplexer Leakage Current
0
VREF
-VREF/2
+VREF/2
±0.01
On/off-leakage current, VIN = 0 or VDD
Input Capacitance
±1
12
CIN
V
µA
pF
INTERNAL REFERENCE
2.49
REF Output Voltage
REF Short-Circuit Current
REF Temperature Coefficient
TCREF
TA = 0°C to +70°C
REFADJ Input Range
For small adjustments
REFADJ High Threshold
To power down the internal reference
Load Regulation (Note 7)
0 to 0.5mA output load
2.5
V
mA
±20
ppm/°C
±100
mV
0.2
mV/mA
VDD - 1.0
V
0.01
1
µF
4.7
10
µF
1.0
VDD +
50mV
V
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
2.51
15
EXTERNAL REFERENCE AT REF
REF Input Voltage Range
VREF
REF Input Current
IREF
200
VREF = 2.5V, fSAMPLE = 250ksps
300
2
Shutdown mode
µA
DIGITAL INPUTS AND OUTPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VLOGIC = 2.7V
2.0
VLOGIC = 1.8V
1.5
VLOGIC = 2.7V
0.8
VLOGIC = 1.8V
0.5
200
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
Output Low Voltage
VOL
ISINK = 1.6mA
VOH
ISOURCE = 1mA
Output High Voltage
Three-State Leakage Current
Three-State Output Capacitance
V
VIN = 0 or VDD
±0.1
mV
±1
15
CS = VDD
±0.1
COUT
CS = VDD
15
µA
pF
0.4
V
±1
µA
VLOGIC - 0.5
ILEAKAGE
V
V
pF
_______________________________________________________________________________________
3
MAX1091/MAX1093
ELECTRICAL CHARACTERISTICS (continued)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.3
1.9
0.9
0.5
2
POWER REQUIREMENTS
Analog Supply Voltage
VDD
2.7
3.6
V
Digital Supply Voltage
VLOGIC
1.8
VDD + 0.3
2.6
2.3
1.2
0.8
10
V
Operating mode,
fSAMPLE = 250ksps
Positive Supply Current
IDD
Standby mode
Internal reference
External reference
Internal reference
External reference
Shutdown mode
VLOGIC Current
Power-Supply Rejection
ILOGIC
PSR
CL = 20pF
150
fSAMPLE = 250ksps
Not converting
VDD = 3V ±10%, full-scale input
2
10
±0.4
±0.9
mA
µA
µA
mV
TIMING CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK Period
tCP
208
ns
CLK Pulse Width High
tCH
40
ns
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
WR to CLK Fall Setup Time
tCWS
40
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR
Setup Time
tCSWS
60
ns
CLK or WR to CS
Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width (Note 8)
tWR
CS Rise to Output Disable
tTC
4
60
CLOAD = 20pF (Figure 1)
20
_______________________________________________________________________________________
ns
100
ns
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
RD Rise to Output Disable
CONDITIONS
MIN
MAX
UNITS
70
ns
20
70
ns
20
110
ns
CLOAD = 20pF (Figure 1)
100
ns
CLOAD = 20pF (Figure 1)
110
ns
tTR
CLOAD = 20pF (Figure 1)
20
RD Fall to Output Data Valid
tDO
CLOAD = 20pF (Figure 1)
HBEN to Output Data Valid
tDO1
CLOAD = 20pF (Figure 1)
RD Fall to INT High Delay
tINT1
CS Fall to Output Data Valid
tDO2
TYP
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
VLOGIC
3kΩ
DOUT
3kΩ
CLOAD
20pF
a) HIGH-Z TO VOH AND VOL TO VOH
DOUT
CLOAD
20pF
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
5
MAX1091/MAX1093
TIMING CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
0.2
MAX1091/93 toc02
0.3
0.20
0.15
1000
0
0.05
IDD (µA)
0.1
WITH INTERNAL
REFERENCE
0
-0.10
-0.2
100
-0.5
-0.1
WITH EXTERNAL
REFERENCE
10
-0.15
-0.3
-0.20
-0.4
1
-0.25
400
600
800
1000
0
1200
200
OUTPUT CODE
600
800
1000
0.1
1200
RL = ∞
CODE = 1010100000
2.1
1.95
1.9
1.90
1.8
1.85
1.7
1.80
3.6
10k
100k
920
910
900
880
-40
-15
10
35
60
2.7
85
3.0
3.3
3.6
VDD (V)
TEMPERATURE (°C)
VDD (V)
STANDBY CURRENT vs. TEMPERATURE
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
900
1.00
-40
-15
10
35
TEMPERATURE (°C)
60
85
1.0
0.8
0.50
880
1.1
0.9
0.75
890
MAX1091/93 toc09
1.25
1.2
POWER-DOWN IDD (µA)
910
MAX1091/93 toc08
920
1.50
POWER-DOWN IDD (µA)
MAX1091/93 toc07
930
1M
890
1.6
3.3
1k
STANDBY CURRENT vs. SUPPLY VOLTAGE
2.0
IDD (mA)
2.00
100
930
STANDBY IDD (µA)
2.05
3.0
10
fSAMPLE (Hz)
SUPPLY CURRENT vs. TEMPERATURE
2.2
MAX1091/93 toc04
RL = ∞
CODE = 1010100000
2.7
1
OUTPUT CODE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.10
400
MAX1091/93 toc06
200
MAX1091/93 toc05
0
IDD (mA)
10,000
0.10
INL (LSB)
INL (LSB)
0.25
MAX1091/93 toc01
0.4
6
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1091/93 toc03
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
STANDBY IDD (µA)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
2.7
3.0
3.3
VDD (V)
3.6
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
OFFSET ERROR (LSB)
2.51
2.50
2.49
2.49
3.0
3.3
-1.0
-40
3.6
-15
OFFSET ERROR
vs. TEMPERATURE
60
85
-0.5
-1.0
60
-0.250
85
3.0
3.3
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
35
60
85
FFT PLOT
150
VDD = 3V
fIN = 50kHz
fSAMPLE = 250ksps
0
-20
AMPLITUDE (dB)
200
ILOGIC (µA)
10
20
MAX1091/93 toc17
250
MAX1091/93 toc16
-15
TEMPERATURE (°C)
-40
-60
-80
-100
100
100
-40
3.6
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
150
-0.250
-0.500
2.7
VDD (V)
200
-0.125
-0.375
TEMPERATURE (°C)
250
0
GAIN ERROR (LSB)
0
-0.750
35
3.6
GAIN ERROR vs. TEMPERATURE
-0.500
10
3.3
0.125
MAX1091/93 toc14
MAX1091/93 toc13
0
-15
3.0
VDD (V)
0.250
GAIN ERROR (LSB)
0.5
-40
2.7
GAIN ERROR vs. SUPPLY VOLTAGE
1.0
OFFSET ERROR (LSB)
35
TEMPERATURE (°C)
VDD (V)
ILOGIC (µA)
10
MAX1091/93 toc15
2.7
0
-0.5
2.48
2.48
0.5
MAX1091/93 toc18
2.50
MAX1091/93 toc12
2.52
VREF (V)
2.51
1.0
MAX1091/93 toc11
2.52
VREF (V)
2.53
MAX1091/93 toc10
2.53
OFFSET ERROR
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
-120
-140
50
50
2.7
3.0
3.3
VDD (V)
3.6
-40
-15
10
35
TEMPERATURE (°C)
60
85
0
200
400
600
800
1000
1200
FREQUENCY (kHz)
_______________________________________________________________________________________
7
MAX1091/MAX1093
Typical Operating Characteristics (continued)
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1091/MAX1093
Pin Description
PIN
8
NAME
FUNCTION
MAX1091
MAX1093
1
1
HBEN
2
2
D7
Three-State Digital I/O Line (D7)
3
3
D6
Three-State Digital I/O Line (D6)
4
4
D5
Three-State Digital I/O Line (D5)
5
5
D4
Three-State Digital I/O Line (D4)
6
6
D3
Three-State Digital I/O Line (D3)
7
7
D2
Three-State Digital I/O Line (D2)
8
8
D1/D9
Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
9
9
D0/D8
Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
10
10
INT
INT goes low when the conversion is complete and the output data is ready.
11
11
RD
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on
the data bus.
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
12
12
WR
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
13
13
CLK
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In
internal clock mode, connect this pin to either VDD or GND.
14
14
CS
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high impedance.
15
—
CH7
Analog Input Channel 7
16
—
CH6
Analog Input Channel 6
17
—
CH5
Analog Input Channel 5
18
—
CH4
Analog Input Channel 4
19
15
CH3
Analog Input Channel 3
20
16
CH2
Analog Input Channel 2
21
17
CH1
Analog Input Channel 1
22
18
CH0
Analog Input Channel 0
23
19
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
24
20
GND
Analog and Digital Ground
25
21
REFADJ
26
22
REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to
GND when using the internal reference.
27
23
VDD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
28
24
VLOGIC
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01µF capacitor. When using an external reference, connect REFADJ to VDD to disable
the internal bandgap reference.
Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can
range from +1.8V to VDD + 300mV.
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Converter Operation
The MAX1091/MAX1093 ADCs use a successiveapproximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 10-bit digital output. Their parallel (8 + 2)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1091/MAX1093.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1091
(Figure 3a) and to CH0–CH3 for the MAX1093 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode, IN+ and IN- are selected from analog input pairs (Table 4) and are internally switched to
either of the analog inputs. This configuration is pseudodifferential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLD as a sample of the
signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-toanalog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 10-bit resolution. This action is equivalent to
transferring a 12pF[(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
REF
(CH7)
(CH6)
(CH5)
(CH4)
CH3
CH2
CH1
REFADJ
AV =
2.05
ANALOG
INPUT
MULTIPLEXER
CHARGE REDISTRIBUTION
10-BIT DAC
COMP
10
COM
SUCCESSIVEAPPROXIMATION
REGISTER
MAX1091
MAX1093
CLOCK
2
CS
WR
RD
1.22V
REFERENCE
T/H
CH0
CLK
17kΩ
8
2
CONTROL LOGIC
&
LATCHES
8
MUX
HBEN
INT
8
8
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
( ) ARE FOR MAX1091 ONLY.
VDD
VLOGIC
GND
D0–D7
8-BIT DATA BUS
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1091/MAX1093
_______________________________________________________________________________________
9
MAX1091/MAX1093
Detailed Description
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Track/Hold
10-BIT CAPACITIVE DAC
REF
COMPARATOR
INPUT
CHOLD
MUX –
+
CH0
CH1
ZERO
12pF
RIN
800Ω
CH2
CH3
CH4
CSWITCH
HOLD
TRACK
CH5
CH6
CH7
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
COM
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
Figure 3a. MAX1091 Simplified Input Structure
10-BIT CAPACITIVE DAC
REF
CH0
COMPARATOR
INPUT
CHOLD
MUX –
+
ZERO
where RS is the source impedance of the input signal,
RIN (800Ω) is the input resistance, and CIN (12pF) is
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1091/
MAX1093’s AC performance.
12pF
RIN
800Ω
CH1
CSWITCH
CH2
TRACK
CH3
T/H
SWITCH
COM
HOLD
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3
Figure 3b. MAX1093 Simplified Input Structure
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the supplies by more than 50mV, limit the forward-bias input
current to 4mA.
10
The MAX1091/MAX1093 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connected
to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative input (-), and the difference of (IN+) - (IN-) is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and C HOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ = 7 (RS + RIN) CIN
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1091/MAX1093 T/H stage offers a 250kHz fulllinear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recommended.
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1091/MAX1093 for either unipolar or bipolar operation. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus
______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval ends (three external
cycles or approximately 1µs in internal clock mode)
(Figure 4). Note that, when the internal acquisition is
combined with the internal clock, the aperture jitter can
be as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisition and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates
acquisition and starts conversion on WR’s rising edge
(Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal INT is provided to allow the
MAX1091/MAX1093 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Table 1. Control Byte Functional Description
BIT
NAME
FUNCTION
PD1 and PD0 select the various clock and power-down modes.
D7, D6
PD1, PD0
0
0
Full Power-Down Mode. Clock mode is unaffected.
0
1
Standby Power-Down Mode. Clock mode is unaffected.
1
0
Normal Operation Mode. Internal clock mode selected.
1
1
Normal Operation Mode. External clock mode selected.
D5
ACQMOD
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
D4
SGL/DIF
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2 and 3).
D3
UNI/BIP
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2.
A2, A1, A0
Address bits A2, A1, A0 select which of the 8/4 (MAX1091/MAX1093) channels are to be converted
(see Tables 3 and 4).
D2, D1, D0
______________________________________________________________________________________
11
MAX1091/MAX1093
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
tCS
CS
tCSWS
tACQ
tCONV
tCSWH
tWR
WR
tDH
tDS
CONTROL
BYTE
D7–D0
ACQMOD = "0"
INT
HIGH-Z
HIGH-Z
tINT1
RD
HBEN
tD0
HIGH-Z
tTR
tD01
HIGH/LOW
BYTE VALID
DOUT
HIGH/LOW
BYTE VALID
HIGH-Z
Figure 4. Conversion Timing Using Internal Acquisition Mode
tCS
CS
tCSWS
tWR
tACQ
tCSHW
tCONV
tDH
tDH
WR
tDS
CONTROL
BYTE
ACQMOD = "1"
D7–D0
INT
CONTROL
BYTE
ACQMOD = "0"
HIGH-Z
HIGH-Z
tINT1
RD
HBEN
tD0
HIGH-Z
DOUT
tD01
HIGH/LOW
BYTE VALID
tTR
HIGH/LOW
BYTE VALID
Figure 5. Conversion Timing Using External Acquisition Mode
12
______________________________________________________________________________________
HIGH-Z
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and D6 must be set to 0. The internal clock frequency is
then selected, resulting in a conversion time of 3.6µs.
When using the internal clock mode, tie the CLK pin
either high or low to prevent the pin from floating.
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to one. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1091/MAX1093 with
clock frequencies lower than 100kHz is not recommended, because it causes a voltage droop across the
ACQUISITION STARTS
tCP
hold capacitor in the T/H stage that results in degraded
performance.
Digital Interface
Input (control byte) and output data are multiplexed on
a three-state parallel interface. This parallel interface
(I/O) can easily be interfaced with standard µPs. The
signals CS, WR, and RD control the write and read
operations. CS represents the chip select signal, which
enables a µP to address the MAX1091/MAX1093 as an
I/O port. When high, CS disables the CLK WR and RD
inputs and forces the interface into a high-impedance
(high-Z) state.
Input Format
The control byte is latched into the device on pins
D7–D0 during a write command. Table 2 shows the
control byte format.
Output Format
The output format for both the MAX1091/MAX1093 is
binary in unipolar mode and two’s complement in bipolar mode. When reading the output data, CS and RD
must be low. When HBEN = 0, the lower 8 bits are read.
With HBEN = 1, the upper 2 bits are available and the
output data bits D7–D2 are set either low in unipolar
mode or set to the value of the MSB in bipolar mode
(Table 5).
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWS tCH
WR
tCL
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = "0"
tCWH
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
______________________________________________________________________________________
13
MAX1091/MAX1093
Selecting Clock Mode
The MAX1091/MAX1093 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The parts retain
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock modes, internal or external acquisition
can be used. At power-up, the MAX1091/MAX1093
enter the default external clock mode.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWS
tDH
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = "1"
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWH
tDH
WR
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW.
ACQMOD = "0"
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
Table 2. Control Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
PD1
PD0
ACQMOD
SGL/DIF
UNI/BIP
A2
A1
A0
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
0
0
0
+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CH1
CH2
CH3
CH4*
CH5*
CH6*
COM
-
+
+
+
+
+
+
*Channels CH4–CH7 apply to MAX1091 only.
14
CH7*
______________________________________________________________________________________
+
-
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
A2
A1
A0
CH0
CH1
CH2
CH3
0
0
0
+
-
0
0
1
-
+
0
1
0
1
CH4*
CH5*
CH6*
CH7*
0
+
-
1
1
-
+
0
0
+
-
1
0
1
-
+
1
1
0
+
-
1
1
1
-
+
*Channels CH4–CH7 apply to MAX1091 only.
Internal and External Reference
Internal Reference
With the internal reference, the full-scale range is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between
REFADJ and GND.
The MAX1091/MAX1093 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
the both the MAX1091 and the MAX1093. The internally
trimmed +1.22V reference is buffered with a +2.05V/V
gain.
External Reference
With both the MAX1091 and MAX1093, an external reference can be placed at either the input (REFADJ) or
the output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1091/MAX1093 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10µs, and no conversions should be attempted during this phase. When
using the internal reference, 500µs is required for VREF
to stabilize.
Table 5. Data-Bus Output (8 + 2 Parallel
Interface)
PIN
HBEN = 0
D0
Bit 0 (LSB)
D1
Bit 1
HBEN = 1
VDD = +3V
50kΩ
Bit 8
Bit 9 (MSB)
MAX1091
MAX1093
330kΩ
BIPOLAR
(UNI/BIP = 0)
UNIPOLAR
(UNI/BIP = 1)
D2
Bit 2
Bit 9
0
D3
Bit 3
Bit 9
0
D4
Bit 4
Bit 9
0
D5
Bit 5
Bit 9
0
D6
Bit 6
Bit 9
0
D7
Bit 7
Bit 9
0
50kΩ
REFADJ
GND
4.7µF
REF
0.01µF
GND
Figure 7. Reference Voltage Adjustment with External
Potentiometer
______________________________________________________________________________________
15
MAX1091/MAX1093
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
V DD . The DC input resistance at REF is 25kΩ.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the reference has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
Save power by placing the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 2). In both software powerdown modes, the parallel interface remains active, but
the ADC does not convert.
ed. A rising edge on WR causes the MAX1091/MAX1093
to exit shutdown mode and return to normal operation.
To achieve full 10-bit accuracy with a 4.7µF reference
bypass capacitor, 500µs is required after power-up.
Waiting 500µs in standby mode, instead of in full-power
mode, can reduce power consumption by a factor of 3 or
more. When using an external reference, only 50µs is
required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode.
Note: Bypassing capacitors larger than 4.7µF between
REF and GND results in longer power-up delays.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Standby Mode
While in standby mode, the supply current is 850µA
(typ). The part powers up on the next rising edge on
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 250ksps.
Figure 8 depicts the nominal, unipolar input/output (I/O)
transfer function and Figure 9 shows the bipolar I/O
transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1 LSB = VREF / 1024.
Shutdown Mode
Shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to
2µA immediately after the current conversion is complet-
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 250ksps is
achieved by completing a conversion every 19 clock
cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
Maximum Sampling Rate/
Achieving 300ksps
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
111 . . . 111
FS = REF + COM
111 . . . 110
ZS = COM
011 . . . 111
FS = REF + COM
2
011 . . . 110
ZS = COM
000 . . . 010
100 . . . 010
100 . . . 001
1 LSB =
100 . . . 000
000 . . . 001
REF
1024
000 . . . 000
011 . . . 111
111 . . . 111
011 . . . 110
111 . . . 110
011 . . . 101
111 . . . 101
000 . . . 001
100 . . . 001
000 . . . 000
100 . . . 000
0
1
2
512
-REF
+ COM
2
REF
1 LSB =
1024
-FS =
COM*
- FS
FS
INPUT VOLTAGE (LSB)
(COM)
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function
16
FS -
3/2
LSB
*COM ≥ VREF / 2
Figure 9. Bipolar Transfer Function
______________________________________________________________________________________
+FS - 1 LSB
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
UNIPOLAR MODE
BIPOLAR MODE
Full Scale
VREF + COM
Positive Full Scale
Zero Scale
COM
Zero Scale
COM
—
—
Negative Full Scale
-VREF/2 + COM
sion cycles, and 2 read cycles. This assumes that the
results of the last conversion are read before the next
control byte is written. Throughputs up to 300ksps can
be achieved by first writing a control word to begin the
acquisition cycle of the next conversion, and then reading the results of the previous conversion from the bus
(Figure 10). This technique allows a conversion to be
completed every 16 clock cycles. Note that the switching of the data bus during acquisition or conversion can
cause additional supply noise, which can make it difficult to achieve true 10-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and don’t lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network
of two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1091/MAX1093s’ powersupply pin. Minimize capacitor lead length for best supply-noise rejection; add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static linearity parameters for the MAX1091/MAX1093 are
measured using the end-point method.
VREF/2 + COM
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
______________________________________________________________________________________
17
MAX1091/MAX1093
Table 6. Full-Scale and Zero-Scale for Unipolar and Bipolar Operation
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
WR
RD
HBEN
D7–D0
CONTROL
BYTE
D7–D0 D9–D8
D7–D0 D9–D8
CONTROL BYTE
LOW HIGH
BYTE BYTE
STATE
LOW
BYTE
ACQUISITION
CONVERSION
ACQUISITION
HIGH
BYTE
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
SUPPLIES
+3V


THD = 20 × log   V2 2 + V3 2 + V4 2 + V5 2  / V1 


where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
R* = 5Ω
VLOGIC = +2V/+3V GND
4.7µF
0.1µF
VDD
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distortion component.
GND
COM
+2V/+3V DGND
DIGITAL
CIRCUITRY
MAX1091
MAX1093
*OPTIONAL
Figure 11. Power-Supply and Grounding Connections
Chip Information
TRANSISTOR COUNT: 5781
18
______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
CLK
+1.8V TO +3.6V
VLOGIC
CS
REF
WR
REFADJ
4.7µF
+1.8V TO +3.6V
+3V
MAX1093 VDD
+2.5V
0.1µF
RD
VLOGIC
+3V
MAX1091 VDD
µP
CONTROL
INPUTS
CLK
µP
CONTROL
INPUTS
CS
REF
WR
REFADJ
4.7µF
0.1µF
RD
HBEN
+2.5V
HBEN
INT
OUTPUT STATUS
INT
OUTPUT STATUS
CH7
D7
CH6
D7
D6
CH5
D6
D5
CH4
D4
CH3
D3
D2
D5
ANALOG
INPUTS
D4
CH3
CH2
D3
CH2
CH1
D2
CH1
D1/D9
CH0
D0/D8
COM
GND
µP DATA BUS
D1/D9
CH0
D0/D8
COM
ANALOG
INPUTS
GND
µP DATA BUS
Pin Configurations (continued)
Ordering Information (continued)
PART
TOP VIEW
TEMP RANGE
PIN-PACKAGE
INL
(LSB)
28 VLOGIC
MAX1093ACEG
0°C to +70°C
24 QSOP
27 VDD
MAX1093BCEG
0°C to +70°C
24 QSOP
±1
D6 3
26 REF
MAX1093AEEG
-40°C to +85°C
24 QSOP
±0.5
D5 4
25 REFADJ
MAX1093BEEG
-40°C to +85°C
24 QSOP
±1
HBEN 1
D7 2
D4 5
D3 6
±0.5
24 GND
MAX1091
23 COM
D2 7
22 CH0
D1/D9 8
21 CH1
D0/D8 9
20 CH2
INT 10
19 CH3
RD 11
18 CH4
WR 12
17 CH5
CLK 13
16 CH6
CS 14
15 CH7
QSOP
______________________________________________________________________________________
19
MAX1091/MAX1093
Typical Operating Circuits
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.