CY7C13451G
4-Mbit (128K × 36) Flow-Through
Sync SRAM
4-Mbit (128K × 36) Flow-Through Sync SRAM
Features
Functional Description
■
128K × 36 common I/O
■
3.3 V core Power Supply (VDD)
■
2.5 V or 3.3 V I/O Supply (VDDQ)
■
Fast Clock-to-output times
❐ 8.0 ns (100 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or Linear Burst Sequences
■
Separate Processor and Controller Address Strobes
■
Synchronous Self Timed Write
■
Asynchronous output enable
■
Available in Pb-free 165-ball FBGA Package
■
ZZ Sleep Mode option
The CY7C13451G is a 128K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE1), depth expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWx, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
The CY7C13451G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C13451G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
100 MHz
Unit
Maximum Access Time
Description
8.0
ns
Maximum Operating Current
180
mA
Maximum CMOS Standby Current
60
mA
Cypress Semiconductor Corporation
Document Number: 001-88572 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 22, 2017
CY7C13451G
Logic Block Diagram
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-88572 Rev. *G
Page 2 of 23
CY7C13451G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read or Write .......................................... 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 12
Document Number: 001-88572 Rev. *G
Switching Characteristics .............................................. 13
Timing Diagrams ............................................................ 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync ZZ Pin Issues Errata Summary .............. 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 3 of 23
CY7C13451G
Pin Configurations
Figure 1. 165-ball FBGA pinout [1]
CY7C13451G (128K × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
R
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
NC
NC
A
A
A
NC/9M
MODE
NC/36M
A
A
NC
NC
A
A
A
A
NC/18M
A1
A0
VDDQ
Note
1. Errata: The ZZ pin (Ball H11) needs to be externally connected to ground. For more information, see “Errata” on page 21.
Document Number: 001-88572 Rev. *G
Page 4 of 23
CY7C13451G
Pin Definitions
Name
A0, A1, A
BWA, BWB,
BWC, BWD
I/O
Description
InputAddress Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the two bit counter.
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
Synchronous LOW to conduct a byte write.
CLK
Input Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when
a new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When
Asynchronou LOW, the I/O pins act as outputs. When deasserted HIGH, I/O pins are tristated and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increSynchronous ments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ [2]
InputZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronou condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
s
has an internal pull down.
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs, DQPA,
DQPB, DQPC, Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
DQPD
the addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tristate condition.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Core of the Device.
VDDQ
I/O Power
Supply
Power Supply for the I/O Circuitry.
Note
2. Errata: The ZZ pin (Ball H11) needs to be externally connected to ground. For more information, see “Errata” on page 21.
Document Number: 001-88572 Rev. *G
Page 5 of 23
CY7C13451G
Pin Definitions (continued)
Name
I/O
Description
MODE
Input Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
NC
–
No Connects. Not Internally connected to the die.
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the
die.
Functional Overview
Single Write Accesses Initiated by ADSP
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CO) is 8.0 ns (100 MHz device).
Single write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active
2. ADSP is asserted LOW.
The CY7C13451G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two bit on-chip wrap
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, and CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSP or ADSC is asserted LOW (if the access is initiated by
ADSC, the write inputs are deasserted during this first cycle).
The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Document Number: 001-88572 Rev. *G
The addresses presented are loaded into the address register
and the burst inputs (GW, BWE, and BWx) are ignored during this
first clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. During byte
writes, BWA controls DQA and BWB controls DQB, BWC controls
DQC, and BWD controls DQD. All I/Os are tristated during a byte
write. Since this is a common I/O device, the asynchronous OE
input signal is deasserted and the I/Os are tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSC is asserted LOW.
3. ADSP is deasserted HIGH
4. The write input signals (GW, BWE, and BWx) indicate a write
access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQ[D:A] is written
into the specified address location. Byte writes are allowed.
During byte writes, BWA controls DQA, BWB controls DQB, BWC
controls DQC, and BWD controls DQD. All I/Os and even a byte
write are tristated when a write is detected. Since this is a
common I/O device, the asynchronous OE input signal is
deasserted and the I/Os are tristated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tristated
after a write cycle is detected, regardless of the state of OE.
Page 6 of 23
CY7C13451G
Burst Sequences
The CY7C13451G provides an on-chip two bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0] and
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
Sleep Mode
01
00
11
10
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
10
11
00
01
11
10
01
00
Fourth
Address
A1, A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-88572 Rev. *G
Page 7 of 23
CY7C13451G
Truth Table
The Truth Table for part CY7C13451G is as follows. [3, 4, 5, 6, 7]
Address
Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
Deselected Cycle,
Power down
None
H
X
X
L
X
L
X
Deselected Cycle,
Power down
None
L
L
X
L
L
X
Deselected Cycle,
Power down
None
L
X
H
L
L
Deselected Cycle,
Power down
None
L
L
X
L
Deselected Cycle,
Power down
None
X
X
H
Sleep Mode, Power down
None
X
X
Read Cycle, Begin Burst
External
L
Read Cycle, Begin Burst
External
Write Cycle, Begin Burst
Cycle Description
ADV WRITE
OE
CLK
DQ
X
X
L–H
Tristate
X
X
X
L–H
Tristate
X
X
X
X
L–H
Tristate
H
L
X
X
X
L–H
Tristate
L
H
L
X
X
X
L–H
Tristate
X
H
X
X
X
X
X
X
Tristate
H
L
L
L
X
X
X
L
L–H
Q
L
H
L
L
L
X
X
X
H
L–H
Tristate
External
L
H
L
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
3. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tristate. OE is a “Do Not Care” for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-88572 Rev. *G
Page 8 of 23
CY7C13451G
Truth Table for Read or Write
The Truth Table for read or write for part CY7C13451G is as follows. [8, 9]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte (A, DQPA)
H
L
H
H
H
L
Write Byte (B, DQPB)
H
L
H
H
L
H
Write Bytes (B, A, DQPA, DQPB)
H
L
H
H
L
L
Write Byte (C, DQPC)
H
L
H
L
H
H
Write Bytes (C, A, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes (C, B, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
H
L
H
L
L
L
Write Byte (D, DQPD)
H
L
L
H
H
H
Write Bytes (D, A, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes (D, B, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
H
L
L
H
L
L
Write Bytes (D, B, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
H
L
L
L
H
L
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
8. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
9. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is done based on the active byte write.
Document Number: 001-88572 Rev. *G
Page 9 of 23
CY7C13451G
Maximum Ratings
Operating Range
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient
Temperature
Range
Automotive
VDD
–40 °C to +125 °C
3.3 V5% / 2.5 V – 5%
+ 10%
to VDD
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on
VDD Relative to GND ...................................–0.5 V to +4.6 V
Neutron Soft Error Immunity
Supply Voltage on
VDDQ Relative to GND .................................. –0.5 V to +VDD
Test
Parameter Description Conditions
DC Voltage Applied to Outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch up Current .................................................... >200 mA
VDDQ
Typ
Max* Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
VOL
VIH
VIL
IX
IOZ
Output LOW Voltage
for 3.3 V, I/O, IOL= 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input Current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
5
A
Input HIGH Voltage
Input LOW
Voltage[10]
Notes
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
11. TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-88572 Rev. *G
Page 10 of 23
CY7C13451G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
Min
Max
Unit
IDD
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
100 MHz
–
180
mA
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN> VIH or VIN < VIL, f = fMAX,
inputs switching
100 MHz
(Automotive)
–
150
mA
ISB2
Automatic CE Power-down
Current – CMOS Inputs
100 MHz
Max. VDD, Device Deselected,
VIN > VDD – 0.3 V or VIN < 0.3 V, (Automotive)
f = 0, inputs static
–
40
mA
ISB3
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD, Device Deselected,
100 MHz
VIN > VDDQ – 0.3 V or VIN < 0.3 V, (Automotive)
f = fMAX, inputs switching
–
120
mA
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN > VIH or VIN < VIL,
f = 0, inputs static
100 MHz
(Automotive)
–
60
mA
Capacitance
Parameter [12]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
165-ball FBGA Unit
Max.
5
pF
5
pF
7
pF
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
165-ball FBGA Unit
Package
16.8
°C/W
3.0
°C/W
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-88572 Rev. *G
Page 11 of 23
CY7C13451G
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.5V
(a)
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
2.5V
OUTPUT
R = 351
VT = 1.25V
(a)
Document Number: 001-88572 Rev. *G
5 pF
INCLUDING
JIG AND
SCOPE
10%
1ns
1ns
(c)
R = 1667
ALL INPUT PULSES
VDDQ
GND
R = 1538
(b)
90%
10%
90%
(b)
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 12 of 23
CY7C13451G
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
-100
Unit
Min
Max
VDD(Typical) to the first Access [15]
1
–
ms
tCYC
Clock Cycle Time
10
–
ns
tCH
Clock HIGH
4.0
–
ns
tCL
Clock LOW
4.0
–
ns
tPOWER
Clock
Output Times
tCDV
Data Output Valid After CLK Rise
–
8.0
ns
tDOH
Data Output Hold After CLK Rise
2.0
–
ns
tCLZ
Clock to Low Z
[16, 17, 18]
0
–
ns
tCHZ
Clock to High Z [16, 17, 18]
–
3.5
ns
tOEV
OE LOW to Output Valid
–
3.5
ns
0
–
ns
–
3.5
ns
tOELZ
tOEHZ
OE LOW to Output Low Z
[16, 17, 18]
OE HIGH to Output High Z
[16, 17, 18]
Setup Times
tAS
Address Setup Before CLK Rise
2.0
–
ns
tADS
ADSP, ADSC Setup Before CLK Rise
2.0
–
ns
tADVS
ADV Setup Before CLK Rise
2.0
–
ns
tWES
GW, BWE, BWx Setup Before CLK Rise
2.0
–
ns
tDS
Data Input Setup Before CLK Rise
2.0
–
ns
tCES
Chip Enable Setup
2.0
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
–
ns
tWEH
GW, BWE, BWx Hold After CLK Rise
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
14. Test conditions shown in (a) of unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is
initiated.
16. tCHLZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 2 on page 12. Transition is measured ± 200 mV from steady state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z
prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-88572 Rev. *G
Page 13 of 23
CY7C13451G
Timing Diagrams
Figure 3. Read Cycle Timing [19]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
[A:B]
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-88572 Rev. *G
Page 14 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [20, 21]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
[A:B]
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
Document Number: 001-88572 Rev. *G
Page 15 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 5. Read/Write Timing [22, 23, 24]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
[A:B]
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
t CDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
23. The data bus (Q) remains in High Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 001-88572 Rev. *G
Page 16 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-88572 Rev. *G
Page 17 of 23
CY7C13451G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Table 1. Ordering Information
Speed
(MHz)
100
Ordering Code
CY7C13451G-100BZXE
Package
Diagram
Part and Package Type
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Operating
Range
Automotive
Ordering Code Definitions
CY
7
C
13451 G - 100 BZ X
E
Temperature Range:
E = Automotive-E
Pb-free
Package Type:
BZ = 165-ball FBGA
Speed Grade: 100 MHz
Process Technology: G 90 nm
Part Identifier: 13451 = FT, 128Kb × 36 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-88572 Rev. *G
Page 18 of 23
CY7C13451G
Package Diagrams
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-88572 Rev. *G
Page 19 of 23
CY7C13451G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
GW
Global Write
µA
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ms
millisecond
TQFP
Thin Quad Flat Pack
MHz
megahertz
WE
Write Enable
ns
nanosecond
Document Number: 001-88572 Rev. *G
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 20 of 23
CY7C13451G
Errata
This section describes the Ram9 Sync SRAM ZZ pin issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
4Mb-Ram9 Synchronous SRAMs: CY7C134**G
165-ball FBGA
Automotive
Product Status
All of the devices in the Ram9 4Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue
Document Number: 001-88572 Rev. *G
Page 21 of 23
CY7C13451G
Document History Page
Document Title: CY7C13451G, 4-Mbit (128K × 36) Flow-Through Sync SRAM
Document Number: 001-88572
Revision
ECN
Orig. of
Change
Submission
Date
**
4077242
PRIT
09/12/2013
New data sheet.
*A
4287129
PRIT
02/20/2014
Updated Electrical Characteristics:
Changed maximum value of IDD parameter from 205 mA to 180 mA.
Changed maximum value of ISB1 parameter from 80 mA to 150 mA.
Changed maximum value of ISB3 parameter from 65 mA to 120 mA.
Changed maximum value of ISB4 parameter from 45 mA to 60 mA.
*B
4419347
PRIT
06/25/2014
Included 100-pin TQFP package related information in all instances across
the document.
Updated Pin Configurations:
Updated Figure 1.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
Added spec 51-85050 *E.
*C
4430376
PRIT
07/04/2014
Changed status from Preliminary to Final.
Removed 100-pin TQFP package related information across the document.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
Removed spec 51-85050 *E.
*D
4598640
PRIT
12/16/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated to new template.
*E
5099908
PRIT
01/22/2016
Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Completing Sunset Review.
*F
5329574
PRIT
06/29/2016
Updated Truth Table.
Updated to new template.
*G
5974265
AESATMP9
11/22/2017
Updated logo and copyright.
Document Number: 001-88572 Rev. *G
Description of Change
Page 22 of 23
CY7C13451G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
®
®
ARM Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
cypress.com/pmic
Touch Sensing
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-88572 Rev. *G
Revised November 22, 2017
Page 23 of 23