AD ADG5206BCPZ-RL7 High voltage, latch-up proof, 8-/16-channel multiplexer Datasheet

High Voltage, Latch-Up Proof,
8-/16-Channel Multiplexers
ADG5206/ADG5207
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
3.5 pF off source capacitance
Off drain capacitance
ADG5206: 64 pF
ADG5207: 33 pF
0.35 pC typical charge injection
±0.02 nA on channel leakage
Low on resistance: 155 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
ADG5207: 8 kV I/O port to supplies
ADG5206
S1
D
S16
10714-001
1-OF-16
DECODER
A0 A1 A2 A3 EN
Figure 1.
ADG5207
APPLICATIONS
S1A
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Battery monitoring
Communication systems
S8A
DA
S1B
DB
S8B
A0 A1 A2 EN
10714-002
1-OF-8
DECODER
Figure 2.
GENERAL DESCRIPTION
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
Rev. A
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to ±22 V.
Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
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ADG5206/ADG5207
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 11
Applications ....................................................................................... 1
ESD Caution................................................................................ 11
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ......................... 12
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 16
Product Highlights ........................................................................... 1
Test Circuits..................................................................................... 21
Revision History ............................................................................... 2
Terminology .................................................................................... 23
Specifications..................................................................................... 3
Applications Information .............................................................. 24
±15 V Dual Supply ....................................................................... 3
Trench Isolation .......................................................................... 24
±20 V Dual Supply ....................................................................... 4
Outline Dimensions ....................................................................... 25
12 V Single Supply ........................................................................ 6
Ordering Guide .......................................................................... 25
36 V Single Supply ........................................................................ 8
Continuous Current per Channel, Sx, D, or Dx ..................... 10
REVISION HISTORY
5/13—Rev. 0 to Rev. A
Added 32-Lead LFCSP ....................................................... Universal
Changes to Features Section and Product Highlights Section.......... 1
Moved Continuous Current per Channel, Sx, D, or Dx Section,
Table 5, and Table 6 .........................................................................10
Changes to Table 7 ...........................................................................11
Changes to Figure 3 .........................................................................12
Changes to Figure 5 .........................................................................13
Changes to Figure 30, Figure 32, and Figure 33 ..........................22
7/12—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
ADG5206/ADG5207
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels,
ΔRON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Match Between Channels, ΔLeakage,
IS (Off ) 1
Drain Off Leakage, ID (Off )
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (On), IS (On) 2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
155
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
V
Ω typ
Test Conditions/Comments
VS = ±10 V, IS = −1 mA;
see Figure 32
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
200
4
225
250
285
Ω max
Ω typ
12
48
65
13
14
15
VS = ±10 V, IS = −1 mA
73
80
90
Ω max
Ω typ
Ω max
nA typ
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V;
see Figure 33
±0.005
±0.1
0.01
±0.15
±0.2
±0.4
0.015
nA max
nA typ
VS = ±10 V, VD =  10 V
VS = ±10 V, VD =  10 V;
see Figure 33
±0.02
±0.1
±0.02
±0.1
0.015
±0.25
±0.6
±3.3
±0.25
±0.4
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
VS = ±10 V, VD =  10 V
VS = VD = ±10 V; see Figure 34
±0.02
±0.1
±0.02
±0.1
0.01
±0.25
±0.6
±3.3
±0.2
±0.4
±1.7
0.03
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 3
Transition Time, tTRANSITION
Unit
3
200
260
180
245
140
200
85
300
320
360
260
270
285
220
240
270
27
Rev. A | Page 3 of 28
nA typ
nA max
nA typ
nA max
nA typ
VS = VD = ±10 V
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 37
ADG5206/ADG5207
Parameter
Charge Injection, QINJ
Data Sheet
25°C
0.35
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
±2
Unit
pC typ
pC typ
dB typ
Off Isolation
±1.8
−90
Channel-to-Channel Crosstalk
−76
dB typ
60
140
6.4
MHz typ
MHz typ
dB typ
3.5
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
VS = 0 V, f = 1 MHz
64
33
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
68
36
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
−3 dB Bandwidth
ADG5206
ADG5207
Insertion Loss
CS (Off )
CD (Off )
ADG5206
ADG5207
CD (On), CS (On)
ADG5206
ADG5207
POWER REQUIREMENTS
IDD
ISS
45
55
0.001
70
1
±9/±22
VDD/VSS
1
2
3
Test Conditions/Comments
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = ±10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
µA typ
µA max
µA typ
µA max
V min/V max
Digital inputs = 0 V or VDD
GND = 0 V
The off channel leakage delta is calculated using the maximum of VS = +10 V and VD = −10 V, or VS = −10 V and VD = +10 V.
The on channel leakage delta is calculated using the maximum of VS = VD = +10 V, or VS = VD = −10 V.
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
130
160
4
12
35
50
180
200
230
13
14
15
58
65
75
Rev. A | Page 4 of 28
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = ±15 V, IS = −1 mA;
see Figure 32
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
Data Sheet
Parameter
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Match Between Channels, ΔLeakage, IS (Off) 1
Drain Off Leakage, ID (Off )
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (On), IS (On) 2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
ADG5206/ADG5207
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
±0.005
±0.1
0.01
nA typ
±0.15
±0.2
±0.4
0.015
nA max
nA typ
±0.02
±0.1
±0.02
±0.1
0.015
±0.25
±0.6
±3.3
±0.25
±0.4
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
VS = VD = ±15 V;
see Figure 34
±0.02
±0.1
±0.02
±0.1
0.01
±0.25
±0.6
±3.3
±0.2
±0.4
±1.7
0.03
2.0
0.8
±0.002
3
nA typ
nA max
nA typ
nA max
nA typ
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD
185
240
175
230
135
185
75
Charge Injection, QINJ
0.45
Off Isolation
±4
−90
Channel-to-Channel Crosstalk
−76
dB typ
ADG5206
ADG5207
Insertion Loss
65
145
5.6
MHz typ
MHz typ
dB typ
CS (Off )
3.3
pF typ
tON (EN)
tOFF (EN)
Test Conditions/Comments
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V;
see Figure 33
VS = ±15 V, VD =  15 V;
see Figure 33
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 3
Transition Time, tTRANSITION
Unit
270
290
320
245
255
270
205
220
245
27
±4
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC typ
dB typ
−3 dB Bandwidth
Rev. A | Page 5 of 28
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 37
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = ±10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 39
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 41
VS = 0 V, f = 1 MHz
ADG5206/ADG5207
Data Sheet
Parameter
CD (Off )
ADG5206
ADG5207
CD (On), CS (On)
ADG5206
ADG5207
POWER REQUIREMENTS
IDD
−40°C to
+60°C
25°C
−40°C to
+85°C
Unit
Test Conditions/Comments
62
32
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
67
35
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
70
0.001
ISS
110
1
±9/±22
VDD/VSS
1
2
3
−40°C to
+125°C
µA typ
µA max
µA typ
µA max
V min/V max
Digital inputs = 0 V or VDD
GND = 0 V
The off channel leakage delta is calculated using the maximum of VS = +15 V and VD = −15 V, or VS = −15 V and VD = +15 V.
The on channel leakage delta is calculated using the maximum of VS = VD = +15 V, or VS = VD = −15 V.
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Match Between Channels, ΔLeakage,
IS (Off ) 1
Drain Off Leakage, ID (Off )
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (On), IS (On) 2
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
350
Unit
V
Ω typ
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA;
see Figure 32
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
500
5
560
610
700
Ω max
Ω typ
20
170
280
21
22
24
VS = 0 V to 10 V, IS = −1 mA
310
335
370
Ω max
Ω typ
Ω max
nA typ
VDD = +13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 33
±0.005
±0.1
0.01
±0.15
±0.2
±0.4
0.015
nA max
nA typ
VS = 1 V/10 V, VD = 1 V/10 V;
see Figure 33
±0.02
±0.1
±0.02
±0.1
0.015
±0.25
±0.6
±3.3
±0.25
±0.4
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
VS = VD = 1 V/10 V; see Figure 34
±0.02
±0.1
±0.02
±0.1
0.01
±0.25
±0.6
±3.3
±0.2
±0.4
±1.7
0.03
Rev. A | Page 6 of 28
nA typ
nA max
nA typ
nA max
nA typ
Data Sheet
Parameter
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
ADG5206/ADG5207
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 3
Transition Time, tTRANSITION
3
Unit
Test Conditions/Comments
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
Break-Before-Make Time Delay, tD
290
290
230
290
230
315
170
Charge Injection, QINJ
0.25
Off Isolation
±0.6
−90
Channel-to-Channel Crosstalk
−76
dB typ
−3 dB Bandwidth
ADG5206
ADG5207
Insertion Loss
50
105
8.55
MHz typ
MHz typ
dB typ
3.6
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
VS = 6 V, f = 1 MHz
71
36
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
75
40
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
tON (EN)
tOFF (EN)
440
480
550
320
340
370
360
390
450
45
CS (Off )
CD (Off )
ADG5206
ADG5207
CD (On), CS (On)
ADG5206
ADG5207
POWER REQUIREMENTS
IDD
±0.7
40
50
65
9/40
VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC typ
dB typ
µA typ
µA max
V min/V max
The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 10 V, or VS = 10 V and VD = 1 V.
The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 10 V.
3
Guaranteed by design; not subject to production test.
1
2
Rev. A | Page 7 of 28
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 37
VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = 0 V to 10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
RL = 50 Ω, CL = 5 pF; see Figure 41
GND = 0 V, VSS = 0 V
ADG5206/ADG5207
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Match Between Channels, ΔLeakage, IS (Off) 1
Drain Off Leakage, ID (Off )
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (On), IS (On) 2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
140
170
4
12
40
55
195
215
245
13
14
15
63
70
80
±0.005
±0.1
0.01
±0.02
±0.1
±0.02
±0.1
0.015
±0.15
±0.2
±0.4
0.015
VS = 0 V to 30 V, IS = −1 mA;
see Figure 32
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
nA max
nA typ
±0.25
±0.6
±3.3
±0.25
±0.4
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
VS = VD = 1 V/30 V;
see Figure 34
±0.02
±0.1
±0.02
±0.1
0.01
±0.25
±0.6
±3.3
±0.2
±0.4
±1.7
0.03
2.0
0.8
0.002
3
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
0.7
tOFF (EN)
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
225
290
215
265
170
215
90
tON (EN)
V
Ω typ
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 3
Transition Time, tTRANSITION
Unit
310
320
350
285
285
295
230
245
270
28
±3
±3
Rev. A | Page 8 of 28
nA typ
nA max
nA typ
nA max
nA typ
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC typ
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 37
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = 0 V to 30 V, RS = 0 Ω,
CL = 1 nF
Data Sheet
Parameter
Off Isolation
Channel-to-Channel Crosstalk
ADG5206/ADG5207
25°C
−90
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C
Unit
dB typ
−76
dB typ
55
115
5.65
MHz typ
MHz typ
dB typ
3.4
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
VS = 18 V, f = 1 MHz
62
32
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
66
35
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
−3 dB Bandwidth
ADG5206
ADG5207
Insertion Loss
CS (Off )
CD (Off )
ADG5206
ADG5207
CD (On), CS (On)
ADG5206
ADG5207
POWER REQUIREMENTS
IDD
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
80
100
130
9/40
VDD
The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 30 V, or VS = 30 V and VD = 1 V.
The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 30 V.
3
Guaranteed by design; not subject to production test.
1
2
Rev. A | Page 9 of 28
µA typ
µA max
V min/V max
GND = 0 V, VSS = 0 V
ADG5206/ADG5207
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5. ADG5206
Parameter
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
25°C
60°C
85°C
125°C
Unit
44
62
32
42
23
28
12
13
mA maximum
mA maximum
47
66
33
44
24
29
12
13
mA maximum
mA maximum
31
45
24
33
19
24
11
12
mA maximum
mA maximum
46
65
33
43
24
28
12
13
mA maximum
mA maximum
25°C
60°C
85°C
125°C
Unit
33
48
25
34
19
24
11
12
mA maximum
mA maximum
35
51
27
36
20
25
11
12
mA maximum
mA maximum
23
34
19
26
15
20
12
12
mA maximum
mA maximum
34
50
26
35
20
25
11
12
mA maximum
mA maximum
Table 6. ADG5207
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
Rev. A | Page 10 of 28
Data Sheet
ADG5206/ADG5207
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx, D, or Dx Pins
ADG5206
ADG5207
Continuous Current, Sx, D, or Dx
Pins2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
28-Lead TSSOP (4-Layer Board)
32-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
HBM ESD
(ESDA/JEDEC JS-001-2011)
ADG5206
All Pins
ADG5207
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
140 mA (pulsed at 1 ms, 10%
duty cycle maximum)
105 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
67.7°C/W
27.27°C/W
As per JEDEC J-STD-020
8 kV
8 kV
2 kV
8 kV
Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
2
See Table 5 and Table 6.
1
Rev. A | Page 11 of 28
ADG5206/ADG5207
Data Sheet
NC
VDD
NC
D
NC
NC
NC
VSS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
28 D
NC
2
27 VSS
NC
3
26 S8
S16
4
25 S7
S15
5
24 S6
S14
6
23 S5
S13
7
S12
8
S11
9
20 S2
S10 10
19 S1
S9 11
18 EN
GND 12
17 A0
NC 13
16 A1
A3 14
15 A2
S16
S15
S14
S13
S12
S11
S10
S9
22 S4
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
ADG5206
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
S8
S7
S6
S5
S4
S3
S2
S1
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
10714-004
GND
A3
A2
NC
NC
A1
A0
EN
9
10
11
12
13
14
15
16
21 S3
1
2
3
4
5
6
7
8
10714-003
ADG5206
TOP VIEW
(Not to Scale)
32
31
30
29
28
27
26
25
VDD
Figure 4. ADG5206 Pin Configuration (LFCSP)
Figure 3. ADG5206 Pin Configuration (TSSOP)
Table 8. ADG5206 Pin Function Descriptions
TSSOP
1
2, 3, 13
4
5
6
7
8
9
10
11
12
14
15
16
17
18
Pin No.
LFCSP
31
12, 13, 26, 27,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
11
14
15
16
Mnemonic
VDD
NC
Description
Most Positive Power Supply Potential.
No Connect. Not internally connected.
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
EN
Source Terminal 16. This pin can be an input or an output.
Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Drain Terminal. This pin can be an input or an output.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
28
NA
29
Exposed Pad
D
Rev. A | Page 12 of 28
Data Sheet
ADG5206/ADG5207
Table 9. ADG5206 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. A | Page 13 of 28
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data Sheet
1
28 DA
DB
2
27 VSS
NC
3
26 S8A
S8B
4
25 S7A
S7B
5
24 S6A
S6B
6
23 S5A
S5B
7
S4B
8
S3B
9
20 S2A
S2B 10
19 S1A
S1B 11
18 EN
GND 12
17 A0
NC 13
16 A1
NC 14
15 A2
22 S4A
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
9
10
11
12
13
14
15
16
21 S3A
ADG5207
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
A2
NC
NC
NC
A1
A0
EN
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
10714-005
ADG5207
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
10714-006
VDD
32
31
30
29
28
27
26
25
NC
DB
NC
VDD
NC
DA
NC
VSS
ADG5206/ADG5207
Figure 5. ADG5207 Pin Configuration (TSSOP)
Figure 6. ADG5207 Pin Configuration (LFCSP)
Table 10. ADG5207 Pin Function Descriptions
TSSOP
1
2
3, 13,
14
4
5
6
7
8
9
10
11
12
15
16
17
18
Pin No.
LFCSP
29
31
11, 12, 12, 26,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
14
15
16
Mnemonic
VDD
DB
NC
Description
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect. Not internally connected.
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
A2
A1
A0
EN
Source Terminal 8B. This pin can be an input or an output.
Source Terminal 7B. This pin can be an input or an output.
Source Terminal 6B. This pin can be an input or an output.
Source Terminal 5B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Source Terminal 5A. This pin can be an input or an output.
Source Terminal 6A. This pin can be an input or an output.
Source Terminal 7A. This pin can be an input or an output.
Source Terminal 8A. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Drain Terminal A. This pin can be an input or an output.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
28
NA
27
Exposed Pad
DA
Rev. A | Page 14 of 28
Data Sheet
ADG5206/ADG5207
Table 11. ADG5207 Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
Rev. A | Page 15 of 28
ADG5206/ADG5207
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
140
150
±18V
±20V
±22V
130
140
ON RESISTANCE (Ω)
110
100
90
80
120
110
100
90
80
70
70
–11.0
–5.5
0
5.5
11.0
16.5
22.0
VS, VD (V)
60
0
15
20
25
30
35
Figure 10. RON as a Function of VS, VD (36 V Single Supply)
200
±13.5V
±15V
±16.5V
150
10
VS, VD (V)
Figure 7. RON as a Function of VS, VD (±20 V Dual Supply)
160
5
10714-108
–16.5
10714-105
60
–22.0
TA = 25°C
180
140
130
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
TA = 25°C
130
120
ON RESISTANCE (Ω)
32.4V
36V
39.6V
TA = 25°C
120
110
100
90
+125°C
+85°C
+60°C
+25°C
–40°C
VDD = +15V
VSS = –15V
160
140
120
100
80
80
–8.50
–4.25
0
4.25
8.50
12.75
17.0
VS, VD (V)
60
–15
10714-106
60
–17.00 –12.75
5
10
+125°C
+85°C
+60°C
+25°C
–40°C
TA = 25°C
150
ON RESISTANCE (Ω)
140
260
210
160
15
VDD = +20V
VSS = –20V
130
120
110
100
90
80
110
60
0
2
4
6
8
10
12
VS, VD (V)
Figure 9. RON as a Function of VS, VD (12 V Single Supply)
60
–20
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 12. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
Rev. A | Page 16 of 28
10714-110
70
10714-107
ON RESISTANCE (Ω)
0
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
160
10.8V
12V
13.2V
310
–5
VS, VD (V)
Figure 8. RON as a Function of VS, VD (±15 V Dual Supply)
360
–10
10714-109
70
Data Sheet
ADG5206/ADG5207
410
150
VDD = 12V
VSS = 0V
100
360
210
160
+125°C
+85°C
+60°C
+25°C
–40°C
110
2
4
6
8
10
12
ID (OFF) + –
IS (OFF) – +
0
–150
–200
–250
IS (OFF) + –
ID (OFF) + –
–300
IS (OFF) – +
ID (OFF) – +
20
25
30
35
VS, VD (V)
–450
0
50
–20
0
LEAKAGE CURRENT (pA)
0
–40
–60
–80
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
20
40
80
100
120
TEMPERATURE (°C)
100
120
–100
–150
IS (OFF) + –
–200
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
60
80
–50
–250
–300
10714-113
LEAKAGE CURRENT (pA)
100
IS, ID (ON) + +
60
Figure 17. Leakage Currents vs. Temperature, 12 V Single Supply
20
IS, ID (ON) – –
40
TEMPERATURE (°C)
Figure 14. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
ID (OFF) – +
20
10714-115
15
IS, ID (ON) – –
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
IS, ID (ON) + +
IS, ID (ON) – –
–350
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 18. Leakage Currents vs. Temperature, 36 V Single Supply
Figure 15. Leakage Currents vs. Temperature, ±15 V Dual Supply
Rev. A | Page 17 of 28
10714-116
10
10714-112
60
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
IS, ID (ON) + +
–400
0
120
–50
80
–160
100
–100
–350
–140
80
0
100
–120
60
TEMPERATURE (°C)
VDD = 36V
VSS = 0V
120
–100
40
Figure 16. Leakage Currents vs. Temperature, ±20 V Dual Supply
140
5
20
50
+125°C
+85°C
+60°C
+25°C
–40°C
0
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
IS, ID (ON) + +
IS, ID (ON) – –
–300
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
IS (OFF) + –
–150
–250
Figure 13. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
160
–100
ID (OFF) – +
VS, VD (V)
180
–50
–200
60
0
0
10714-114
LEAKAGE CURRENT (pA)
260
10714-111
ON RESISTANCE (Ω)
50
310
ADG5206/ADG5207
Data Sheet
0
TA = 25°C
VDD = +15V
–20 VSS = –15V
–40
–40
–60
ADG5206
ADG5207
–80
NO DECOUPLING
CAPACITORS
–60
–80
DECOUPLING
CAPACITORS
–100
–100
–120
–120
–140
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–140
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Off Isolation vs. Frequency, ±15 V Dual Supply
10714-120
ACPSRR (dB)
TA = 25°C
VDD = +15V
–20 VSS = –15V
10714-117
OFF ISOLATION (dB)
0
Figure 22. ACPSRR vs. Frequency, ±15 V Dual Supply
0
–5
BETWEEN S1A AND S2A
BETWEEN S16 AND S1
BETWEEN S1A AND S8B
–20
–6
–7
ATTENUATION (dB)
CROSSTALK (dB)
–40
–60
–80
–100
–8
ADG5207
–9
–10
ADG5206
–11
–12
–120
100k
1M
10M
100M
1G
FREQUENCY (Hz)
10714-118
Figure 20. Crosstalk vs. Frequency, ±15 V Dual Supply
40
= +15V,
= +20V,
= +12V,
= +36V,
VSS
VSS
VSS
VSS
8
= –15V
= –20V
= 0V
= 0V
7
6
30
25
20
15
10
0
–20
1G
VDD
VDD
VDD
VDD
= +15V,
= +20V,
= +12V,
= +36V,
VSS
VSS
VSS
VSS
= –15V
= –20V
= 0V
= 0V
5
4
3
2
1
0
5
–1
TA = 25°C
DEMUX (DRAIN TO SOURCE)
–10
0
10
20
30
40
VS (V)
10714-119
CHARGE INJECTION (pC)
35
VDD
VDD
VDD
VDD
100M
Figure 23. Bandwidth
CHARGE INJECTION (pC)
45
10M
FREQUENCY (Hz)
Figure 21. Charge Injection vs. Source Voltage, Drain to Source
–2
–20
TA = 25°C
MUX (SOURCE TO DRAIN)
–10
0
10
20
30
40
VS (V)
Figure 24. Charge Injection vs. Source Voltage, Source to Drain
Rev. A | Page 18 of 28
10714-122
–160
10k
TA = 25°C
–14 VDD = +15V
VSS = –15V
–15
100k
1M
10714-121
–13
TA = 25°C
VDD = +15V
VSS = –15V
–140
Data Sheet
3.0
1.4
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
MUX (SOURCE TO DRAIN)
1.2
1.0
2.0
CHARGE INJECTION (pC)
CHARGE INJECTION (pC)
2.5
ADG5206/ADG5207
1.5
1.0
0.5
0
MUX (SOURCE TO DRAIN)
0.8
0.6
0.4
0.2
0
–0.2
–0.5
–8
–6
–4
–2
0
2
4
6
8
10
VS (V)
Figure 25. QINJ as a Function of VS for Different Temperatures, ±15 V Dual Supply
2.5
2
1
0
–5
0
5
10
15
7
8
9
10
MUX (SOURCE TO DRAIN)
1.5
1.0
0.5
0
–1.5
10714-201
–10
Figure 26. QINJ as a Function of VS for Different Temperatures, ±20 V Dual Supply
0
VDD
VDD
VDD
VDD
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V
= 0V
= –15V
= –20V
250
200
150
100
20
40
60
80
TEMPERATURE (°C)
100
120
10714-123
50
0
10
15
20
25
30
Figure 29. QINJ as a Function of VS for Different Temperatures, 36 V Single Supply
300
–20
5
VS (V)
450
TIME (ns)
6
–1.0
VS (V)
0
–40
5
–0.5
–1
350
4
2.0
3
400
3
–40°C
+25°C
+85°C
+125°C
MUX (SOURCE TO DRAIN)
4
–2
–15
2
Figure 28. QINJ as a Function of VS for Different Temperatures, 12 V Single Supply
3.0
–40°C
+25°C
+85°C
+125°C
1
VS (V)
CHARGE INJECTION (pC)
CHARGE INJECTION (pC)
5
0
10714-203
6
–0.6
10714-202
–0.4
10714-200
–1.0
–10
Figure 27. tTRANSITION Time vs. Temperature
Rev. A | Page 19 of 28
ADG5206/ADG5207
Data Sheet
100
60
TA = 25°C
VDD = +15V
VSS = –15V
50
80
TA = 25°C
VDD = +15V
VSS = –15V
60
CAPACITANCE (pF)
DRAIN OFF
40
20
40
SOURCE/DRAIN ON
30
DRAIN OFF
20
10
SOURCE OFF
SOURCE OFF
–10
–5
0
VS (V)
5
10
15
0
–15
10714-124
0
–15
Figure 30. ADG5206 Capacitance vs. Source Voltage, ±15 V Dual Supply
–10
–5
0
VS (V)
5
10
15
10714-125
CAPACITANCE (pF)
SOURCE/DRAIN ON
Figure 31. ADG5207 Capacitance vs. Source Voltage, ±15 V Dual Supply
Rev. A | Page 20 of 28
Data Sheet
ADG5206/ADG5207
TEST CIRCUITS
ID (ON)
V
S1
NC
D
A
S2
D
10714-300
IDS
VS
RON = V/IDS
S16
NC = NO CONNECT
VD
Figure 32. On Resistance
Figure 34. On Leakage
ID (OFF)
IS (OFF)
S1
A
VD
10714-302
S
D
A
VS
VD
10714-301
S16
A
Figure 33. Off Leakage
3V
ADDRESS
DRIVE (VIN)
tr < 20ns
tf < 20ns
50%
50%
VSS
VDD
VSS
A0
0V
VIN
tTRANSITION
VDD
S1
A1
50Ω
VS
S2
A2
A3
tTRANSITION
S3 TO S16
ADG52061
90%
3V
OUTPUT
OUTPUT
D
EN
GND
300Ω
35pF
10714-034
90%
0V
1SIMILAR CONNECTION FOR ADG5207.
Figure 35. Address to Output Switching Times, tTRANSITION
3V
ENABLE
DRIVE (VIN)
50%
VSS
VDD
VSS
A0
50%
S1
VS
A1
S2 TO S16
0V
A2
A3
tOFF (EN)
ADG52061
OUTPUT
0.9VOUT
D
EN
OUTPUT
VIN
50Ω
GND
300Ω
35pF
0.1VOUT
1SIMILAR
Figure 36. Enable Delay, tON (EN), tOFF (EN)
Rev. A | Page 21 of 28
CONNECTION FOR ADG5207.
10714-036
tON (EN)
0V
VDD
ADG5206/ADG5207
Data Sheet
VDD
VSS
VDD
VSS
3V
ADDRESS
DRIVE (VIN)
A0
VIN
0V
S1
A1
50Ω
VS
S2 TO S15
A2
A3
S16
80%
ADG52061
80%
OUTPUT
3V
OUTPUT
D
EN
GND
300Ω
35pF
10714-035
tBBM
1SIMILAR CONNECTION FOR ADG5207.
Figure 37. Break-Before-Make Time Delay, tD
VDD
VSS
VDD
VSS
A0
3V
A1
VIN
A2
0V
A3
VOUT
RS
ΔVOUT
ADG52061
Sx
D
VOUT
EN
QINJ = CL × ΔVOUT
CL
1nF
GND
VS
10714-037
VIN
1SIMILAR CONNECTION FOR ADG5207.
Figure 38. Charge Injection
VSS
VDD
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
Sx
VSS
0.1µF
0.1µF
VDD
50Ω
NETWORK
ANALYZER
VSS
50Ω
Sx
50Ω
VS
VS
D
D
RL
50Ω
VOUT
VS
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
Figure 39. Off Isolation
VDD
VSS
VDD
S1
VSS
RL
50Ω
D
S2
VS
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
10714-030
VOUT
0.1µF
Figure 40. Channel-to-Channel Crosstalk
Rev. A | Page 22 of 28
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 41. Bandwidth
0.1µF
NETWORK
ANALYZER
RL
50Ω
GND
10714-032
GND
VOUT
10714-033
VDD
Data Sheet
ADG5206/ADG5207
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN represents digital input capacitance.
ISS
ISS represents the negative supply current.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
RFLAT (ON) is the flatness defined as the difference between the
maximum and the minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINH
VINH is the minimum input voltage for Logic 1.
On Response
On response is the frequency response of the on switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 23 of 28
ADG5206/ADG5207
Data Sheet
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is turned
off. The ADG5206/ADG5207 high voltage switches allow singlesupply operation from 9 V to 40 V and dual-supply operation
from ±9 V to ±22 V.
NMOS
PMOS
TRENCH ISOLATION
P WELL
N WELL
TRENCH
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latchup proof switch.
Rev. A | Page 24 of 28
BURIED OXIDE LAYER
HANDLE WAFER
Figure 42. Trench Isolation
10714-038
In the ADG5206/ADG5207, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
Data Sheet
ADG5206/ADG5207
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
SEATING
PLANE
8°
0°
0.20
0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 43. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 44. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 × 5 mm Body, Very Very Thin Quad (CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5206BRUZ
ADG5206BRUZ-RL7
ADG5206BCPZ-RL7
ADG5207BRUZ
ADG5207BRUZ-RL7
ADG5207BCPZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
Package Option
RU-28
RU-28
CP-32-12
RU-28
RU-28
CP-32-12
ADG5206/ADG5207
Data Sheet
NOTES
Rev. A | Page 26 of 28
Data Sheet
ADG5206/ADG5207
NOTES
Rev. A | Page 27 of 28
ADG5206/ADG5207
Data Sheet
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10714-0-5/13(A)
Rev. A | Page 28 of 28