MB91520 Series
32-bit FR81S Microcontroller
The MB91520 series is a Cypress 32-bit microcontroller designed for automotive devices. This series contains the FR81S CPU
which is compatible with the FR family.
Note:This series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of
sub-clock, CSV initial value and LVD initial value. Please see "Ordering Information" for details.
Features
FR81S CPU Core
Peripheral Functions
32-bit RISC, load/store architecture, pipeline 5-stage
structure
Clock generation (equipped with SSCG function)
Main oscillation (4 MHz to 16 MHz)
Sub oscillation (32 kHz) or none sub oscillation
PLL multiplication rate : 1 to 20 times
Equipped with a 100 kHz CR oscillator
Maximum operating frequency: 80 MHz (Source oscillation
= 4.0 MHz and 20 multiplied (PLL clock multiplication
system))
General-purpose register : 32 bits × 16 sets
16-bit fixed length instructions (basic instruction),
1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift order etc.
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead reduction during branch process
Register interlock function
Easy assembler writing
The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of
program and data access.
Instruction compatibility with the FR Family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for
instructions and the data.
Control access privilege in both privilege mode and
user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register 32-bit × 16 sets
Cypress Semiconductor Corporation
Document Number: 002-04662 Rev. *F
•
Built-in program flash memory capacity
MB91F522: 256 +64 KB
MB91F523: 384 + 64 KB
MB91F524: 512 + 64 KB
MB91F525: 768 + 64 KB
MB91F526: 1024 + 64 KB
Flash memory for built-in data (WorkFlash) 64 KB
Built-in RAM capacity
Main RAM
MB91F522: 48 KB
MB91F523: 48 KB
MB91F524: 64 KB
MB91F525: 96 KB
MB91F526: 128 KB
Backup RAM 8 KB
General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub
oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub
oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub
oscillation)
MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub
oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub
oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub
oscillation)
Included I2C open drain corresponding ports:16 sets
External bus interface
22-bit address, 16-bit data
DMA Controller
Up to 16 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and
software)
A/D converter (successive approximation type)
12-bit resolution : Max. 48 ch (32 ch + 16 ch)
Conversion time : 1.4 μs
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 5, 2017
MB91520 Series
D/A converter (R-2R type)
8-bit resolution : 2 ch
External interrupt input: 8 channels × 2 units total
16 channels
Level ("H" / "L"), or edge detection (rising or falling)
enabled
Multi-function serial communication (built-in
transmission/reception FIFO memory) : Max.12 channels
5 V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11
CMOS hysteresis input
< UART (Asynchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions
provided
DMA transfer support
<CSIO (Synchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
SPI supported; master and slave systems supported;
5 to 16, 20, 24, 32-bit data length can be set.
Built-in dedicated baud rate generator (Master
operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
LIN protocol revision 2.1 supported
Master and slave systems supported
Framing error and overrun error detection
LIN synch break generation and detection; LIN synch
delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the reload
counter
DMA transfer support
Hard assist function
< I2 C >
2 channels ch.3 , ch.4 Standard mode/fast mode
supported.
6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode
supported.
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Standard mode (Max. 100 kbps) / fast mode (Max. 400
kbps) supported
DMA transfer supported (for transmission only)
CAN Controller (CAN) : 3 channels
Transfer speed : Up to 1 Mbps
128-transmission/reception message buffering :
1 channel (ch.0),
Document Number: 002-04662 Rev. *F
64-transmission/reception message buffering :
2 channels (ch.1 and ch.2)
PPG: 16-bit × Max. 48 channels
LED drive output 4 channels 11 ch to 14 ch
Reload timer : 16-bit × Max.8 channels
Free-run timer :
16-bit × 3 channels
32-bit × Max 3 channels
Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Waveform generator : 6 channels
Up/Down counter
8-/16-bit Up/Down counter × 2 channels
Real-time clock (RTC) (for day, hours, minutes, seconds)
Main or sub oscillation frequency can be selected for
the operation clock
Calibration: Real-time clock (RTC) of the subclock drive
The main clock to sub clock ratio can be corrected by
setting the real-time clock prescaler
Clock Supervisor
Monitoring abnormality (by damaged quartz, etc.) of
suboscillation (32 kHz) (dual clock products)
of the outside and main oscillation (4 MHz)
When abnormality is detected, it switches to the CR
clock.
Initial value ON/OFF can be selected by the part
number.
Base timer : Max.2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can
be selected and used
As for the PWC function and the reload timer function,
a pair of 16-bit timers can be used as one 32-bit timer
in the cascade mode
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog (possible to set the valid range for
counter clearing)
NMI (non-maskable interrupt)
Interrupt controller
Interrupt request batch read
The interrupt existence from two or more peripherals
can be read by a series of register.
I/O relocation
Peripheral function pins can be reassigned.
Low-power consumption mode
Sleep / Stop / Watch / Sub RUN mode
Stop (power shutdown) / Watch (power shutdown)
mode
Page 2 of 280
MB91520 Series
Power-on reset
Low-voltage detection reset (independently monitor the
external power supply and the internal power supply)
The external power supply can select initial value
ON/OFF by the part number.
Device Package : 176/144/120/100/80/64
CMOS 90 nm Technology
Power supplies
5 V Power supply
The internal 1.2 V is generated from 5 V with the
voltage step-down circuit
Document Number: 002-04662 Rev. *F
Page 3 of 280
MB91520 Series
Contents
1.
Product Lineup .......................................................................................................................................... 5
2.
Pin Assignment ....................................................................................................................................... 12
3.
Pin Description ........................................................................................................................................ 18
4.
I/O Circuit Type ....................................................................................................................................... 35
5.
Handling Precautions .............................................................................................................................. 40
6.
Handling Devices .................................................................................................................................... 44
7.
Block Diagram ......................................................................................................................................... 47
8.
Memory Map ........................................................................................................................................... 53
9.
I/O Map.................................................................................................................................................... 55
10. Interrupt Vector Table ............................................................................................................................ 109
11. Electrical Characteristics ....................................................................................................................... 133
12. Example Characteristics ....................................................................................................................... 193
13. Ordering Information MB91F52xxxB*1 .................................................................................................. 196
14. Ordering Information MB91F52xxxC*1 .................................................................................................. 203
15. Ordering Information MB91F52xxxD .................................................................................................... 210
16. Ordering Information MB91F52xxxE..................................................................................................... 214
17. Package Dimensions ............................................................................................................................ 218
18. Errata..................................................................................................................................................... 225
19. Major Changes ...................................................................................................................................... 228
Document Number: 002-04662 Rev. *F
Page 4 of 280
MB91520 Series
1.
Product Lineup
Product Lineup Comparison 64 Pins
MB91F522B
MB91F523B
MB91F524B
MB91F525B
MB91F526B
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5 ns (80 MHz)
Flash Capacity (Program)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB (1024+64) KB
Flash Capacity (Data)
64 KB
RAM Capacity
(48+8) KB
(64+8) KB
(96+8) KB
(128+8) KB
External BUS I/F
None
(22 address/16 data/4 cs)
DMA Transfer
16 ch
16-bit Base Timer
None
Free-run Timer
16 bit × 3 ch, 32 bit × 1 ch
Input capture
16 bit × 4 ch, 32 bit × 5 ch
Output Compare
16 bit × 6 ch, 32 bit × 4 ch
16-bit Reload Timer
7 ch
PPG
16 bit × 21 ch
Up/down Counter
2 ch
Clock Supervisor
Yes
External Interrupt
8 ch × 2 units
A/D converter
12 bit × 13 ch (1 unit), 12 bit × 13 ch (1 unit)
D/A converter (8 bit)
1 ch
Multi-Function Serial Interface
8 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
44 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
NMI request function
Yes
Operation guaranteed temperature (TA)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V *2
Package
LQD064
*1: Only channel 5, channel 6 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 5 of 280
MB91520 Series
Product Lineup Comparison 80 Pins
MB91F522D
System Clock
Minimum instruction execution time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22 address/16 data/4 cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
MB91F523D
MB91F524D
MB91F525D
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
MB91F526D
(1024+64) KB
(128+8) KB
None
16 ch
1 ch
16 bit × 3 ch, 32 bit × 2 ch
16 bit × 4 ch, 32 bit × 5 ch
16 bit × 6 ch, 32 bit × 4 ch
7 ch
16 bit × 27 ch
2 ch
Yes
8 ch × 2 units
12 bit × 16 ch (1 unit), 12 bit × 16 ch (1 unit)
D/A converter (8 bit)
1 ch
Multi-Function Serial Interface
9 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
56 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
Operation guaranteed temperature
-40 °C to +125 °C
(TA)
Power supply
2.7 V to 5.5 V *2
Package
LQH080
*1: Only channel 5, channel 6 and channel 11 support the I 2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 6 of 280
MB91520 Series
Product Lineup Comparison 100 Pins
MB91F522F
System Clock
Minimum instruction execution time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22 address/16 data/4 cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
MB91F523F
MB91F524F
MB91F525F
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
MB91F526F
(1024+64) KB
(128+8) KB
None
16 ch
1 ch
16 bit × 3 ch, 32 bit × 3 ch
16 bit × 4 ch, 32 bit × 6 ch
16 bit × 6 ch, 32 bit × 6 ch
8 ch
16 bit × 34 ch
2 ch
Yes
8 ch × 2 units
12 bit × 21 ch (1 unit), 12 bit × 16 ch (1 unit)
D/A converter (8 bit)
2 ch
Multi-Function Serial Interface
12 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
76 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
Operation guaranteed temperature
-40 °C to +125 °C
(TA)
Power supply
2.7 V to 5.5 V *2
Package
LQI100
*1: Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 7 of 280
MB91520 Series
Product Lineup Comparison 120 Pins
MB91F522J
System Clock
Minimum instruction execution time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22 address/16 data/4 cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
MB91F523J
MB91F524J
MB91F525J
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
MB91F526J
(1024+64) KB
(128+8) KB
None
16 ch
2 ch
16 bit × 3 ch, 32 bit × 3 ch
16 bit × 4 ch, 32 bit × 6 ch
16 bit × 6 ch, 32 bit × 6 ch
8 ch
16 bit × 38 ch
2 ch
Yes
8 ch × 2 units
12 bit × 26 ch (1 unit), 12 bit × 16 ch (1 unit)
D/A converter (8 bit)
2 ch
Multi-Function Serial Interface
12 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
96 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
Operation guaranteed temperature (TA)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V *2
Package
LQM120
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 8 of 280
MB91520 Series
Product Lineup Comparison 144 Pins
MB91F522K
System Clock
Minimum instruction execution time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22 address/16 data/4 cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
MB91F523K
MB91F524K
MB91F525K
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
MB91F526K
(1024+64) KB
(128+8) KB
Yes
16 ch
2 ch
16 bit × 3 ch, 32 bit × 3 ch
16 bit × 4 ch, 32 bit × 6 ch
16 bit × 6 ch, 32 bit × 6 ch
8 ch
16 bit × 44 ch
2 ch
Yes
8 ch × 2 units
12 bit × 32 ch (1 unit), 12 bit × 16 ch (1 unit)
D/A converter (8 bit)
2 ch
Multi-Function Serial Interface
12 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
120 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
Operation guaranteed temperature (TA)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V *2
Package
LQS144, LQN144
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 9 of 280
MB91520 Series
Product Lineup Comparison 176 Pins
MB91F522L
MB91F523L
MB91F524L
MB91F525L
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
MB91F526L
System Clock
Minimum instruction execution time
Flash Capacity (Program)
(1024+64) KB
Flash Capacity (Data)
RAM Capacity
(128+8) KB
External BUS I/F
Yes
(22 address/16 data/4 cs)
DMA Transfer
16 ch
16-bit Base Timer
2 ch
Free-run Timer
16 bit × 3 ch, 32 bit × 3 ch
Input capture
16 bit × 4 ch, 32 bit × 6 ch
Output Compare
16 bit × 6 ch, 32 bit × 6 ch
16-bit Reload Timer
8 ch
PPG
16 bit × 48 ch
Up/down Counter
2 ch
Clock Supervisor
Yes
External Interrupt
8 ch × 2 units
A/D converter
12 bit × 32 ch (1 unit), 12 bit × 16 ch (1 unit)
D/A converter (8 bit)
2 ch
Multi-Function Serial Interface
12 ch*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
152 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
Operation guaranteed temperature (TA)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V *2
Package
LQP176
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 10 of 280
MB91520 Series
Table for Clock Supervisor and External Low Voltage Detection Reset Initial Value ON/OFF
Clock
CSV Initial Value
LVD Initial Value
ON
single
OFF
ON
Dual
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Function
S
U
H
K
W
Y
J
L
ＭＢ９１Ｆ５２Ｘ□△○
│││└→Ｒｅｖｉｓｉｏｎ：Ｂ, Ｃ, Ｄ, Ｅ
││└─→Ｆｕｎｃｔｉｏｎ：See the table for clock supervisor and external
｜｜
low voltage detection reset initial value ON/OFF.
│└──→ＰＫＧ Ｔｙｐｅ：Ｂ ６４ｐｉｎ
│
Ｄ ８０ ｐｉｎ
│
Ｆ １００ ｐｉｎ
│
Ｊ １２０ ｐｉｎ
│
Ｋ １４４ ｐｉｎ
│
Ｌ １７６ ｐｉｎ
└───→Ｍｅｍｏｒｙ Ｓｉｚｅ：２ ２５６ＫＢ
３ ３８４ＫＢ
４ ５１２ＫＢ
５ ７６８ＫＢ
６ １ＭＢ
Document Number: 002-04662 Rev. *F
Page 11 of 280
MB91520 Series
2.
Pin Assignment
MB91F52xB
MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
VSS
1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
2
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
3
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
4
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
5
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
6
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
7
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
8
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0
9
MD1
MD0
P126/SIN0_0/INT6_0
DEBUGIF
52
51
50
49
X1
X0
54
53
X1A/P135/DTTI_0
VSS
56
55
RSTX
X0A/P136
58
57
C
VSS
60
59
P006/ADTG1_1/INT2_1/TX2(64)
P005/ADTG0_1/INT7_1/RX2(64)
62
61
VCC
P011/WOT/INT3_1
64
63
(TOP VIEW)
●
TOP VIEW
MB91F522B,
MB91F523B,
MB91F524B,
MB91F525B,
MB91F526B
48
P122/SIN6_0/AN31/OCU8_0/INT9_1
47
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
46
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
45
P110/TX1(64)/SCS63_0/AN22
44
NM IX
43
P105/AN17/PPG13_0
42
P104/AN16/PPG12_0
41
P103/AN15/PPG11_0
40
P102/AN14/PPG10_0/INT10_0
39
AVCC0
38
AVRH0
P036/OCU7_1/TOT5_0/BIN0_0
10
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
11
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
12
37
AVS S 0/AVRL0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
13
36
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
14
35
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P047/AN45/TRG8_0/TIN3_2/SOT0_1
15
34
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
P053/AN44/PPG35_0/INT14_1/SCK0_1
16
33
VSS
LQFP-64
LQD064
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
* In a single clock product, pin 56 and pin 57 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 12 of 280
MB91520 Series
MB91F52xD
MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
62 DEBUGIF
61 VCC
64 P127/SOT0_0
63 P126/SIN0_0/INT6_0
66 MD1
65 MD0
68 X1
67 X0
70 X1A/P135/DTTI_0
69 VSS
72 RSTX
71 X0A/P136
74 C
73 VSS
76 P003/SIN2_0/TIOB1_1/INT3_0
75 P001/TIOA1_1
78 P006/SCS2_0/ADTG1_1/INT2_1/TX2(64)
77 P005/SCK2_0/ADTG0_1/INT7_1/RX2(64)
80 VCC
79 P011/WOT/SOT2_1/INT3_1
(TOP VIEW)
●
VSS
1
60
VSS
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
2
59
P122/SIN6_0/AN31/OCU8_0/INT9_1
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
3
58
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P026/SCK4_1/PPG26_0/TIN3_0
4
57
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
5
56
P114/SCS61_0/AN26/PPG18_0/RTO2_0
P031/SCS42_1/PPG29_0
6
55
P110/TX1(64)/SCS63_0/AN22
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
7
54
NM IX
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
8
53
P107/AN19/PPG15_0
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
9
52
P105/AN17/PPG13_0
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
10
51
P104/AN16/PPG12_0
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0
11
50
P103/AN15/PPG11_0
P036/OCU7_1/TOT5_0/BIN0_0
12
49
P102/AN14/PPG10_0/INT10_0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
13
48
P100/AN12/PPG8_0
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
14
47
AVCC0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
15
46
AVRH0
P044/SCS9_0/ICU6_1/TRG2_1
16
45
AVS S 0/AVRL0
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
17
44
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P047/AN45/TRG8_0/TIN3_2/SOT0_1
18
43
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P053/AN44/PPG35_0/INT14_1/SCK0_1
19
42
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
VCC
20
41
VSS
TOP VIEW
MB91F522D,
MB91F523D,
MB91F524D,
MB91F525D,
MB91F526D
LQFP-80
LQH080
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
* In a single clock product, pin 70 and pin 71 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 13 of 280
MB91520 Series
MB91F52xF
MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
VSS
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/SOT4_1/PPG25_0/TIN2_0
P026/SCK4_1/PPG26_0/TIN3_0
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P030/SCS41_1/PPG28_0/TOT1_0
P031/SCS42_1/PPG29_0/TOT2_0
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/OCU6_1/TOT6_0/ZIN0_0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/ICU7_1/TRG1_1
P044/SCS9_0/ICU6_1/TRG2_1
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P047/AN45/TRG8_0/TIN3_2/SOT0_1
P053/AN44/PPG35_0/INT14_1/SCK0_1
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
77 DEBUGIF
76 VCC
79 P127/SOT0_0
78 P126/SIN0_0/INT6_0
82 MD1
81 MD0
80 P130/SCK0_0
84 X1
83 X0
87 X0A/P136
86 X1A/P135/DTTI_0
85 VSS
89 P133/TX2(64)
88 RSTX
92 VSS
91 P144/SCK1_1
90 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
94 P000/SIN1_0/INT2_0
93 C
97 P005/SCK2_0/ADTG0_1/INT7_1
96 P003/SIN2_0/TIOB1_1/INT3_0
95 P001/SOT1_0/TIOA1_1
99 P011/WOT/SOT2_1/INT3_1
98 P006/SCS2_0/ADTG1_1/INT2_1
100 VCC
(TOP VIEW)
●
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TOP VIEW
MB91F522F,
MB91F523F,
MB91F524F,
MB91F525F,
MB91F526F
LQFP-100
LQI100
VSS
P122/SIN6_0/AN31/OCU8_0/INT9_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0
P111/RX1(64)/SCS62_0/AN23/INT1_0
P110/TX1(64)/SCS63_0/AN22
NMIX
P107/AN19/PPG15_0
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0
P101/SOT7_0/SDA7/AN13/PPG9_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)/SCS11_0/AN9
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
VSS
50 VCC
49 P087/DAO0/PPG7_0/INT8_0
48 P086/DAO1/PPG6_0
47 P082/SIN5_0/AN1/PPG2_0
46 P081/SOT5_0/SDA5/AN0/PPG1_0
45 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
44 P152/SCS53_0
43 P073/AN33/ICU3_2
42 P072/SIN4_0/AN34/ICU2_2/INT5_0
41 P071/SCK4_2/AN35/ICU1_2/MONCLK
40 P070/ICU0_2
39 P067/AN36/FRCK5_0/AIN0_1
38 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
37 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
36 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
35 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
34 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
33 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
32 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
31 AVSS1/AVRL1
30 AVRH1
29 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
28 AVCC1
27 P055/SIN10_0/AN43/PPG37_0/TIN4_1
26 VSS
* In a single clock product, pin 86 and pin 87 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 14 of 280
MB91520 Series
MB91F52xJ
MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
VSS
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/SOT3_1/TRG6_1/TRG4_0
P022/SCK3_1/TRG7_1/TRG5_0
P023/SCS3_1/PPG32_0/TIN0_0
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/SOT4_1/PPG25_0/TIN2_0
P026/SCK4_1/PPG26_0/TIN3_0
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P030/SCS41_1/PPG28_0/TOT1_0
P031/SCS42_1/PPG29_0/TOT2_0
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/OCU6_1/TOT6_0/ZIN0_0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/ICU7_1/TRG1_1
P044/SCS9_0/ICU6_1/TRG2_1
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/ICU4_1/TRG4_1
P047/AN45/TRG8_0/TIN3_2/SOT0_1
P050/TRG5_1/PPG33_0
P053/AN44/PPG35_0/INT14_1/SCK0_1
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
91 VCC
92 DEBUGIF
93 P125/OCU11_0
94 P126/SIN0_0/INT6_0
95 P127/SOT0_0
96 P130/SCK0_0
97 MD0
98 MD1
99 X0
100 X1
101 VSS
102 X1A/P135/DTTI_0
103 X0A/P136
104 RSTX
105 P132/SCS1_0/ADTG1_0
106 P133/TX2(64)
107 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
108 P144/SCK1_1
109 VSS
110 C
111 P000/SIN1_0/TIOA0_1/INT2_0
112 P001/SOT1_0/TIOA1_1
113 P002/SCK1_0/TIOB0_1
114 P003/SIN2_0/TIOB1_1/INT3_0
115 P005/SCK2_0/ADTG0_1/INT7_1
116 P006/SCS2_0/ADTG1_1/INT2_1
117 P007
118 P010
119 P011/WOT/SOT2_1/TIOA0_0/INT3_1
120 VCC
(TOP VIEW)
●
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
TOP VIEW
MB91F522J,
MB91F523J,
MB91F524J,
MB91F525J,
MB91F526J
LQFP-120
LQM120
VSS
P122/SIN6_0/AN31/OCU8_0/INT9_1
P120/AN30/OCU6_0/PPG22_0/INT9_0
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0
P113/AN25/PPG17_0/RTO1_0
P112/AN24/PPG16_0/RTO0_0
P111/RX1(64)/SCS62_0/AN23/INT1_0
P110/TX1(64)/SCS63_0/AN22
NMIX
P155/AN21
P154/AN20
P107/AN19/PPG15_0
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0
P101/SOT7_0/SDA7/AN13/PPG9_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)/SCS11_0/AN9
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
P056/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P074/SCK4_0/SCL4
P075/SIN3_0/INT4_0
P076/SOT3_0/SDA3
P077/SCK3_0/SCL3
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
* In a single clock product, pin 102 and pin 103 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 15 of 280
MB91520 Series
MB91F52xK
MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P017/D31/TRG2_0
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0
P052/A20/PPG34_0/INT14_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109 VCC
110 DEBUGIF
111 P124/OCU10_0
112 P125/OCU11_0
113 P126/SIN0_0/INT6_0
114 P127/SOT0_0
115 P130/SCK0_0
116 MD0
117 MD1
118 X0
119 X1
120 VSS
121 X1A/P135/DTTI_0
122 X0A/P136
123 RSTX
124 P131/ADTG0_0
125 P132/SCS1_0/ADTG1_0
126 P133/TX2(64)
127 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
128 P144/SCK1_1
129 VSS
130 C
131 P000/D16/SIN1_0/TIOA0_1/INT2_0
132 P001/D17/SOT1_0/TIOA1_1
133 P002/D18/SCK1_0/TIOB0_1
134 P003/D19/SIN2_0/TIOB1_1/INT3_0
135 P004/D20/SOT2_0
136 P005/D21/SCK2_0/ADTG0_1/INT7_1
137 P006/D22/SCS2_0/ADTG1_1/INT2_1
138 P007/D23
139 P010/D24
140 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
141 P012/D26/TIOB0_0
142 P013/D27/TIOA1_0
143 P014/D28/TIOB1_0
144 VCC
(TOP VIEW)
●
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TOP VIEW
MB91F522K,
MB91F523K,
MB91F524K,
MB91F525K,
MB91F526K
LQS144/LQN144
LQFP-144
VSS
P123/OCU9_0
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0
P120/AN30/OCU6_0/PPG22_0/INT9_0
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0
P113/AN25/PPG17_0/RTO1_0
P112/AN24/PPG16_0/RTO0_0
P111/RX1(64)/SCS62_0/AN23/INT1_0
P110/TX1(64)/SCS63_0/AN22
NMIX
P155/AN21
P154/AN20
P107/AN19/PPG15_0
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0
P101/SOT7_0/SDA7/AN13/PPG9_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
VSS
72 VCC
71 P087/DAO0/PPG7_0/INT8_0
70 P086/DAO1/PPG6_0
69 P085/PPG5_0
68 P084/SCS51_0/AN3/PPG4_0
67 P083/SCS50_0/AN2/PPG3_0
66 P082/SIN5_0/AN1/PPG2_0
65 P081/SOT5_0/SDA5/AN0/PPG1_0
64 P080/SCS52_0/PPG0_0
63 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
62 P152/SCS53_0
61 P077/SCK3_0/SCL3
60 P076/SOT3_0/SDA3
59 P075/SIN3_0/INT4_0
58 P074/SCK4_0/SCL4
57 P073/SOT4_0/SDA4/AN33/ICU3_2
56 P072/SIN4_0/AN34/ICU2_2/INT5_0
55 P071/SCK4_2/AN35/ICU1_2/MONCLK
54 P070/ICU0_2
53 P067/AN36/FRCK5_0/AIN0_1
52 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
51 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
50 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
49 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
48 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
47 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
46 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
45 P143/SOT10_0/SDA10/PPG39_0/TOT4_1
44 P142/SCK10_0/SCL10/PPG38_0/TIN7_1
43 AVSS1/AVRL1
42 AVRH1
41 P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
40 AVCC1
39 P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
38 P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
37 VSS
* In a single clock product, pin 121 and pin 122 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 16 of 280
MB91520 Series
MB91F52xL
MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P170/PPG36_1
P017/D31/TRG2_0
P171/PPG37_1
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P172/PPG38_1
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P173/PPG39_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P174/TRG8_1
P175/TRG9_1
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P176/TRG10_0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P177/TRG11_0
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0
P052/A20/PPG34_0/INT14_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
133 VCC
134 DEBUGIF
135 P160/PPG30_1
136 P161/PPG31_1
137 P124/OCU10_0
138 P125/OCU11_0
139 P126/SIN0_0/INT6_0
140 P127/SOT0_0
141 P130/SCK0_0
142 P162/TRG5_2
143 P163/TRG6_2
144 MD0
145 MD1
146 X0
147 X1
148 VSS
149 X1A/P135/DTTI_0
150 X0A/P136
151 RSTX
152 P131/ADTG0_0
153 P132/SCS1_0/ADTG1_0
154 P133/TX2(64)
155 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
156 P144/SCK1_1
157 VSS
158 C
159 P000/D16/SIN1_0/TIOA0_1/INT2_0
160 P001/D17/SOT1_0/TIOA1_1
161 P002/D18/SCK1_0/TIOB0_1
162 P003/D19/SIN2_0/TIOB1_1/INT3_0
163 P004/D20/SOT2_0
164 P164/PPG32_1
165 P005/D21/SCK2_0/ADTG0_1/INT7_1
166 P165/PPG33_1
167 P006/D22/SCS2_0/ADTG1_1/INT2_1
168 P007/D23
169 P166/PPG34_1
170 P010/D24
171 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
172 P012/D26/TIOB0_0
173 P167/PPG35_1
174 P013/D27/TIOA1_0
175 P014/D28/TIOB1_0
176 VCC
(TOP VIEW)
●
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
TOP VIEW
MB91F522L,
MB91F523L,
MB91F524L,
MB91F525L,
MB91F526L
LQFP-176
LQP176
VSS
P123/OCU9_0
P197/PPG29_1
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0
P120/AN30/OCU6_0/PPG22_0/INT9_0
P196/FRCK3_1/PPG28_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0
P195/FRCK4_1/PPG27_1
P194/FRCK5_1/PPG26_1
P113/AN25/PPG17_0/RTO1_0
P112/AN24/PPG16_0/RTO0_0
P111/RX1(64)/SCS62_0/AN23/INT1_0
P110/TX1(64)/SCS63_0/AN22
NMIX
P155/AN21
P154/AN20
P193/PPG25_1
P107/AN19/PPG15_0
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0
P101/SOT7_0/SDA7/AN13/PPG9_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P192/PPG24_1/TOT1_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
P191/TIN1_1
P190/TIN0_1
VSS
88 VCC
87 P087/DAO0/PPG7_0/INT8_0
86 P086/DAO1/PPG6_0
85 P085/PPG5_0
84 P084/SCS51_0/AN3/PPG4_0
83 P083/SCS50_0/AN2/PPG3_0
82 P082/SIN5_0/AN1/PPG2_0
81 P081/SOT5_0/SDA5/AN0/PPG1_0
80 P080/SCS52_0/PPG0_0
79 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
78 P152/SCS53_0
77 P077/SCK3_0/SCL3
76 P076/SOT3_0/SDA3
75 P075/SIN3_0/INT4_0
74 P074/SCK4_0/SCL4
73 P187/PPG47_0
72 P186/PPG46_0
71 P073/SOT4_0/SDA4/AN33/ICU3_2
70 P072/SIN4_0/AN34/ICU2_2/INT5_0
69 P071/SCK4_2/AN35/ICU1_2/MONCLK
68 P070/ICU0_2
67 P067/AN36/FRCK5_0/AIN0_1
66 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
65 P185/PPG45_0
64 P184/PPG44_0
63 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
62 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
61 P183/PPG43_0
60 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
59 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
58 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
57 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
56 P182/PPG42_0
55 P143/SOT10_0/SDA10/PPG39_0/TOT4_1
54 P142/SCK10_0/SCL10/PPG38_0/TIN7_1
53 AVSS1/AVRL1
52 AVRH1
51 P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
50 AVCC1
49 P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
48 P181/PPG41_0
47 P180/PPG40_0
46 P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
45 VSS
* In a single clock product, pin 149 and pin 150 are the general-purpose ports.
Document Number: 002-04662 Rev. *F
Page 17 of 280
MB91520 Series
3.
Pin Description
Pin No.
64
-
-
-
-
-
2 *1
-
-
-
80
-
-
-
-
-
2 *1
-
-
-
100
-
-
-
-
-
2 *1
-
-
-
120
-
-
-
-
-
2 *1
3 *1
4 *1
5 *1
144
2
3
-
4
-
5
6
7
8
Pin Name
Polarity
P015
-
176
2
3
4
5
6
7
8
9
10
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
General-purpose I/O port
D29
-
TRG0_0
-
PPG trigger 0 input (0)
P016
-
General-purpose I/O port
D30
-
TRG1_0
-
P170
-
PPG36_1
-
P017
-
D31
-
TRG2_0
-
P171
-
PPG37_1
-
A
A
External bus data bit29 I/O (0)
External bus data bit30 I/O (0)
PPG trigger 1 input (0)
A
General-purpose I/O port
PPG ch.36 output (1)
General-purpose I/O port
A
External bus data bit31 I/O (0)
PPG trigger 2 input (0)
A
General-purpose I/O port
PPG ch.37 output (1)
P020
-
General-purpose I/O port
ASX *2, *3, *4, *5
-
External bus/Address strobe output
SIN3_1
-
TRG3_0
-
F
Multi-function serial ch.3 serial data input (1)
PPG trigger 3 input (0)
TIN0_2
-
Reload timer ch.0 event input (2)
RTO5_1
-
Waveform generator ch.5 output pin (1)
P021
-
General-purpose I/O port
CS0X *5
-
SOT3_1
-
TRG6_1
-
External bus chip select 0 output
Multi-function serial ch.3 serial data output
(1)
PPG trigger 6 input (1)
TRG4_0
-
PPG trigger 4 input (0)
P022
-
General-purpose I/O port
CS1X *5
-
SCK3_1
-
TRG7_1
-
PPG trigger 7 input (1)
TRG5_0
-
PPG trigger 5 input (0)
A
External bus chip select 1 output
F
Multi-function serial ch.3 clock I/O (1)
P023
-
General-purpose I/O port
RDX *5
-
External bus/Read strobe output
SCS3_1
-
PPG32_0
-
PPG ch.32 output (0)
TIN0_0
-
Reload timer ch.0 event input (0)
A
Serial chip select 3 output (1)
Page 18 of 280
MB91520 Series
Pin No.
64
3 *1
-
-
-
4 *1
-
-
-
80
3 *1
-
-
4 *1
5 *1
-
-
6
*1
100
3 *1
4 *1
-
5 *1
6 *1
-
7 *1
8
*1
120
6 *1
7 *1
-
9
10
-
8 *1
9 *1
-
11
12
-
10 *1
11
144
*1
13
14
Pin Name
Polarity
176
11
12
13
14
15
16
17
18
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P024
-
General-purpose I/O port
WR0X *2, *3, *4, *5
-
External bus/Write strobe 0 output
Multi-function serial ch.4 serial data input (1)
SIN4_1
-
PPG24_0
-
F
PPG ch.24 output (0)
TIN1_0
-
Reload timer ch.1 event input (0)
RTO4_1
-
Waveform generator ch.4 output pin (1)
INT15_0
-
INT15 External interrupt input (0)
P025
-
General-purpose I/O port
WR1X *4, *5
-
SOT4_1
-
PPG25_0
-
External bus/Write strobe 1 output
Multi-function serial ch.4 serial data output
(1)
PPG ch.25 output (0)
TIN2_0
-
Reload timer ch.2 event input (0)
A
P172
-
PPG38_1
-
P026
-
A00 *3, *4, *5
-
SCK4_1
-
PPG26_0
-
PPG ch.26 output (0)
TIN3_0
-
Reload timer ch.3 event input (0)
A
General-purpose I/O port
PPG ch.38 output (1)
General-purpose I/O port
External bus/Address bit0 output (0)
F
Multi-function serial ch.4 clock I/O (1)
P027
-
General-purpose I/O port
A01 *2, *3, *4, *5
-
External bus/Address bit1 output (0)
SCS40_1
-
PPG27_0
-
A
Serial chip select 40 I/O (1)
PPG ch.27 output (0)
TOT0_0
-
Reload timer ch.0 output (0)
RTO3_1
-
Waveform generator ch.3 output pin (1)
P173
-
PPG39_1
-
P030
-
A02 *4, *5
-
SCS41_1
-
PPG28_0
-
PPG ch.28 output (0)
TOT1_0
-
Reload timer ch.1 output (0)
A
General-purpose I/O port
PPG ch.39 output (1)
General-purpose I/O port
External bus/Address bit2 output (0)
A
Serial chip select 41 output (1)
P031
-
General-purpose I/O port
A03 *3, *4, *5
-
External bus/Address bit3 output (0)
SCS42_1
-
PPG29_0
-
PPG ch.29 output (0)
TOT2_0 *3
-
Reload timer ch.2 output (0)
A
Serial chip select 42 output (1)
Page 19 of 280
MB91520 Series
Pin No.
64
5 *1
6
*1
7 *1
-
8 *1
80
7 *1
8
*1
9 *1
-
10
*1
100
9 *1
10
*1
11 *1
12
13
120
12 *1
13
*1
14 *1
15
16
144
15
16
17
18
19
Pin Name
Polarity
176
19
20
21
22
23
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P032
-
General-purpose I/O port
A04 *2, *3, *4, *5
-
External bus/Address bit4 output (0)
SCS43_1
-
PPG30_0
-
A
Serial chip select 43 output (1)
PPG ch.30 output (0)
TOT3_0
-
Reload timer ch.3 output (0)
RTO2_1
-
Waveform generator ch.2 output pin (1)
P033
-
General-purpose I/O port
A05 *2, *3, *4, *5
-
External bus/Address bit5 output (0)
PPG31_0
-
PPG ch.31 output (0)
ICU3_3
-
TIN4_0
-
Reload timer ch.4 event input (0)
RTO1_1
-
Waveform generator ch.1 output pin (1)
SCK3_2
-
Multi-function serial ch.3 clock I/O (2)
A
Input capture ch.3 input (3)
P034
-
General-purpose I/O port
A06 *2, *3, *4, *5
-
External bus/Address bit6 output (0)
OCU11_1
-
Output compare ch.11 output (1)
ICU2_3
-
A
Input capture ch.2 input (3)
TIN5_0
-
Reload timer ch.5 event input (0)
RTO0_1
-
SOT3_2
-
P150
SOT8_0/
SDA8
OCU10_1
-
Waveform generator ch.0 output pin (1)
Multi-function serial ch.3 serial data output
(2)
General-purpose I/O port
Multi-function serial ch.8 serial data output
(0)/ I2C bus serial data I/O
Output compare ch.10 output (1)
TRG6_0
-
PPG trigger 6 input (0)
ICU1_3
-
Input capture ch.1 input (3)
TIN6_0
-
Reload timer ch.6 event input (0)
P151
SCK8_0/
SCL8 *2, *3
OCU9_1
-
General-purpose I/O port
Multi-function serial ch.8 clock I/O (0)/
I2C bus serial clock I/O
Output compare ch.9 output (1)
TRG7_0
-
ICU0_3
-
Input capture ch.0 input (3)
TIN7_0
-
Reload timer ch.7 event input (0)
ZIN0_2
-
U/D counter ch.0 ZIN input (2)
DTTI_1
-
Waveform generator ch.1 input pin (1)
-
F
F
PPG trigger 7 input (0)
Page 20 of 280
MB91520 Series
Pin No.
64
9 *1
80
11
*1
10
12
*1
*1
-
-
100
14 *1
15 *1
16
*1
120
17 *1
18 *1
19
*1
144
20
21
22
25
26
-
-
-
-
-
27
-
-
-
-
-
28
11
13
*1
*1
12
14
*1
*1
17 *1
18 *1
20 *1
21 *1
23
24
29
30
P035
A07 *2, *3, *4, *5
-
General-purpose I/O port
-
External bus/Address bit7 output
SIN8_0 *2, *3
-
Multi-function serial ch.8 serial data input (0)
OCU8_1
-
TOT4_0
-
Reload timer ch.4 output (0)
AIN0_0
-
U/D counter ch.0 AIN input (0)
INT11_0
-
INT11 External interrupt input (0)
15
*1
*1
19 *1
22 *1
25
31
Document Number: 002-04662 Rev. *F
I
Output compare ch.8 output (1)
P036
-
General-purpose I/O port
A08 *2, *3, *4, *5
-
External bus/Address bit8 output (0)
SCS8_0 *2, *3
-
OCU7_1
-
TOT5_0
-
Reload timer ch.5 output (0)
BIN0_0
-
U/D counter ch.0 BIN input (0)
A
Serial chip select 8 I/O (0)
Output compare ch.7 output (1)
P037
-
General-purpose I/O port
A09 *4, *5
-
External bus/Address bit9 output (0)
OCU6_1
-
TOT6_0
-
Reload timer ch.6 output (0)
ZIN0_0
-
U/D counter ch.0 ZIN input (0)
P174
-
TRG8_1
-
P175
-
TRG9_1
-
A
A
A
Output compare ch.6 output (1)
General-purpose I/O port
PPG trigger 8 input (1)
General-purpose I/O port
PPG trigger 9 input (1)
P040
-
General-purpose I/O port
A10 *2, *3, *4, *5
-
External bus/Address bit10 output (0)
PPG23_1
-
TOT7_0
-
AIN1_0
-
U/D counter ch.1 AIN input (0)
SIN0_1
-
Multi-function serial ch.0 serial data input (1)
P041
-
General-purpose I/O port
A11 *2, *3, *4, *5
-
External bus/Address bit11 output (0)
SIN9_0
-
ICU9_1
-
BIN1_0
-
U/D counter ch.1 BIN input (0)
INT12_0
-
INT12 External interrupt input (0)
P042
-
General-purpose I/O port
-
External bus/Address bit12 output
Multi-function serial ch.9 serial data output
(0)
ADC analog 47 input
A12
13
Function*9
Polarity
176
24
I/O
Circuit
types*8
Pin Name
*2, *3, *4, *5
SOT9_0
-
AN47
-
A
I
B
PPG ch.23 output (1)
Reload timer ch.7 output (0)
Multi-function serial ch.9 serial data input (0)
Input capture ch.9 input (1)
ICU8_1
-
Input capture ch.8 input (1)
TRG0_1
-
PPG trigger 0 input (1)
ZIN1_0
-
U/D counter ch.1 ZIN input (0)
Page 21 of 280
MB91520 Series
Pin No.
64
-
-
80
-
16
*1
14
17
*1
*1
-
-
-
-
15
18
*1
*1
-
-
-
-
-
-
-
-
100
20 *1
21 *1
22 *1
-
-
23 *1
-
-
-
-
120
23 *1
24 *1
25 *1
26 *1
-
27 *1
-
28 *1
-
-
144
26
27
28
29
-
30
-
31
32
33
Pin Name
Polarity
176
32
33
34
35
36
37
38
39
40
41
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P043
-
A13 *4, *5
-
General-purpose I/O port
ICU7_1
-
TRG1_1
-
PPG trigger 1 input (1)
P044
-
General-purpose I/O port
A14 *3, *4, *5
-
SCS9_0
-
A
External bus/Address bit13 output (0)
Input capture ch.7 input (1)
External bus/Address bit14 output (0)
A
Serial chip select 9 I/O (0)
ICU6_1
-
Input capture ch.6 input (1)
TRG2_1
-
PPG trigger 2 input (1)
P045
-
General-purpose I/O port
A15 *2, *3, *4, *5
-
External bus/Address bit15 output (0)
SCK9_0
-
AN46
-
Multi-function serial ch.9 clock I/O (0)
G
ADC analog 46 input
ICU5_1
-
Input capture ch.5 input (1)
TRG3_1
-
PPG trigger 3 input (1)
TOT1_2
-
Reload timer ch.1 output (2)
P046
-
General-purpose I/O port
A16 *5
-
ICU4_1
-
TRG4_1
-
P176
-
TRG10_0
-
A
External bus/Address bit16 output (0)
Input capture ch.4 input (1)
PPG trigger 4 input (1)
A
General-purpose I/O port
PPG trigger 10 input (0)
P047
-
General-purpose I/O port
A17 *2, *3, *4, *5
-
External bus/Address bit17 output (0)
AN45
-
TRG8_0
-
TIN3_2
-
SOT0_1
-
P177
-
TRG11_0
-
P050
-
A18 *5
-
ADC analog 45 input
B
A
PPG trigger 8 input (0)
Reload timer ch.3 event input (2)
Multi-function serial ch.0 serial data output
(1)
General-purpose I/O port
PPG trigger 11 input (0)
General-purpose I/O port
A
External bus/Address bit18 output
TRG5_1
-
PPG33_0
-
PPG trigger 5 input (1)
P051
-
A19
-
TRG9_0
-
PPG trigger 9 input (0)
P052
-
General-purpose I/O port
A20
-
PPG34_0
-
INT14_0
-
PPG ch.33 output (0)
General-purpose I/O port
A
A
External bus/Address bit19 output
External bus/Address bit20 output
PPG ch.34 output (0)
INT14 External interrupt input (0)
Page 22 of 280
MB91520 Series
Pin No.
64
80
16
19
*1
*1
-
-
17
22
*1
*1
-
-
-
-
19
24
*1
*1
-
-
100
24 *1
-
27 *1
-
-
29 *1
-
120
29 *1
-
-
38
-
-
-
*1
35 *1
-
34
35
32 *1
33
144
39
41
44
Pin Name
Polarity
176
42
43
46
47
48
49
51
54
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P053
-
General-purpose I/O port
A21 *2, *3, *4, *5
-
External bus/Address bit21 output
AN44
-
PPG35_0
-
INT14_1
-
INT14 External interrupt input (1)
SCK0_1
-
Multi-function serial ch.0 clock I/O (1)
P054
-
General-purpose I/O port
B
ADC analog 44 input
PPG ch.35 output (0)
SYSCLK
-
PPG36_0
-
PPG ch.36 output (0)
A
External bus/System clock output
P055
-
General-purpose I/O port
CS2X *2, *3, *4, *5
-
External bus chip select 2 output
SIN10_0
-
AN43
-
PPG37_0
-
PPG ch.37 output (0)
TIN4_1
-
Reload timer ch.4 event input (1)
P180
-
PPG40_0
-
P181
-
PPG41_0
-
P056
-
General-purpose I/O port
CS3X *5
-
External bus chip select 3 output
ICU9_0
-
Input capture ch.9 input (0)
PPG0_1
-
ICU0_1
-
Input capture ch.0 input (1)
G
A
A
A
Multi-function serial ch.10 serial data input (0)
ADC analog 43 input
General-purpose I/O port
PPG ch.40 output (0)
General-purpose I/O port
PPG ch.41 output (0)
PPG ch.0 output (1)
TIN5_1
-
Reload timer ch.5 event input (1)
DTTI_2
-
Waveform generator ch.0-ch.5 input pin (2)
P057
-
General-purpose I/O port
RDY *2, *3, *4, *5
-
External bus/Ready input (0)
SCK10_1
-
Multi-function serial ch.10 clock I/O (1)
AN42
-
ICU8_0
-
TRG0_2
-
PPG trigger 0 input (2)
PPG1_1
-
PPG ch.1 output (1)
ICU1_1
-
Input capture ch.1 input (1)
TIN6_1
-
Reload timer ch.6 event input (1)
P142
SCK10_0/
SCL10
PPG38_0
-
-
General-purpose I/O port
Multi-function serial ch.10 clock I/O (0)/
I2C bus serial clock I/O
PPG ch.38 output (0)
TIN7_1
-
Reload timer ch.7 event input (1)
-
ADC analog 42 input
G
F
Input capture ch.8 input (0)
Page 23 of 280
MB91520 Series
Pin No.
64
-
-
-
22
23
-
-
80
-
-
-
27
28
29
-
100
-
-
32
33
34
35
-
120
-
-
38
39
40
41
-
144
45
-
46
47
48
49
-
56
57
58
59
60
61
Document Number: 002-04662 Rev. *F
Function*9
Polarity
P143
SOT10_0/SDA1
0
PPG39_0
-
-
General-purpose I/O port
Multi-function serial ch.10 serial data output
(0)/ I2C bus serial data I/O
PPG ch.39 output (0)
TOT4_1
-
Reload timer ch.4 output (1)
176
55
I/O
Circuit
types*8
Pin Name
-
P182
-
PPG42_0
-
F
A
General-purpose I/O port
PPG ch.42 output (0)
P060
-
General-purpose I/O port
SCS10_0
-
Serial chip select 10 I/O (0)
PPG2_1
-
ICU2_1
-
TOT5_1
-
Reload timer ch.5 output (1)
INT13_0
-
INT13 External interrupt input (0)
P061
-
SOT10_1
-
General-purpose I/O port
Multi-function serial ch.10
serial data output (1)
ADC analog 41 input
A
PPG ch.2 output (1)
Input capture ch.2 input (1)
AN41
-
ICU6_0
-
PPG3_1
-
PPG ch.3 output (1)
ICU3_1
-
Input capture ch.3 input (1)
B
Input capture ch.6 input (0)
TOT6_1
-
Reload timer ch.6 output (1)
INT13_1
-
INT13 External interrupt input (1)
P062
-
General-purpose I/O port
SCS10_1
-
Serial chip select 10 I/O (1)
SCS40_0
-
Serial chip select 40 I/O (0)
AN40
-
B
ADC analog 40 input
PPG4_1
-
FRCK0_0
-
Free-run timer 0 clock input (0)
TOT7_1
-
Reload timer ch.7 output (1)
ZIN1_1
-
U/D counter ch.1 ZIN input (1)
P063
-
General-purpose I/O port
SCS41_0
-
Serial chip select 41 output (0)
AN39
-
B
PPG ch.4 output (1)
ADC analog 39 input
PPG5_1
-
FRCK1_0
-
Free-run timer 1 clock input (0)
BIN1_1
-
U/D counter ch.1 BIN input (1)
P183
-
PPG43_0
-
A
PPG ch.5 output (1)
General-purpose I/O port
PPG ch.43 output (0)
Page 24 of 280
MB91520 Series
Pin No.
64
24
-
80
30
-
100
36
37
120
42
43
144
50
51
62
63
-
-
-
-
64
-
-
-
-
-
65
-
-
26
27
31
32
-
33
34
38
39
40
41
42
44
45
46
47
48
52
53
54
55
56
Polarity
176
-
25
Pin Name
66
67
68
69
70
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P064
-
General-purpose I/O port
SCS42_0
-
Serial chip select 42 output (0)
AN38
-
FRCK2_0
-
B
ADC analog 38 input
Free-run timer 2 clock input (0)
AIN1_1
-
U/D counter ch.1 AIN input (1)
PPG43_1
-
PPG ch.43 output (1)
P065
-
General-purpose I/O port
SCS43_0
-
FRCK3_0
-
Serial chip select 43 output (0)
A
Free-run timer 3 clock input (0)
ZIN0_1
-
U/D counter ch.0 ZIN input (1)
PPG44_1
-
PPG ch.44 output (1)
P184
-
PPG44_0
-
P185
-
PPG45_0
-
P066
-
SOT4_2
-
SCS3_0
-
AN37
-
ADC analog 37 input
FRCK4_0
-
Free-run timer 4 clock input (0)
BIN0_1
-
U/D counter ch.0 BIN input (1)
General-purpose I/O port
A
A
B
General-purpose I/O port
PPG ch.44 output (0)
General-purpose I/O port
PPG ch.45 output (0)
General-purpose I/O port
Multi-function serial ch.4
serial data output (2)
Serial chip select 3 I/O (0)
P067
-
AN36
-
FRCK5_0
-
AIN0_1
-
P070
-
ICU0_2
-
P071
-
SCK4_2
-
AN35
-
ICU1_2
-
Input capture ch.1 input (2)
MONCLK
-
Clock monitor output pin
B
ADC analog 36 input
Free-run timer 5 clock input (0)
U/D counter ch.0 AIN input (1)
A
G
General-purpose I/O port
Input capture ch.0 input (2)
General-purpose I/O port
Multi-function serial ch.4
clock I/O (2)
ADC analog 35 input
P072
-
General-purpose I/O port
SIN4_0
-
Multi-function serial ch.4 serial data input (0)
AN34
-
ICU2_2
-
Input capture ch.2 input (2)
INT5_0
-
INT5 External interrupt input (0)
G
ADC analog 34 input
Page 25 of 280
MB91520 Series
Pin No.
64
-
80
35
*3
100
43 *4
120
49
144
57
-
-
-
-
-
72
-
-
-
-
-
73
-
-
-
50
58
74
-
-
-
51
59
75
-
-
-
52
60
76
-
-
-
53
61
77
-
-
44
54
62
78
28
-
29
30
36
-
37
38
45
-
46
47
55
-
56
57
63
64
65
66
79
80
81
82
Document Number: 002-04662 Rev. *F
Function*9
Polarity
P073
SOT4_0/
SDA4 *3, *4
AN33
-
-
General-purpose I/O port
Multi-function serial ch.4 serial data output
(0)/I2C bus serial data I/O
ADC analog 33 input
ICU3_2
-
Input capture ch.3 input (2)
176
71
I/O
Circuit
types*8
Pin Name
-
P186
-
PPG46_0
-
D
A
General-purpose I/O port
PPG ch.46 output (0)
P187
-
PPG47_0
-
P074
SCK4_0/
SCL4
P075
-
SIN3_0
-
INT4_0
-
P076
SOT3_0/
SDA3
P077
SCK3_0/
SCL3
P152
-
SCS53_0
-
P153
SCK5_0/
SCL5
AN32
-
FRCK1_1
-
Free-run timer 1 clock input (1)
INT4_1
-
INT4 External interrupt input (1)
P080
-
General-purpose I/O port
SCS52_0
-
PPG0_0
-
PPG ch.0 output (0)
P081
SOT5_0/
SDA5
AN0
-
-
General-purpose I/O port
Multi-function serial ch.5 serial data output
(0)/I2C bus serial data I/O
ADC analog 0 input
PPG1_0
-
PPG ch.1 output (0)
General-purpose I/O port
-
A
E
-
-
F
-
E
E
A
-
-
P082
-
SIN5_0
-
AN1
-
PPG2_0
-
PPG ch.47 output (0)
General-purpose I/O port
Multi-function serial ch.4 clock I/O (0)/
I2C bus serial clock I/O
General-purpose I/O port
Multi-function serial ch.3 serial data input (0)
INT4 External interrupt input (0)
-
General-purpose I/O port
G
A
G
G
General-purpose I/O port
Multi-function serial ch.3 serial data output
(0)/I2C bus serial data I/O
General-purpose I/O port
Multi-function serial ch.3 clock I/O (0)/
I2C bus serial clock I/O
General-purpose I/O port
Serial chip select 53 output (0)
General-purpose I/O port
Multi-function serial ch.5 clock I/O (0)/
I2C bus serial clock I/O
ADC analog 32 input
Serial chip select 52 output (0)
Multi-function serial ch.5 serial data input (0)
ADC analog 1 input
PPG ch.2 output (0)
Page 26 of 280
MB91520 Series
Pin No.
64
-
-
-
-
31
80
-
-
-
-
39
100
-
-
-
48
49
120
-
-
-
58
59
144
67
68
69
70
71
83
84
85
86
87
-
-
-
-
90
-
-
-
-
-
91
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
74
75
76
-
Polarity
176
-
-
Pin Name
92
93
94
95
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P083
-
SCS50_0
-
AN2
-
PPG3_0
-
PPG ch.3 output (0)
P084
-
General-purpose I/O port
SCS51_0
-
AN3
-
PPG4_0
-
P085
-
PPG5_0
-
P086
-
DAO1
-
PPG6_0
-
PPG ch.6 output (0)
P087
-
General-purpose I/O port
DAO0
-
PPG7_0
-
INT8_0
-
P190
-
TIN0_1
-
General-purpose I/O port
B
B
Serial chip select 50 I/O (0)
ADC analog 2 input
Serial chip select 51 output (0)
ADC analog 3 input
PPG ch.4 output (0)
A
General-purpose I/O port
PPG ch.5 output (0)
General-purpose I/O port
C
C
DAC analog 1 output
DAC analog 0 output
PPG ch.7 output (0)
INT8 External interrupt input (0)
A
General-purpose I/O port
Reload timer ch.0 event input (1)
P191
-
TIN1_1
-
P090
-
AN4
-
ICU0_0
-
TIN2_1
-
Reload timer ch.2 event input (1)
P091
-
General-purpose I/O port
AN5
-
ADC analog 5 input
PPG41_1
-
ICU1_0
-
Input capture ch.1 input (0)
TIN3_1
-
Reload timer ch.3 event input (1)
P092
-
General-purpose I/O port
AN6
-
ADC analog 6 input
PPG40_1
-
ICU2_0
-
Input capture ch.2 input (0)
TOT0_1
-
Reload timer ch.0 output (1)
P192
-
General-purpose I/O port
PPG24_1
-
TOT1_1
-
A
General-purpose I/O port
Reload timer ch.1 event input (1)
General-purpose I/O port
B
B
B
A
ADC analog 4 input
Input capture ch.0 input (0)
PPG ch.41 output (1)
PPG ch.40 output (1)
PPG ch.24 output (1)
Reload timer ch.1 output (1)
Page 27 of 280
MB91520 Series
Pin No.
64
80
34
42
*1
*1
-
-
35
36
-
-
-
-
43
44
48
*1
-
40
49
*1
*1
100
52
-
53
54
55
59
60
61
120
62
-
63
64
65
69
70
71
144
77
78
79
80
81
85
86
87
Pin Name
Polarity
176
96
97
98
99
100
104
105
106
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P093
-
General-purpose I/O port
TX0_1
-
CAN transmission data 0 output (1)
SIN11_0
-
Multi-function serial ch.11 serial data input (0)
AN7
-
J
ADC analog 7 input
ICU4_2
-
PPG16_1
-
Input capture ch.4 input (2)
PPG ch.16 output (1)
ICU3_0
-
Input capture ch.3 input (0)
TOT2_1 *2, *3
-
Reload timer ch.2 output (1)
P094
-
General-purpose I/O port
AN8
-
ICU4_0
-
TOT3_1
-
Reload timer ch.3 output (1)
P095
-
General-purpose I/O port
TX0(128)
-
SCS11_0
-
B
B
ADC analog 8 input
Input capture ch.4 input (0)
CAN transmission data 0 output
Serial chip select 11 I/O (0)
AN9
-
ADC analog 9 input
P096
-
General-purpose I/O port
RX0(128)
SOT11_0/
SDA11
AN10
-
-
CAN reception data 0 input
Multi-function serial ch.11 serial data output
(0)/I2C bus serial data I/O
ADC analog 10 input
INT0_0
-
INT0 External interrupt input (0)
P097
SCK11_0/
SCL11
AN11
-
General-purpose I/O port
Multi-function serial ch.11 clock I/O (0)/
I2C bus serial clock I/O
ADC analog 11 input
-
G
-
G
ICU5_0
-
Input capture ch.5 input (0)
PPG17_1
-
PPG ch.17 output (1)
P100
SCK7_0/
SCL7 *3
AN12
-
-
General-purpose I/O port
Multi-function serial ch.7 clock I/O (0)/
I2C bus serial clock I/O
ADC analog 12 input
PPG8_0
-
PPG ch.8 output (0)
P101
SOT7_0/
SDA7
AN13
-
-
General-purpose I/O port
Multi-function serial ch.7 serial data output
(0)/I2C bus serial data I/O
ADC analog 13 input
PPG9_0
-
PPG ch.9 output (0)
-
-
G
G
P102
-
General-purpose I/O port
SIN7_0 *2, *3
-
Multi-function serial ch.7 serial data input (0)
AN14
-
PPG10_0
-
PPG ch.10 output (0)
INT10_0
-
INT10 External interrupt input (0)
G
ADC analog 14 input
Page 28 of 280
MB91520 Series
Pin No.
64
80
41
50
*1
*1
42
51
*1
*1
43
52
*1
*1
-
-
-
53
100
62
63
64
65
66
120
72
73
74
75
76
144
88
89
90
91
92
107
108
109
110
111
-
-
-
-
112
-
-
-
77
93
113
-
-
-
78
94
114
44
54
67
79
95
115
-
-
55
-
-
68
69
-
80
81
82
96
97
98
Polarity
176
-
45
Pin Name
116
117
118
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P103
-
SCS73_0 *2, *3
-
AN15
-
PPG11_0
-
PPG ch.11 output (0)
P104
-
General-purpose I/O port
SCS72_0 *2, *3
-
AN16
-
PPG12_0
-
PPG ch.12 output (0)
P105
-
General-purpose I/O port
SCS71_0 *2, *3
-
AN17
-
PPG13_0
-
PPG ch.13 output (0)
P106
-
General-purpose I/O port
SCS70_0
-
AN18
-
PPG14_0
-
P107
-
AN19
-
PPG15_0
-
P193
-
PPG25_1
-
P154
-
AN20
-
P155
-
AN21
-
NMIX
N
General-purpose I/O port
H
H
H
H
Serial chip select 73 output (0)
ADC analog 15 input
Serial chip select 72 output (0)
ADC analog 16 input
Serial chip select 71 output (0)
ADC analog 17 input
Serial chip select 70 I/O (0)
ADC analog 18 input
PPG ch.14 output (0)
General-purpose I/O port
B
ADC analog 19 input
PPG ch.15 output (0)
A
B
B
M
General-purpose I/O port
PPG ch.25 output (1)
General-purpose I/O port
ADC analog 20 input
General-purpose I/O port
ADC analog 21 input
Non-masking interrupt input
P110
-
TX1(64)
-
General-purpose I/O port
SCS63_0
-
AN22
-
ADC analog 22 input
B
CAN transmission data 1 output
Serial chip select 63 output (0)
P111
-
General-purpose I/O port
RX1(64)
-
CAN reception data 1 input
SCS62_0
-
AN23
-
ADC analog 23 input
INT1_0
-
INT1 External interrupt input (0)
P112
-
General-purpose I/O port
AN24
-
PPG16_0
-
RTO0_0
-
G
B
Serial chip select 62 output (0)
ADC analog 24 input
PPG ch.16 output (0)
Waveform generator ch. 0 output pin (0)
Page 29 of 280
MB91520 Series
Pin No.
64
-
-
-
-
46
47
-
-
-
80
-
-
-
56
57
58
-
-
-
100
-
-
-
70
71
72
73
-
-
120
83
-
-
84
85
86
87
-
88
144
99
-
-
100
101
102
103
-
104
Pin Name
Polarity
176
119
120
121
122
123
124
125
126
127
Document Number: 002-04662 Rev. *F
I/O
Circuit
types*8
Function*9
P113
-
AN25
-
General-purpose I/O port
PPG17_0
-
RTO1_0
-
Waveform generator ch. 1 output pin (0)
P194
-
General-purpose I/O port
FRCK5_1
-
PPG26_1
-
B
A
ADC analog 25 input
PPG ch.17 output (0)
Free-run timer 5 clock input (1)
PPG ch.26 output (1)
P195
-
FRCK4_1
-
General-purpose I/O port
PPG27_1
-
PPG ch.27 output (1)
P114
-
General-purpose I/O port
SCS61_0
-
Serial chip select 61 output (0)
AN26
-
PPG18_0
-
PPG ch.18 output (0)
RTO2_0
-
Waveform generator ch.2 output pin (0)
P115
-
General-purpose I/O port
RX1_1
SOT6_0/
SDA6
AN27
-
CAN reception data 1 input (1)
Multi-function serial ch.6 serial data output
(0)/I2C bus serial data I/O
ADC analog 27 input
PPG19_0
-
PPG ch.19 output (0)
RTO3_0
-
Waveform generator ch.3 output pin (0)
INT1_1
-
INT1 External interrupt input (1)
P116
SCK6_0/
SCL6
AN28
-
General-purpose I/O port
Multi-function serial ch.6 clock I/O (0)/
I2C bus serial clock I/O
ADC analog 28 input
PPG20_0
-
PPG ch.20 output (0)
RTO4_0
-
Waveform generator ch.4 output pin (0)
A
B
-
G
-
G
Free-run timer 4 clock input (1)
ADC analog 26 input
P117
-
General-purpose I/O port
SCS60_0
-
Serial chip select 60 I/O (0)
AN29
-
PPG21_0
-
PPG ch.21 output (0)
RTO5_0
-
Waveform generator ch.5 output pin (0)
P196
-
General-purpose I/O port
FRCK3_1
-
PPG28_1
-
PPG ch.28 output (1)
P120
-
General-purpose I/O port
B
A
ADC analog 29 input
Free-run timer 3 clock input (1)
AN30
-
OCU6_0
-
ADC analog 30 input
PPG22_0
-
PPG ch.22 output (0)
INT9_0
-
INT9 External interrupt input (0)
B
Output compare ch.6 output (0)
Page 30 of 280
MB91520 Series
Pin No.
64
80
100
120
144
176
-
-
-
-
105
128
48
-
59
-
74
-
89
-
106
-
129
130
-
-
-
-
107
131
49
62
77
92
110
134
-
-
-
-
-
135
-
-
-
-
-
136
-
-
-
-
111
137
-
-
-
93
112
138
50
63
78
94
113
139
-
64
79
95
114
140
-
-
80
96
115
141
-
-
-
-
-
142
-
-
-
-
-
143
51
65
81
97
116
52
66
82
98
53
67
83
99
54
68
84
56
70
86
57
71
87
Pin Name
Polarity
P121
-
PPG23_0
-
PPG ch.23 output (0)
-
General-purpose I/O port
-
Multi-function serial ch.6 serial data input (0)
AN31
-
OCU8_0
-
Output compare ch.8 output (0)
INT9_1
-
INT9 External interrupt input (1)
P197
-
PPG29_1
-
P123
-
OCU9_0
-
DEBUGIF
-
P160
-
PPG30_1
-
P161
-
PPG31_1
-
P124
-
OCU10_0
-
P125
-
OCU11_0
-
P126
-
SIN0_0
-
INT6_0
-
P127
-
SOT0_0
-
P130
-
SCK0_0
-
P162
-
TRG5_2
-
144
MD0
-
117
145
MD1
118
146
X0
100
119
147
102
121
149
Document Number: 002-04662 Rev. *F
Output compare ch.7 output (0)
P122
-
150
General-purpose I/O port
A
SIN6_0
P163
122
Function*9
OCU7_0
TRG6_2
103
I/O
Circuit
types*8
J
A
A
L
A
A
A
A
ADC analog 31 input
General-purpose I/O port
PPG ch.29 output (1)
General-purpose I/O port
Output compare ch.9 output (0)
MDI I/O for debugger (OCD)
General-purpose I/O port
PPG ch.30 output (1)
General-purpose I/O port
PPG ch.31 output (1)
General-purpose I/O port
Output compare ch.10 output (0)
General-purpose I/O port
Output compare ch.11 output (0)
General-purpose I/O port
F
Multi-function serial ch.0 serial data input (0)
INT6 External interrupt input (0)
A
F
A
A
General-purpose I/O port
Multi-function serial ch.0 serial data output
(0)
General-purpose I/O port
Multi-function serial ch.0 clock I/O (0)
General-purpose I/O port
PPG trigger 5 input (2)
General-purpose I/O port
PPG trigger 6 input (2)
K
Mode pin 0
-
K
Mode pin 1
-
N
Main clock oscillation input
X1
-
N
Main clock oscillation output
P135
-
DTTI_0
-
A
General-purpose I/O port
Waveform generator ch.0-ch.5 input pin (0)
X1A
-
O
Sub clock oscillation output
P136
-
A
General-purpose I/O port
X0A
-
O
Sub clock oscillation input
Page 31 of 280
MB91520 Series
Pin No.
64
80
100
120
144
176
58
72
88
104
123
151
-
-
-
-
124
152
-
-
-
105
125
153
-
-
-
-
-
-
-
-
-
-
-
-
-
75
*1
-
76
*1
-
-
89
90
91
94
*1
95 *1
-
96 *1
-
-
106
107
108
111
*1
112
*1
113
*1
114
*1
-
-
126
127
128
131
132
133
134
135
-
154
155
156
159
160
161
162
163
164
Document Number: 002-04662 Rev. *F
Pin Name
Polarity
I/O
Circuit
types*8
RSTX
N
M
P131
-
ADTG0_0
-
P132
-
SCS1_0
-
ADTG1_0
-
P133
-
TX2(64)
-
A
Function*9
External reset input
General-purpose I/O port
A/D converter external trigger input 0 (0)
General-purpose I/O port
A
Serial chip select 1 I/O (0)
A/D converter external trigger input 1 (0)
A
General-purpose I/O port
CAN transmission data 2 output
P134
-
General-purpose I/O port
RX2(64)
-
CAN reception data 2 input
SCS1_1
-
ICU7_0
-
Input capture ch.7 input (0)
INT7_0
-
INT7 External interrupt input (0)
P144
-
SCK1_1
-
F
F
Serial chip select 1 I/O (1)
General-purpose I/O port
Multi-function serial ch.1 clock I/O (1)
P000
-
General-purpose I/O port
D16 *4, *5
-
External bus data bit16 I/O (0)
SIN1_0
-
TIOA0_1 *4
-
TIOA output of Base timer ch.0 (1)
INT2_0
-
INT2 External interrupt input (0)
P001
-
General-purpose I/O port
D17 *3, *4, *5
-
F
A
Multi-function serial ch.1 serial data input (0)
External bus data bit17 I/O
Multi-function serial ch.1 serial data output
(0)
SOT1_0 *3
-
TIOA1_1
-
TIOA I/O of Base timer ch.1 (1)
P002
-
General-purpose I/O port
D18 *5
-
SCK1_0
-
TIOB0_1
-
TIOB input of Base timer ch.0 (1)
P003
-
General-purpose I/O port
D19 *3, *4, *5
-
SIN2_0
-
TIOB1_1
-
TIOB input of Base timer ch.1 (1)
INT3_0
-
INT3 External interrupt input (0)
P004
-
General-purpose I/O port
D20
-
SOT2_0
-
P164
-
PPG32_1
-
F
External bus data bit18 I/O
Multi-function serial ch.1 clock I/O (0)
External bus data bit19 I/O
F
A
A
Multi-function serial ch.2 serial data input (0)
External bus data bit20 I/O (0)
Multi-function serial ch.2 serial data output
(0)
General-purpose I/O port
PPG ch.32 output (1)
Page 32 of 280
MB91520 Series
Pin No.
64
80
61
77
*1
*1
100
97 *1
120
144
Pin Name
Polarity
176
115
136
165
*1
*1
*1
-
62
78
*1
*1
-
98 *1
-
-
166
116
137
167
*1
*1
*1
P005
-
General-purpose I/O port
-
External bus data bit21 I/O (0)
SCK2_0 *2
-
ADTG0_1
-
INT7_1
-
INT7 External interrupt input (1)
*7
-
CAN reception data 2 input
P165
-
PPG33_1
-
-
-
-
-
-
-
-
63
79
*1
*1
-
-
-
-
-
-
-
-
-
99 *1
-
-
-
-
117
*1
138
168
-
-
169
118
*1
119
*1
-
-
-
-
139
140
141
-
142
143
170
171
172
173
174
175
Multi-function serial ch.2 clock I/O (0)
F
A
General-purpose I/O port
PPG ch.33 output (1)
P006
-
General-purpose I/O port
-
External bus data bit22 I/O (0)
SCS2_0 *2
-
ADTG1_1
-
INT2_1
-
INT2 External interrupt input (1)
*7
-
CAN transmission data 2 output
Serial chip select 2 I/O (0)
A
A/D converter external trigger input 1 (1)
P007
-
D23 *5
-
P166
-
PPG34_1
-
P010
-
D24 *5
-
P011
-
General-purpose I/O port
WOT
-
RTC output signal
D25 *2, *3, *4, *5
-
A
A
A
General-purpose I/O port
External bus data bit23 I/O
General-purpose I/O port
PPG ch.34 output (1)
General-purpose I/O port
External bus data bit24 I/O
SOT2_1 *2
-
TIOA0_0 *2, *3, *4
-
External bus data bit25 I/O
Multi-function serial ch.2 serial data output
(1)
TIOA output of Base timer ch.0 (0)
INT3_1
-
INT3 External interrupt input (1)
P012
-
General-purpose I/O port
D26
-
TIOB0_0
-
P167
-
PPG35_1
-
P013
-
D27
-
TIOA1_0
-
P014
-
D28
-
TIOB1_0
-
A
A
External bus data bit26 I/O
TIOB input of Base timer ch.0 (0)
A
General-purpose I/O port
PPG ch.35 output (1)
General-purpose I/O port
A
External bus data bit27 I/O
TIOA I/O of Base timer ch.1 (0)
General-purpose I/O port
A
18
23
28
34
40
50
AVCC1
-
-
39
47
58
68
84
103
AVCC0
-
-
Document Number: 002-04662 Rev. *F
A/D converter external trigger input 0 (1)
D22 *2, *3, *4, *5
TX2(64) *4, *5, *6,
-
Function*9
D21 *2, *3, *4, *5
RX2(64) *4, *5, *6,
-
I/O
Circuit
types*8
External bus data bit28 I/O
TIOB input of Base timer ch.1 (0)
Analog power supply for AD/DA convertor
unit1
Analog power supply for AD/DA convertor
unit0
Page 33 of 280
MB91520 Series
Pin No.
Pin Name
Polarity
I/O
Circuit
types*8
Function*9
64
80
100
120
144
176
20
25
30
36
42
52
AVRH1
-
-
38
46
57
67
83
102
AVRH0
-
-
21
26
31
37
43
53
AVSS1/
AVRL1
-
-
GND for AD/DA convertor unit1
Lower limit reference voltage for AD
convertor unit1
37
45
56
66
82
101
AVSS0/
AVRL0
-
-
GND for AD/DA convertor unit0
Lower limit reference voltage for AD
convertor unit0
60
74
93
110
130
158
C
-
-
External capacity connection output
VCC
-
-
+5.0V power supply
VSS
-
-
GND
-
20
25
30
36
44
32
40
50
60
72
88
-
61
76
91
109
133
64
80
100
120
144
176
1
1
1
1
1
1
-
21
26
31
37
45
33
41
51
61
73
89
-
60
75
90
108
132
55
69
85
101
120
148
59
73
92
109
129
157
Upper limit reference voltage for AD
convertor unit1
Upper limit reference voltage for AD
convertor unit0
*1: There is a restriction of pin functions. See "Pin Name" of this table.
*2: not supported in 64 pin
*3: not supported in 80 pin
*4: not supported in 100 pin
*5: not supported in 120 pin
*6: not supported in 144 pin
*7: not supported in 176 pin
*8: For the I/O circuit types, see I/O Circuit Type.
*9: For switching, see "I/O Port" in HARDWARE MANUAL.
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4.
I/O Circuit Type
Type
Circuit
Remarks
Pull-up control
Digital output
Digital output
A
•General-purpose I/O port
•Output 4 mA
•Pull-up resistor control 50 kΩ
•Automotive input
Automotive input
Standby control
Pull-up control
Digital output
Digital output
B
•Analog input, General-purpose I/O port
•Output 4 mA
•Pull-up resistor control 50 kΩ
•Automotive input
Automotive input
Standby control
Analog input
Pull-up control
Digital output
Digital output
C
•DAC output, General-purpose I/O port
•Output 4 mA
•Pull-up resistor control 50 kΩ
•Automotive input
Automotive input
Standby control
DAC output
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MB91520 Series
Type
Circuit
Remarks
Pull-up control
Digital output
Digital output
D
•I2C Analog input, General-purpose I/O port
•Output 3 mA
•Pull-up resistor control 50 kΩ
•I2C hysteresis input
I2C input
Standby control
Analog input
Pull-up control
Digital output
Digital output
E
•I2C,General-purpose I/O port
•Output 3 mA
•Pull-up resistor control 50 kΩ
•I2C hysteresis input
I2C input
Standby control
Pull-up control
Digital output
Digital output
F
•General-purpose I/O port
•Output 4 mA
•Pull-up resistor control 50 kΩ
•CMOS hysteresis input
CMOS-hys input
Standby control
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MB91520 Series
Type
Circuit
Remarks
Pull-up control
Digital output
Digital output
G
•Analog input, General-purpose I/O port
•Output 4 mA
•Pull-up resistor control 50 kΩ
• CMOS hysteresis input
CMOS-hys input
Standby control
Analog input
Pull-up control
Digital output
Digital output
H
•Analog input, General-purpose I/O port
•Output 12 mA
•Pull-up resistor control 50 kΩ
•Automotive input
Automotive input
Standby control
Analog input
Digital output
Digital output
I
• General-purpose I/O port (5 V tolerant)
• Output 4 mA
• CMOS hysteresis input
CMOS-hys input
Standby control
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MB91520 Series
Type
Circuit
Remarks
Digital output
• Analog input, General-purpose I/O port (5 V
tolerant)
• Output 4 mA
• CMOS hysteresis input
Digital output
J
CMOS-hys input
Standby control
Analog input
Mode input
K
Control
•Mode I/O
• CMOS hysteresis input
Digital output
•Open-drain I/O
•Output 25 mA (Nch open-drain)
•TTL input
L
TTL input
• CMOS hysteresis input
•Pull-up resistor 50 kΩ
M
CMOS-hys input
Input
•Main oscillation I/O
N
Standby control
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MB91520 Series
Type
Circuit
Remarks
Input
•Sub oscillation I/O
O
Standby control
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MB91520 Series
5.
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that
must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor
devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or
over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current
flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should
be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large
current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called
latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury
or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
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Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection,
and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are
demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical
devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be
responsible for damages arising from such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the
board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the
flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to
be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should
conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC
leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to
open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a
ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
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MB91520 Series
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70 % relative humidity, and at temperatures
between 5 °C and 30 °C.
When you open Dry Package that recommends humidity 40 % to 70 % relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125 °C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40 % and 70 %. Use of an apparatus for ion generation
may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the
level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such
cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the
device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
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MB91520 Series
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If
devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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6.
Handling Devices
This section explains the latch-up prevention and pin processing.
For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied
between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases
excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum
ratings in device application.
Also, the analog power supply (AVCC, AVRH) and analog input must not be exceed the digital power supply (VCC) when the
power supply to the analog system is turned on or off.
In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC) and analog power supplies
(AVCC, AVRH) simultaneously. Or, turn on the digital power supply (VCC), and then turn on analog power supplies (AVCC,
AVRH).
Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect at
least a 2 kΩ resistor to each of the unused pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated
in the same way as for the input pins.
Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be at the same
potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power supply
or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the
total output current standard, etc. As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple
Vcc or Vss systems are connected, the device cannot operate correctly even within the guaranteed operating range.
Figure 1 Power Supply Input Pins
Vcc
Vss
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
The power supply pins should be connected to VCC and VSS pins of this device at the low impedance from the power supply
source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended
to use as a bypass capacitor between VCC and VSS pins.
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Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out X0
and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the
device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode pins (MD1, MD0)
Connect the MD1 and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection of test mode caused
by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the printed circuit board. Also, use the
low-impedance pin connection.
During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, the voltage rising must be monotonic during
power-on.
Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate
at the free running frequency of the self-oscillator circuit built in the PLL clock. This operation is not guaranteed.
Treatment of A/D converter power supply pins
Connect the pins to have AVCC = AVRH = VCC and AVSS/AVRL = VSS even if the A/D converter is not used.
Notes on using external clock
An external clock is not supported. None of the external direct clock input can be used for both main clock and sub clock.
Power-on sequence of A/D converter analog inputs
Be sure to turn on the digital power supply (Vcc) first, and then turn on the A/D converter power supplies (AVcc, AVRH, AVRL)
and analog inputs (AN0 to AN47). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the
digital power supply (Vcc). When the AVRH pin voltage is turned on or off, it must not exceed AVCC. Even if a common analog
input pin is used as an input port, its input voltage must not exceed AVcc. (However, the analog power supply and digital power
supply can be turned on or off simultaneously.)
Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the internal
stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the latest data sheet.
Note: Please see the latest data sheet for a detailed specification of the operation voltage.
Function switching of a multiplexed port
To switch between the port function and the multiplexed pin function, use the PFR (port function register). However, if a pin is
also used for an external bus, its function is switched by the external bus setting. For details, see " I/O PORTS" in the hardware
manual.
Low-power consumption mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off), follow the procedure
explained in "Activating the sleep mode, watch mode, or stop mode" or "Activating the watch mode (power-off) or stop
mode(power-off)" of " POWER CONSUMPTION CONTROL" in the hardware manual.
Take the following notes when using a monitor debugger.
•
•
Do not set a break point for the low-power consumption transition program.
Do not execute an operation step for the low-power consumption transition program.
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Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, taking care not to
clear its status flag erroneously must be followed.
The program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.)
By the Byte, Half-word, or Word access, data is written to the control bits and status flag simultaneously. During this time, take
care not to clear other bits (in this case, the bits of status flag) erroneously.
Note: These points can be ignored because the bit instructions are already taken the points into consideration.
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7.
Block Diagram
MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
FR81s CPU core
Debug
Interface
M P U
CR oscillator
Instruction
Data
XBS
Regulator
Power-on reset
XBS Crossbar Switch
Wild register
Timing
Protection Unit
RAM
48K/64K/96K/128K
・Main Flash
256K/384K/512K/768K/
1024KB +64KB
From Master
To Slave
On-chip bus layer 2
From Master
To Slave
On-chip bus layer 1
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
Clock /
Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp
RAM +8KB
Async Bus Bridge (PCLK1 <-> PCLK2)
CAN prescaler
Ｉ/Ｏ port setting
32bit Free-run timer(1ch)
FRCK
32bit Input capture(5ch)
ICU
16bit Peripheral Bus
RTC／WDT1 Calibration
Bus
performance
counter
Operation mode
register
MD0,MD1,P00
32bit Peripheral Bus (APB)
RX,T
On-chip bus(AHB)
Flash
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
16bit Free-run timer (3ch)
DTTI,RTO
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (13ch + 13ch)
32bit Output compare(4ch)
Port
I/O
ADTG,AIN
Multi-function serial interface (8ch)
OCU
Base timer (1ch)
TIOA,TIOB
U/D counter (2ch)
SOUT,
SIN,
SCK
Bus Bridge (32bit <-> 16bit)
AIN,BIN,ZI
PPG(21ch)
Reload timer (7ch)
TRG,PPG
TIN,TOT
I/O
8bit DA converter (1ch)
Bus Bridge (32bit <-> 16bit)
DAO
Port
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
DMA transfer request generate/clear
Clock supervisor
NMI
NMIX
Interrupt request batch read
Clock control （divide control）
RST
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
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MB91520 Series
MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
FR81s CPU core
Debug
Interface
M P U
CR oscillator
Instruction
Data
XBS
Regulator
Power-on reset
XBS Crossbar Switch
Wild register
Timing
Protection Unit
・Main Flash
256K/384K/512K/768K/
1024KB +64KB
From Master
To Slave
On-chip bus layer 2
From Master
To Slave
On-chip bus layer 1
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
Clock /
Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp
RAM +8KB
Async Bus Bridge (PCLK1 <-> PCLK2)
CAN prescaler
Ｉ/Ｏ port setting
32bit Free-run timer(2ch)
FRCK
32bit Input capture(5ch)
ICU
16bit Peripheral Bus
RTC／WDT1 Calibration
Bus
performance
counter
Operation mode
register
MD0,MD1,P00
32bit Peripheral Bus (APB)
RX,T
On-chip bus(AHB)
RAM
48K/64K/96K/128K
Flash
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
16bit Free-run timer (3ch)
DTTI,RTO
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (21ch + 16ch)
32bit Output compare(4ch)
Port
I/O
ADTG,AIN
Multi-function serial interface (9ch)
OCU
Base timer (1ch)
TIOA,TIOB
U/D counter (2ch)
SOUT,
SIN,
SCK
Bus Bridge (32bit <-> 16bit)
AIN,BIN,ZI
PPG(27ch)
Reload timer (7ch)
TRG,PPG
TIN,TOT
I/O
8bit DA converter (2ch)
Bus Bridge (32bit <-> 16bit)
DAO
Port
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
DMA transfer request generate/clear
Clock supervisor
NMI
NMIX
Interrupt request batch read
Clock control （divide control）
RST
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
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MB91520 Series
MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
Regulator
FR81s CPU core
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
Power-on reset
XBS Crossbar Switch
Wild register
Timing Protection
Unit
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
From Master
On-chip bus layer 2
To Slave
From Master
On-chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp
RAM +8KB
CAN prescaler
Ｉ/Ｏ port setting
32bit Free-run timer(3ch)
FRCK
32bit Input capture(6ch)
ICU
16bit Peripheral Bus
RTC／WDT1 Calibration
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
Async Bus Bridge (PCLK1 <-> PCLK2)
32bit Peripheral Bus (APB)
RX,TX
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
DTTI,RTO
16bit Free-run timer (3ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (21ch + 16ch)
32bit Output compare(6ch)
Multi-function serial interface (12ch)
OCU
I / O Port
On-chip bus(AHB)
RAM
48K/64K/96K/128K
Base timer (1ch)
TIOA,TIOB
U/D counter (2ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
AIN,BIN,ZIN
PPG(34ch)
Reload timer (8ch)
TRG,PPG
TIN,TOT
I / O Port
8bit DA converter (2ch)
Bus Bridge (32bit <-> 16bit)
DAO
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control （divide control）
RSTX
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
Document Number: 002-04662 Rev. *F
Page 49 of 280
MB91520 Series
MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
Regulator
FR81s CPU core
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
Power-on reset
XBS Crossbar Switch
Wild register
Timing Protection
Unit
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
From Master
On-chip bus layer 2
To Slave
From Master
On-chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp
RAM +8KB
CAN prescaler
Ｉ/Ｏ port setting
32bit Free-run timer(3ch)
FRCK
32bit Input capture(6ch)
ICU
16bit Peripheral Bus
RTC／WDT1 Calibration
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
Async Bus Bridge (PCLK1 <-> PCLK2)
32bit Peripheral Bus (APB)
RX,TX
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
DTTI,RTO
16bit Free-run timer (3ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (26ch + 16ch)
32bit Output compare(6ch)
Multi-function serial interface (12ch)
OCU
I / O Port
On-chip bus(AHB)
RAM
48K/64K/96K/128K
Base timer (2ch)
TIOA,TIOB
U/D counter (2ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
AIN,BIN,ZIN
PPG(38ch)
Reload timer (8ch)
TRG,PPG
TIN,TOT
I / O Port
8bit DA converter (2ch)
Bus Bridge (32bit <-> 16bit)
DAO
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control （divide control）
RSTX
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
Document Number: 002-04662 Rev. *F
Page 50 of 280
MB91520 Series
MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
Regulator
FR81s CPU core
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
Power-on reset
XBS Crossbar Switch
Wild register
Timing Protection
Unit
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
From Master
On-chip bus layer 2
To Slave
From Master
On-chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
RX,TX
RAM ECC Control
(BackUp RAM)
32
BackUp
RAM +8KB
CAN prescaler
RTC／WDT1 Calibration
32bit Free-run timer(3ch)
32bit Input capture(6ch)
ICU
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
Async Bus Bridge (PCLK1 <-> PCLK2)
Ｉ/Ｏ port setting
FRCK
16
16bit Peripheral Bus
D,A,
ASX,CS,
RDX,
WRX,
SYSCLK,
RDY
Clock / Bus
Bridge
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
DTTI,RTO
16bit Free-run timer (3ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 16ch)
32bit Output compare(6ch)
Multi-function serial interface (12ch)
OCU
I / O Port
On-chip bus(AHB)
RAM
48K/64K/96K/128K
Base timer (2ch)
TIOA,TIOB
U/D counter (2ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
AIN,BIN,ZIN
PPG(44ch)
Reload timer (8ch)
TRG,PPG
TIN,TOT
I / O Port
8bit DA converter (2ch)
Bus Bridge (32bit <-> 16bit)
DAO
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control （divide control）
RSTX
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
Document Number: 002-04662 Rev. *F
Page 51 of 280
MB91520 Series
MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
Regulator
FR81s CPU core
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
Power-on reset
XBS Crossbar Switch
Wild register
Timing Protection
Unit
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
From Master
On-chip bus layer 2
To Slave
From Master
On-chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (3ch)
Peripheral Bus
Bridge
RX,TX
RAM ECC Control
(BackUp RAM)
32
BackUp
RAM +8KB
CAN prescaler
RTC／WDT1 Calibration
32bit Free-run timer(3ch)
32bit Input capture(6ch)
ICU
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
Async Bus Bridge (PCLK1 <-> PCLK2)
Ｉ/Ｏ port setting
FRCK
16
16bit Peripheral Bus
D,A,
ASX,CS,
RDX,
WRX,
SYSCLK,
RDY
Clock / Bus
Bridge
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
DTTI,RTO
16bit Free-run timer (3ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 16ch)
32bit Output compare(6ch)
Multi-function serial interface (12ch)
OCU
I / O Port
On-chip bus(AHB)
RAM
48K/64K/96K/128K
Base timer (2ch)
TIOA,TIOB
U/D counter (2ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
AIN,BIN,ZIN
PPG(48ch)
Reload timer (8ch)
TRG,PPG
TIN,TOT
I / O Port
8bit DA converter (2ch)
Bus Bridge (32bit <-> 16bit)
DAO
Clock monitor
External interrupt input(16ch)
MONCLK
INT
Real time clock
WOT
Watchdog timer(SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control （divide control）
RSTX
Reset control register
Low-power consumption setting register
Delay interrupt
Low-voltage detection
（External power supply low-voltage detection）
Low-voltage detection
（Internal power supply low-voltage detection）
Clock control （Clock setting,
Main timer, Sub timer, PLL timer）
Interrupt controller
Document Number: 002-04662 Rev. *F
Page 52 of 280
MB91520 Series
8.
Memory Map
MB91F522, MB91F523, MB91F524
MB91F522
0000 0000H
MB91F523
I/O
0000 4000H
0000 6000H
0001 0000H
BackUp RAM (8KB)
I/O
I/O
0000 4000H
0000 6000H
0001 0000H
BackUp RAM (8KB)
I/O
I/O
0000 4000H
0000 6000H
0001 0000H
RAM (48KB)
RAM (48KB)
0001 C000H
MB91F524
0000 0000H
0000 0000H
BackUp RAM (8KB)
I/O
RAM (64KB)
0001 C000H
0002 0000H
Reserved
Reserved
Reserved
0007 0000H
0007 0000H
0007 0000H
Flash memory
Flash memory
(256+64)KB
Flash memory
(384+64)KB
000C 0000H
(512+64)KB
000E 0000H
Reserved
000F FC00H
0010 0000H
Interrupt vector
Reset vector
Reserved
000F FC00H
0010 0000H
Reserved
0033 0000H
0034 0000H
WorkFlash
(64KB)
Interrupt vector
Reset vector
8000 0000H
0033 0000H
0034 0000H
0039 2000H
WorkFlash
(64KB)
Document Number: 002-04662 Rev. *F
Reserved
0033 0000H
0034 0000H
Reserved
0039 2000H
WorkFlash
(64KB)
Reserved
8000 0000H
External area
External area
FFFF FFFFH
Interrupt vector
Reset vector
0039 0000H
8000 0000H
External area
FFFF FFFFH
0010 0000H
Reserved
0039 0000H
Reserved
000F FC00H
FFFF FFFFH
Page 53 of 280
MB91520 Series
MB91F525, MB91F526
MB91F525
MB91F526
0000 0000H
0000 0000H
I/O
0000 4000H
0000 6000H
BackUp RAM (8KB)
I/O
0000 4000H
0000 6000H
BackUp RAM (8KB)
I/O
I/O
0001 0000H
0001 0000H
RAM (96KB)
RAM (128KB)
0002 8000H
0003 0000H
Reserved
Reserved
0007 0000H
0007 0000H
Flash memory
(768+64)KB
000F FC00H
0010 0000H
0014 0000H
Interrupt vector
Reset vector
Flash memory
Flash memory
(1024+64)KB
000F FC00H
0010 0000H
Interrupt vector
Reset vector
Flash memory
0018 0000H
Reserved
Reserved
0033 0000H
0034 0000H
WorkFlash
(64KB)
0039 0000H
0039 2000H
0033 0000H
0034 0000H
0039 0000H
Reserved
0039 2000H
External area
External area
Document Number: 002-04662 Rev. *F
Reserved
8000 0000H
8000 0000H
FFFF FFFFH
WorkFlash
(64KB)
FFFF FFFFH
Page 54 of 280
MB91520 Series
9.
I/O Map
The following I/O map shows the relationship between memory space and registers for peripheral resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090H
000094 H
000098 H
00009C H
0000A0 H
0000A4 H
0000A8 H
Address offset value/ register name
+1
+2
+0
+3
BT1TMR[R] H
BT1TMCR[R/W]B,H,W
0000000000000000
00000000 00000000
BT1STC[R/W] B
-
00000000
-
-
BT1PCSR/BT1PRLL[R /W] H
BT1PDU T/BT1PRLH/BT1DTBF[R/W] H
0000000000000000
0000000000000000
BTSEL[R/W] B
Base timer 1
BTSSSR[W] B,H
-
----000 0
Block
-------- ------11
ADERH [R/W]B, H, W
ADERL [R/W]B, H, W
00000000 00000000
00000000 00000000
ADCS1 [R/W] B, H,W
ADCS0 [R/W] B, H,W
ADCR1 [R] B, H,W
ADCR0 [R] B, H,W
00000000
00000000
------XX
XXXXX XXX
ADCT1 [R/W] B, H,W
ADCT0 [R/W] B, H,W
ADSCH [R/W] B, H,W
ADECH [R/W] B, H,W
00010000
00101100
---00000
---00000
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)The access by the data
access attribute not described
is disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
· "1": Initial value "1"
· "0": Initial value "0"
· "X": Initial value undefined
· "-": Reserved bit/Undefined bit
· "*": Initial value "0" or "1" according to the setting
Note: The access to addresses not described is disabled.
Document Number: 002-04662 Rev. *F
Page 55 of 280
MB91520 Series
Address offset value / Register name
Block
+0
+1
+2
+3
PDR00 [R/W] B,H,W PDR01 [R/W] B,H,W PDR02 [R/W] B,H,W PDR03 [R/W] B,H,W
000000H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR04 [R/W] B,H,W PDR05 [R/W] B,H,W PDR06 [R/W] B,H,W PDR07 [R/W] B,H,W
000004H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR08 [R/W] B,H,W PDR09 [R/W] B,H,W PDR10 [R/W] B,H,W PDR11 [R/W] B,H,W
000008H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Port Data Register
PDR12 [R/W] B,H,W PDR13 [R/W] B,H,W PDR14 [R/W] B,H,W PDR15 [R/W] B,H,W
00000CH
XXXXXXXX
-XXXXXXX
---XXX---XXXXXX
000010H
―
―
―
―
000014H
―
―
―
―
PDR16 [R/W] B,H,W PDR17 [R/W] B,H,W PDR18 [R/W] B,H,W PDR19 [R/W] B,H,W
000018H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00001CH
to
―
―
―
―
Reserved
000034H
WDTECR0 [R/W]
000038H
B,H,W
―
―
―
---00000
Watchdog Timer
[S]
WDTCR0 [R/W]
WDTCPR0 [W]
WDTCR1 [R]
WDTCPR1 [W]
00003CH
B,H,W
B,H,W
B,H,W
B,H,W
-0--0000
00000000
----0110
00000000
000040H
―
―
―
―
Reserved
DICR [R/W]
000044H
B,H,W
―
―
―
Delayed Interrupt
-------0
000048H
to
―
―
―
―
Reserved
00005CH
TMRLRA0 [R/W] H
TMR0 [R] H
000060H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Reload Timer 0
TMRLRB0 [R/W] H
TMCSR0 [R/W] B,H,W
000064H
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA7 [R/W] H
TMR7 [R] H
000068H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Reload Timer 7
TMRLRB7 [R/W] H
TMCSR7 [R/W] B,H,W
00006CH
XXXXXXXX XXXXXXXX
00000000 0-000000
FRS8 [R/W] B,H,W
Free-run timer selection
000070H
―
--00--00 --00--00 --00--00
register 8
FRS9 [R/W] B,H,W
Free-run timer selection
000074H
―
--00--00 --00--00 --00--00
register 9
OCLS67 [R/W]
OCU67 Output level control
000078H
―
―
―
B,H,W
register
----0000
OCLS89 [R/W]
OCU89 Output level control
00007CH
―
―
―
B,H,W
register
----0000
BT0TMR [R] H
BT0TMCR [R/W] H
000080H
Base Timer 0
00000000 00000000
-000--00 -000-000
Address
Document Number: 002-04662 Rev. *F
Page 56 of 280
MB91520 Series
Address
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
to
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
Address offset value / Register name
+0
+1
+2
+3
BT0TMCR2 [R/W] B BT0STC [R/W] B
―
―
-------0
-0-0-0-0
BT0PCSR/BT0PRLL [R/W] H
BT0PDUT/BT0PRLH/BT0DTBF [R/W] H
00000000 00000000
00000000 00000000
―
―
―
―
BT1TMR [R] H
BT1TMCR [R/W] H
00000000 00000000
-000--00 -000-000
BT1TMCR2 [R/W] B BT1STC [R/W] B
―
―
-------0
-0-0-0-0
BT1PCSR/BT1PRLL [R/W] H
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
00000000 00000000
BTSEL01 [R/W] B
BTSSSR [W] B,H
―
----0000
-------- ------11
―
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA3 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB3 [R/W] H
XXXXXXXX XXXXXXXX
000118H
00011CH
000120H
000124H
000128H
―
―
00012CH
000130H
000134H
―
000138H
to
0001B4H
―
―
―
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H,W
00000000 0-000000
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B,H,W
00000000 0-000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSR3 [R/W] B,H,W
00000000 0-000000
MSCY4 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY5 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCCP6 [R/W] W
00000000 00000000 00000000 00000000
OCCP7 [R/W] W
00000000 00000000 00000000 00000000
OCSH67 [R/W]
OCSL67 [R/W]
―
B,H,W
B,H,W
---0--00
0000--00
OCCP8 [R/W] W
00000000 00000000 00000000 00000000
OCCP9 [R/W] W
00000000 00000000 00000000 00000000
OCSH89 [R/W]
OCSL89 [R/W]
―
B,H,W
B,H,W
---0--00
0000--00
Document Number: 002-04662 Rev. *F
―
―
―
Block
Reserved
Base Timer 1
Base Timer 0,1
Reserved
Reload Timer 1
Reload Timer 2
Reload Timer 3
Input Capture 4,5
Cycle measurement data
register 45
Output
Compare 6,7
32-bit OCU
Output
Compare 8,9
32-bit OCU
Reserved
Page 57 of 280
MB91520 Series
Address
0001B8H
0001BCH
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
0001D8H
0001DCH
0001E0H
to
0001ECH
0001F0H
0001F4H
0001F8H
0001FCH
000200H
to
000238H
00023CH
000240H
000244H
000248H
00024CH
000250H
000254H
Address offset value / Register name
+0
+1
+2
+3
EPFR64 [R/W]
EPFR65 [R/W]
EPFR66 [R/W]
EPFR67 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
-----000000-000
--000000
----0000
EPFR68 [R/W]
EPFR69 [R/W]
EPFR70 [R/W]
EPFR71 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
----0000
----0000
---00000
-0-0-0-0
EPFR72 [R/W]
EPFR73 [R/W]
EPFR74 [R/W]
EPFR75 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
000000-0
00000000
00000000
00000000
EPFR76 [R/W]
EPFR77 [R/W]
EPFR78 [R/W]
EPFR79 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
--000000
------00
00000000
EPFR80 [R/W]
EPFR81 [R/W]
EPFR82 [R/W]
EPFR83 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
---00000
00000000
00000000
-0000000
EPFR84 [R/W]
EPFR85 [R/W]
EPFR86 [R/W]
EPFR87 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
--000000
---00000
------00
EPFR88 [R/W]
B,H,W
―
―
―
-------0
―
―
―
―
TMRLRA4 [R/W] H
TMR4 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB4 [R/W] H
TMCSR4 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
―
―
―
―
TMRLRA5 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB5 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA6 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB6 [R/W] H
XXXXXXXX XXXXXXXX
TMR5 [R] H
XXXXXXXX XXXXXXXX
TMCSR5 [R/W] B, H,W
00000000 0-000000
TMR6 [R] H
XXXXXXXX XXXXXXXX
TMCSR6 [R/W] B, H,W
00000000 0-000000
―
―
―
―
DACR0 [R/W] B,H,W DADR0 [R/W] B,H,W DACR1 [R/W] B,H,W DADR1 [R/W] B,H,W
-------0
XXXXXXXX
-------0
XXXXXXXX
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
TCDT3 [R/W] W
00000000 00000000 00000000 00000000
TCCSH3 [R/W]
TCCSL3 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
TCDT4 [R/W] W
00000000 00000000 00000000 00000000
TCCSH4 [R/W]
TCCSL4 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
Document Number: 002-04662 Rev. *F
Block
Extended port function
register
Reserved
Reload Timer 4
Reserved
Reload Timer 5
Reload Timer 6
Reserved
DA Converter
Free-run Timer 3
32-bit FRT
Free-run Timer 4
32-bit FRT
Page 58 of 280
MB91520 Series
Address
000258H
to
0002C0H
0002C4H
to
0002FCH
000300H
to
00030CH
+0
Address offset value / Register name
+1
+2
+3
Block
―
―
―
―
Reserved
―
―
―
―
Reserved
―
―
―
―
Reserved
000310H
―
―
000314H
000318H
00031CH
―
―
―
―
000328H
00032CH
―
000330H
000334H
―
000338H
00033CH
―
000340H
000344H
―
000348H
00034CH
―
000350H
000354H
―
000358H
00035CH
―
000360H
000364H
―
―
―
000320H
000324H
MPUCR [R/W] H
000000-0 ----0100
―
―
―
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR [R/W] H
―
-------- 00000--0
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR [R/W] H
―
-------- 00000--0
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
―
000000-0 00000--0
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
―
000000-0 00000--0
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
―
000000-0 00000--0
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
―
000000-0 00000--0
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
―
000000-0 00000--0
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
―
000000-0 00000--0
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6 [R/W] H
―
000000-0 00000--0
Document Number: 002-04662 Rev. *F
MPU [S]
(Only CPU core can access
this area)
Page 59 of 280
MB91520 Series
Address
+0
000370H
to
0003ACH
0003B0H
to
0003FCH
+3
―
PACR7 [R/W] H
000000-0 00000--0
―
―
―
―
Reserved [S]
―
ICSEL0 [R/W] B,H,W ICSEL1 [R/W] B,H,W ICSEL2 [R/W] B,H,W
-----000
-----000
-------0
ICSEL5 [R/W] B,H,W ICSEL6 [R/W] B,H,W
000404H
―
-----000
----0000
ICSEL10 [R/W]
ICSEL8 [R/W] B,H,W ICSEL9 [R/W] B,H,W
000408H
B,H,W
------00
------00
------00
ICSEL13 [R/W]
ICSEL14 [R/W]
00040CH
―
B,H,W
B,H,W
------00
------00
ICSEL16 [R/W]
ICSEL17 [R/W]
ICSEL18 [R/W]
000410H
B,H,W
B,H,W
B,H,W
----0000
------00
---00000
ICSEL20 [R/W]
ICSEL21 [R/W]
ICSEL22 [R/W]
000414H
B,H,W
B,H,W
B,H,W
-----000
------00
------00
IRPR0H [R] B,H,W IRPR0L [R] B,H,W IRPR1H [R] B,H,W
000418H
00-----00-----00-----IRPR3H [R] B,H,W
00041CH
―
―
000000-IRPR4H [R] B,H,W IRPR4L [R] B,H,W IRPR5H [R] B,H,W
000420H
0000---0000---0000---IRPR6H [R] B,H,W IRPR6L [R] B,H,W IRPR7H [R] B,H,W
000424H
--00---0000----0-00--IRPR8H [R] B,H,W IRPR8L [R] B,H,W IRPR9H [R] B,H,W
000428H
--0-----00-----0-----IRPR10H [R] B,H,W IRPR10L [R] B,H,W IRPR11H [R] B,H,W
00042CH
-0------0-----0------IRPR12H [R] B,H,W IRPR12L [R] B,H,W IRPR13H [R] B,H,W
000430H
--0000-----00-00-----IRPR14H [R] B,H,W IRPR14L [R] B,H,W IRPR15H [R] B,H,W
000434H
00000000
00000000
000----ICSEL24 [R/W]
ICSEL25 [R/W]
ICSEL26 [R/W]
000438H
B,H,W
B,H,W
B,H,W
------00
---00000
-------0
00043CH
―
―
―
000400H
Document Number: 002-04662 Rev. *F
Block
MPU [S]
(Only CPU core can access
this area)
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000368H
00036CH
Address offset value / Register name
+1
+2
―
ICSEL3 [R/W] B,H,W
-------0
ICSEL7 [R/W] B,H,W
----0000
ICSEL11 [R/W]
B,H,W
-----000
ICSEL15 [R/W]
B,H,W
------00
ICSEL19 [R/W]
B,H,W
-----000
ICSEL23 [R/W]
B,H,W
------00
IRPR1L [R] B,H,W
00-----IRPR3L [R] B,H,W
000000-IRPR5L [R] B,H,W
000----IRPR7L [R] B,H,W
------00
IRPR9L [R] B,H,W
-0-----IRPR11L [R] B,H,W
0------IRPR13L [R] B,H,W
00-----IRPR15L [R] B,H,W
0000000ICSEL27 [R/W]
B,H,W
-------0
―
Reserved [S]
DMA request generation
and clear
Interrupt Request Batch
Reading Register
DMA request generation
and clear
Reserved [S]
Page 60 of 280
MB91520 Series
Address
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
+0
ICR00 [R/W] B,H,W
---11111
ICR04 [R/W] B,H,W
---11111
ICR08 [R/W] B,H,W
---11111
ICR12 [R/W] B,H,W
---11111
ICR16 [R/W] B,H,W
---11111
ICR20 [R/W] B,H,W
---11111
ICR24 [R/W] B,H,W
---11111
ICR28 [R/W] B,H,W
---11111
ICR32 [R/W] B,H,W
---11111
ICR36 [R/W] B,H,W
---11111
ICR40 [R/W] B,H,W
---11111
ICR44 [R/W] B,H,W
---11111
Address offset value / Register name
+1
+2
ICR01 [R/W] B,H,W ICR02 [R/W] B,H,W
---11111
---11111
ICR05 [R/W] B,H,W ICR06 [R/W] B,H,W
---11111
---11111
ICR09 [R/W] B,H,W ICR10 [R/W] B,H,W
---11111
---11111
ICR13 [R/W] B,H,W ICR14 [R/W] B,H,W
---11111
---11111
ICR17 [R/W] B,H,W ICR18 [R/W] B,H,W
---11111
---11111
ICR21 [R/W] B,H,W ICR22 [R/W] B,H,W
---11111
---11111
ICR25 [R/W] B,H,W ICR26 [R/W] B,H,W
---11111
---11111
ICR29 [R/W] B,H,W ICR30 [R/W] B,H,W
---11111
---11111
ICR33 [R/W] B,H,W ICR34 [R/W] B,H,W
---11111
---11111
ICR37 [R/W] B,H,W ICR38 [R/W] B,H,W
---11111
---11111
ICR41 [R/W] B,H,W ICR42 [R/W] B,H,W
---11111
---11111
ICR45 [R/W] B,H,W ICR46 [R/W] B,H,W
---11111
---11111
000470H
to
00047CH
―
―
―
000480H
RSTRR [R]
B,H,W
XXXX--XX
RSTCR [R/W]
B,H,W
111----0
STBCR [R/W]
B,H,W *
000---11
+3
ICR03 [R/W] B,H,W
---11111
ICR07 [R/W] B,H,W
---11111
ICR11 [R/W] B,H,W
---11111
ICR15 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
ICR23 [R/W] B,H,W
---11111
ICR27 [R/W] B,H,W
---11111
ICR31 [R/W] B,H,W
---11111
ICR35 [R/W] B,H,W
---11111
ICR39 [R/W] B,H,W
---11111
ICR43 [R/W] B,H,W
---11111
ICR47 [R/W] B,H,W
---11111
―
―
Block
Interrupt Controller [S]
Reserved [S]
Reset Control [S]
Power Control [S]
*: Writing STBCR by DMA is
forbidden
Reserved [S]
―
―
―
―
DIVR0 [R/W] B,H,W DIVR1 [R/W] B,H,W DIVR2 [R/W] B,H,W
000488H
―
Clock Control [S]
000----0001---0011---00048CH
―
―
―
―
Reserved [S]
IORR0 [R/W] B,H,W IORR1 [R/W] B,H,W IORR2 [R/W] B,H,W IORR3 [R/W] B,H,W
000490H
-0000000
-0000000
-0000000
-0000000
IORR4 [R/W] B,H,W IORR5 [R/W] B,H,W IORR6 [R/W] B,H,W IORR7 [R/W] B,H,W
DMA request by
000494H
-0000000
-0000000
-0000000
-0000000
peripheral [S]
IORR8 [R/W] B,H,W IORR9 [R/W] B,H,W IORR10 [R/W] B,H,W IORR11 [R/W] B,H,W
000498H
-0000000
-0000000
-0000000
-0000000
IORR12 [R/W] B,H,W IORR13 [R/W] B,H,W IORR14 [R/W] B,H,W IORR15 [R/W] B,H,W
DMA request by
00049CH
-0000000
-0000000
-0000000
-0000000
peripheral [S]
0004A0H
―
―
―
―
Reserved
CANPRE [R/W]
0004A4H
B,H,W
―
―
―
CAN prescaler
---00000
CSCFG[R/W]B,H,W CMCFG[R/W]B,H,W
Clock monitor control
0004A8H
―
―
---0---00000000
register
ADERH0[R/W] B,H
ADERL0[R/W] B,H
Analog input control register
0004ACH
11111111 11111111
11111111 11111111
0
000484H
Document Number: 002-04662 Rev. *F
Page 61 of 280
MB91520 Series
Address
0004B0H
0004B4H
0004B8H
0004BCH
0004C0H
0004C4H
0004C8H
0004CCH
to
00050CH
000510H
000514H
000518H
00051CH
000520H
000524H
000528H
00052CH
000530H
000534H
to
00054CH
000550H
000554H
000558H
Address offset value / Register name
+1
+2
+3
ADERL1[R/W] B,H
―
11111111 11111111
―
―
―
―
CUCR0 [R/W] B,H,W
CUTD0 [R/W] B,H,W
-------- ---0--00
10000000 00000000
CUTR0 [R] B,H,W
-------- 00000000 00000000 00000000
―
―
―
―
CUCR1 [R/W] B,H,W
CUTD1 [R/W] B,H,W
-------- ---0--00
11000011 01010000
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
+0
―
―
―
―
MTMCR [R/W]
STMCR [R/W] B,H,W
B,H,W
0000-111
00001111
PLLCR [R/W] B,H,W
CSTBR [R/W] B,H,W PTMCR [R/W] B,H,W
-------- 11110000
-0000000
00-----CPUAR [R/W] B,H,W
―
―
―
0----XXX
―
―
―
―
CCPSSELR [R/W]
CCPSDIVR [R/W]
B,H,W
―
―
B,H,W
-------0
-000-000
CCPLLFBR [R/W]
CCSSFBR0 [R/W]
CCSSFBR1 [R/W]
―
B,H,W
B,H,W
B,H,W
-0000000
--000000
---00000
CCSSCCR0 [R/W]
CCSSCCR1 [R/W] H,W
―
B,H,W
000----- -----------0000
CCCGRCR0 [R/W] CCCGRCR1 [R/W] CCCGRCR2 [R/W]
―
B,H,W
B,H,W
B,H,W
00----00
00000000
00000000
CCRTSELR [R/W]
CCPMUCR0 [R/W] CCPMUCR1 [R/W]
B,H,W
―
B,H,W
B,H,W
0------0
0-----00
0--00000
CSELR [R/W] B,H,W CMONR [R] B,H,W
001---00
001---00
―
―
EIRR0 [R/W] B,H,W ENIR0 [R/W] B,H,W
XXXXXXXX
00000000
EIRR1 [R/W] B,H,W ENIR1 [R/W] B,H,W
XXXXXXXX
00000000
―
―
Document Number: 002-04662 Rev. *F
―
―
ELVR0 [R/W] B,H,W
00000000 00000000
ELVR1 [R/W] B,H,W
00000000 00000000
―
―
Block
Analog input control register
1
Reserved
RTC/WDT1 calibration
Reserved
Clock Control [S]
Reset Control [S]
Reserved [S]
Clock Control 2 [S]
Clock Control 2 [S]
Reserved
External Interrupt
(INT0 to 7)
External Interrupt
(INT8 to 15)
Reserved
Page 62 of 280
MB91520 Series
Address
+0
00055CH
―
000560H
―
000564H
―
000568H
WTHR [R/W] B,H
---00000
00056CH
―
000570H
to
00057CH
―
000580H
000584H
000588H
to
00058CH
000590H
000594H
000598H
00059CH
to
0005BCH
0005C0H
to
0005FCH
―
―
―
―
Block
Real Time Clock (RTC)
Clock Supervisor
Reserved
REGSEL [R/W]
B,H,W
0110011LVD5R [R/W]
B,H,W
-------1
―
―
LVD5F [R/W]
B,H,W
00000001
LVD [R/W]
B,H,W
01000--0
―
―
―
―
―
PMUSTR [R/W]
B,H,W
0-----1X
PMUINTF0 [R/W]
B,H,W
00000000
―
PMUCTLR [R/W]
B,H,W
0-00---PMUINTF1 [R/W]
B,H,W
00000000
―
PWRTMCTL [R/W]
B,H,W
-----011
PMUINTF2 [R/W]
B,H,W
0000---―
―
―
―
―
Reserved
―
―
―
―
Reserved
Regulator Control / Low
Voltage Detection
000604H
000608H
00060CH
―
Document Number: 002-04662 Rev. *F
―
―
Reserved
―
PMU
―
―
ASR0 [R/W] W
00000000 00000000 -------- 1111-001
ASR1 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR2 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR3 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000600H
000610H
to
00063CH
Address offset value / Register name
+1
+2
+3
WTDR [R/W] H
―
00000000 00000000
WTCRH [R/W] B
WTCRM [R/W] B,H WTCRL [R/W] B,H
------00
00000000
----00-0
WTBRH [R/W] B
WTBRM [R/W] B
WTBRL [R/W] B
--XXXXXX
XXXXXXXX
XXXXXXXX
WTMR [R/W] B,H
WTSR [R/W] B
―
--000000
--000000
CSVCR [R/W] B
―
―
000111--
External Bus
Interface [S]
―
Reserved [S]
Page 63 of 280
MB91520 Series
Address
Address offset value / Register name
+1
+2
ACR0 [R/W] W
-------- -------- -------- 01--00-ACR1 [R/W] W
-------- -------- -------- XX--XX-ACR2 [R/W] W
-------- -------- -------- XX--XX-ACR3 [R/W] W
-------- -------- -------- XX--XX--
+0
000640H
000644H
000648H
00064CH
000650H
to
00067CH
―
―
000684H
000688H
00068CH
000710H
Block
External Bus
Interface [S]
―
AWR0 [R/W] W
----1111 00000000 11110000 00000-0AWR1 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR2 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR3 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000680H
000690H
to
0006FCH
000700H
to
00070CH
―
+3
Reserved [S]
External Bus
Interface [S]
External Bus
Interface [S]
―
―
―
―
Reserved [S]
―
―
―
―
Reserved
BPCCRA [R/W] B
00000000
000714H
000718H
00071CH
BPCCRB [R/W] B
BPCCRC [R/W] B
00000000
00000000
BPCTRA [R/W] W
00000000 00000000 00000000 00000000
BPCTRB [R/W] W
00000000 00000000 00000000 00000000
BPCTRC [R/W] W
00000000 00000000 00000000 00000000
―
Bus Performance
Counter
000720H
to
0007F8H
―
―
―
―
Reserved
0007FCH
BMODR [R] B, H, W
XXXXXXXX
―
―
―
Mode Register
000800H
to
00083CH
―
―
―
―
Reserved [S]
―
FSTR [R/W] B
-----001
Flash Memory
Register [S]
―
―
Reserved [S]
FCTLR [R/W] H
-0--1000 0--0----
000840H
000844H
to
000854H
―
―
000858H
―
―
00085CH
to
00087CH
―
―
Document Number: 002-04662 Rev. *F
WREN [R/W] H
00000000 00000000
―
―
Wild Register [S]
Reserved [S]
Page 64 of 280
MB91520 Series
Address
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
+0
Address offset value / Register name
+1
+2
WRAR00 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Document Number: 002-04662 Rev. *F
+3
Block
Wild Register [S]
Wild Register [S]
Page 65 of 280
MB91520 Series
Address offset value / Register name
+1
+2
WRDR12 [R/W] W
0008E4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13 [R/W] W
0008E8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13 [R/W] W
0008ECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14 [R/W] W
0008F0H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14 [R/W] W
0008F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15 [R/W] W
0008F8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15 [R/W] W
0008FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TPUUNLOCK [R/W] W
000900H
00000000 00000000 00000000 00000000
TPUVST [R/W]
TPULST [R] B,H,W
000904H
―
B,H,W
-------0
-----000
TPUCFG [R/W] B,H,W
000908H
-------0 0-000000 -------- -------0
TPUTIR [R] B,H,W
00090CH
―
―
00000000
TPUTST [R] B,H,W
000910H
―
―
00000000
TPUTIE [R/W] B,H,W
000914H
―
―
00000000
TPUTMID [R] B,H,W
000918H
00000000 00000000 00000000 00000000
00091CH
to
―
―
―
00092CH
TPUTCN00 [R/W] B,H,W
000930H
000000-- 00000000 00000000 00000000
TPUTCN01 [R/W] B,H,W
000934H
000000-- 00000000 00000000 00000000
TPUTCN02 [R/W] B,H,W
000938H
000000-- 00000000 00000000 00000000
TPUTCN03 [R/W] B,H,W
00093CH
000000-- 00000000 00000000 00000000
TPUTCN04 [R/W] B,H,W
000940H
000000-- 00000000 00000000 00000000
TPUTCN05 [R/W] B,H,W
000944H
000000-- 00000000 00000000 00000000
TPUTCN06 [R/W] B,H,W
000948H
000000-- 00000000 00000000 00000000
TPUTCN07 [R/W] B,H,W
00094CH
000000-- 00000000 00000000 00000000
TPUTCN10 [R/W]
000950H
B,H,W
―
―
---00000
Address
+0
Document Number: 002-04662 Rev. *F
+3
Block
Wild Register [S]
Wild Register [S]
―
―
―
―
―
Time Protection Unit [S]
―
Page 66 of 280
MB91520 Series
Address
000954H
000958H
00095CH
000960H
000964H
000968H
00096CH
+0
TPUTCN11 [R/W]
B,H,W
---00000
TPUTCN12 [R/W]
B,H,W
---00000
TPUTCN13 [R/W]
B,H,W
---00000
TPUTCN14 [R/W]
B,H,W
---00000
TPUTCN15 [R/W]
B,H,W
---00000
TPUTCN16 [R/W]
B,H,W
---00000
TPUTCN17 [R/W]
B,H,W
---00000
+3
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Block
Time Protection
Unit [S]
TPUTCC0 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC1 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC2 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC3 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC4 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC5 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC6 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC7 [R] B,H,W
-------- 00000000 00000000 00000000
000970H
000974H
000978H
00097CH
000980H
000984H
000988H
00098CH
000990H
to
0009FCH
000A00H
to
000BECH
Address offset value / Register name
+1
+2
―
―
―
―
―
―
―
―
000BF0H
000BF4H
―
000BF8H
―
000BFCH
―
Document Number: 002-04662 Rev. *F
HSCFR [R/W] B,H,W
-------- ------00 00000000 00000000
―
―
―
MBR [R/W] B,H,W
―
00------ XXXXXXXX
UER [W] B,H,W
―
-------- -------X
Reserved
OCDU
OCDU
Page 67 of 280
MB91520 Series
Address
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
000C48H
000C4CH
000C50H
000C54H
000C58H
000C5CH
000C60H
+0
Address offset value / Register name
+1
+2
+3
DCCR0 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR0 [R/W] H
DTCR0 [R/W] H
0------- -----000
00000000 00000000
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR1 [R/W] H
DTCR1 [R/W] H
0------- -----000
00000000 00000000
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR2 [R/W] H
DTCR2 [R/W] H
0------- -----000
00000000 00000000
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR3 [R/W] H
DTCR3 [R/W] H
0------- -----000
00000000 00000000
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR4 [R/W] H
DTCR4 [R/W] H
0------- -----000
00000000 00000000
DSAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR5 [R/W] H
DTCR5 [R/W] H
0------- -----000
00000000 00000000
DSAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6 [R/W] W
0----000 --00--00 00000000 0-000000
Document Number: 002-04662 Rev. *F
Block
DMA
Controller
[S]
Page 68 of 280
MB91520 Series
Address
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000C80H
000C84H
000C88H
000C8CH
000C90H
000C94H
000C98H
000C9CH
000CA0H
000CA4H
000CA8H
000CACH
000CB0H
000CB4H
000CB8H
000CBCH
000CC0H
000CC4H
+0
Address offset value / Register name
+1
+2
+3
DCSR6 [R/W] H
DTCR6 [R/W] H
0------- -----000
00000000 00000000
DSAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR7 [R/W] H
DTCR7 [R/W] H
0------- -----000
00000000 00000000
DSAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR8 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR8 [R/W] H
DTCR8 [R/W] H
0------- -----000
00000000 00000000
DSAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR9 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR9 [R/W] H
DTCR9 [R/W] H
0------- -----000
00000000 00000000
DSAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR10 [R/W] H
DTCR10 [R/W] H
0------- -----000
00000000 00000000
DSAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR11 [R/W] H
DTCR11 [R/W] H
0------- -----000
00000000 00000000
DSAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR12 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR12 [R/W] H
DTCR12 [R/W] H
0------- -----000
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
DMA
Controller
[S]
Page 69 of 280
MB91520 Series
Address
+0
000CC8H
000CCCH
000CD0H
000CD4H
000CD8H
000CDCH
000CE0H
000CE4H
000CE8H
000CECH
000CF0H
000CF4H
000CF8H
000CFCH
000D00H
to
000DF0H
―
000DF4H
―
Address offset value / Register name
+1
+2
+3
DSAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR13 [R/W] H
DTCR13 [R/W] H
0------- -----000
00000000 00000000
DSAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR14 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR14 [R/W] H
DTCR14 [R/W] H
0------- -----000
00000000 00000000
DSAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR15 [R/W] H
DTCR15 [R/W] H
0------- -----000
00000000 00000000
DSAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000DF8H
000DFCH
000E00H
000E04H
000E08H
000E0CH
000E10H
000E14H
000E18H
000E1CH
―
DDR00 [R/W] B,H,W
00000000
DDR04 [R/W] B,H,W
00000000
DDR08 [R/W] B,H,W
00000000
DDR12 [R/W] B,H,W
00000000
―
―
DDR16 [R/W] B,H,W
00000000
―
―
―
DNMIR [R/W] B
0------0
DMACR[R/W] W
0------- -------- 0------- -------―
―
DDR01 [R/W] B,H,W DDR02 [R/W] B,H,W
00000000
00000000
DDR05 [R/W] B,H,W DDR06 [R/W] B,H,W
00000000
00000000
DDR09 [R/W] B,H,W DDR10 [R/W] B,H,W
00000000
00000000
DDR13 [R/W] B,H,W DDR14 [R/W] B,H,W
-0000000
---000-―
―
―
―
DDR17 [R/W] B,H,W DDR18 [R/W] B,H,W
00000000
00000000
―
―
Document Number: 002-04662 Rev. *F
―
―
DILVR [R/W] B
---11111
―
DDR03 [R/W] B,H,W
00000000
DDR07 [R/W] B,H,W
00000000
DDR11 [R/W] B,H,W
00000000
DDR15 [R/W] B,H,W
--000000
―
―
DDR19 [R/W] B,H,W
00000000
―
Block
DMA
Controller
[S]
Reserved [S]
DMA
Controller
[S]
Reserved [S]
Data Direction
Register
Data Direction
Register
Reserved
Page 70 of 280
MB91520 Series
Address
000E70H
000E74H
+0
PFR00 [R/W] B,H,W
00000000
PFR04 [R/W] B,H,W
00000000
PFR08 [R/W] B,H,W
00000000
PFR12 [R/W] B,H,W
00000000
―
―
PFR16 [R/W] B,H,W
00000000
―
PDDR00 [R] B,H,W
XXXXXXXX
PDDR04 [R] B,H,W
XXXXXXXX
PDDR08 [R] B,H,W
XXXXXXXX
PDDR12 [R] B,H,W
XXXXXXXX
―
―
PDDR16 [R] B,H,W
XXXXXXXX
―
EPFR00 [R/W]
B,H,W
00000000
EPFR04 [R/W]
B,H,W
----00-0
EPFR08 [R/W]
B,H,W
---00000
EPFR12 [R/W]
B,H,W
----0000
―
―
000E78H
―
000E7CH
EPFR28 [R/W]
B,H,W
--000-0-
000E80H
―
000E20H
000E24H
000E28H
000E2CH
000E30H
000E34H
000E38H
000E3CH
000E40H
000E44H
000E48H
000E4CH
000E50H
000E54H
000E58H
000E5CH
000E60H
000E64H
000E68H
000E6CH
Address offset value / Register name
+1
+2
PFR01 [R/W] B,H,W PFR02 [R/W] B,H,W
00000000
00000000
PFR05 [R/W] B,H,W PFR06 [R/W] B,H,W
00000000
00000000
PFR09 [R/W] B,H,W PFR10 [R/W] B,H,W
00000000
00000000
PFR13 [R/W] B,H,W PFR14 [R/W] B,H,W
-0000000
---000-―
―
―
―
PFR17 [R/W] B,H,W PFR18 [R/W] B,H,W
00000000
00000000
―
―
PDDR01 [R] B,H,W PDDR02 [R] B,H,W
XXXXXXXX
XXXXXXXX
PDDR05 [R] B,H,W PDDR06 [R] B,H,W
XXXXXXXX
XXXXXXXX
PDDR09 [R] B,H,W PDDR10 [R] B,H,W
XXXXXXXX
XXXXXXXX
PDDR13 [R] B,H,W PDDR14 [R] B,H,W
-XXXXXXX
---XXX-―
―
―
―
PDDR17 [R] B,H,W PDDR18 [R] B,H,W
XXXXXXXX
XXXXXXXX
―
―
EPFR01 [R/W]
EPFR02 [R/W]
B,H,W
B,H,W
-0-0-000
----0000
EPFR05 [R/W]
EPFR06 [R/W]
B,H,W
B,H,W
----0000
----000EPFR09 [R/W]
EPFR10 [R/W]
B,H,W
B,H,W
-----00----0000
EPFR13 [R/W]
EPFR14 [R/W]
B,H,W
B,H,W
------00
------00
―
―
―
―
EPFR26 [R/W]
―
B,H,W
00000000
EPFR29 [R/W]
B,H,W
―
00000000
EPFR33 [R/W]
EPFR34 [R/W]
B,H,W
B,H,W
-----00-----00-
Document Number: 002-04662 Rev. *F
+3
PFR03 [R/W] B,H,W
00000000
PFR07 [R/W] B,H,W
00000000
PFR11 [R/W] B,H,W
00000000
PFR15 [R/W] B,H,W
--000000
―
―
PFR19 [R/W] B,H,W
00000000
―
PDDR03 [R] B,H,W
XXXXXXXX
PDDR07 [R] B,H,W
XXXXXXXX
PDDR11 [R] B,H,W
XXXXXXXX
PDDR15 [R] B,H,W
--XXXXXX
―
―
PDDR19 [R] B,H,W
XXXXXXXX
―
EPFR03 [R/W]
B,H,W
---000-0
EPFR07 [R/W]
B,H,W
---00000
EPFR11 [R/W]
B,H,W
----0000
EPFR15 [R/W]
B,H,W
-----000
―
―
EPFR27 [R/W]
B,H,W
---0----
Block
Port Function
Register
Reserved
Port Direct
Read Register
Reserved
Extended Port
Function Register
―
EPFR35 [R/W]
B,H,W
---00000
Page 71 of 280
MB91520 Series
Address
000E84H
000E88H
000E8CH
000E90H
000E94H
000E98H
000E9CH
000EA0H
to
000EBCH
000EC0H
000EC4H
000EC8H
000ECCH
000ED0H
000ED4H
000ED8H
000EDCH
to
000F3CH
000F40H
000F44H
000F48H
to
000F64H
+0
EPFR36 [R/W]
B,H,W
----000-
Address offset value / Register name
+1
+2
+3
Block
―
―
―
―
―
EPFR42 [R/W]
B,H,W
------00
EPFR43 [R/W]
B,H,W
0--0000-
EPFR44 [R/W]
B,H,W
-00---0―
―
EPFR56 [R/W]
B,H,W
-----0-0
EPFR60 [R/W]
B,H,W
----00-0
EPFR45 [R/W]
B,H,W
-0000000
―
―
EPFR57 [R/W]
B,H,W
----00-0
EPFR61 [R/W]
B,H,W
-----00-
―
―
―
―
EPFR58 [R/W]
B,H,W
----00-0
EPFR62 [R/W]
B,H,W
-----00-
―
―
EPFR59 [R/W]
B,H,W
----00-0
EPFR63 [R/W]
B,H,W
---0000-
―
―
―
―
Reserved
PPER00 [R/W]
B,H,W
00000000
PPER04 [R/W]
B,H,W
00000000
PPER08 [R/W]
B,H,W
00000000
PPER12 [R/W]
B,H,W
00000000
―
―
PPER16 [R/W]
B,H,W
00000000
PPER01 [R/W]
B,H,W
00000000
PPER05 [R/W]
B,H,W
00000000
PPER09 [R/W]
B,H,W
00000000
PPER13 [R/W]
B,H,W
-0000000
―
―
PPER17 [R/W]
B,H,W
00000000
PPER02 [R/W]
B,H,W
00000000
PPER06 [R/W]
B,H,W
00000000
PPER10 [R/W]
B,H,W
00000000
PPER14 [R/W]
B,H,W
---000-―
―
PPER18 [R/W]
B,H,W
00000000
PPER03 [R/W]
B,H,W
00000000
PPER07 [R/W]
B,H,W
00000000
PPER11 [R/W]
B,H,W
00000000
PPER15 [R/W]
B,H,W
--000000
―
―
PPER19 [R/W]
B,H,W
00000000
Port Pull-up/down
Enable Register
―
―
―
―
Reserved
―
―
Port Enable Register
―
―
KeyCodeRegister
―
―
Reserved
PORTEN [R/W]
B,H,W
―
-------0
KEYCDR [R/W] H
00000000 00000000
―
Document Number: 002-04662 Rev. *F
―
Extended Port
Function Register
Page 72 of 280
MB91520 Series
Address
000F68H
000F6CH
000F70H
000F74H
000F78H
to
000F7CH
000F80H
000F84H
Address offset value / Register name
+1
+2
+3
MSCY6 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY7 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RCRH0 [W] H,W
RCRL0 [W] B,H,W
UDCRH0 [R] H,W UDCRL0 [R] B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
CCR0 [R/W] B,H
CSR0 [R/W] B
―
00000000 -0001000
00000000
+0
―
―
RCRH1 [W] H,W
RCRL1 [W] B,H,W
XXXXXXXX
XXXXXXXX
CCR1 [R/W] B,H
00000000 -0001000
Reserved
UDCRH1 [R] H,W
00000000
UDCRL1 [R] B,H,W
00000000
CSR1 [R/W] B
00000000
Up/Down Counter 1
―
―
―
000F8CH
―
―
MSCH67 [R]
B,H,W
00000000
000F98H
000F9CH
―
OCCP10 [R/W] W
00000000 00000000 00000000 00000000
OCCP11 [R/W] W
00000000 00000000 00000000 00000000
OCSH1011 [R/W]
―
B,H,W
---0--00
―
―
―
MSCL45 [R/W]
B,H,W
------00
MSCL67 [R/W]
B,H,W
------00
000FA4H
OCSL1011 [R/W]
B,H,W
0000--00
OCLS1011 [R/W]
B,H,W
----0000
TCCSH5
[R/W]B,H,W
0-----00
TCCSL5 [R/W]B,H,W
-1-00000
―
―
000FACH
to
000FCCH
―
―
―
―
000FD4H
000FD8H
―
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
LSYNS1 [R/W]
ICS45 [R/W] B,H,W
―
B,H,W
00000000
00000000
Document Number: 002-04662 Rev. *F
Output Compare 10,11
32-bit OCU
OCU1011
Output level control register
Free-run Timer 5
32-bit FRT
000FA8H
000FD0H
Input Capture 4,5
32-bit ICU
Cycle and pulse width
measurement control 45
Input Capture 6,7
32-bit ICU
Cycle and pulse width
measurement control 67
Output Compare 10,11
32-bit OCU
CPCLR5 [R/W] W
11111111 11111111 11111111 11111111
TCDT5 [R/W] W
00000000 00000000 00000000 00000000
000FA0H
Up/Down Counter 0
―
000F88H
000F94H
Input
Capture 6,7
Cycle measurement data
register 67
―
MSCH45 [R]
B,H,W
00000000
000F90H
Block
Reserved
Input
Capture 4,5
32-bit ICU
Page 73 of 280
MB91520 Series
Address
+0
000FDCH
000FE0H
000FE4H
―
000FE8H
000FECH
000FF0H
―
000FF4H
Address offset value / Register name
+1
+2
+3
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS67 [R/W] B,H,W
―
―
00000000
IPCP8 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP9 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS89 [R/W] B,H,W
―
―
00000000
MSCY8 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY9 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000FF8H
Block
Input
Capture 6,7
32-bit ICU
Input
Capture 8,9
32-bit ICU
Input
Capture 8,9
32-bit ICU
Cycle measurement data
register 89
000FFCH
―
―
MSCH89 [R] B,H,W
00000000
MSCL89 [R/W]
B,H,W
------00
Cycle and pulse width
measurement control 89
001000H
SACR [R/W] B,H,W
-------0
PICD [R/W] B,H,W
----0011
―
―
Clock Control
001004H
to
00112CH
―
―
―
―
Reserved
001130H
―
―
―
CRCCR [R/W] B,H,W
-0000000
CRCINIT [R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN [R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR [R] B,H,W
11111111 11111111 11111111 11111111
001134H
001138H
00113CH
001140H
to
0011FCH
001200H
001204H
001208H
00120CH
001210H
001214H
001218H
―
―
―
CRC calculation unit
―
TCGS [R/W] B,H,W
TCGSE [R/W] B,H,W
―
―
------00
-----000
CPCLRB0/CPCLR0 [W] H,W
TCDT0 [R/W] H,W
11111111 11111111
00000000 00000000
TCCS0 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1 [W] H,W
TCDT1 [R/W] H,W
11111111 11111111
00000000 00000000
TCCS1 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2 [W] H,W
TCDT2 [R/W] H,W
11111111 11111111
00000000 00000000
TCCS2 [R/W] B,H,W
00000000 01000000 ----0000 --------
Document Number: 002-04662 Rev. *F
Reserved
16-bit Free-run timer
synchronous activation
16-bit Free-run Timer 0
16-bit Free-run Timer 1
16-bit Free-run Timer 2
Page 74 of 280
MB91520 Series
Address
00121CH
to
001230H
001234H
001238H
00123CH
001240H
001244H
001248H
00124CH
001250H
001254H
001258H
00125CH
001260H
001264H
to
001278H
00127CH
001280H
001284H
001288H
00128CH
to
001298H
00129CH
+0
Address offset value / Register name
+1
+2
―
―
―
+3
―
FRS0 [R/W] B,H,W
-------- --00--00 --00--00 --00--00
FRS1 [R/W] B,H,W
―
--00--00 --00--00
FRS2 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS3 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS4 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
―
―
―
―
OCCPB0/OCCP0 [R/W] H,W
OCCPB1/OCCP1 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD01 [R/W]
OCS01 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB2/OCCP2 [R/W] H,W
OCCPB3/OCCP3 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD23 [R/W]
OCS23 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB4/OCCP4 [R/W] H,W
OCCPB5/OCCP5 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD45 [R/W]
OCS45 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
―
―
IPCP0 [R] H,W
00000000 00000000
ICS01 [R/W] B,H,W
------00 00000000
IPCP2 [R] H,W
00000000 00000000
ICS23 [R/W] B,H,W
------00 00000000
―
―
IPCP1 [R] H,W
00000000 00000000
LSYNS [R/W] B,H,W
―
----0000
IPCP3 [R] H,W
00000000 00000000
―
―
Block
Reserved
16-bit Free-run timer
selection
Reserved
16-bit Output compare 0/1
16-bit Output compare 2/3
16-bit Output compare 4/5
Reserved
16-bit Input capture 0/1
16-bit Input capture 2/3
―
―
―
―
Reserved
―
―
―
―
Reserved
Document Number: 002-04662 Rev. *F
Page 75 of 280
MB91520 Series
Address
0012A0H
0012A4H
0012A8H
0012ACH
0012B0H
0012B4H
0012B8H
to
0012CCH
Address offset value / Register name
+1
+2
+3
TMRR0 [R/W] H,W
TMRR1 [R/W] H,W
00000000 00000001
00000000 00000001
TMRR2 [R/W] H,W
―
―
00000000 00000001
DTSCR0 [R/W]
DTSCR1 [R/W]
DTSCR2 [R/W]
B,H,W
B,H,W
B,H,W
―
00000000
00000000
00000000
DTMNS0 [R/W]
DTIR0 [R/W] B,H,W
―
―
B,H,W
000000-00---000
SIGCR10 [R/W]
SIGCR20 [R/W]
―
B,H,W
―
B,H,W
00000000
000000-1
PICS0 [R/W] B,H,W
000000-- -------- -------- -------+0
―
0012D0H
0012D4H
0012D8H
0012DCH
to
0012FCH
001300H
001304H
001308H
00130CH
001310H
001314H
001318H
00131CH
001320H
001324H
001328H
―
―
―
―
Reserved
16-bit Free-run timer
selection
A/D activation compare
FRS6 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS7 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
16-bit Free-run timer
selection
A/D activation compare
―
―
―
―
Reserved
Reserved
―
―
ADTSE0[R/W] B,H,W
00000000 00000000 00000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
00000000 00000000
Document Number: 002-04662 Rev. *F
Waveform generator
0/1/2
FRS5 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
―
ADTSS0[R/W]
B,H,W
-------0
Block
12-bit A/D converter 1/2 unit
Page 76 of 280
MB91520 Series
Address
00132CH
001330H
001334H
001338H
00133CH
001340H
001344H
001348H
00134CH
001350H
001354H
001358H
00135CH
001360H
001364H
001368H
00136CH
001370H
001374H
001378H
00137CH
001380H
001384H
001388H
00138CH
Address offset value / Register name
+0
+1
+2
+3
ADCOMP16/ADCOMPB16[R/W] H,W
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP18/ADCOMPB18[R/W] H,W
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP22/ADCOMPB22[R/W] H,W
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP24/ADCOMPB24[R/W] H,W
ADCOMP25/ADCOMPB25[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP26/ADCOMPB26[R/W] H,W
ADCOMP27/ADCOMPB27[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP28/ADCOMPB28[R/W] H,W
ADCOMP29/ADCOMPB29[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP30/ADCOMPB30[R/W] H,W
ADCOMP31/ADCOMPB31[R/W] H,W
00000000 00000000
00000000 00000000
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS8[R/W] B,H,W
ADTCS9[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS10[R/W] B,H,W
ADTCS11[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS12[R/W] B,H,W
ADTCS13[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS14[R/W] B,H,W
ADTCS15[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS16[R/W] B,H,W
ADTCS17[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS18[R/W] B,H,W
ADTCS19[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS20[R/W] B,H,W
ADTCS21[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS22[R/W] B,H,W
ADTCS23[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS24[R/W] B,H,W
ADTCS25[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS26[R/W] B,H,W
ADTCS27[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS28[R/W] B,H,W
ADTCS29[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS30[R/W] B,H,W
ADTCS31[R/W] B,H,W
00000000 0010---00000000 0010---ADTCD0[R] B,H,W
ADTCD1[R] B,H,W
10--0000 00000000
10--0000 00000000
Document Number: 002-04662 Rev. *F
Block
12-bit A/D converter 1/2 unit
Page 77 of 280
MB91520 Series
Address
001390H
001394H
001398H
00139CH
0013A0H
0013A4H
0013A8H
0013ACH
0013B0H
0013B4H
0013B8H
0013BCH
0013C0H
0013C4H
0013C8H
0013CCH
0013D0H
0013D4H
0013D8H
0013DCH
0013E0H
0013E4H
0013E8H
0013ECH
0013F0H
Address offset value / Register name
+1
+2
+3
ADTCD2[R] B,H,W
ADTCD3[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD4[R] B,H,W
ADTCD5[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD6[R] B,H,W
ADTCD7[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD8[R] B,H,W
ADTCD9[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD10[R] B,H,W
ADTCD11[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD12[R] B,H,W
ADTCD13[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD14[R] B,H,W
ADTCD15[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD16[R] B,H,W
ADTCD17[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD18[R] B,H,W
ADTCD19[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD20[R] B,H,W
ADTCD21[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD22[R] B,H,W
ADTCD23[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD24[R] B,H,W
ADTCD25[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD26[R] B,H,W
ADTCD27[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD28[R] B,H,W
ADTCD29[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD30[R] B,H,W
ADTCD31[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTECS0[R/W] B,H,W
ADTECS1[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS2[R/W] B,H,W
ADTECS3[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS4[R/W] B,H,W
ADTECS5[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS6[R/W] B,H,W
ADTECS7[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS8[R/W] B,H,W
ADTECS9[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS10[R/W] B,H,W
ADTECS11[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS12[R/W] B,H,W
ADTECS13[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS14[R/W] B,H,W
ADTECS15[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS16[R/W] B,H,W
ADTECS17[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS18[R/W] B,H,W
ADTECS19[R/W] B,H,W
-------0 ---00000
-------0 ---00000
+0
Document Number: 002-04662 Rev. *F
Block
12-bit A/D converter 1/2 unit
Page 78 of 280
MB91520 Series
Address
0013F4H
0013F8H
0013FCH
001400H
001404H
001408H
00140CH
001410H
001414H
001418H
00141CH
001420H
001424H
001428H
00142CH
001430H
001434H
001438H
00143CH
001440H
001444H
Address offset value / Register name
+0
+1
+2
+3
ADTECS20[R/W] B,H,W
ADTECS21[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS22[R/W] B,H,W
ADTECS23[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS24[R/W] B,H,W
ADTECS25[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS26[R/W] B,H,W
ADTECS27[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS28[R/W] B,H,W
ADTECS29[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADTECS30[R/W] B,H,W
ADTECS31[R/W] B,H,W
-------0 ---00000
-------0 ---00000
ADRCUT0[R/W] B,H,W
ADRCLT0[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCUT1[R/W] B,H,W
ADRCLT1[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCUT2[R/W] B,H,W
ADRCLT2[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCUT3[R/W] B,H,W
ADRCLT3[R/W] B,H,W
----0000 00000000
----0000 00000000
ADRCCS0[R/W]
ADRCCS1[R/W]
ADRCCS2[R/W]
ADRCCS3[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS4[R/W]
ADRCCS5[R/W]
ADRCCS6[R/W]
ADRCCS7[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS8[R/W]
ADRCCS9[R/W]
ADRCCS10[R/W]
ADRCCS11[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS12[R/W]
ADRCCS13[R/W]
ADRCCS14[R/W]
ADRCCS15[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS16[R/W]
ADRCCS17[R/W]
ADRCCS18[R/W]
ADRCCS19[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS20[R/W]
ADRCCS21[R/W]
ADRCCS22[R/W]
ADRCCS23[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS24[R/W]
ADRCCS25[R/W]
ADRCCS26[R/W]
ADRCCS27[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCCS28[R/W]
ADRCCS29[R/W]
ADRCCS30[R/W]
ADRCCS31[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADRCOT0[R] B,H,W
00000000 00000000 00000000 00000000
ADRCIF0[R,W] B,H,W
00000000 00000000 00000000 00000000
ADSCANS0[R/W]
B,H,W
―
―
―
000-----
Document Number: 002-04662 Rev. *F
Block
12-bit A/D converter 1/2 unit
Page 79 of 280
MB91520 Series
Address
001448H
00144CH
001450H
001454H
001458H
00145CH
001460H
001464H
001468H
00146CH
001470H
001474H
001478H
00147CH
001480H
001484H
001488H
00148CH
001490H
001494H
001498H
to
0014B4H
Address offset value / Register name
Block
+1
+2
+3
ADNCS1[R/W]
ADNCS2[R/W]
ADNCS3[R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS5[R/W]
ADNCS6[R/W]
ADNCS7[R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS9[R/W]
ADNCS10[R/W]
ADNCS11[R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS13[R/W]
ADNCS14[R/W]
ADNCS15[R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
12-bit A/D converter 1/2 unit
ADPRTF0[R] B,H,W
00000000 00000000 00000000 00000000
ADEOCF0[R] B,H,W
11111111 11111111 11111111 11111111
ADCS0[R] B,H,W
ADCH0[R] B,H,W ADMD0[R/W] B,H,W
0------- ----------00000
0---0000
ADSTPCS0[R/W]
ADSTPCS1[R/W]
ADSTPCS2[R/W]
ADSTPCS3[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADSTPCS4[R/W]
ADSTPCS5[R/W]
ADSTPCS6[R/W]
ADSTPCS7[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
―
ADTSS1[R/W]
B,H,W
―
―
―
-------0
12-bit A/D converter 2/2 unit
ADTSE1[R/W] B,H,W
-------- -------- 00000000 00000000
ADCOMP32/ADCOMPB32[R/W] H,W
ADCOMP33/ADCOMPB33[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP34/ADCOMPB34[R/W] H,W
ADCOMP35/ADCOMPB35[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP36/ADCOMPB36[R/W] H,W
ADCOMP37/ADCOMPB37[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP38/ADCOMPB38[R/W] H,W
ADCOMP39/ADCOMPB39[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP40/ADCOMPB40[R/W] H,W
ADCOMP41/ADCOMPB41[R/W] H,W
12-bit A/D converter 2/2 unit
00000000 00000000
00000000 00000000
ADCOMP42/ADCOMPB42[R/W] H,W
ADCOMP43/ADCOMPB43[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP44/ADCOMPB44[R/W] H,W
ADCOMP45/ADCOMPB45[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP46/ADCOMPB46[R/W] H,W
ADCOMP47/ADCOMPB47[R/W] H,W
00000000 00000000
00000000 00000000
+0
ADNCS0[R/W]
B,H,W
0-000-00
ADNCS4[R/W]
B,H,W
0-000-00
ADNCS8[R/W]
B,H,W
0-000-00
ADNCS12[R/W]
B,H,W
0-000-00
―
Document Number: 002-04662 Rev. *F
―
―
―
Reserved
Page 80 of 280
MB91520 Series
Address
0014B8H
0014BCH
0014C0H
0014C4H
0014C8H
0014CCH
0014D0H
0014D4H
0014D8H
to
0014F4H
0014F8H
0014FCH
001500H
001504H
001508H
00150CH
001510H
001514H
001518H
to
001534H
Address offset value / Register name
+0
+1
+2
+3
ADTCS32[R/W] B,H,W
ADTCS33[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS34[R/W] B,H,W
ADTCS35[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS36[R/W] B,H,W
ADTCS37[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS38[R/W] B,H,W
ADTCS39[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS40[R/W] B,H,W
ADTCS41[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS42[R/W] B,H,W
ADTCS43[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS44[R/W] B,H,W
ADTCS45[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS46[R/W] B,H,W
ADTCS47[R/W] B,H,W
00000000 0010---00000000 0010---―
―
ADTCD32[R] B,H,W
10--0000 00000000
ADTCD34[R] B,H,W
10--0000 00000000
ADTCD36[R] B,H,W
10--0000 00000000
ADTCD38[R] B,H,W
10--0000 00000000
ADTCD40[R] B,H,W
10--0000 00000000
ADTCD42[R] B,H,W
10--0000 00000000
ADTCD44[R] B,H,W
10--0000 00000000
ADTCD46[R] B,H,W
10--0000 00000000
―
Document Number: 002-04662 Rev. *F
―
―
―
ADTCD33[R] B,H,W
10--0000 00000000
ADTCD35[R] B,H,W
10--0000 00000000
ADTCD37[R] B,H,W
10--0000 00000000
ADTCD39[R] B,H,W
10--0000 00000000
ADTCD41[R] B,H,W
10--0000 00000000
ADTCD43[R] B,H,W
10--0000 00000000
ADTCD45[R] B,H,W
10--0000 00000000
ADTCD47[R] B,H,W
10--0000 00000000
―
―
Block
12-bit A/D converter 2/2 unit
Reserved
12-bit A/D converter 2/2 unit
12-bit A/D converter 2/2 unit
Reserved
Page 81 of 280
MB91520 Series
Address
001538H
00153CH
001540H
001544H
001548H
00154CH
001550H
001554H
001558H
to
001574H
001578H
00157CH
001580H
001584H
001588H
00158CH
001590H
001594H
001598H
to
0015A4H
Address offset value / Register name
+0
+1
+2
+3
ADTECS32[R/W] B,H,W
ADTECS33[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS34[R/W] B,H,W
ADTECS35[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS36[R/W] B,H,W
ADTECS37[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS38[R/W] B,H,W
ADTECS39[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS40[R/W] B,H,W
ADTECS41[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS42[R/W] B,H,W
ADTECS43[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS44[R/W] B,H,W
ADTECS45[R/W] B,H,W
-------0 ----0000
-------0 ----0000
ADTECS46[R/W] B,H,W
ADTECS47[R/W] B,H,W
-------0 ----0000
-------0 ----0000
―
ADRCUT4[R/W] B,H,W
----0000 00000000
ADRCUT5[R/W] B,H,W
----0000 00000000
ADRCUT6[R/W] B,H,W
----0000 00000000
ADRCUT7[R/W] B,H,W
----0000 00000000
ADRCCS32[R/W]
ADRCCS33[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS36[R/W]
ADRCCS37[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS40[R/W]
ADRCCS41[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS44[R/W]
ADRCCS45[R/W]
B,H,W
B,H,W
00000000
00000000
―
―
―
―
ADRCLT4[R/W] B,H,W
----0000 00000000
ADRCLT5[R/W] B,H,W
----0000 00000000
ADRCLT6[R/W] B,H,W
----0000 00000000
ADRCLT7[R/W] B,H,W
----0000 00000000
ADRCCS34[R/W]
ADRCCS35[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS38[R/W]
ADRCCS39[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS42[R/W]
ADRCCS43[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS46[R/W]
ADRCCS47[R/W]
B,H,W
B,H,W
00000000
00000000
―
―
ADRCOT1 [R] B,H,W
-------- -------- 00000000 00000000
ADRCIF1 [R,W] B,H,W
-------- -------- 00000000 00000000
0015A8H
0015ACH
0015B0H
―
ADSCANS1 [R/W]
B,H,W
000-----
Document Number: 002-04662 Rev. *F
―
―
Block
12-bit A/D converter 2/2 unit
Reserved
12-bit A/D converter 2/2 unit
12-bit A/D converter 2/2 unit
Reserved
12-bit A/D converter 2/2 unit
―
Page 82 of 280
MB91520 Series
Address
0015B4H
0015B8H
0015BCH
0015C0H
0015C4H
0015C8H
0015CCH
0015D0H
0015D4H
to
00174CH
001750H
001754H
001758H
00175CH
001760H
001764H
001768H
00176CH
001770H
001774H
Address offset value / Register name
Block
+1
+2
+3
ADNCS17 [R/W]
ADNCS18 [R/W]
ADNCS19 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS21 [R/W]
ADNCS22 [R/W]
ADNCS23 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
―
―
―
―
―
―
12-bit A/D converter 2/2 unit
ADPRTF1 [R] B,H,W
-------- -------- 00000000 00000000
ADEOCF1 [R] B,H,W
-------- -------- 11111111 11111111
ADCS1 [R] B,H,W
ADCH1 [R] B,H,W ADMD1 [R/W] B,H,W
0------- ----------00000
0---0000
ADSTPCS8 [R/W]
ADSTPCS9 [R/W] ADSTPCS10 [R/W] ADSTPCS11 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
+0
ADNCS16 [R/W]
B,H,W
0-000-00
ADNCS20 [R/W]
B,H,W
0-000-00
―
―
―
―
SCR0/(IBCR0)[R/W]
SMR0[R/W]
B,H,W
B,H,W
0--00000
000-00-0
― /(RDR10/(TDR10))[R/W] B,H,W
-------- -------- *3
SACSR0[R/W] B,H,W
0----000 00000000
STMCR0[R/W] B,H,W
00000000 00000000
― /(SCSTR30)/
― /(SCSTR20)/
(LAMSR0)
(LAMCR0)
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
― /(SCSFR20)
―
[R/W] B,H,W
-------- *3
―/(TBYTE30)/
(LAMESR0)
[R/W] B,H,W
-------- *3
―/(TBYTE20)
/(LAMERT0)
[R/W] B,H,W
-------- *3
BGR0[R/W] H, W
00000000 00000000
FCR10[R/W]
FCR00[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR0[R/W] B,H,W
00000000 00000000
Document Number: 002-04662 Rev. *F
―
―
Reserved
SSR0[R/W]
ESCR0/(IBSR0)[R/W
B,H,W
] B,H,W
0-000011
00000000
RDR00/(TDR00)[R/W] B,H,W
-------0 00000000 *1
STMR0[R] B,H,W
00000000 00000000
Multi-UART0
― /(SCSCR0/SFUR0)[R/W] B,H,W
*1:
Byte
access is possible
-------- -------- *3 *4
only for access to lower 8
― /(SCSTR10)
― /(SCSTR00)/
bits.
/(SFLR10)
(SFLR00)
[R/W] B,H,W
[R/W] B,H,W
*2: Reserved because I2C
-------- *3
-------- *3
mode is not set immediately
― /(SCSFR10)
― /(SCSFR00)
after reset.
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
*3: Reserved because CSIO
TBYTE00/(LAMRID0)
mode is not set immediately
―/(TBYTE10)/
/
after reset.
(LAMIER0)
(LAMTID0)
[R/W] B,H,W
[R/W] B,H,W
*4: Reserved because
-------- *3
00000000
LIN2.1 mode is not set
― /(ISMK0)
― /(ISBA0)
immediately after reset.
[R/W] B,H,W
[R/W] B,H,W
-------- *2
-------- *2
FBYTE0[R/W] B,H,W
00000000 00000000
―
―
Page 83 of 280
MB91520 Series
Address
001778H
00177CH
001780H
001784H
001788H
00178CH
001790H
001794H
001798H
00179CH
Address offset value / Register name
Block
+0
+1
+2
+3
SCR1/(IBCR1) [R/W]
ESCR1/(IBSR1)[R/W
SMR1[R/W] B,H,W SSR1[R/W] B,H,W
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
Multi-UART1
― /(RDR11/(TDR11))[R/W] B,H,W
RDR01/(TDR01)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR1[R/W] B,H,W
STMR1[R] B,H,W
0----000 00000000
00000000 00000000
Multi-UART1
STMCR1[R/W] B,H,W
― /(SCSCR1/SFUR1)[R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
*1: Byte access is possible
only for access to lower 8
― /(SCSTR31)/
― /(SCSTR21)/
― /(SCSTR11)/
― /(SCSTR01)/
bits.
(LAMSR1)
(LAMCR1)
(SFLR11)
(SFLR01)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
*2: Reserved because I2C
-------- *3
-------- *3
-------- *3
-------- *3
mode is not set immediately
― /(SCSFR21)[R/W]
― /(SCSFR11)
― /(SCSFR01)
―
after reset.
B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
TBYTE01/(LAMRID1)
―/(TBYTE31)/
―/(TBYTE21)/
―/(TBYTE11)/
/
(LAMESR1)
(LAMERT1)
(LAMIER1)
(LAMTID1)
Multi-UART1
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
*3
*3
*3
---------------------00000000
*3: Reserved because CSIO
― /(ISMK1)[R/W]
― /(ISBA1)[R/W] mode is not set immediately
BGR1[R/W] H,W
B,H,W
B,H,W
after reset.
00000000 00000000
-------- *2
-------- *2
*4: Reserved because
FCR11[R/W]
FCR01[R/W]
FBYTE1[R/W] B,H,W
LIN2.1 mode is not set
B,H,W
B,H,W
00000000 00000000
immediately after reset.
---00100
-0000000
FTICR1[R/W] B,H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Page 84 of 280
MB91520 Series
Address offset value / Register name
Block
+0
+1
+2
+3
SCR2/(IBCR2)[R/W]
ESCR2/(IBSR2)[R/W
SMR2[R/W] B,H,W SSR2[R/W] B,H,W
0017A0H
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
― /(RDR12/(TDR12))[R/W] B,H,W
RDR02/(TDR02)[R/W] B,H,W
0017A4H
Multi-UART2
-------- -------- *3
-------0 00000000 *1
SACSR2[R/W] B,H,W
STMR2[R] B,H,W
0017A8H
*1: Byte access is possible
0----000 00000000
00000000 00000000
only for access to lower 8
STMCR2[R/W] B,H,W
― /(SCSCR2/SFUR2)[R/W] B,H,W
0017ACH
bits.
*3 *4
00000000 00000000
-------- -------― /(SCSTR32)/
― /(SCSTR22)/
― /(SCSTR12)/
― /(SCSTR02)/
*2: Reserved because I2C
(LAMSR2)
(LAMCR2)
(SFLR12)
(SFLR02)
mode is not set immediately
0017B0H
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
*3
*3
*3
*3
----------------------------― /(SCSFR22)
― /(SCSFR12)
― /(SCSFR02)
*3: Reserved because CSIO
0017B4H
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
mode is not set immediately
-------- *3
-------- *3
-------- *3
after reset.
TBYTE02/(LAMRID2)
―/(TBYTE32)/
―/(TBYTE22)/
―/(TBYTE12)/
/
*4: Reserved because
(LAMESR2)
(LAMERT2)
(LAMIER2)
0017B8H
(LAMTID2)
LIN2.1 mode is not set
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
immediately after reset.
-------- *3
-------- *3
-------- *3
00000000
― /(ISMK2)[R/W]
― /(ISBA2)[R/W]
BGR2[R/W] H, W
0017BCH
B,H,W
B,H,W
00000000 00000000
-------- *2
-------- *2
FCR12[R/W]
FCR02[R/W]
FBYTE2[R/W] B,H,W
0017C0H
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
Multi-UART2
FTICR2[R/W] B,H,W
0017C4H
―
―
00000000 00000000
Address
Document Number: 002-04662 Rev. *F
Page 85 of 280
MB91520 Series
Address
0017C8H
0017CCH
0017D0H
0017D4H
0017D8H
0017DCH
0017E0H
0017E4H
0017E8H
0017ECH
0017F0H
0017F4H
0017F8H
0017FCH
001800H
Address offset value / Register name
Block
+0
+1
+2
+3
SCR3/(IBCR3) [R/W]
ESCR3/(IBSR3)[R/W
SMR3[R/W] B,H,W SSR3[R/W] B,H,W
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
― /(RDR13/(TDR13))[R/W] B,H,W
RDR03/(TDR03)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR3[R/W] B,H,W
STMR3[R] B,H,W
0----000 00000000
00000000 00000000
Multi-UART3
STMCR3[R/W] B,H,W
― /(SCSCR3/SFUR3)[R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
*1: Byte access is possible
― /(SCSTR33)/
― /(SCSTR23)/
― /(SCSTR13)/
― /(SCSTR03)/
only for access to lower 8
(LAMSR3)
(LAMCR3)
(SFLR13)
(SFLR03)
bits.
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
-------- *3
*2: Reserved because I2C
mode is not set immediately
― /(SCSFR23)
― /(SCSFR13)
― /(SCSFR03)
―
after reset.
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
TBYTE03/(LAMRID3) *3: Reserved because CSIO
―/(TBYTE33)/
―/(TBYTE23)/
―/(TBYTE13)/
mode is not set immediately
/
(LAMESR3)
(LAMERT3)
(LAMIER3)
after reset.
(LAMTID3)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W]
B,H,W
-------- *3
-------- *3
-------- *3
*4: Reserved because
00000000
LIN2.1
mode is not set
― /(ISMK3)[R/W]
― /(ISBA3)[R/W]
BGR3[R/W] H, W
immediately
after reset.
B,H,W
B,H,W
00000000 00000000
*2
*2
--------------FCR13[R/W]
FCR03[R/W]
FBYTE3[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
FTICR3[R/W] B,H,W
―
―
00000000 00000000
SCR4/(IBCR4) [R/W]
ESCR4/(IBSR4)[R/W
SMR4[R/W] B,H,W SSR4[R/W] B,H,W
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
Multi-UART4
― /(RDR14/(TDR14))[R/W] B,H,W
RDR04/(TDR04)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
*1: Byte access is possible
SACSR4[R/W] B,H,W
STMR4[R] B,H,W
only for access to lower 8
0----000 00000000
00000000 00000000
bits.
STMCR4[R/W] B,H,W
― /(SCSCR4/SFUR4)[R/W] B,H,W
*2: Reserved because I2C
00000000 00000000
-------- -------- *3 *4
mode
is not set immediately
― /(SCSTR34)/
― /(SCSTR24)/
― /(SCSTR14)/
― /(SCSTR04)/
after reset.
(LAMSR4)
(LAMCR4)
(SFLR14)
(SFLR04)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
-------- *3
Document Number: 002-04662 Rev. *F
Page 86 of 280
MB91520 Series
Address
+0
001804H
―
001808H
―/(TBYTE34)/
(LAMESR4)
[R/W] B,H,W
-------- *3
00180CH
001810H
001814H
001818H
00181CH
001820H
001824H
001828H
00182CH
001830H
001834H
Address offset value / Register name
+1
+2
― /(SCSFR24)
― /(SCSFR14)
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
―/(TBYTE24)/
(LAMERT4)
[R/W] B,H,W
-------- *3
BGR4[R/W] H, W
00000000 00000000
FCR14[R/W]
FCR04[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR4[R/W] B,H,W
00000000 00000000
SCR5/(IBCR5) [R/W]
SMR5[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR15/(TDR15))[R/W] B,H,W
-------- -------- *3
SACSR5[R/W] B,H,W
0----000 00000000
STMCR5[R/W] B,H,W
00000000 00000000
― /(SCSTR35)/
― /(SCSTR25)/
(LAMSR5)
(LAMCR5)
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
― /(SCSFR25)
―
[R/W] B,H,W
-------- *3
―/(TBYTE35)/
(LAMESR5)
[R/W] B,H,W
-------- *3
―/(TBYTE25)/
(LAMERT5)
[R/W] B,H,W
-------- *3
BGR5[R/W] H, W
00000000 00000000
FCR15[R/W]
FCR05[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR5[R/W] B,H,W
00183CH
00000000 00000000
SCR6/(IBCR6) [R/W]
SMR6[R/W] B,H,W
001840H
B,H,W
000-00-0
0--00000
001838H
Document Number: 002-04662 Rev. *F
Block
+3
― /(SCSFR04)
[R/W] B,H,W
-------- *3
TBYTE04/(LAMRID4)
―/(TBYTE14)/
Multi-UART4
/
(LAMIER4)
(LAMTID4)
[R/W] B,H,W
*3: Reserved because CSIO
[R/W]
B,H,W
-------- *3
mode is not set immediately
00000000
after reset.
― /(ISMK4)[R/W]
― /(ISBA4)[R/W]
B,H,W
B,H,W
*4: Reserved because
-------- *2
-------- *2
LIN2.1 mode is not set
immediately after reset.
FBYTE4[R/W] B,H,W
00000000 00000000
―
―
ESCR5/(IBSR5)[R/W
] B,H,W
00000000
RDR05/(TDR05)[R/W] B,H,W
-------0 00000000 *1
STMR5[R] B,H,W
00000000 00000000
Multi-UART5
― /(SCSCR5/SFUR5)[R/W] B,H,W
-------- -------- *3 *4
*1: Byte access is possible
― /(SCSTR15)/
― /(SCSTR05)/
only for access to lower 8
(SFLR15)
(SFLR05)
bits.
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
*2: Reserved because I2C
mode is not set immediately
― /(SCSFR15)
― /(SCSFR05)
after reset.
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
TBYTE05/(LAMRID5) *3: Reserved because CSIO
―/(TBYTE15)/
mode is not set immediately
/
(LAMIER5)
after reset.
(LAMTID5)
[R/W] B,H,W
[R/W]
B,H,W
-------- *3
*4: Reserved because
00000000
LIN2.1 mode is not set
― /(ISMK5)[R/W]
― /(ISBA5)[R/W]
immediately after reset.
B,H,W
B,H,W
-------- *2
-------- *2
SSR5[R/W] B,H,W
0-000011
FBYTE5[R/W] B,H,W
00000000 00000000
―
―
SSR6[R/W] B,H,W
0-000011
ESCR6/(IBSR6)[R/W
] B,H,W
00000000
Multi-UART6
Page 87 of 280
MB91520 Series
Address
001844H
001848H
00184CH
001850H
001854H
001858H
00185CH
001860H
001864H
001868H
00186CH
001870H
001874H
001878H
00187CH
001880H
Address offset value / Register name
Block
+0
+1
+2
+3
― /(RDR16/(TDR16))[R/W] B,H,W
RDR06/(TDR06)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR6[R/W] B,H,W
STMR6[R] B,H,W
0----000 00000000
00000000 00000000
STMCR6[R/W] B,H,W
― /(SCSCR6/SFUR6)[R/W] B,H,W
Multi-UART6
00000000 00000000
-------- -------- *3 *4
― /(SCSTR36)/
― /(SCSTR26)/
― /(SCSTR16)/
― /(SCSTR06)/
*1: Byte access is possible
(LAMSR6)
(LAMCR6)
(SFLR16)
(SFLR06)
only for access to lower 8
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
bits.
*3
*3
*3
*3
----------------------------― /(SCSFR26)
― /(SCSFR16)
― /(SCSFR06)
*2: Reserved because I2C
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
mode is not set immediately
*3
*3
*3
---------------------after reset.
TBYTE06/(LAMRID6)
―/(TBYTE36)/
―/(TBYTE26)/
―/(TBYTE16)/
/
*3: Reserved because CSIO
(LAMESR6)
(LAMERT6)
(LAMIER6)
(LAMTID6)
mode is not set immediately
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
-------- *3
-------- *3
-------- *3
00000000
― /(ISMK6)[R/W]
― /(ISBA6)[R/W]
*4: Reserved because
BGR6[R/W] H, W
B,H,W
B,H,W
LIN2.1
mode is not set
00000000 00000000
-------- *2
-------- *2
immediately after reset.
FCR16[R/W]
FCR06[R/W]
FBYTE6[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
FTICR6[R/W] B,H,W
―
―
00000000 00000000
SCR7/(IBCR7) [R/W]
ESCR7/(IBSR7)[R/W
Multi-UART7
SMR7[R/W] B,H,W SSR7[R/W] B,H,W
B,H,W
] B,H,W
*1: Byte access is possible
000-00-0
0-000011
0--00000
00000000
only for access to lower 8
― /(RDR17/(TDR17))[R/W] B,H,W
RDR07/(TDR07)[R/W] B,H,W
bits.
-------- -------- *3
-------0 00000000 *1
*2: Reserved because I2C
SACSR7[R/W] B,H,W
STMR7[R] B,H,W
mode is not set immediately
0----000 00000000
00000000 00000000
after reset.
STMCR7[R/W] B,H,W
― /(SCSCR7/SFUR7)[R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
― /(SCSTR37)/
― /(SCSTR27)/
― /(SCSTR17)/
― /(SCSTR07)/
(LAMSR7)
(LAMCR7)
(SFLR17)
(SFLR07)
Multi-UART7
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
-------- *3
*3: Reserved because CSIO
― /(SCSFR27)
― /(SCSFR17)
― /(SCSFR07)
mode is not set immediately
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
-------- *3
-------- *3
-------- *3
TBYTE07/(LAMRID7)
*4: Reserved because
―/(TBYTE37)/
―/(TBYTE27)/
―/(TBYTE17)/
/
LIN2.1 mode is not set
(LAMESR7)
(LAMERT7)
(LAMIER7)
(LAMTID7)
immediately after reset.
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
*3
*3
*3
---------------------00000000
Document Number: 002-04662 Rev. *F
Page 88 of 280
MB91520 Series
Address
001884H
001888H
00188CH
001890H
001894H
001898H
00189CH
0018A0H
0018A4H
0018A8H
0018ACH
0018B0H
0018B4H
Address offset value / Register name
Block
+1
+2
+3
― /(ISMK7)[R/W]
― /(ISBA7)[R/W]
BGR7[R/W] H, W
B,H,W
B,H,W
00000000 00000000
-------- *2
-------- *2
FCR17[R/W]
FCR07[R/W]
FBYTE7[R/W] B,H,W
Multi-UART7
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
FTICR7[R/W] B,H,W
―
―
00000000 00000000
SCR8/(IBCR8) [R/W]
ESCR8/(IBSR8)[R/W
SMR8[R/W] B,H,W SSR8[R/W] B,H,W
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
― /(RDR18/(TDR18))[R/W] B,H,W
RDR08/(TDR08)[R/W] B,H,W
Multi-UART8
-------- -------- *3
-------0 00000000 *1
SACSR8[R/W] B,H,W
STMR8[R] B,H,W
*1: Byte access is possible
0----000 00000000
00000000 00000000
only for access to lower 8
STMCR8[R/W] B,H,W
― /(SCSCR8/SFUR8)[R/W] B,H,W
bits.
00000000 00000000
-------- -------- *3 *4
― /(SCSTR38)/
― /(SCSTR28)/
― /(SCSTR18)/
― /(SCSTR08)/
*2: Reserved because I2C
(LAMSR8)
(LAMCR8)
(SFLR18)
(SFLR08)
mode is not set immediately
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
-------- *3
-------- *3
-------- *3
-------- *3
― /(SCSFR28)
― /(SCSFR18)
― /(SCSFR08)
*3: Reserved because CSIO
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
mode is not set immediately
-------- *3
-------- *3
-------- *3
after reset.
TBYTE08/(LAMRID8)
―/(TBYTE38)/
―/(TBYTE28)/
―/(TBYTE18)/
/
*4: Reserved because
(LAMESR8)
(LAMERT8)
(LAMIER8)
(LAMTID8)
LIN2.1 mode is not set
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
immediately after reset.
-------- *3
-------- *3
-------- *3
00000000
― /(ISMK8)[R/W]
― /(ISBA8)[R/W]
BGR8[R/W] H,W
B,H,W
B,H,W
00000000 00000000
-------- *2
-------- *2
FCR18[R/W]
FCR08[R/W]
FBYTE8[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
Multi-UART8
FTICR8[R/W] B,H,W
―
―
00000000 00000000
+0
Document Number: 002-04662 Rev. *F
Page 89 of 280
MB91520 Series
Address
0018B8H
0018BCH
0018C0H
0018C4H
0018C8H
0018CCH
0018D0H
0018D4H
0018D8H
0018DCH
0018E0H
0018E4H
0018E8H
0018ECH
Address offset value / Register name
Block
+0
+1
+2
+3
SCR9/(IBCR9) [R/W]
ESCR9/(IBSR9)[R/W
SMR9[R/W] B,H,W SSR9[R/W] B,H,W
B,H,W
] B,H,W
000-00-0
0-000011
0--00000
00000000
― /(RDR19/(TDR19))[R/W] B,H,W
RDR09/(TDR09)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR9[R/W] B,H,W
STMR9[R] B,H,W
0----000 00000000
00000000 00000000
Multi-UART9
STMCR9[R/W] B,H,W
― /(SCSCR9/SFUR9)[R/W] B,H,W
*1: Byte access is possible
*3 *4
00000000 00000000
-------- -------only for access to lower 8
― /(SCSTR39)/
― /(SCSTR29)/
― /(SCSTR19)/
― /(SCSTR09)/
bits.
(LAMSR9)
(LAMCR9)
(SFLR19)
(SFLR09)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
*2: Reserved because I2C
-------- *3
-------- *3
-------- *3
-------- *3
mode is not set immediately
― /(SCSFR29)
― /(SCSFR19)
― /(SCSFR09)
after reset.
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
-------- *3
-------- *3
-------- *3
*3: Reserved because CSIO
TBYTE09/(LAMRID9)
mode is not set immediately
―/(TBYTE39)/
―/(TBYTE29)/
―/(TBYTE19)/
/
after reset.
(LAMESR9)
(LAMERT9)
(LAMIER9)
(LAMTID9)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
*4: Reserved because
-------- *3
-------- *3
-------- *3
00000000
LIN2.1 mode is not set
― /(ISMK9)[R/W]
― /(ISBA9)[R/W]
immediately after reset.
BGR9[R/W] H, W
B,H,W
B,H,W
00000000 00000000
-------- *2
-------- *2
FCR19[R/W]
FCR09[R/W]
FBYTE9[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
FTICR9[R/W] B,H,W
―
―
00000000 00000000
SCR10/(IBCR10)
ESCR10/(IBSR10)
Multi-UART10
SMR10[R/W] B,H,W SSR10[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
000-00-0
0-000011
0--00000
00000000
*1: Byte access is possible
― /(RDR110/(TDR110))[R/W] B,H,W
RDR010/(TDR010)[R/W] B,H,W
only for access to lower 8
-------- -------- *3
-------0 00000000 *1
bits.
SACSR10[R/W] B,H,W
STMR10[R] B,H,W
*2: Reserved because I2C
0----000 00000000
00000000 00000000
mode is not set immediately
STMCR10[R/W] B,H,W
― /(SCSCR10/SFUR10)[R/W] B,H,W
after reset.
00000000 00000000
-------- -------- *3 *4
Document Number: 002-04662 Rev. *F
Page 90 of 280
MB91520 Series
Address
0018F0H
0018F4H
0018F8H
0018FCH
001900H
001904H
001908H
00190CH
001910H
001914H
001918H
00191CH
001920H
001924H
001928H
00192CH
001930H
to
0019D8H
Address offset value / Register name
Block
+1
+2
+3
― /(SCSTR210)/
― /(SCSTR110)/
― /(SCSTR010)/
(LAMCR10)
(SFLR110)[R/W]
(SFLR010)[R/W]
[R/W] B,H,W
B,H,W
B,H,W
-------- *3
-------- *3
-------- *3
― /(SCSFR210)
― /(SCSFR110)
― /(SCSFR010)
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
Multi-UART10
-------- *3
-------- *3
-------- *3
―/(TBYTE310)/
―/(TBYTE210)/
―/(TBYTE110)/
TBYTE010/(LAMRID *3: Reserved because CSIO
(LAMESR10)
(LAMERT10)
(LAMIER10)
10)/(LAMTID10) mode is not set immediately
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
-------- *3
-------- *3
-------- *3
00000000
*4: Reserved because
― /(ISMK10)[R/W] ― /(ISBA10)[R/W]
BGR10[R/W] H, W
LIN2.1 mode is not set
B,H,W
B,H,W
00000000 00000000
immediately after reset.
-------- *2
-------- *2
FCR110[R/W]
FCR010[R/W]
FBYTE10[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
FTICR10[R/W] B,H,W
―
―
00000000 00000000
SCR11/(IBCR11)
ESCR11/(IBSR11)
SMR11[R/W] B,H,W SSR11[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
000-00-0
0-000011
0--00000
00000000
― /(RDR111/(TDR111))[R/W] B,H,W
RDR011/(TDR011)[R/W] B,H,W
Multi-UART11
-------- -------- *3
-------0 00000000 *1
*1: Byte access is possible
SACSR11[R/W] B,H,W
STMR11[R] B,H,W
only for access to lower 8
0----000 00000000
00000000 00000000
bits.
STMCR11[R/W] B,H,W
― /(SCSCR11/SFUR11)[R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
*2: Reserved because I2C
― /(SCSTR311)/
― /(SCSTR211)/
― /(SCSTR111)/
― /(SCSTR011)/
mode is not set immediately
(LAMSR11)
(LAMCR11)
(SFLR111)[R/W]
(SFLR011)[R/W]
after reset.
[R/W] B,H,W
[R/W] B,H,W
B,H,W
B,H,W
-------- *3
-------- *3
-------- *3
-------- *3
*3: Reserved because CSIO
― /(SCSFR211)
― /(SCSFR111)
― /(SCSFR011)
mode is not set immediately
―
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
after reset.
-------- *3
-------- *3
-------- *3
―/(TBYTE311)/
―/(TBYTE211)/
―/(TBYTE111)/
TBYTE011/(LAMRID
*4: Reserved because
(LAMESR11)
(LAMERT11)
(LAMIER11)
11)/(LAMTID11)
LIN2.1 mode is not set
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
immediately after reset.
-------- *3
-------- *3
-------- *3
00000000
― /(ISMK11)[R/W]
― /(ISBA11)[R/W]
BGR11[R/W] H, W
B,H,W
B,H,W
00000000 00000000
-------- *2
-------- *2
FCR111[R/W]
FCR011[R/W]
FBYTE11[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
---00100
-0000000
Multi-UART11
FTICR11[R/W] B,H,W
―
―
00000000 00000000
+0
― /(SCSTR310)/
(LAMSR10)
[R/W] B,H,W
-------- *3
―
Document Number: 002-04662 Rev. *F
―
―
―
Reserved
Page 91 of 280
MB91520 Series
Address
0019DCH
0019E0H
0019E4H
0019E8H
0019ECH
0019F0H
0019F4H
0019F8H
0019FCH
001A00H
001A04H
001A08H
001A0CH
001A10H
001A14H
001A18H
to
001A2CH
001A30H
001A34H
001A38H
001A3CH
001A40H
001A44H
001A48H
001A4CH
001A50H
Address offset value / Register name
+1
+2
+3
GATEC0 [R/W]
GATEC2 [R/W]
―
B,H,W
―
B,H,W
------00
------00
GATEC4 [R/W]
―
B,H,W
―
―
------00
―
―
―
―
GTRS0 [R/W] B,H,W
GTRS1 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS2 [R/W] B,H,W
GTRS3 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS4 [R/W] B,H,W
GTRS5 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS6 [R/W] B,H,W
GTRS7 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS8 [R/W] B,H,W
GTRS9 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS10 [R/W] B,H,W
GTRS11 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS12 [R/W] B,H,W
GTRS13 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS14 [R/W] B,H,W
GTRS15 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS16 [R/W] B,H,W
GTRS17 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS18 [R/W] B,H,W
GTRS19 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS20 [R/W] B,H,W
GTRS21 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
GTRS22 [R/W] B,H,W
GTRS23 [R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
+0
―
―
―
―
―
―
GTREN0 [R/W] H,W
00000000 00000000
GTREN2 [R/W] H,W
00000000 00000000
PCN0 [R/W] B,H,W
00000000 000000-0
PDUT0 [W] H,W
XXXXXXXX XXXXXXXX
PCN200 [R/W] B,H,W
--000000 -----110
PTPC0 [R/W] H,W
00000000 00000000
PHCSR0 [W] H,W
XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *F
―
―
―
―
―
―
GTREN1 [R/W] H,W
00000000 00000000
―
―
PCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PTMR0 [R] H,W
11111111 11111111
PSDR0 [R/W] H,W
00000000 00000000
PCMDWD0 [R/W] B,H,W
-------- ----0000
PLCSR0 [W] H,W
XXXXXXXX XXXXXXXX
Block
PPG GATE control
Reserved
PPG
controller
PPG
controller
Reserved
Reserved
PPG
controller
PPG0
* for communication
Page 92 of 280
MB91520 Series
Address
001A54H
001A58H
001A5CH
001A60H
001A64H
001A68H
001A6CH
001A70H
001A74H
001A78H
001A7CH
001A80H
001A84H
001A88H
001A8CH
001A90H
001A94H
001A98H
001A9CH
001AA0H
001AA4H
001AA8H
001AACH
001AB0H
001AB4H
Address offset value / Register name
+1
+2
+3
PHDUT0 [W] H,W
PLDUT0 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PCMDDT0 [R/W] H,W
―
―
00000000 00000000
PCN1 [R/W] B,H,W
PCSR1 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT1 [W] H,W
PTMR1 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN201 [R/W] B,H,W
PSDR1 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC1 [R/W] H,W
PCMDWD1 [R/W] B,H,W
00000000 00000000
-------- ----0000
PHCSR1 [W] H,W
PLCSR1 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PHDUT1 [W] H,W
PLDUT1 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PCMDDT1 [R/W] H,W
―
―
00000000 00000000
PCN2 [R/W] B,H,W
PCSR2 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT2 [W] H,W
PTMR2 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN202 [R/W] B,H,W
PSDR2 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC2 [R/W] H,W
PCMDWD2 [R/W] B,H,W
00000000 00000000
-------- ----0000
PHCSR2 [W] H,W
PLCSR2 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PHDUT2 [W] H,W
PLDUT2 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PCMDDT2 [R/W] H,W
―
―
00000000 00000000
PCN3 [R/W] B,H,W
PCSR3 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT3 [W] H,W
PTMR3 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN203 [R/W] B,H,W
PSDR3 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC3 [R/W] H,W
PCMDWD3 [R/W] B,H,W
00000000 00000000
-------- ----0000
PHCSR3 [W] H,W
PLCSR3 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PHDUT3 [W] H,W
PLDUT3 [W] H,W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PCMDDT3 [R/W] H,W
―
―
00000000 00000000
PCN4 [R/W] B,H,W
PCSR4 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT4 [W] H,W
PTMR4 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
+0
Document Number: 002-04662 Rev. *F
Block
PPG0
* for communication
PPG1
* for communication
PPG1
* for communication
PPG2
* for communication
PPG2
* for communication
PPG3
* for communication
PPG4
Page 93 of 280
MB91520 Series
Address
001AB8H
001ABCH
001AC0H
001AC4H
001AC8H
001ACCH
001AD0H
001AD4H
001AD8H
001ADCH
001AE0H
001AE4H
001AE8H
001AECH
001AF0H
001AF4H
001AF8H
001AFCH
001B00H
001B04H
001B08H
001B0CH
001B10H
001B14H
Address offset value / Register name
+0
+1
+2
+3
PCN204 [R/W] B,H,W
PSDR4 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC4 [R/W] H,W
―
―
00000000 00000000
PCN5 [R/W] B,H,W
PCSR5 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT5 [W] H,W
PTMR5 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN205 [R/W] B,H,W
PSDR5 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC5 [R/W] H,W
―
―
00000000 00000000
PCN6 [R/W] B,H,W
PCSR6 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT6 [W] H,W
PTMR6 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN206 [R/W] B,H,W
PSDR6 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC6 [R/W] H,W
―
―
00000000 00000000
PCN7 [R/W] B,H,W
PCSR7 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT7 [W] H,W
PTMR7 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN207 [R/W] B,H,W
PSDR7 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC7 [R/W] H,W
―
―
00000000 00000000
PCN8 [R/W] B,H,W
PCSR8 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT8 [W] H,W
PTMR8 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN208 [R/W] B,H,W
PSDR8 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC8 [R/W] H,W
―
―
00000000 00000000
PCN9 [R/W] B,H,W
PCSR9 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT9 [W] H,W
PTMR9 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN209 [R/W] B,H,W
PSDR9 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC9 [R/W] H,W
―
―
00000000 00000000
PCN10 [R/W] B,H,W
PCSR10 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT10 [W] H,W
PTMR10 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
Document Number: 002-04662 Rev. *F
Block
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
Page 94 of 280
MB91520 Series
Address
001B18H
001B1CH
001B20H
001B24H
001B28H
001B2CH
001B30H
001B34H
001B38H
001B3CH
001B40H
001B44H
001B48H
001B4CH
001B50H
001B54H
001B58H
001B5CH
001B60H
001B64H
001B68H
001B6CH
001B70H
001B74H
Address offset value / Register name
+0
+1
+2
+3
PCN210 [R/W] B,H,W
PSDR10 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC10 [R/W] H,W
―
―
00000000 00000000
PCN11 [R/W] B,H,W
PCSR11 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT11 [W] H,W
PTMR11 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN211 [R/W] B,H,W
PSDR11 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC11 [R/W] H,W
―
―
00000000 00000000
PCN12 [R/W] B,H,W
PCSR12 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT12 [W] H,W
PTMR12 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN212 [R/W] B,H,W
PSDR12 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC12 [R/W] H,W
―
―
00000000 00000000
PCN13 [R/W] B,H,W
PCSR13 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT13 [W] H,W
PTMR13 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN213 [R/W] B,H,W
PSDR13 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC13 [R/W] H,W
―
―
00000000 00000000
PCN14 [R/W] B,H,W
PCSR14 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT14 [W] H,W
PTMR14 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN214 [R/W] B,H,W
PSDR14 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC14 [R/W] H,W
―
―
00000000 00000000
PCN15 [R/W] B,H,W
PCSR15 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT15 [W] H,W
PTMR15 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN215 [R/W] B,H,W
PSDR15 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC15 [R/W] H,W
―
―
00000000 00000000
PCN16 [R/W] B,H,W
PCSR16 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT16 [W] H,W
PTMR16 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
Document Number: 002-04662 Rev. *F
Block
PPG10
PPG11
PPG11
PPG12
PPG13
PPG14
PPG15
PPG16
Page 95 of 280
MB91520 Series
Address
001B78H
001B7CH
001B80H
001B84H
001B88H
001B8CH
001B90H
001B94H
001B98H
001B9CH
001BA0H
001BA4H
001BA8H
001BACH
001BB0H
001BB4H
001BB8H
001BBCH
001BC0H
001BC4H
001BC8H
001BCCH
Address offset value / Register name
+0
+1
+2
+3
PCN216 [R/W] B,H,W
PSDR16 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC16 [R/W] H,W
―
―
00000000 00000000
PCN17 [R/W] B,H,W
PCSR17 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT17 [W] H,W
PTMR17 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN217 [R/W] B,H,W
PSDR17 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC17 [R/W] H,W
―
―
00000000 00000000
PCN18 [R/W] B,H,W
PCSR18 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT18 [W] H,W
PTMR18 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN218 [R/W] B,H,W
PSDR18 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC18 [R/W] H,W
―
―
00000000 00000000
PCN19 [R/W] B,H,W
PCSR19 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT19 [W] H,W
PTMR19 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN219 [R/W] B,H,W
PSDR19 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC19 [R/W] H,W
―
―
00000000 00000000
PCN20 [R/W] B,H,W
PCSR20 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT20 [W] H,W
PTMR20 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN220 [R/W] B,H,W
PSDR20 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC20 [R/W] H,W
―
―
00000000 00000000
PCN21 [R/W] B,H,W
PCSR21 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT21 [W] H,W
PTMR21 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN221 [R/W] B,H,W
PSDR21 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC21 [R/W] H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
PPG16
PPG17
PPG18
PPG19
PPG20
PPG21
PPG21
Page 96 of 280
MB91520 Series
Address
001BD0H
001BD4H
001BD8H
001BDCH
001BE0H
001BE4H
001BE8H
001BECH
001BF0H
001BF4H
001BF8H
001BFCH
001C00H
001C04H
001C08H
001C0CH
001C10H
001C14H
001C18H
001C1CH
001C20H
001C24H
001C28H
001C2CH
Address offset value / Register name
+0
+1
+2
+3
PCN22 [R/W] B,H,W
PCSR22 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT22 [W] H,W
PTMR22 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN222 [R/W] B,H,W
PSDR22 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC22 [R/W] H,W
―
―
00000000 00000000
PCN23 [R/W] B,H,W
PCSR23 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT23 [W] H,W
PTMR23 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN223 [R/W] B,H,W
PSDR23 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC23 [R/W] H,W
―
―
00000000 00000000
PCN24 [R/W] B,H,W
PCSR24 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT24 [W] H,W
PTMR24 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN224 [R/W] B,H,W
PSDR24 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC24 [R/W] H,W
―
―
00000000 00000000
PCN25 [R/W] B,H,W
PCSR25 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT25 [W] H,W
PTMR25 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN225 [R/W] B,H,W
PSDR25 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC25 [R/W] H,W
―
―
00000000 00000000
PCN26 [R/W] B,H,W
PCSR26 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT26 [W] H,W
PTMR26 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN226 [R/W] B,H,W
PSDR26 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC26 [R/W] H,W
―
―
00000000 00000000
PCN27 [R/W] B,H,W
PCSR27 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT27 [W] H,W
PTMR27 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN227 [R/W] B,H,W
PSDR27 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC27 [R/W] H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
PPG22
PPG23
PPG24
PPG25
PPG26
PPG27
PPG27
PPG27
Page 97 of 280
MB91520 Series
Address
001C30H
001C34H
001C38H
001C3CH
001C40H
001C44H
001C48H
001C4CH
001C50H
001C54H
001C58H
001C5CH
001C60H
001C64H
001C68H
001C6CH
001C70H
001C74H
001C78H
001C7CH
001C80H
001C84H
001C88H
001C8CH
Address offset value / Register name
+0
+1
+2
+3
PCN28 [R/W] B,H,W
PCSR28 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT28 [W] H,W
PTMR28 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN228 [R/W] B,H,W
PSDR28 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC28 [R/W] H,W
―
―
00000000 00000000
PCN29 [R/W] B,H,W
PCSR29 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT29 [W] H,W
PTMR29 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN229 [R/W] B,H,W
PSDR29 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC29 [R/W] H,W
―
―
00000000 00000000
PCN30 [R/W] B,H,W
PCSR30 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT30 [W] H,W
PTMR30 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN230 [R/W] B,H,W
PSDR30 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC30 [R/W] H,W
―
―
00000000 00000000
PCN31 [R/W] B,H,W
PCSR31 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT31 [W] H,W
PTMR31 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN231 [R/W] B,H,W
PSDR31 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC31 [R/W] H,W
―
―
00000000 00000000
PCN32 [R/W] B,H,W
PCSR32 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT32 [W] H,W
PTMR32 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN232 [R/W] B,H,W
PSDR32 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC32 [R/W] H,W
―
―
00000000 00000000
PCN33 [R/W] B,H,W
PCSR33 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT33 [W] H,W
PTMR33 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN233 [R/W] B,H,W
PSDR33 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC33 [R/W] H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
PPG28
PPG29
PPG30
PPG31
PPG32
PPG32
PPG33
PPG33
Page 98 of 280
MB91520 Series
Address
001C90H
001C94H
001C98H
001C9CH
001CA0H
001CA4H
001CA8H
001CACH
001CB0H
001CB4H
001CB8H
001CBCH
001CC0H
001CC4H
001CC8H
001CCCH
001CD0H
001CD4H
001CD8H
001CDCH
001CE0H
001CE4H
001CE8H
001CECH
Address offset value / Register name
+0
+1
+2
+3
PCN34 [R/W] B,H,W
PCSR34 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT34 [W] H,W
PTMR34 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN234 [R/W] B,H,W
PSDR34 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC34 [R/W] H,W
―
―
00000000 00000000
PCN35 [R/W] B,H,W
PCSR35 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT35 [W] H,W
PTMR35 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN235 [R/W] B,H,W
PSDR35 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC35 [R/W] H,W
―
―
00000000 00000000
PCN36 [R/W] B,H,W
PCSR36 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT36 [W] H,W
PTMR36 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN236 [R/W] B,H,W
PSDR36 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC36 [R/W] H,W
―
―
00000000 00000000
PCN37 [R/W] B,H,W
PCSR37 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT37 [W] H,W
PTMR37 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN237 [R/W] B,H,W
PSDR37 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC37 [R/W] H,W
―
―
00000000 00000000
PCN38 [R/W] B,H,W
PCSR38 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT38 [W] H,W
PTMR38 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN238 [R/W] B,H,W
PSDR38 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC38 [R/W] H,W
―
―
00000000 00000000
PCN39 [R/W] B,H,W
PCSR39 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT39 [W] H,W
PTMR39 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN239 [R/W] B,H,W
PSDR39 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC39 [R/W] H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
PPG34
PPG35
PPG36
PPG37
PPG37
PPG38
PPG39
PPG39
Page 99 of 280
MB91520 Series
Address
001CF0H
001CF4H
001CF8H
001CFCH
001D00H
001D04H
001D08H
001D0CH
001D10H
001D14H
001D18H
001D1CH
001D20H
001D24H
001D28H
001D2CH
001D30H
001D34H
001D38H
001D3CH
001D40H
001D44H
001D48H
001D4CH
Address offset value / Register name
+0
+1
+2
+3
PCN40 [R/W] B,H,W
PCSR40 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT40 [W] H,W
PTMR40 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN240 [R/W] B,H,W
PSDR40 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC40 [R/W] H,W
―
―
00000000 00000000
PCN41 [R/W] B,H,W
PCSR41 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT41 [W] H,W
PTMR41 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN241 [R/W] B,H,W
PSDR41 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC41 [R/W] H,W
―
―
00000000 00000000
PCN42 [R/W] B,H,W
PCSR42 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT42 [W] H,W
PTMR42 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN242 [R/W] B,H,W
PSDR42 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC42 [R/W] H,W
―
―
00000000 00000000
PCN43 [R/W] B,H,W
PCSR43 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT43 [W] H,W
PTMR43 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN243 [R/W] B,H,W
PSDR43 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC43 [R/W] H,W
―
―
00000000 00000000
PCN44 [R/W] B,H,W
PCSR44 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT44 [W] H,W
PTMR44 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN244 [R/W] B,H,W
PSDR44 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC44 [R/W] H,W
―
―
00000000 00000000
PCN45 [R/W] B,H,W
PCSR45 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT45 [W] H,W
PTMR45 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN245 [R/W] B,H,W
PSDR45 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC45 [R/W] H,W
―
―
00000000 00000000
Document Number: 002-04662 Rev. *F
Block
PPG40
PPG41
PPG42
PPG43
PPG44
PPG45
Page 100 of 280
MB91520 Series
Address
001D50H
001D54H
001D58H
001D5CH
001D60H
001D64H
001D68H
001D6CH
001D70H
to
001FFCH
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
002028H
00202CH
002030H,
002034H
002038H
00203CH
002040H
002044H
002048H
Address offset value / Register name
+0
+1
+2
+3
PCN46 [R/W] B,H,W
PCSR46 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT46 [W] H,W
PTMR46 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN246 [R/W] B,H,W
PSDR46 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC46 [R/W] H,W
―
―
00000000 00000000
PCN47 [R/W] B,H,W
PCSR47 [W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT47 [W] H,W
PTMR47 [R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN247 [R/W] B,H,W
PSDR47 [R/W] H,W
--000000 -----110
00000000 00000000
PTPC47 [R/W] H,W
―
―
00000000 00000000
―
―
CTRLR0 [R/W] B,H,W
-------- 000-0001
ERRCNT0 [R] B,H,W
00000000 00000000
INTR0 [R] B,H,W
00000000 00000000
BRPER0 [R/W] B,H,W
-------- ----0000
IF1CREQ0 [R/W] B,H,W
0------- 00000001
IF1MSK20 [R/W] B,H,W
11-11111 11111111
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1MCTR0 [R/W] B,H,W
00000000 0---0000
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTB10 [R/W] B,H,W
00000000 00000000
―
―
―
―
―
―
Block
PPG46
PPG47
Reserved
STATR0 [R/W] B,H,W
-------- 00000000
BTR0 [R/W] B,H,W
-0100011 00000001
TESTR0 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK0 [R/W] B,H,W
-------- 00000000
IF1MSK10 [R/W] B,H,W
11111111 11111111
IF1ARB10 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA20 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W] B,H,W
00000000 00000000
―
―
―
―
CAN0
(128msb)
Reserved(IF1 data mirror)
―
―
―
―
IF2CREQ0 [R/W] B,H,W
0------- 00000001
IF2MSK20 [R/W] B,H,W
11-11111 11111111
IF2ARB20 [R/W] B,H,W
00000000 00000000
Document Number: 002-04662 Rev. *F
―
―
―
―
IF2CMSK0 [R/W] B,H,W
-------- 00000000
IF2MSK10 [R/W] B,H,W
11111111 11111111
IF2ARB10 [R/W] B,H,W
00000000 00000000
Page 101 of 280
MB91520 Series
Address
00204CH
002050H
002054H
002058H
00205CH
002060H,
002064H
002068H
to
00207CH
002080H
002084H
002088H
00208CH
002090H
002094H
002098H
00209CH
0020A0H
0020A4H
0020A8H
0020ACH
0020B0H
0020B4H
0020B8H
0020BCH
Address offset value / Register name
+0
+1
+2
+3
IF2MCTR0 [R/W] B,H,W
―
―
00000000 0---0000
IF2DTA10 [R/W] B,H,W
IF2DTA20 [R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB10 [R/W] B,H,W
IF2DTB20 [R/W] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
Block
Reserved(IF2 data mirror)
―
TREQR20 [R] B,H,W
00000000 00000000
TREQR40 [R] B,H,W
00000000 00000000
TREQR60 [R] B,H,W
00000000 00000000
TREQR80 [R] B,H,W
00000000 00000000
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT40 [R] B,H,W
00000000 00000000
NEWDT60 [R] B,H,W
00000000 00000000
NEWDT80 [R] B,H,W
00000000 00000000
INTPND20 [R] B,H,W
00000000 00000000
INTPND40 [R] B,H,W
00000000 00000000
INTPND60 [R] B,H,W
00000000 00000000
INTPND80 [R] B,H,W
00000000 00000000
MSGVAL20 [R] B,H,W
00000000 00000000
MSGVAL40 [R] B,H,W
00000000 00000000
MSGVAL60 [R] B,H,W
00000000 00000000
MSGVAL80 [R] B,H,W
00000000 00000000
0020C0H
to
0020FCH
Document Number: 002-04662 Rev. *F
TREQR10 [R] B,H,W
00000000 00000000
TREQR30 [R] B,H,W
00000000 00000000
TREQR50 [R] B,H,W
00000000 00000000
TREQR70 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
NEWDT30 [R] B,H,W
00000000 00000000
NEWDT50 [R] B,H,W
00000000 00000000
NEWDT70 [R] B,H,W
00000000 00000000
INTPND10 [R] B,H,W
00000000 00000000
INTPND30 [R] B,H,W
00000000 00000000
INTPND50 [R] B,H,W
00000000 00000000
INTPND70 [R] B,H,W
00000000 00000000
MSGVAL10 [R] B,H,W
00000000 00000000
MSGVAL30 [R] B,H,W
00000000 00000000
MSGVAL50 [R] B,H,W
00000000 00000000
MSGVAL70 [R] B,H,W
00000000 00000000
―
CAN0
(128msb)
CAN0
(128msb)
Page 102 of 280
MB91520 Series
Address
002100H
002104H
002108H
00210CH
002110H
002114H
002118H
00211CH
002120H
002124H
002128H
00212CH
002130H,
002134H
002138H
00213CH
002140H
002144H
002148H
00214CH
002150H
002154H
002158H
00215CH
002160H,
002164H
002168H
to
00217CH
002180H
002184H
002188H
00218CH
Address offset value / Register name
+0
+1
+2
+3
CTRLR1 [R/W] B,H,W
STATR1 [R/W] B,H,W
-------- 000-0001
-------- 00000000
ERRCNT1 [R] B,H,W
BTR1 [R/W] B,H,W
00000000 00000000
-0100011 00000001
INTR1 [R] B,H,W
TESTR1 [R/W] B,H,W
00000000 00000000
-------- X00000-BRPER1 [R/W] B,H,W
―
―
-------- ----0000
IF1CREQ1 [R/W] B,H,W
IF1CMSK1 [R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK21 [R/W] B,H,W
IF1MSK11 [R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB21 [R/W] B,H,W
IF1ARB11 [R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR1 [R/W] B,H,W
―
―
00000000 0---0000
IF1DTA11 [R/W] B,H,W
IF1DTA21 [R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB11 [R/W] B,H,W
IF1DTB21 [R/W] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
Block
CAN1
(64msb)
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ1 [R/W] B,H,W
0------- 00000001
IF2MSK21 [R/W] B,H,W
11-11111 11111111
IF2ARB21 [R/W] B,H,W
00000000 00000000
IF2MCTR1 [R/W] B,H,W
00000000 0---0000
IF2DTA11 [R/W] B,H,W
00000000 00000000
IF2DTB11 [R/W] B,H,W
00000000 00000000
―
―
―
―
―
―
―
―
IF2CMSK1 [R/W] B,H,W
-------- 00000000
IF2MSK11 [R/W] B,H,W
11111111 11111111
IF2ARB11 [R/W] B,H,W
00000000 00000000
―
―
IF2DTA21 [R/W] B,H,W
00000000 00000000
IF2DTB21 [R/W] B,H,W
00000000 00000000
―
―
―
―
CAN1
(64msb)
Reserved (IF2 data mirror)
―
TREQR21 [R] B,H,W
00000000 00000000
TREQR41 [R] B,H,W
00000000 00000000
―
―
―
―
Document Number: 002-04662 Rev. *F
TREQR11 [R] B,H,W
00000000 00000000
TREQR31 [R] B,H,W
00000000 00000000
―
―
―
―
Page 103 of 280
MB91520 Series
Address
002190H
002194H
002198H
00219CH
0021A0H
0021A4H
0021A8H
0021ACH
0021B0H
0021B4H
0021B8H
0021BCH
0021C0H
to
0021FCH
002200H
002204H
002208H
00220CH
002210H
002214H
002218H
00221CH
002220H
002224H
002228H
00222CH
002230H,
002234H
002238H
00223CH
002240H
Address offset value / Register name
+0
+1
+2
+3
NEWDT21 [R] B,H,W
NEWDT11 [R] B,H,W
00000000 00000000
00000000 00000000
NEWDT41 [R] B,H,W
NEWDT31 [R] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
INTPND21 [R] B,H,W
INTPND11 [R] B,H,W
00000000 00000000
00000000 00000000
INTPND41 [R] B,H,W
INTPND31 [R] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
MSGVAL21 [R] B,H,W
MSGVAL11 [R] B,H,W
00000000 00000000
00000000 00000000
MSGVAL41 [R] B,H,W
MSGVAL31 [R] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
Block
CAN1
(64msb)
―
CTRLR2 [R/W] B,H,W
-------- 000-0001
ERRCNT2 [R] B,H,W
00000000 00000000
INTR2 [R] B,H,W
00000000 00000000
BRPER2 [R/W] B,H,W
-------- ----0000
IF1CREQ2 [R/W] B,H,W
0------- 00000001
IF1MSK22 [R/W] B,H,W
11-11111 11111111
IF1ARB22 [R/W] B,H,W
00000000 00000000
IF1MCTR2 [R/W] B,H,W
00000000 0---0000
IF1DTA12 [R/W] B,H,W
00000000 00000000
IF1DTB12 [R/W] B,H,W
00000000 00000000
―
―
―
―
STATR2 [R/W] B,H,W
-------- 00000000
BTR2 [R/W] B,H,W
-0100011 00000001
TESTR2 [R/W] B,H,W
-------- X00000-―
IF1CMSK2 [R/W] B,H,W
-------- 00000000
IF1MSK12 [R/W] B,H,W
11111111 11111111
IF1ARB12 [R/W] B,H,W
00000000 00000000
―
CAN2
(64msb)
IF1DTA22 [R/W] B,H,W
00000000 00000000
IF1DTB22 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ2 [R/W] B,H,W
0------- 00000001
Document Number: 002-04662 Rev. *F
―
―
―
―
IF2CMSK2 [R/W] B,H,W
-------- 00000000
Page 104 of 280
MB91520 Series
Address
002244H
002248H
00224CH
002250H
002254H
002258H
00225CH
002260H,
002264H
002268H
to
00227CH
002280H
002284H
002288H
00228CH
002290H
002294H
002298H
00229CH
0022A0H
0022A4H
0022A8H
0022ACH
0022B0H
0022B4H
0022B8H
0022BCH
0022C0H
to
0022FCH
002300H
002304H
002308H
Address offset value / Register name
+0
+1
+2
+3
IF2MSK22 [R/W] B,H,W
IF2MSK12 [R/W] B,H,W
11-11111 11111111
11111111 11111111
IF2ARB22 [R/W] B,H,W
IF2ARB12 [R/W] B,H,W
00000000 00000000
00000000 00000000
IF2MCTR2 [R/W] B,H,W
―
00000000 0---0000
IF2DTA12 [R/W] B,H,W
IF2DTA22 [R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB12 [R/W] B,H,W
IF2DTB22 [R/W] B,H,W
00000000 00000000
00000000 00000000
―
―
―
―
―
―
―
―
Block
Reserved (IF2 data mirror)
―
TREQR22 [R] B,H,W
00000000 00000000
TREQR42 [R] B,H,W
00000000 00000000
―
―
―
―
NEWDT22 [R] B,H,W
00000000 00000000
NEWDT42 [R] B,H,W
00000000 00000000
―
―
―
―
INTPND22 [R] B,H,W
00000000 00000000
INTPND42 [R] B,H,W
00000000 00000000
―
―
―
―
MSGVAL22 [R] B,H,W
00000000 00000000
MSGVAL42 [R] B,H,W
00000000 00000000
―
―
―
―
TREQR12 [R] B,H,W
00000000 00000000
TREQR32 [R] B,H,W
00000000 00000000
―
―
―
―
NEWDT12 [R] B,H,W
00000000 00000000
NEWDT32 [R] B,H,W
00000000 00000000
―
―
―
―
INTPND12 [R] B,H,W
00000000 00000000
INTPND32 [R] B,H,W
00000000 00000000
―
―
―
―
MSGVAL12 [R] B,H,W
00000000 00000000
MSGVAL32 [R] B,H,W
00000000 00000000
―
―
―
―
CAN2
(64msb)
―
DFCTLR [R/W] B,H,W
-0------ -------―
―
FLIFCTLR [R/W]
B,H,W
―
---0--00
Document Number: 002-04662 Rev. *F
―
―
FLIFFER1 [R/W]
B,H,W
--------
DFSTR [R/W] B,H,W
-----001
―
FLIFFER2 [R/W]
B,H,W
--------
WorkFlash
Flash / WorkFlash
Page 105 of 280
MB91520 Series
Address
+0
Address offset value / Register name
+1
+2
00230CH
to
0023FCH
002400H
002404H
002408H
―
SEEARX [R] B,H,W
-0000000 00000000
EECSRX [R/W]
B,H,W
―
----00-―
00240CH
to
002FFCH
003000H
003004H
003008H
00300CH
003010H
003014H
003018H
00301CH
003020H
003034H
003038H
00303CH
003040H
003044H
Block
Reserved
DEEARX [R] B,H,W
-0000000 00000000
EFEARX [R/W] B,H,W
-0000000 00000000
XBS RAM
ECC control
EFECRX [R/W] B,H,W
-------0 00000000 00000000
―
SEEARA [R] B,H,W
-----000 00000000
EECSRA [R/W]
B,H,W
―
----00--
Reserved
DEEARA [R] B,H,W
-----000 00000000
EFEARA [R/W] B,H,W
-----000 00000000
EFECRA [R/W] B,H,W
-------0 00000000 00000000
TEAR0X[R] B,H,W
000----- -------- -0000000 00000000
TEAR1X[R] B,H,W
000----- -------- -0000000 00000000
TEAR2X[R] B,H,W
000----- -------- -0000000 00000000
TAEARX [R/W] B,H,W
TASARX [R/W] B,H,W
-1111111 11111111
-0000000 00000000
TFECRX [R/W]
TICRX [R/W]
TTCRX [R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRX [W]
TKCCRX [R/W]
B,H,W
―
―
B,H,W
0------00----00
Backup RAM
ECC control
―
003024H
to
00302CH
003030H
+3
―
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
-----111 11111111
-----000 00000000
TFECRA [R/W]
TICRA [R/W]
TTCRA [R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRA [R/W]
TKCCRA [R/W]
B,H,W
―
―
B,H,W
0------00----00
Document Number: 002-04662 Rev. *F
RAM/ diagnosis
XBS RAM
Reserved
RAM/ diagnosis
Backup RAM
RAM/ diagnosis
Backup RAM
Page 106 of 280
MB91520 Series
Address
+0
Address offset value / Register name
+1
+2
003048H
to
0030FCH
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
003124H
003128H
to
003FFCH
004000H
to
005FFCH
006000H
to
00EFFCH
00F000H
to
00FEFCH
00FF00H
―
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR2[R/W] H,W
00000000 0-----00
00FF14H
00FFFCH
BUSDIGSR1[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
BUS diagnosis
―
Reserved
Backup-RAM
Backup RAM area
―
―
―
―
Reserved
―
―
―
―
Reserved [S]
―
―
OCDU [S]
DSUCR [R/W] B,H,W
-------- -------0
―
PCSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PSSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
to
00FFF4H
00FFF8H
Block
Reserved
BUSADR0 [R] W
00000000 00000000 00000000 00000000
BUSADR1 [R] W
00000000 00000000 00000000 00000000
BUSADR2 [R] W
00000000 00000000 00000000 00000000
BUSDIGSR3[R/W] H,W
―
―
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--000- 00000000
―
―
―
―
BUSADR3 [R] W
00000000 00000000 00000000 00000000
BUSADR4 [R] W
00000000 00000000 00000000 00000000
00FF04H
to
00FF0CH
00FF10H
+3
Reserved [S]
OCDU [S]
OCDU [S]
―
Reserved [S]
EDIR1 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDIR0 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
Document Number: 002-04662 Rev. *F
Page 107 of 280
MB91520 Series
[S]: It is a system register. The illegal instruction exception (data access error) is generated in these registers in the user mode
when reading and writing to it.
Document Number: 002-04662 Rev. *F
Page 108 of 280
MB91520 Series
10. Interrupt Vector Table
This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.
Interrupt Vector
64 Pins
Interrupt Number
Default
Interrupt
Offset Address for
Hexa
Level
Decimal
TBR
Decimal
Reset
0
0
3FCH 000FFFFCH
System reserved
1
1
3F8H
000FFFF8H
System reserved
2
2
3F4H
000FFFF4H
System reserved
3
3
3F0H
000FFFF0H
System reserved
4
4
3ECH 000FFFECH
FPU exception
5
5
3E8H 000FFFE8H
Exception of instruction access protection violation
6
6
3E4H 000FFFE4H
Exception of data access protection violation
7
7
3E0H 000FFFE0H
Data access error interrupt
8
8
3DCH 000FFFDCH
INTE instruction
9
9
3D8H 000FFFD8H
Instruction break
10
0A
3D4H 000FFFD4H
System reserved
11
0B
3D0H 000FFFD0H
System reserved
12
0C
3CCH 000FFFCCH
System reserved
13
0D
3C8H 000FFFC8H
Exception of invalid instruction
14
0E
3C4H 000FFFC4H
NMI request
Error generation during internal bus diagnosis
15 (FH)
XBS RAM double-bit error generation
15
0F
3C0H 000FFFC0H
Fixed
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH 000FFFBCH
External interrupt 8-15
17
11
ICR01
3B8H 000FFFB8H
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H 000FFFB4H
Reload timer 3/6/7
19
13
ICR03
3B0H 000FFFB0H
Multi-function serial interface ch.0 (reception
completed)
20
14
ICR04
3ACH 000FFFACH
Multi-function serial interface ch.0 (status)
Multi-function serial interface
21
15
ICR05
3A8H 000FFFA8H
ch.0 (transmission completed)
22
16
ICR06
3A4H 000FFFA4H
23
17
ICR07
3A0H 000FFFA0H
24
18
ICR08
39CH 000FFF9CH
25
19
ICR09
398H
000FFF98H
Multi-function serial interface
ch.3 (reception completed)
26
1A
ICR10
394H
000FFF94H
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
27
1B
ICR11
390H
000FFF90H
ch.3 (transmission completed)
Interrupt Factor
Document Number: 002-04662 Rev. *F
RN
-
-
0
1*7
2*2
3*2
4*1
5*1
-*6
-*6
-*6
-*6
10*1
11
Page 109 of 280
MB91520 Series
Interrupt Factor
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
16-bit Free-run timer 0 (0 detection) /
(compare clear)
PPG 1/10/11/20/30/31
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/24/35
PPG 7/16/17/27/37
PPG 19
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Document Number: 002-04662 Rev. *F
Interrupt Number
Default
Interrupt
Offset Address for
Hexa
Level
Decimal
TBR
Decimal
RN
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H
17
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
38
25
26
ICR21
ICR22
368H
364H
000FFF68H
000FFF64H
-*6
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
45
2A
2B
2C
2D
ICR26
ICR27
ICR28
ICR29
354H
350H
34CH
348H
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
26*3
27*3
28*3
29
46
2E
ICR30
344H
000FFF44H
30
Page 110 of 280
MB91520 Series
Interrupt Factor
Clock calibration unit (sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/10/11/14/15/16/17/22/27/28/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching/measurement)
A/D converter
32/34/35/37/38/40/41/42/43/44/45/46/47
32-bit OCU7/11 (match)
32-bit OCU8/9 (match)
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System reserved
(Used for REALOSTM*8)
System reserved
(Used for REALOS)
Document Number: 002-04662 Rev. *F
Interrupt Number
Default
Interrupt
Offset Address for
Hexa
Level
Decimal
TBR
Decimal
RN
47
2F
ICR31
340H
000FFF40H 31*1,*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*5
51
33
ICR35
330H
000FFF30H
35
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
60
3A
3B
3C
ICR42
ICR43
ICR44
314H
310H
30CH
000FFF14H
000FFF10H
000FFF0CH
42
43
-*6
61
3D
ICR45
308H
000FFF08H
-
62
63
3E
3F
ICR46
ICR47
304H
300H
000FFF04H
000FFF00H
-
64
40
-
2FCH
000FFEFCH
-
65
41
-
2F8H
000FFEF8H
-
Page 111 of 280
MB91520 Series
Interrupt Factor
Interrupt Number
Default
Interrupt
Offset Address for
Hexa
Level
Decimal
TBR
Decimal
RN
66
42
2F4H 000FFEF4H
|
|
|
|
255
FF
000H
000FFC00H
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
*8: REALOS is a trademark of Cypress.
Used with the INT instruction
Document Number: 002-04662 Rev. *F
Page 112 of 280
MB91520 Series
80 Pins
Interrupt Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection
violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
External interrupt 8-15
External low-voltage detection interrupt
Reload timer 0/1/4/5
Reload timer 3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Offset
Hexa
Level
Decimal
Decimal
0
0
3FCH
1
1
3F8H
2
2
3F4H
3
3
3F0H
4
4
3ECH
5
5
3E8H
Default
Address for
TBR
RN
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
6
6
-
3E4H
000FFFE4H
-
7
8
9
10
11
12
13
14
7
8
9
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15 (FH)
Fixed
3C0H
000FFFC0H
-
16
10
ICR00
3BCH
000FFFBCH
0
17
11
ICR01
3B8H
000FFFB8H
1*7
18
19
12
13
ICR02
ICR03
3B4H
3B0H
000FFFB4H
000FFFB0H
2*2
3*2
20
14
ICR04
3ACH
000FFFACH
4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
23
16
17
ICR06
ICR07
3A4H
3A0H
000FFFA4H
000FFFA0H
-*6
-*6
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
26
1A
ICR10
394H
000FFF94H
10*1
27
1B
ICR11
390H
000FFF90H
11
Page 113 of 280
MB91520 Series
Interrupt Factor
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
16-bit Free-run timer 0 (0 detection) /
(compare clear)
PPG 1/10/11/20/30/31
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/15/24/35
PPG 7/16/17/26/27/37
PPG 8/18/19/29
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Offset
Hexa
Level
Decimal
Decimal
Default
Address for
TBR
RN
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H
17
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
38
25
26
ICR21
ICR22
368H
364H
000FFF68H
000FFF64H
-*6
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
45
2A
2B
2C
2D
ICR26
ICR27
ICR28
ICR29
354H
350H
34CH
348H
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
26*3
27*3
28*3
29
46
2E
ICR30
344H
000FFF44H
30
Page 114 of 280
MB91520 Series
Interrupt Factor
Clock calibration unit
(sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/10/11/12/14/15/16/17/19/22/26/27/28/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching/measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU7/11 (match)
32-bit OCU8/9 (match)
Base timer 1 IRQ0
Base timer 1 IRQ1
DMAC
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Offset
Hexa
Level
Decimal
Decimal
Default
Address for
TBR
RN
47
2F
ICR31
340H
000FFF40H 31*1,*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*5
51
33
ICR35
330H
000FFF30H
35*5
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
60
3A
3B
3C
ICR42
ICR43
ICR44
314H
310H
30CH
000FFF14H
000FFF10H
000FFF0CH
42
43
-*6
61
3D
ICR45
308H
000FFF08H
45
62
3E
ICR46
304H
000FFF04H
-
63
3F
ICR47
300H
000FFF00H
-
Page 115 of 280
MB91520 Series
Interrupt Factor
System reserved
(Used for REALOS)
System reserved
(Used for REALOS)
Used with the INT instruction
Interrupt Number
Interrupt
Offset
Hexa
Level
Decimal
Decimal
Default
Address for
TBR
RN
64
40
-
2FCH
000FFEFCH
-
65
41
-
2F8H
000FFEF8H
-
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *F
Page 116 of 280
MB91520 Series
100 Pins
Interrupt number
Interrupt Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection
violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
External interrupt 8-15
External low-voltage detection interrupt
Reload timer 0/1/4/5
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Decimal Hexa Decimal Level
TBR
0
0
3FCH 000FFFFCH 1
1
3F8H 000FFFF8H 2
2
3F4H 000FFFF4H 3
3
3F0H 000FFFF0H 4
4
3ECH 000FFFECH 5
5
3E8H 000FFFE8H 6
6
-
3E4H 000FFFE4H
-
7
8
9
10
11
12
13
14
7
8
9
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15 (FH)
Fixed
3C0H 000FFFC0H
-
16
10
ICR00
3BCH 000FFFBCH
0
17
11
ICR01
3B8H 000FFFB8H 1*7
18
19
12
13
ICR02
ICR03
3B4H 000FFFB4H 2*2
3B0H 000FFFB0H 3*2
20
14
ICR04
3ACH 000FFFACH 4*1
21
15
ICR05
3A8H 000FFFA8H 5*1
22
16
ICR06
3A4H 000FFFA4H 6*1
23
17
ICR07
3A0H 000FFFA0H 7*1
24
18
ICR08
39CH 000FFF9CH 8*1
25
19
ICR09
398H 000FFF98H 9*1
26
1A
ICR10
394H 000FFF94H 10*1
Page 117 of 280
MB91520 Series
Interrupt number
Interrupt Factor
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
16-bit Free-running timer 0 (0 detection) /
(compare clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG 1/10/11/20/21/30/31
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/32/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/35/44
PPG 6/7/16/17/26/27/37
PPG 8/9/18/19/28/29
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
27
1B
ICR11
390H 000FFF90H
11
28
1C
ICR12
38CH 000FFF8CH 12*1
29
1D
ICR13
388H 000FFF88H
30
1E
ICR14
384H 000FFF84H 14*1
31
1F
ICR15
380H 000FFF80H
32
20
ICR16
37CH 000FFF7CH 16*1
33
21
ICR17
378H 000FFF78H
17
34
22
ICR18
374H 000FFF74H
-
35
23
ICR19
370H 000FFF70H
-
36
24
ICR20
36CH 000FFF6CH
-
37
25
ICR21
368H 000FFF68H
-
38
26
ICR22
364H 000FFF64H 22*1
39
27
ICR23
360H 000FFF60H
40
28
ICR24
35CH 000FFF5CH 24*3
41
29
ICR25
358H 000FFF58H 25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H 000FFF54H 26*3
350H 000FFF50H 27*3
34CH 000FFF4CH 28*3
13
15
23
Page 118 of 280
MB91520 Series
Interrupt number
Interrupt Factor
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/9/10/11/12/13/14/15/16
17/18/19/22/23/26/27/28/29/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
45
2D
ICR29
348H 000FFF48H 29*1
46
2E
ICR30
344H 000FFF44H
30
47
2F
ICR31
340H 000FFF40H
31*1,
*4
48
30
ICR32
33CH 000FFF3CH 32
49
31
ICR33
338H 000FFF38H
50
32
ICR34
334H 000FFF34H 34*5
51
33
ICR35
330H 000FFF30H 35*5
52
34
ICR36
32CH 000FFF2CH 36*1
53
35
ICR37
328H 000FFF28H
54
36
ICR38
324H 000FFF24H 38*1
55
37
ICR39
320H 000FFF20H
56
38
ICR40
31CH 000FFF1CH 40
33
37
39
Page 119 of 280
MB91520 Series
Interrupt number
Interrupt Factor
32-bit ICU5 (fetching/measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU 6/7/10/11 (match)
32-bit OCU 8/9 (match)
Base timer 1 IRQ0
Base timer 1 IRQ1
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System reserved
(Used for REALOS)
System reserved
(Used for REALOS)
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
57
39
ICR41
318H 000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H 000FFF14H
310H 000FFF10H
42
43
60
3C
ICR44
30CH 000FFF0CH 44
61
3D
ICR45
308H 000FFF08H
45
62
63
3E
3F
ICR46
ICR47
304H 000FFF04H
300H 000FFF00H
-
64
40
-
2FCH 000FFEFCH
-
65
41
-
2F8H 000FFEF8H
-
66
42
2F4H 000FFEF4H
|
|
|
|
255
FF
000H 000FFC00H
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Used with the INT instruction
Document Number: 002-04662 Rev. *F
Page 120 of 280
MB91520 Series
120 Pins
Interrupt Number
Default
Interrupt
Offset Address for RN
Decimal Hexa Decimal Level
TBR
Reset
0
0
3FCH 000FFFFCH
System reserved
1
1
3F8H 000FFFF8H
System reserved
2
2
3F4H 000FFFF4H
System reserved
3
3
3F0H 000FFFF0H
System reserved
4
4
3ECH 000FFFECH
FPU exception
5
5
3E8H 000FFFE8H
Exception of instruction access protection violation
6
6
3E4H 000FFFE4H
Exception of data access protection violation
7
7
3E0H 000FFFE0H
Data access error interrupt
8
8
3DCH 000FFFDCH
INTE instruction
9
9
3D8H 000FFFD8H
Instruction break
10
0A
3D4H 000FFFD4H
System reserved
11
0B
3D0H 000FFFD0H
System reserved
12
0C
3CCH 000FFFCCH
System reserved
13
0D
3C8H 000FFFC8H
Exception of invalid instruction
14
0E
3C4H 000FFFC4H
NMI request
Error generation during internal bus diagnosis
15 (FH)
XBS RAM double-bit error generation
15
0F
3C0H 000FFFC0H
Fixed
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00 3BCH 000FFFBCH 0
External interrupt 8-15
17
11
ICR01 3B8H 000FFFB8H 1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02 3B4H 000FFFB4H 2*2
Reload timer 2/3/6/7
19
13
ICR03 3B0H 000FFFB0H 3*2
Multi-function serial interface
ch.0 (reception completed)
20
14
ICR04 3ACH 000FFFACH 4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
21
15
ICR05 3A8H 000FFFA8H 5*1
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
22
16
ICR06 3A4H 000FFFA4H 6*1
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
23
17
ICR07 3A0H 000FFFA0H 7*1
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
24
18
ICR08 39CH 000FFF9CH 8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
25
19
ICR09 398H 000FFF98H 9*1
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
26
1A
ICR10 394H 000FFF94H 10*1
Multi-function serial interface
ch.3 (status)
Interrupt Factor
Document Number: 002-04662 Rev. *F
Page 121 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/35/44
PPG 6/7/16/17/26/27/37
PPG 8/9/18/19/28/29
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
27
1B
ICR11
390H 000FFF90H
11
28
1C
ICR12
38CH 000FFF8CH 12*1
29
1D
ICR13
388H 000FFF88H
30
1E
ICR14
384H 000FFF84H 14*1
31
1F
ICR15
380H 000FFF80H
32
20
ICR16
37CH 000FFF7CH 16*1
33
21
ICR17
378H 000FFF78H
17
34
22
ICR18
374H 000FFF74H
-
35
23
ICR19
370H 000FFF70H
-
36
24
ICR20
36CH 000FFF6CH
-
37
25
ICR21
368H 000FFF68H
-
38
26
ICR22
364H 000FFF64H 22*1
39
27
ICR23
360H 000FFF60H
40
28
ICR24
35CH 000FFF5CH 24*3
41
29
ICR25
358H 000FFF58H 25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H 000FFF54H 26*3
350H 000FFF50H 27*3
34CH 000FFF4CH 28*3
13
15
23
Page 122 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/9/10/11/12/13/14/15/16/
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit ( CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
45
2D
ICR29
348H 000FFF48H 29*1
46
2E
ICR30
344H 000FFF44H
47
2F
ICR31
340H 000FFF40H 31*1, *4
48
30
ICR32
33CH 000FFF3CH
32
49
31
ICR33
338H 000FFF38H
33
50
32
ICR34
334H 000FFF34H 34*5
51
33
ICR35
330H 000FFF30H 35*5
52
34
ICR36
32CH 000FFF2CH 36*1
53
35
ICR37
328H 000FFF28H
54
36
ICR38
324H 000FFF24H 38*1
55
37
ICR39
320H 000FFF20H
39
56
38
ICR40
31CH 000FFF1CH
40
30
37
Page 123 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
32-bit ICU5 (fetching/measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU 6/7/10/11 (match)
32-bit OCU 8/9 (match)
Base timer 1 IRQ0
Base timer 1 IRQ1
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System reserved
(Used for REALOS)
System reserved
(Used for REALOS)
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
57
39
ICR41
318H 000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H 000FFF14H
310H 000FFF10H
42
43
60
3C
ICR44
30CH 000FFF0CH
44
61
3D
ICR45
308H 000FFF08H
45
62
63
3E
3F
ICR46
ICR47
304H 000FFF04H
300H 000FFF00H
-
64
40
-
2FCH 000FFEFCH
-
65
41
-
2F8H 000FFEF8H
-
66
42
2F4H 000FFEF4H
|
|
|
|
255
FF
000H 000FFC00H
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Used with the INT instruction
Document Number: 002-04662 Rev. *F
Page 124 of 280
MB91520 Series
144 Pins
Interrupt Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection
violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
External interrupt 8-15
External low-voltage detection interrupt
Reload timer 0/1/4/5
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Hexa
Level
Decimal
Decimal
0
0
1
1
2
2
3
3
4
4
5
5
-
Offset
Default
Address for
TBR
RN
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
6
6
-
3E4H
000FFFE4H
-
7
8
9
10
11
12
13
14
7
8
9
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15 (FH)
Fixed
3C0H
000FFFC0H
-
16
10
ICR00
3BCH
000FFFBCH
0
17
11
ICR01
3B8H
000FFFB8H
1*7
18
19
12
13
ICR02
ICR03
3B4H
3B0H
000FFFB4H
000FFFB0H
2*2
3*2
20
14
ICR04
3ACH
000FFFACH
4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
16
ICR06
3A4H
000FFFA4H
6*1
23
17
ICR07
3A0H
000FFFA0H
7*1
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
26
1A
ICR10
394H
000FFF94H
10*1
Page 125 of 280
MB91520 Series
Interrupt Factor
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31/40/41
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/34/35/44
PPG 6/7/16/17/26/27/36/37
PPG 8/9/18/19/28/29/38/39
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Hexa
Level
Decimal
Decimal
Offset
Default
Address for
TBR
RN
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H
17
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22*1
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H
350H
34CH
000FFF54H
000FFF50H
000FFF4CH
26*3
27*3
28*3
Page 126 of 280
MB91520 Series
Interrupt Factor
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit ( CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU 6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *F
Interrupt Number
Interrupt
Hexa
Level
Decimal
Decimal
Offset
Default
Address for
TBR
RN
45
2D
ICR29
348H
000FFF48H
29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H 31*1, *4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*5
51
33
ICR35
330H
000FFF30H
35*5
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
Page 127 of 280
MB91520 Series
Interrupt Factor
32-bit ICU5 (fetching/measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU 6/7/10/11 (match)
32-bit OCU8/9 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System reserved
(Used for REALOS)
System reserved
(Used for REALOS)
Interrupt Number
Interrupt
Hexa
Level
Decimal
Decimal
Offset
Default
Address for
TBR
RN
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45
62
63
3E
3F
ICR46
ICR47
304H
300H
000FFF04H
000FFF00H
-
64
40
-
2FCH
000FFEFCH
-
65
41
-
2F8H
000FFEF8H
-
66
42
2F4H
000FFEF4H
|
|
|
|
255
FF
000H
000FFC00H
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Used with the INT instruction
Document Number: 002-04662 Rev. *F
Page 128 of 280
MB91520 Series
176 Pins
Interrupt Number
Interrupt Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection
violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
External interrupt 8-15
External low-voltage detection interrupt
Reload timer 0/1/4/5
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Decimal Hexa Decimal Level
TBR
0
0
3FCH 000FFFFCH 1
1
3F8H 000FFFF8H
2
2
3F4H 000FFFF4H
3
3
3F0H 000FFFF0H
4
4
3ECH 000FFFECH 5
5
3E8H 000FFFE8H
6
6
-
3E4H
000FFFE4H
-
7
8
9
10
11
12
13
14
7
8
9
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15 (FH)
Fixed
3C0H 000FFFC0H
-
16
10
ICR00
3BCH 000FFFBCH
0
17
11
ICR01
3B8H
000FFFB8H
1*7
18
19
12
13
ICR02
ICR03
3B4H
3B0H
000FFFB4H
000FFFB0H
2*2
3*2
20
14
ICR04
3ACH 000FFFACH 4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
16
ICR06
3A4H
000FFFA4H
6*1
23
17
ICR07
3A0H
000FFFA0H
7*1
24
18
ICR08
39CH 000FFF9CH 8*1
25
19
ICR09
398H
000FFF98H
26
1A
ICR10
394H
000FFF94H 10*1
9*1
Page 129 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
CAN0
CAN1
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
Up/down counter 0
Up/down counter 1
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31/40/41
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/34/35/44/45
PPG 6/7/16/17/26/27/36/37/46/47
PPG 8/9/18/19/28/29/38/39
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH 000FFF8CH 12*1
29
1D
ICR13
388H
000FFF88H
30
1E
ICR14
384H
000FFF84H 14*1
31
1F
ICR15
380H
000FFF80H
32
20
ICR16
37CH 000FFF7CH 16*1
33
21
ICR17
378H
000FFF78H
17
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH 000FFF6CH
-
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H 22*1
39
27
ICR23
360H
000FFF60H
40
28
ICR24
35CH 000FFF5CH 24*3
41
29
ICR25
358H
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H 000FFF54H 26*3
350H 000FFF50H 27*3
34CH 000FFF4CH 28*3
13
15
23
000FFF58H 25*3
Page 130 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *F
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
45
2D
ICR29
348H
000FFF48H 29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*1,
*4
48
30
ICR32
33CH 000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H 34*5
51
33
ICR35
330H
000FFF30H 35*5
52
34
ICR36
32CH 000FFF2CH 36*1
53
35
ICR37
328H
000FFF28H
54
36
ICR38
324H
000FFF24H 38*1
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH 000FFF1CH
40
37
Page 131 of 280
MB91520 Series
Interrupt Number
Interrupt Factor
32-bit ICU5 (fetching/measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU 6/7/10/11 (match)
32-bit OCU 8/9 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System reserved
(Used for REALOS)
System reserved
(Used for REALOS)
Default
Interrupt
Offset Address for RN
Level
Decimal Hexa Decimal
TBR
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH 000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45
62
63
3E
3F
ICR46
ICR47
304H
300H
000FFF04H
000FFF00H
-
64
40
-
2FCH 000FFEFCH
-
65
41
-
2F8H
-
000FFEF8H
66
42
2F4H 000FFEF4H
|
|
|
|
255
FF
000H 000FFC00H
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Used with the INT instruction
Document Number: 002-04662 Rev. *F
Page 132 of 280
MB91520 Series
11. Electrical Characteristics
Absolute Maximum Ratings
Rating
Parameter
Power supply voltage *1,*2
Analog power supply voltage *1,*2
Analog reference voltage *1
Input voltage *1
Analog pin input voltage *1
Output voltage *1
Maximum clamp current
Total maximum clamp current
Symbol
Unit
Min
Max
VCC
VSS-0.3
VSS+6.0
V
AVCC
VSS-0.3
VSS+6.0
V
AVRH ≤ AVCC ≤
VCC
AVRH ≤ AVCC
VSS-0.3
VSS+6.0
V
VSS-0.3
VCC+0.3
V
VSS-0.3
VCC+0.3
V
VSS-0.3
VCC+0.3
V
4.0
mA
*6
20
mA
*6
15
mA
"L" level maximum output current *3
30
mA
4
mA
*9
"L" level average output current *4
12
mA
*10
100
mA
"L" level total output current *5
120
mA
-15
mA
"H" level maximum output current*3
-30
mA
-4
mA
*9
"H" level average output current*4
-12
mA
*10
-100
mA
"H" level total output current *5
-120
mA
TA: -40 °C to +105 °C
882
mW
*8
Power
PD
consumption
TA: -40 °C to +125 °C
675
mW
*8
-40
+105
°C
Operating temperature
TA
-40
+125
°C
*7
Storage temperature
Tstg
-55
+150
°C
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V
*2: Caution must be taken that AVCC, AVRH do not exceed VCC upon power-on and under other circumstances.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for
a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: · Corresponding pins: all general-purpose ports except P035, 041, 093, 122.
· Use within recommended operating conditions.
· Use at DC voltage (current).
· The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.
· The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated
values at any time regardless of instantaneously or constantly when the + B signal is input.
· Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential
can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
· Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the
pin, the microcontroller may operate incompletely.
· Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not
function in the power supply voltage.
· Do not leave + B input pins open.
*7: When it is used under this condition, contact your sales representative.
Document Number: 002-04662 Rev. *F
AVRH
VI
VIA5
Vo
ICLAMP
Σ|ICLAMP|
IOL1
IOL2
IOLAV1
IOLAV2
ΣIOL1
ΣIOL2
IOH1
IOH2
IOHAV1
IOHAV2
ΣIOH1
ΣIOH2
Remarks
Page 133 of 280
MB91520 Series
*8: It is a standard when four-layer substrate is used.
*9: Corresponding pins: General-purpose ports other than those of P103, P104, P105 and P106.
*10: Corresponding pins: General-purpose ports of P103, P104, P105 and P106.
Sample Recommended Circuit
MB91520 series
Protective diode
Limiting resistor current
+B input (12 to 16V)
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Value
Parameter
Power supply voltage
Smoothing capacitor *2
Symbol
VCC,
AVCC
CS
Unit
Min
Max
4.5
5.5
V
3.0
3.6
V
2.7
5.5
V
4.7
(tolerance within ±50 %)
µF
Remarks
Recommended operation
guarantee range (When 5.0 V is
used)
Recommended operation
guarantee range (When 3.3 V is
used)
Operation guarantee range*1
Use a ceramic capacitor or a
capacitor that has the similar
frequency characteristics. Use a
capacitor with a capacitance
greater than CS as the smoothing
capacitor on the VCC pin.
-40
+105
°C
-40
+125
°C
*3
*1: When it is used outside recommended operation guarantee range (range of the operation guarantee),contact your sales
representative.
The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed
operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the
Operating temperature
TA
Document Number: 002-04662 Rev. *F
Page 134 of 280
MB91520 Series
minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
*2: See the following diagram for details on the connection of smoothing capacitor C S.
*3: When it is used under this condition, contact your sales representative.
· C Pin Connection Diagram
C
CS
VSS
VSS
AVSS
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other
than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with
respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application
under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04662 Rev. *F
Page 135 of 280
MB91520 Series
DC Characteristics
(TA: -40 °C to +105 °C, VCC = AVcc = 5.0 V ± 10 %/3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Pin
Parameter Symbol
Conditions
Name
Min
Typ
Operating frequency FCP = 80 MHz,
60
Fcpp = 40 MHz, at normal operation
Operating frequency FCP = 80 MHz,
70
Fcpp = 40 MHz, at Flash write
Operating frequency FCP = 80 MHz,
70
Fcpp = 40 MHz, at Flash erase
Operating frequency FCP = 64 MHz,
54
Fcpp = 32 MHz, at normal operation
Operating frequency FCP = 64 MHz,
ICC5
64
Fcpp = 32 MHz, at Flash write
Operating frequency FCP = 64 MHz,
64
Fcpp = 32 MHz, at Flash erase
Operating frequency FCP = 48 MHz,
46
Fcpp = 24 MHz, at normal operation
Operating frequency FCP = 48 MHz,
56
Fcpp = 24 MHz, at Flash write
Operating frequency FCP = 48 MHz,
56
Fcpp = 24 MHz, at Flash erase
Operating frequency FCP = 80 MHz,
ICCS5
45
Fcpp = 40 MHz, at CPU sleep mode
Power
Operating frequency FCP = 80 MHz,
supply
VCC
ICCBS5
23
Fcpp = 40 MHz, at bus sleep mode
current
When using crystal 4
1500
MHz TA = +25 °C*
When using built-in CR
Watch
clock 50 kHz
450
ICCT5
mode
TA = +25 °C*
When using sub clock
32 kHz
460
TA = +25 °C*
ICCH5
Stop mode
TA = +25 °C*
450
When using crystal 4
1100
MHz TA = +25 °C*
When using built-in CR
Watch
clock 50 kHz ,
77
ICCT52
mode
TA = +25 °C*
(power off)
When using sub clock
32 kHz
100
TA = +25 °C*
ICCH52
Document Number: 002-04662 Rev. *F
Stop mode
(power off)
TA = +25 °C*
-
74
Max
Unit
80
mA
90
mA
90
mA
71
mA
81
mA
81
mA
62
mA
72
mA
72
mA
61
mA
51
mA
Remarks
2610
2000
µA
2000
2000
µA
1300
267
µA
LVD/
RTC
operation,
Backup RAM
8 KB
retention
µA
Backup RAM
8 KB
retention
285
265
Page 136 of 280
MB91520 Series
(TA: -40 °C to +125 °C, VCC = AVcc = 5.0 V ± 10 %/3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Pin
Parameter Symbol
Conditions
Name
Min
Typ
Operating frequency FCP = 80 MHz,
60
Fcpp = 40 MHz, at normal operation
Operating frequency FCP = 80 MHz,
70
Fcpp = 40 MHz, at Flash write
Operating frequency FCP = 80 MHz,
70
Fcpp = 40 MHz, at Flash erase
Operating frequency FCP = 64 MHz,
54
Fcpp = 32 MHz, at normal operation
Operating frequency FCP = 64 MHz,
ICC5
64
Fcpp = 32 MHz, at Flash write
Operating frequency FCP = 64 MHz,
64
Fcpp = 32 MHz, at Flash erase
Operating frequency FCP = 48 MHz,
46
Fcpp = 24 MHz, at normal operation
Operating frequency FCP = 48 MHz,
56
Fcpp = 24 MHz, at Flash write
Operating frequency FCP = 48 MHz,
56
Fcpp = 24 MHz, at Flash erase
Operating frequency FCP = 80 MHz,
ICCS5
45
Fcpp = 40 MHz, at CPU sleep mode
Power
Operating frequency FCP = 80 MHz,
supply
VCC
ICCBS5
23
Fcpp = 40 MHz, at bus sleep mode
current
When using crystal 4
1500
MHz TA = +25 °C*
When using built-in CR
Watch
clock 50 kHz
450
ICCT5
mode
TA = +25 °C*
When using sub clock
32 kHz
460
TA = +25 °C*
ICCH5
Stop mode
TA = +25 °C*
450
When using crystal 4
1100
MHz TA = +25 °C*
When using built-in CR
Watch
clock 50 kHz ,
77
ICCT52
mode
TA = +25 °C*
(power off)
When using sub clock
32 kHz
100
TA = +25 °C*
ICCH52
Document Number: 002-04662 Rev. *F
Stop mode
(power off)
TA = +25 °C*
-
74
Max
Unit
102
mA
115
mA
115
mA
92
mA
105
mA
105
mA
82
mA
95
mA
95
mA
82
mA
72
mA
Remarks
2610
2000
µA
2000
2000
µA
1300
267
µA
LVD/
RTC
operation,
Backup
RAM
8 KB
retention
µA
Backup
RAM 8 KB
retention
285
265
Page 137 of 280
MB91520 Series
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/Vcc = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Input leak
current
Input
capacitance 1
Symbol
IIL
Other than
VCC,VSS,
AVCC, AVSS, C
RUP1
RSTX, NMIX
Pull-up
resistance
RUP3
“L” level
output voltage
All input pins
CIN1
RUP2
“H” level
output voltage
Pin Name
P073,074
076,077
Port pin other
than P035,
041,073,074,
076,077,093,
122
VOH1
Normal output
pin
VOH2
P073,074,076,
077
VOH3
P103 to 106
VOL1
Normal output
pin
VOL2
P073,074,076,
077
VOL3
P103 to 106
Document Number: 002-04662 Rev. *F
Conditions
Unit
Min
Typ
Max
VCC = AVCC = 5.5 V
VSS<VI<VCC
-5
-
5
µA
-
-
5
15
pF
VCC = 5.0 V ± 10 %
Vcc = 3.3 V ± 0.3 V
VCC = 5.0 V ± 10 %
Vcc = 3.3 V ± 0.3 V
VCC = 5.0 V ± 10 %
25
45
25
33
25
-
100
140
60
90
100
Vcc = 3.3 V ± 0.3 V
45
-
140
VCC
-0.5
-
Vcc = 4.5 V
IOH = -4.0 mA
Vcc = 3.0 V
IOH = -2.0 mA
Vcc = 4.5 V
IOH = -3.0 mA
Vcc = 4.5 V
IOH = -12.0 mA
Vcc = 3.0 V
IOH = -8.0 mA
Vcc = 4.5 V
IOL = 4.0 mA
Vcc = 3.0 V
IOL = 2.0 mA
Vcc = 4.5 V
IOL = 3.0 mA
Vcc = 4.5 V
IOL = 12.0 mA
Vcc = 3.0 V
IOL = 8.0 mA
Remarks
kΩ
kΩ
VCC
V
VCC
-0.5
-
VCC
V
VCC
-0.5
-
VCC
V
0
-
0.4
V
0
-
0.4
V
0
-
0.4
V
I2C pin
output
I2C pin
output
Page 138 of 280
MB91520 Series
Value
Parameter
Symbol
VIH1
“H” level
input voltage
VIH3
Pin Name
P000,002,003,
005,020,022,
024,026,150,
151,035,041,
045,055,057,
071-077,081,
082,093,096,
097,100-102,
111,115,116,
122,126,130,
134,142,143,
144,153
Port other than
VIH1
VIH5
RSTX,NMIX,MD
0,MD1
VIHT
DEBUGIF
VIL1
“L” level
input voltage
VIL3
P000,002,003,
005,020,022,
024,026,150,
151,035,041,
045,055,057,
071-077,081,
082,093,096,
097,100-102,
111,115,116,
122,126,130,
134,142,143,
144,153
Port other than
VIH1
VIL5
RSTX,NMIX,MD
0,MD1
VILT
DEBUGIF
Conditions
Unit
Min
Typ
Max
0.7×
VCC
-
VCC
V
Automotive input
level
CMOS
hysteresis input
level
0.8×
VCC
-
VCC
V
0.8×
VCC
-
VCC
V
TTL input level
2
-
VCC
V
CMOS
hysteresis input
level
Vss
-
0.3×
VCC
V
Vss
-
0.5×
VCC
V
Vss
-
0.2×
VCC
V
Vss
-
0.8
V
CMOS
hysteresis input
level
Automotive
input level
CMOS
hysteresis input
level
TTL input level
Remarks
*: It is a standard in BRAMSC (Backup RAM sleep control bit) = 1 (Enter the state of the sleep at the standby mode) condition.
Document Number: 002-04662 Rev. *F
Page 139 of 280
MB91520 Series
AC Characteristics
(1) Main Clock Timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Parameter
Symbol
Source oscillation
clock frequency
Source oscillation
clock cycle time
Pin
Name
Value
Conditions
Unit
Min
Typ
Max
FC
X0, X1
-
4
16
MHz
tCYL
X0, X1
62.5
250
-
ns
FCP
2
80
FCPP
1
40
Internal operating
clock frequency*1
-
-
1
40
MHz
FCPT
tCP
-
tCPP
Internal operating
clock cycle time*1
-
1
32
12.5
500
25
1000
-
25
1000
ns
tCPT
31.25
CAN PLL jitter
(during lock)
tPJ
-
-10
1000
-
10
ns
Remarks
CPU clock
Peripheral bus
clock
External bus clock
(When VCC = 5.0 V
is used) *2
External bus clock
(When VCC = 3.3 V
is used)
CPU clock
Peripheral bus
clock
External bus clock
(When VCC = 5.0 V
is used)
External bus clock
(When VCC = 3.3 V
is used)
FCP = 80 MHz
(4 MHz Multiplied
by 20)
Built-in CR
oscillation
FCCR
50
100
150
kHz
frequency
*1: The maximum / minimum value is defined when using the main clock and PLL clock.
*2: Please use it with external load capacity 12 pF or less for VCC = 3.3 V ± 0.3 V (40 MHz operation).
X0,X1 clock timing
tCYL
X0
Document Number: 002-04662 Rev. *F
Page 140 of 280
MB91520 Series
CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
Document Number: 002-04662 Rev. *F
Page 141 of 280
MB91520 Series
(1-2) Sub clock timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Parameter
Source oscillation clock
frequency
Source oscillation clock
cycle time
Symbol
FCL
Pin
Name
Value
Conditions
X0A, X1A
Unit
Min
Typ
Max
-
32.768
-
kHz
-
30.52
-
µs
Remarks
tLCYL
X0A, X1A
X0A,X1A clock timing
tLCYL
X0A
Document Number: 002-04662 Rev. *F
Page 142 of 280
MB91520 Series
Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
MB91F52x recommended guaranteed
operation range
MB91F52x guaranteed operation
range
Power supply voltage V CC (V)
5.5
4.5
2.7
PLL guaranteed operation
range
2
4
80
Internal operation clock frequency F CP (MHz)
Note: The power supply voltage, which is the low-voltage detection setting voltage or lower, is in the reset
state.
Document Number: 002-04662 Rev. *F
Page 143 of 280
MB91520 Series
Oscillation clock frequency vs. Internal operation clock frequency
Internal operation clock frequency
PLL clock
Main Clock Multiplied Multiplied Multiplied Multiplied
...
by 1
by 2
by 3
by 4
Oscillation
clock frequency
4 MHz
2 MHz
4 MHz
8 MHz
12 MHz
16 MHz
...
Multiplied Multiplied
by 19
by 20
76 MHz
80 MHz
Example of oscillation circuit
X0
4MHz
C1=10pF
X1
R=0Ω
C2=10pF
Note: As to the product with its clock supervisor’s initial value is “ON”, when the oscillator is unable to start
within 20 ms from the stop state the clock supervisor will detect the oscillation stop. As a result, the CPU
moves to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20 ms. Moreover, it is
recommended to be designed after the match evaluation of the circuit is requested to the departure
pendulum maker when the oscillation circuit is composed.
Document Number: 002-04662 Rev. *F
Page 144 of 280
MB91520 Series
AC characteristics are specified by the following measurement reference voltage values.
Input Signal Waveform
Hysteresis Input Pin (Automotive)
Output Signal Waveform
Output Pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis Input Pin (CMOS schmitt)
0.7Vcc
0.3Vcc
Document Number: 002-04662 Rev. *F
Page 145 of 280
MB91520 Series
(2) Reset Input
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Parameter
Value
Pin
Conditions
Name
Symbol
Unit
Reset input time
tRSTL
RSTX
–
Min
Max
10
–
µs
Oscillation time of
oscillator* +100
100
–
µs
–
µs
1
–
µs
Width for reset
input removal
Remarks
When normal
operation
At Stop mode
At Power-on*2
At Watch mode
*1: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90 %. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.
*2: In case of using MB91F52xxxD or MB91F52xxxE and corresponding to note in (3) Power-on Conditions of next
subsection, assert RSTX with power-on.
tRSTL
RSTX
0.2 vcc
0.2 vcc
At Stop mode
tRSTL
RSTX
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 μs
Oscillation time
of oscillator
Internal reset
Document Number: 002-04662 Rev. *F
Oscillation stabilization
waiting time
Instruction
execution
Page 146 of 280
MB91520 Series
(3) Power-on Conditions
(3-1) [MB9152xxxB/MB9152xxxC/MB9152xxxD]
(TA: -40 °C to +125 °C, VSS = 0.0 V)
Parameter
Symbol
Value
Pin
Name
Conditions
Unit
Min
Typ
Max
Remarks
Level detection
voltage
Level detection
hysteresis width
–
VCC
–
2.024
2.2
2.376
V
–
VCC
–
–
100
–
mV
Level detection time
–
–
–
–
–
30
µs
*1
tOFF
VCC
–
50
–
–
ms
*2
Power ramp rate
dV/dt
VCC
VCC:
0.2 V to 2.376 V
–
–
4
C pin voltage at
Power-on
–
C
–
–
–
60
Power off time
mV/µs *3
mV
*4
*1: This spec is at 4 mV/µs of power ramp rate. If the power ramp rate is faster than 4mV/µs, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: Vcc must be held below 0.2 V for a minimum period of tOFF.
*3: Power-on can detect by satisfying power ramp rate when power off time is not satisfied.
*4: C-pin voltage is below 60 mV when VCC is turned on again.
Note:
When using MB91F52xxxB/C, either *2 or *3 or *4 must be satisfied. When neither *2 nor *3 nor *4 can be
satisfied, use MB91F52xxxD and assert external reset (RSTX) at power-up and at any brownout event.
Power off time, Power ramp rate, C pin voltage at Power-on
tOFF
VCC
0.2V
0.2V
dV/dt
C pin
Document Number: 002-04662 Rev. *F
=60mV
≤60mV
Page 147 of 280
MB91520 Series
(3-2) [MB9152xxxE]
(TA: -40 °C to +125 °C, VSS = 0.0 V)
Parameter
Symbol
Value
Pin
Name
Conditions
Unit
Min
Typ
Max
Remarks
Level detection
voltage
Level detection
hysteresis width
–
VCC
–
2.024
2.2
2.376
V
–
VCC
–
–
100
–
mV
Level detection time
–
–
–
–
–
30
µs
*1
tOFF1
VCC
Vcc ≤ 0.2 V
50
–
–
ms
*2
tOFF2
VCC
Vcc ≤ 1.3 V
100
–
–
µs
*4
–
–
50
mV/µs *3
–
–
1000
mV/µs *4
Power off time
dV/dt
VCC
dV/dt
VCC
–
C
–
–
–
60
|dV/dt|
Vcc
VCC:
Between 2.4 V
and 4.5 V
–
–
50
Power ramp rate
C pin voltage at
Power-on
Maximum ramp rate
guaranteed to not
generate power-on
reset
VCC:
0.2 V to 2.376 V
(tOFF1 <50 ms )
VCC:
1.3 V to 2.376 V
(tOFF2 ≥ 100 µs)
mV
*5
mV/µs *6
*1: The specified level detection time applies only for power ramp rate of 1000 mV/µs or less.
*2: Vcc must be held below 0.2 V for a minimum period of tOFF1.
*3: Power-on can detect by satisfying power ramp rate when tOFF1 is not satisfied.
*4: Vcc must be held below 1.3 V for a minimum period of tOFF2.
Power ramp rate must be 1000 mV/µs or less from 1.3 V to 2.376 V.
Power-on can detect by satisfying power ramp rate and power off time.
*5: C-pin voltage is below 60 mV when VCC is turned on again.
*6: This specification is specified the power supply fluctuation after power on detection. When VCC voltage is
between 2.4 V and 4.5 V, the power supply fluctuation is below 50 mV/us, the detection of power-on is suppressed.
The power-on does not detect in any power fluctuation between 4.5 V and 5.5 V.
Note: When using MB91F52xxxE, either *2 or *3 or *4 or *5 must be satisfied. When neither *2 nor *3 nor *4 nor *5
can be satisfied, assert external reset (RSTX) at power-up and at any brownout event.
Power off time, Power ramp rate, C pin voltage at Power-on
*2
tOFF1
*3
*4
tOFF2
VCC
50ms
VCC
VCC
100us
0.2V
0.2V
50mV/us
dV/dt
1.3V
1.3V
*5
2.376V
VCC
dV/dt
C pin
Document Number: 002-04662 Rev. *F
=60mV
≤60mV
Page 148 of 280
MB91520 Series
Maximum ramp rate guaranteed to not generate power-on reset
5.5V
4.5V
VCC
|dV/dt|
Document Number: 002-04662 Rev. *F
|dV/dt|
2.4V
Page 149 of 280
MB91520 Series
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1) Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR : MD0 = 0, SMR: SCINV = 0, SCR:SPI = 0
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V±0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Serial clock cycle
time
SCK ↓ →
SOT delay time
Valid SIN →
SCK ↑ setup time
Symbol
tSCYC
tSLOVI
tIVSHI
SCK ↑ →
Valid SIN hold time
tSHIXI
Serial clock
"H"pulse width
tSHSL
Pin Name
Conditions
SCK0 to SCK11
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
SCK3 , SCK4
SIN3 , SIN4
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-1
0
-
ns
-
33
ns
-
SCK0 to SCK11
SIN0 to SIN11
Remarks
Internal
shift
clock
mode
output pin :
CL = 50 pF
SCK0 to SCK11
Serial clock
"L" pulse width
SCK ↓ →
SOT delay time
tSLSH
tSLOVE
Valid SIN →
SCK ↑ setup time
tIVSHE
SCK ↑ →
Valid SIN hold time
tSHIXE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
-
-
300
ns
10
-
ns
20
-
ns
External shift
clock
mode
output pin:
CL = 50 pF
SCK0 to SCK11
SIN0 to SIN11
SCK fall time
tF
SCK0 to SCK11
-
5
ns
SCK rise time
tR
SCK0 to SCK11
-
5
ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400 kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *F
Page 150 of 280
MB91520 Series
Internal shift clock mode
tSCYC
2.4V
SCKx
0.8V
0.8V
tSLOVI
2.4V
SOTx
0.8V
tIVSHI
SINx
tSHIXI
VIH1
VIH1
VIL1
VIL1
External shift clock mode
tSLSH
SCKx
tSHSL
VIH1
VIH1
VIL1
tF
SOTx
VIL1
tSLOVE
tR
2.4V
0.8V
tIVSHE
SINx
Document Number: 002-04662 Rev. *F
tSHIXE
VIH1
VIH1
VIL1
VIL1
Page 151 of 280
MB91520 Series
(4-1-2) Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR : MD0 = 0, SMR: SCINV = 1, SCR:SPI = 0
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Serial clock cycle
time
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
SCK ↓ →
Valid SIN hold time
Serial clock
"H"pulse width
Symbol
tSCYC
tSHOVI
tIVSLI
tSLIXI
Pin Name
Conditions
SCK0 to SCK11
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
SCK3 , SCK4
SIN3, SIN4
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
0
-
ns
-
SCK0 to SCK11
SIN0 to SIN11
tSHSL
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
SCK0 to SCK11
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
tSLSH
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSLE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
Remarks
Internal
shift
clock
mode
output pin :
CL = 50 pF
External shift
clock
mode
output pin:
CL = 50 pF
-
SCK0 to SCK11
SIN0 to SIN11
SCK fall time
tF
SCK0 to SCK11
-
5
ns
SCK rise time
tR
SCK0 to SCK11
-
5
ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400 kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *F
Page 152 of 280
MB91520 Series
Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSHOVI
2.4V
SOTx
0.8V
tIVSLI
SINx
tSLIXI
VIH1
VIH1
VIL1
VIL1
External shift clock mode
tSHSL
SCKx
tSLSH
VIH1
VIH1
VIL1
tR
SOTx
VIL1
tSHOVE
tF
2.4V
0.8V
tIVSLE
SINx
Document Number: 002-04662 Rev. *F
tSLIXE
VIH1
VIH1
VIL1
VIL1
Page 153 of 280
MB91520 Series
(4-1-3) Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 0, SMR:SCINV = 0, SCR:SPI = 1
(TA:-40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V)
Value
Parameter
Serial clock cycle time
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
Symbol
tSCYC
tSHOVI
tIVSLI
Pin Name
Conditions
SCK0 to SCK11
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
SCK3 , SCK4
SIN3 , SIN4
-
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
SCK ↓ →
Valid SIN hold time
tSLIXI
SCK0 to SCK11
SIN0 to SIN11
0
-
ns
SOT→SCK↓
delay time
tSOVLI
SCK0 to SCK11
SOT0 to SOT11
2tCPP
-30
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+
10
-
ns
2tCPP
-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
Remarks
Internal shift clock
mode output pin :
CL = 50 pF
SCK0 to SCK11
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
tSLSH
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSHE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
-
External shift clock
mode output pin:
CL = 50 pF
SCK0 to SCK11
SIN0 to SIN11
SCK fall time
tF
SCK0 to SCK11
-
5
ns
SCK rise time
tR
SCK0 to SCK11
-
5
ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400 kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *F
Page 154 of 280
MB91520 Series
Internal shift clock mode
tSCYC
2.4V
SCKx
tSHOVI
0.8V
0.8V
tSOVLI
SOTx
2.4V
2.4V
0.8V
0.8V
tIVSLI
SINx
tSLIXI
VIH
VIH
VIL
VIL
External shift clock mode
tSLSH
VIH
SCKx
VIH
VIL
VIL
tR
tSHOVE
2.4V
2.4V
0.8V
0.8V
IVSLE
ttIVSHE
SINx
VIH
VIL
tF
*
SOTx
tSHSL
tSLIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
Document Number: 002-04662 Rev. *F
Page 155 of 280
MB91520 Series
(4-1-4) Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 0, SMR:SCINV = 1, SCR:SPI = 1
(TA:-40 °C to +125 °C, VCC = A VCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ±0.3 V, VSS = AVSS = 0.0V)
Value
Parameter
Serial clock cycle
time
SCK↓→
SOT delay time
Valid SIN →
SCK↑setup time
Symbol
tSCYC
tSLOVI
tIVSHI
Pin Name
Conditions
SCK0 to SCK11
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
SCK3 , SCK4
SIN3 , SIN4
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
SCK↑→
Valid SIN hold time
tSHIXI
SCK0 to SCK11
SIN0 to SIN11
0
-
ns
SOT→SCK↑
delay time
tSOVHI
SCK0 to SCK11
SOT0 to SOT11
2tCPP-30
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
Remarks
Internal shift clock
mode output pin :
CL = 50 pF
SCK0 to SCK11
Serial clock
"L" pulse width
SCK↓→
SOT delay time
tSLSH
tSLOVE
Valid SIN →
SCK↑setup time
tIVSHE
SCK↑→
Valid SIN hold time
tSHIXE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
SCK3 , SCK4
SOT3 , SOT4
-
External shift clock
mode output pin:
CL = 50 pF
SCK0 to SCK11
SIN0 to SIN11
SCK fall time
tF
SCK0 to SCK11
-
5
ns
SCK rise time
tR
SCK0 to SCK11
-
5
ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400 kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *F
Page 156 of 280
MB91520 Series
Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSOVHI
SOTx
tSLOVI
2.4V
2.4V
0.8V
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
External shift clock mode
tSHSL
tSLSH
tR
VIH
SCKx
VIH
VIL
VIH
VIL
VIL
tSLOVE
*
SOTx
tF
tF
2.4V
2.4V
0.8V
0.8V
tIVSHE
SINx
tSHIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
Document Number: 002-04662 Rev. *F
Page 157 of 280
MB91520 Series
(4-1-5) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0,
When Serial chip select is used : SCSCR:CSEN = 1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV = 0,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL = 1
(TA:-40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V±0.3 V, VSS = AVSS = 0.0V)
Value
Parameter
SCS↓→SCK↓
setup time
SCK↑→SCS↑
hold time
SCS
deselect time
Symbol
tCSSI
tCSHI
tCSDI
Pin Name
SCK1, SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
Document Number: 002-04662 Rev. *F
Conditions
-
Unit
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
tCSDS-50
tCSDS+50
*3
*3
Remarks
ns
ns
ns
Internal shift
clock mode
output pin :
CL = 50 pF
ns
ns
Page 158 of 280
MB91520 Series
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Remarks
Max
SCK1 to SCK11
SCS1 to SCS3,
ns
3tCPP+30
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCK↑→SCS↑
tCSHE
ns
SCS70 to SCS73,
hold time
+0
SCS8 to SCS11
SCS1 to SCS3,
SCS40 to SCS43,
SCS
SCS50 to SCS53,
tCSDE
ns
External shift
deselect time
SCS60 to SCS63,
3tCPP+30
clock mode
SCS70 to SCS73,
output pin:
SCS8 to SCS11
CL = 50 pF
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
40
ns
SCS8 to SCS11
SCS↓→SOT
tDSE
SOT1 , SOT2 ,
delay time
SOT5 to SOT11
SCS3,
SCS40 to SCS43
300
ns
SOT3 , SOT4
SCS1 to SCS3,
SCS40 to SCS43,
External shift
SCS50 to SCS53,
SCS↑→SOT
clock mode
tDEE
SCS60 to SCS63,
+0
ns
delay time
output pin:
SCS70 to SCS73,
CL = 50 pF
SCS8 to SCS11
SOT1 to SOT11
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
Internal shift
SCS50 to SCS53,
3tCPP-10
3tCPP+50
ns
SCK↓→SCS↓
clock mode
SCS60 to SCS63,
clock switch
tSCC
Round operation
SCS70 to SCS73,
time
output pin:
SCS8 to SCS11
CL = 50 pF
SCK3 , SCK4
SCS3 ,
3tCPP-300 3tCPP+50
ns
SCS40 to SCS43
*1: tCSSU = SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD = SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS = SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
SCS↓→SCK↓
setup time
tCSSE
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *F
Page 159 of 280
MB91520 Series
SCS output
tCSDI
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSSE
tCSHE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
External shift clock mode
Document Number: 002-04662 Rev. *F
Page 160 of 280
MB91520 Series
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
Document Number: 002-04662 Rev. *F
Page 161 of 280
MB91520 Series
(4-1-6) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0,
When Serial chip select is used : SCSCR:CSEN = 1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV = 1,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL = 1
(TA:-40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V)
Value
Parameter
SCS↓→SCK↑
setup time
SCK↓→SCS↑
hold time
SCS
deselect time
Symbol
tCSSI
tCSHI
tCSDI
Pin Name
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
Document Number: 002-04662 Rev. *F
Conditions
-
Unit
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
tCSDS-50
tCSDS+50
*3
*3
Remarks
ns
ns
ns
Internal shift
clock mode
output pin :
CL = 50 pF
ns
ns
Page 162 of 280
MB91520 Series
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Remarks
Max
SCK1 to SCK11
SCS1 to SCS3,
ns
3tCPP+30
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCK↓→SCS↑
tCSHE
ns
SCS70 to SCS73,
hold time
+0
SCS8 to SCS11
SCS1 to SCS3,
SCS40 to SCS43,
SCS
SCS50 to SCS53,
tCSDE
ns
External shift
deselect time
SCS60 to SCS63,
3tCPP+30
clock mode
SCS70 to SCS73,
output pin:
SCS8 to SCS11
CL = 50 pF
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
40
ns
SCS8 to SCS11
SCS↓→SOT
tDSE
SOT1 , SOT2,
delay time
SOT5 to SOT11
SCS3,
SCS40 to SCS43
300
ns
SOT3 , SOT4
SCS1 to SCS3,
SCS40 to SCS43,
External shift
SCS50 to SCS53,
SCS↑→SOT
clock mode
tDEE
SCS60 to SCS63,
+0
ns
delay time
output pin:
SCS70 to SCS73,
CL = 50 pF
SCS8 to SCS11
SOT1 to SOT11
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
Internal shift
SCS50 to SCS53,
ns
clock mode
3tCPP-10
3tCPP+50
SCK↑→SCS↓
SCS60 to SCS63,
Round
clock switch
tSCC
SCS70 to SCS73,
operation
time
SCS8 to SCS11
output pin:
CL = 50 pF
SCK3 , SCK4
SCS3 ,
3tCPP-300
3tCPP+50
ns
SCS40 to SCS43
*1: tCSSU = SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD = SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS = SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
SCS↓→SCK↑
setup time
tCSSE
Please see the hardware manual for details of above-mentioned *1,*2, and *3
Document Number: 002-04662 Rev. *F
Page 163 of 280
MB91520 Series
SCS output
tCSDI
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSSE
tCSHE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
External shift clock mode
Document Number: 002-04662 Rev. *F
Page 164 of 280
MB91520 Series
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
Document Number: 002-04662 Rev. *F
Page 165 of 280
MB91520 Series
(4-1-7) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0,
When Serial chip select is used : SCSCR:CSEN = 1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV = 0,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL = 0
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3V±0.3V, VSS = AVSS = 0.0V)
Value
Parameter
SCS↑→SCK↓
setup time
SCK↑→SCS↓
hold time
SCS
deselect time
Symbol
tCSSI
tCSHI
tCSDI
Pin Name
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCK1 to SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
Document Number: 002-04662 Rev. *F
Conditions
Unit
Min
Max
tCSSU-50
tCSSU+0
*1
*1
ns
tCSSU-50
tCSSU
+300
ns
*1
Remarks
*1
-
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300 tCSHD+50
*2
*2
tCSDS-50
tCSDS+50
*3
*3
ns
Internal shift
clock mode
output pin :
CL = 50 pF
ns
ns
Page 166 of 280
MB91520 Series
Value
Parameter
Symbol
SCS↑→SCK↓
setup time
tCSSE
SCK↑→SCS↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCS↑→SOT
delay time
tDSE
Pin Name
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 , SOT2,
SOT5 to SOT11
SCS3 ,
SCS40 to SCS43
SOT3 , SOT4
Conditions
Unit
Min
Max
3tCPP+3
0
-
ns
-
ns
3tCPP+3
0
-
ns
-
40
ns
-
300
ns
+0
-
Remarks
External shift
clock mode
output pin:
CL = 50 pF
SCS1 to ~SCS3,
SCS40 to SCS43,
External shift
SCS50 to SCS53,
SCS↓→SOT
clock mode
tDEE
SCS60 to SCS63,
+0
ns
delay time
output pin:
SCS70 to SCS73,
CL = 50 pF
SCS8 to SCS11
SOT1 to SOT11
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
3tCPP+5
Internal shift
SCS50 to SCS53,
3tCPP-10
ns
0
SCK↓→SCS↑
clock mode
SCS60 to SCS63,
clock
switch
tSCC
Round operation
SCS70 to SCS73,
time
output pin:
SCS8 to SCS11
CL = 50 pF
SCK3 , SCK4
3tCPP-30
3tCPP+5
SCS3 ,
ns
0
0
SCS40 to SCS43
*1: tCSSU = SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD = SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS = SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *F
Page 167 of 280
MB91520 Series
tCSDI
SCS output
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode
tCSDE
SCS input
tCSSE
tCSHE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
External shift clock mode
Document Number: 002-04662 Rev. *F
Page 168 of 280
MB91520 Series
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
Document Number: 002-04662 Rev. *F
Page 169 of 280
MB91520 Series
(4-1-8) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0,
When Serial chip select is used: SCSCR:CSEN = 1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV = 1,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL = 0
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
SCS↑→SCK↑
setup time
SCK↓→SCS↓
hold time
SCS
deselect time
Symbol
tCSSI
tCSHI
tCSDI
Pin Name
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
Document Number: 002-04662 Rev. *F
Conditions
-
Unit
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
tCSDS-50
tCSDS+50
*3
*3
Remarks
ns
ns
ns
Internal shift
clock mode
output pin :
CL = 50 pF
ns
ns
Page 170 of 280
MB91520 Series
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Remarks
Max
SCK1 to SCK11
SCS1 to SCS3,
ns
3tCPP+30
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCK↓→SCS↓
tCSHE
ns
SCS70 to SCS73,
hold time
+0
SCS8 to SCS11
SCS1 to SCS3,
SCS40 to SCS43,
SCS
SCS50 to SCS53,
tCSDE
ns
External shift
deselect time
SCS60 to SCS63,
3tCPP+30
clock mode
SCS70 to SCS73,
output pin:
SCS8 to SCS11
CL = 50 pF
SCS1 , SCS2,
SCS50~SCS53,
SCS60~SCS63,
SCS70~SCS73,
40
ns
SCS8~SCS11
SCS↑→SOT
tDSE
SOT1 , SOT2,
delay time
SOT5~SOT11
SCS3 ,
SCS40~SCS43
300
ns
SOT3 ,SOT4
SCS1 to SCS3,
SCS40 to SCS43,
External shift
SCS50 to SCS53,
SCS↓→SOT
clock mode
tDEE
SCS60 to SCS63,
+0
ns
delay time
output pin:
SCS70 to SCS73,
CL = 50 pF
SCS8 to SCS11
SOT1 to SOT11
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
Internal shift
SCS50 to SCS53,
3tCPP-10
3tCPP+50
SCK↑→SCS↑
clock mode
SCS60 to SCS63,
clock switch
tSCC
ns
Round operation
SCS70 to SCS73,
time
output pin:
SCS8 to SCS11
CL = 50 pF
SCK3 , SCK4
SCS3 ,
3tCPP-300 3tCPP+50
SCS40 to SCS43
*1: tCSSU = SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD = SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS = SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
SCS↑→SCK↑
setup time
tCSSE
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *F
Page 171 of 280
MB91520 Series
tCSDI
SCS output
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode
tCSDE
SCS input
tCSSE
tCSHE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Slave mode
Document Number: 002-04662 Rev. *F
Page 172 of 280
MB91520 Series
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode, Example of switching clock by round operation (x,y=0,1,2,3)
Document Number: 002-04662 Rev. *F
Page 173 of 280
MB91520 Series
(4-2) UART (Asynchronous serial interface) timing
Bit setting: SMR : MD2 = 0, SMR:MD1 = 0, SMR : MD0 = 0
Bit setting: SMR : MD2 = 0, SMR:MD1 = 0, SMR : MD0 = 1
When external clock is selected (BGR:EXT = 1)
(TA: -40 °C to +125°C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V)
Value
Parameter
Symbol
Serial clock
"L" pulse width
tSLSH
Serial clock
"H"pulse width
tSHSL
Pin Name
Conditions
SCK0 to SCK11
Unit
Min
Max
tCPP+10
-
ns
tCPP+10
-
ns
output pin:
CL = 50 pF
-
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
VIL
tF
tSHSL
VIH
SCK
Remarks
tSLSH
VIH
VIH
VIL
VIL
When external clock is selected
Document Number: 002-04662 Rev. *F
Page 174 of 280
MB91520 Series
(4-3) LIN Interface (v2.1)( Asynchronous Serial Interface for LIN (v2.1)) timing
Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 1
(TA:-40°C to +125°C, VCC = AVCC = 5.0 V±10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
Serial clock
"L" pulse width
tSLSH
tCPP+10
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
SCK0 to SCK11
output pin:
CL = 50 pF
-
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
SCK
VIL
tF
tSHSL
VIH
Remarks
tSLSH
VIH
VIH
VIL
VIL
When external clock is selected
Document Number: 002-04662 Rev. *F
Page 175 of 280
MB91520 Series
(4-4) I2C timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Standard Mode
Parameter
SCL clock frequency
Repeat "start" condition
hold time
SDA ↓ → SCL ↓
Symbol
fSCL
tHDSTA
Period of "L" for SCL
clock
tLOW
Period of "H" for SCL
clock
tHIGH
Repeat "start" condition
setup time
SCL ↑ → SDA ↓
tSUSTA
Pin Name
SCK3 to
SCK11
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
SCK3 to
SCK11,
(SCL)
SCK3 to
SCK11,
(SCL)
SCK3 to
SCK11,
(SCL)
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
"Stop" condition setup
time
SCL ↑ → SDA ↑
tSUSTO
Bus-free time between
"stop" condition and
"start" condition
tBUF
–
Noise filter
tSP
–
Fast Mode*3
Conditions
CL = 50 pF
R = (VP/IOL) *1
–
Unit
Min
Max
Min
Max
0
100
0
400
kHz
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
3.45*2
0
0.9*3
μs
250
–
100
–
ns
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
2tCPP*4
–
2tCPP*4
–
ns
Remarks
Notes: Only ch.3 and ch.4 are standard mode/fast mode correspondence. In ch.5-ch.8, ch.10, and ch.11, only a standard mode is
correspondences.
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of
Document Number: 002-04662 Rev. *F
Page 176 of 280
MB91520 Series
"tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8 MHz or more when use I2C.
・I2C timing
SDA
tSUDAT
tSUSTA
tBUF
tLOW
SCL
tHDSTA
tHDDAT
Document Number: 002-04662 Rev. *F
tHIGH
tHDSTA
tSP
tSUSTO
Page 177 of 280
MB91520 Series
(5) Timer input timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Input pulse width
tTIWH,
tTIWL
Pin Name
Conditions
TIN0 to TIN7
ICU0 to ICU9
FRCK0 to FRCK5
TIOA0, TIOA1,
TIOB0, TIOB1,
AIN0, AIN1,
BIN0, BIN1,
ZIN0, ZIN1
Unit
–
Min
Max
4tCPP
–
Remarks
ns
Timer input timing
TINx,
ICUx,
FRCKx,
TIOAx,TIOBx
AINx,BINx,ZINx
tTIWH
tTIWL
VIH
VIH
VIL
VIL
(6) Trigger input timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Input pulse width
Pin Name
Conditions
INT0 to
INT15,
ADTG,
RX0,
RX1,
RX2
tTRGH,
tTRGL
Unit
Min
Max
5tCPP
–
ns
1
–
μs
Remarks
–
At stop mode
Trigger input timing
tTRGL
tTRGH
INTx
ADTG
RXx
VIH
Document Number: 002-04662 Rev. *F
VIH
VIL
VIL
Page 178 of 280
MB91520 Series
(7) NMI input timing
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Input pulse width
Symbol
Pin Name
tNMIL
Conditions
–
NMIX
Unit
Min
Max
4tCPP
–
Remarks
ns
NMIX input timing
tNMIL
NMIX
VIH5
VIH5
VIL5
VIL5
(8) Low voltage detection (External low-voltage detection)
(TA: -40 °C to +125 °C, VSS = AVSS = 0.0 V)
Parameter
Power supply
voltage range
Symbol
Pin
Name
VDP5
Detection
voltage*3
VDL
Hysteresis width
VHYS
Value
Conditions
-
VCC
*1
-
Unit
Min
Typ
Max
2.7
-
5.5
-8%
LVD5F
_SEL
[3:0]
+8%
V
-
0.1
-
V
Remarks
V
LVD5F_SEL[3:0] are
programmable.
Refer to the
hardware manual.
When power-supply
voltage rises
Low voltage
Td
30
µs
detection time
Power supply
VCC
-2
2
V/ms *2
voltage regulation
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low voltage
detection by detecting voltage (VDL).
*3: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V).
This LVD setting cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation
voltage, as this detection level is below the minimum guaranteed MCU operation voltage (2.7 V).
Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *F
Page 179 of 280
MB91520 Series
(9) Low voltage detection (Internal low-voltage detection)
(TA: -40 °C to +125 °C, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
Name
Value
Conditions
Unit
Min
Typ
Max
Power supply
voltage range
VRDP5
-
0.6
-
1.4
V
Detection
voltage*2
VRDL
*1
0.8
0.9
1.0
V
Hysteresis width
VRHYS
-
0.1
-
V
-
Remarks
When
power-supply
voltage falls
When
power-supply
voltage rises
-
Low voltage
30
µs
detection time
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: The detection voltage of the internal low voltage detection is 0.9 V ± 0.1 V.
This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage,
as this detection level is below the minimum guaranteed MCU operation voltage.
Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
(10) External bus I/F (synchronous mode) timing
(TA: -40 °C to +105 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
(external load capacitance 50 pF)
Value
Parameter
Symbol
Pin Name
Unit
Min
VCC = 5.0 V ± 10 %*1
25
Cycle time
tCYC
SYSCLK
Remarks
Max
-
ns
31.25
VCC = 3.3 V ± 0.3 V
ASX delay time
tCHASL,
tCHASH
SYSCLK
ASX
0.5
18
ns
CS0X to CS3X
delay time
tCHCSL,
tCHCSH
SYSCLK
CS0X to
CS3X
0.5
18
ns
A00 to A21
delay time
tCHAV,
tCHAX
SYSCLK
A00 to A21
0.5
18
ns
RDX delay
time
tCHRL,
tCHRH
SYSCLK
RDX
0.5
18
ns
RDX
minimum pulse
tRLRH
RDX
tCYC×
2 - 20
-
ns
RWT = 1, set RWT to 1 or more.*2
Data setup →
RDX↑time
tDSRH
18+tCYC
-
ns
Same as above
RDX↑→
data hold
tRHDH
0
-
ns
RDX
D16 to D31
Document Number: 002-04662 Rev. *F
Page 180 of 280
MB91520 Series
Value
Parameter
Symbol
Pin Name
Unit
Min
Max
WRnX delay
time
tCHWL,
tCHWH
SYSCLK
WR0X,
WR1X
0.5
18
ns
WRnX
minimum pulse
tWLWH
WR0X,
WR1X
tCYC - 10
-
ns
SYSCLK↑→
data output
time
tCHDV
0.5
18
ns
SYSCLK↑→
data hold time
tCHDX
-
18
ns
SYSCLK↑→
address output
time
tCHMAV
0.5
18
ns
SYSCLK↑→
address hold
time
Remarks
WWT = 0 *2
SYSCLK
D16 to D31
SYSCLK
D16 to D31
tCHMAX
-
18
ns
Set WRCS to 1 or more.
In multiplex mode, set as follows:
Set CSWR and CSRD to 2 or
more.
ASCY must satisfy the following
conditions because of setting
ADCY > ASCY and protocol
violation prevention.
ADCY +1 ≤ ACS + CSRD
ADCY +1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
See Hardware Manual for details.
*1: Please use it with external load capacity 12 pF or less for VCC = 3.3 V ± 0.3 V (40 MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (t CYC × the number of expanded cycles) to the rated
value.
Document Number: 002-04662 Rev. *F
Page 181 of 280
MB91520 Series
External bus I/F (synchronous mode, read operation, and multiplex mode) timing
t1
t3
t2
t4
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
RDCS=0
ACS=0
tCHRL
tCHRH
RWT=1
RDX
tRLRH
CSRD=2
ADCY=1
tCHMAV
D16D16~D31
to D31
tCHMAX
Read Data
Valid Address
tRHDH
tDSRH
External bus I/F (synchronous mode, read operation, and split mode) timing
t1
t3
t2
t4
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
RDCS=0
ACS=0
tCHRL
tCHRH
RWT=1
RDX
CSRD=0
tRLRH
tCHAV
A00
to A21
A00~A21
D16
to D31
D16~D31
tCHAX
Valid Address
Read Data
tDSRH
Document Number: 002-04662 Rev. *F
tRHDH
Page 182 of 280
MB91520 Series
External bus I/F (synchronous mode, write operation, and multiplex mode) timing
t1
t4
t3
t2
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
WRCS=1
ACS=0
tCHWL
WR0X
to WR1X
WR0X~WR1X
tCHMAV
D16
to D31
D16~D31
tCHWH
tWLWH
CSWR=2
WWT=0
ADCY=1
tCHDX
tCHDV
Write Data
Valid Address
External bus I/F (synchronous mode, write operation, and split mode) timing
t1
t4
t3
t2
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
tCHCSH
WRCS=1
CS0X~CS3X
CS0X
to CS3X
ACS=0
tCHWL
WR0X~WR1X
WR0X
to WR1X
tCHWH
tWLWH
CSWR=0
WWT=0
tCHAV
A00
to A21
A00~A21
tCHDV
D16~D31
D16
to D31
Document Number: 002-04662 Rev. *F
tCHAX
Valid Address
tCHDX
Write Data
Page 183 of 280
MB91520 Series
(11) External bus I/F (asynchronous mode) timing
(TA: -40 °C to +105 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
(external load capacitance 50pF)
Value
Parameter
Symbol
Pin Name
Unit
Min
VCC = 5.0 V ± 10 %*1
25
Cycle time
tCYC
SYSCLK
-
ns
31.25
Address setup →
RDX↑time
tASRH
RDX↑→
Address hold
Remarks
Max
VCC = 3.3 V ± 0.3 V
2×tCYC - 12
2×tCYC +
12
ns
RWT = 1,
set RWT to 1 or more. *2
tRHAH
tCYC - 12
tCYC + 12
ns
Set RDCS to 1 or more.
Data setup→
RDX↑time
tDSRH
18 +
tCYC
-
ns
RWT = 1,
set RWT to 1 or more.
RDX↑→
Data hold
tRHDH
0
-
ns
Address setup→
WRnX↑time
tASWH
tCYC - 12
tCYC + 12
ns
WWT = 0 *2
WRnX↑→
Address hold
tWHAH
WR0X to
WR1X
A00 to A21
tCYC - 12
tCYC + 12
ns
Set WRCS to 1 or more.
Data setup→
WRnX↑time
tDSWH
tCYC - 16
tCYC + 16
ns
WWT = 0 *2
WRnX↑→
Data hold
tWHDH
WR0X to
WR1X
D16 to D31
tCYC - 16
tCYC +
16
ns
Set WRCS to 1 or more.
tCYC-16
tCYC+ 16
ns
ASCY = 0
ns
In multiplex mode, set as follows:
Set CSWR and CSRD to 2 or
more.
ASCY must satisfy the following
conditions because of setting
ADCY > ASCY and protocol
violation prevention.
ADCY +1 ≤ ACS + CSRD
ADCY +1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
See Hardware Manual for details.
Address setup →
ASX↑time
ASX↑→Address
hold
RDX
A00 to A21
RDX
D16 to D31
tMASASH
ASX
D16 to D31
tMASHAH
tCYC-16
tCYC + 16
*1: Please use it with external load capacity 12 pF or less for VCC = 3.3 V ± 0.3 V (40 MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (t CYC × the number of expanded cycles) to the rated
value.
Document Number: 002-04662 Rev. *F
Page 184 of 280
MB91520 Series
External bus I/F (asynchronous mode, read operation, and multiplex mode) Timing
t1
t3
t2
t4
t5
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
RDCS=1
ACS=0
RWT=1
RDX
CSRD=2
ADCY=1
Read Data
Valid Address
D16~D31
D16
to D31
tRHDH
tMASASH
tMASHAH
tDSRH
External bus I/F (asynchronous mode, read operation, and split mode) Timing
t1
t3
t2
t4
t5
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
RDCS=1
ACS=0
RWT=1
RDX
A00
to A21
A00~A21
CSRD=0
Valid Address
tASRH
D16~D31
D16
to D31
tDSRH
Document Number: 002-04662 Rev. *F
tRHAH
Read Data
tRHDH
Page 185 of 280
MB91520 Series
External bus I/F (asynchronous mode, write operation, and multiplex mode) Timing
t1
t3
t2
t4
tCYC
SYSCLK
ASCY=0
ASX
CS0X~CS3X
CS0X
to CS3X
CS3X
CS0X
to
WRCS=1
ACS=0
WR0X~WR1X
WR0X
to WR1X
CSWR=2
WWT=0
ADCY=1
Write Data
Valid Address
D16
to D31
D16~D31
tMASASH
tMASHAH
tDSWH
tWHDH
External bus I/F (Asynchronous mode, write operation, and split mode) Timing
t1
t3
t2
t4
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
WR0X
to WR1X
WR0X~WR1X
A00~A21
A00
to A21
WRCS=1
ACS=0
CSWR=0
WWT=0
Valid Address
tASWH
D16
to D31
D16~D31
tDSWH
Document Number: 002-04662 Rev. *F
tWHAH
Write Data
tWHDH
Page 186 of 280
MB91520 Series
(12) External bus I/F (ready) Timing
(TA: -40 °C to +105 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
(external load capacitance 50 pF)
Parameter
Symbol
Value
Pin
Name
Min
Max
Unit
Remarks
If using RDY, set SYSCLK
to 20 MHz or less.
Cycle time
tCYC
SYSCLK
50
-
ns
RDY setup time →
SYSCLK↑
tRDYS
SYSCLK,
RDY
28
-
ns
SYSCLK↑→
RDY hold time
tRDYH
SYSCLK,
RDY
0
-
ns
External bus I/F (ready) Timing
t1
t2
t3
t4
t5
t6
tCYC
SYSCLK
ASX
ASCY=0
CS0X~CS3X
RDCS=0
ACS=0
RDX
RWT=2
CSRD=2
RDY
Auto wait cycle
tRDYS
tRDYH
Added cycle by RDY
Document Number: 002-04662 Rev. *F
Page 187 of 280
MB91520 Series
A/D Converter
(1) 12-bit A/D Converter Electrical Characteristics
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin Name
Unit
Min
Typ
Max
Resolution
-
-
-
-
12
bit
Total error
-
-
-
-
±12
LSB
Linearity error
-
-
-
-
± 4.0
LSB
Differential linearity
error
-
-
-
-
± 1.9
LSB
Zero transition voltage
VOT
AN0 to AN47
Full-scale transition
voltage
VFST
AN0 to AN47
Sampling time
tSMP
-
0.7
-
Compare time
tCMP
-
0.7
A/D conversion time
tCNV
-
Analog port input
current
IAIN
Analog input voltage
-
AVRL+
12.5LSB
AVRH+
10.5LSB
V
V
1LSB =
(VFST-VOT)/
4094
-
µs
*1
-
-
µs
*1
1.4
-
-
µs
*1
AN0 to AN47
-1.0
-
+1.0
µA
VAVSS ≤
VAIN ≤ VAVCC
VAIN
AN0 to AN47
AVRL
-
AVRH
V
AVRH
AVRH
3.0
-
5.5
V
AVRL
AVSS/
AVRL
-
0.0
-
V
-
0.47
0.63
mA
-
0.47
0.7
mA
-
-
2.5
µA
*2
-
1
1.96
mA
Per unit
-
-
1.6
µA
*2
Reference voltage
IA
Power supply current
AVRL11.5LSB
AVRH13.5LSB
Remarks
AVCC*3
IAH
IR
-
Per unit
TA: +105 °C
Per unit
TA: +125 °C
AVRH
IRH
Variation between
AN0 to AN47
4
LSB
channels
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
*3: The power supply current described only current value on A/D converter.
The total AVcc current value must be calculated the power supply current for A/D converter and D/A converter.
(Note) Please use the clock of 0.5 MHz-20 MHz for the output clock of A/D converter to guarantee accuracy.
Document Number: 002-04662 Rev. *F
Page 188 of 280
MB91520 Series
(2) Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Linearity error
: Deviation of the actual conversion characteristics from a straight line that connects
the zero transition point ("0000 0000 0000"← →"0000 0000 0001") to the full-scale
transition point ("1111 1111 1110"← →"1111 1111 1111").
Differential linearity
error
: Deviation of the input voltage from the ideal value that is required to change the
output code by LSB.
Linearity error of digital output N =
VNT - {1LSB × (N - 1) + VOT}
1LSB
Differential linearity error of digital output N =
V(N + 1) T - VNT
[LSB]
- 1 LSB
[LSB]
1LSB
1LSB =
VOT
VFST
VFST - VOT
4094
[V]
: Voltage at which the digital output changes from “000 H” to “001 H”.
: Voltage at which the digital output changes from “FFE H” to “FFF H”.
Document Number: 002-04662 Rev. *F
Page 189 of 280
MB91520 Series
(3) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling period for analog voltages may not be sufficient. In this case, it is
recommended to connect the capacitor (approx. 0.1 μF) to the analog input pin.
Analog input circuit model
R
Comparator
Analog input
C
During sampling: ON
R
C
1.9 kΩ (Max)
8.30 pF (Max)
(4.5 V ≤ AVCC ≤ 5.5 V)
4.3 kΩ (Max)
8.30 pF (Max)
(3.0 V ≤ AVCC ≤ 3.6 V)
Note: Listed values must be considered as reference values.
12-bit A/D
Document Number: 002-04662 Rev. *F
Page 190 of 280
MB91520 Series
Flash Memory
(1) Electrical Characteristics
Parameter
Value
Unit
Min
Typ
Max
–
200
800
ms
–
300
1100
ms
–
400
2000
ms
–
700
3700
ms
8-bit writing time
–
9
288
µs
16-bit writing time
–
12
384
µs
ECC writing time
–
9
288
µs
Sector erase time
Remarks
8 Kbytes sector*1,
excluding internal preprogramming time
8 Kbytes sector*1,
including internal preprogramming time
64 Kbytes sector*1,
excluding internal preprogramming time
64 Kbytes sector*1,
including internal preprogramming time
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
1,000 cycles/
20 years,
Erase cycle*2/
10,000 cycles/
–
–
–
Average TA = +85 °C*3
Data retain time
10 years,
100,000 cycles/
5 years
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into
normalized value at + 85 °C).
(2) Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might be shut down while writing or erasing, be sure to turn the power off by using an external
voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection
voltage (VDL*), hold Vcc at 2.7 V or more within the duration calculated by the following expression:
Td*[µs] + (period of PCLK [µs] × 257) + 50 [µs]
*: See “4.AC Characteristics (8) Low-voltage detection (External low-voltage detection) ”
Document Number: 002-04662 Rev. *F
Page 191 of 280
MB91520 Series
D/A Converter
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Value
Pin
Parameter
Symbol
Condition
Unit
Name
Min
Typ
Max
Resolution
Differential linearity
error
-
-
–
–
–
8
bit
-
-
–
–
–
± 3.0
LSB
Conversion time
-
-
–
–
0.47
2.37
0.58
2.90
0.69
3.43
µs
µs
Ro
DA0,
DA1
–
3.1
3.8
4.5
kΩ
IA
AVCC
–
–
475
580
µA
IAH
AVCC
–
–
–
7.5
µA
Output impedance
Power supply current
*1
Remarks
CL = 20
CL = 100
Each
channel
When
powerdown
Each
channel
*1: The power supply current described only current value on D/A converter.
The total AVcc current value must be calculated the power supply current for D/A converter and A/D converter.
Document Number: 002-04662 Rev. *F
Page 192 of 280
MB91520 Series
12. Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
MB91F526
Document Number: 002-04662 Rev. *F
Page 193 of 280
MB91520 Series
MB91F526
Document Number: 002-04662 Rev. *F
Page 194 of 280
MB91520 Series
MB91F526
Document Number: 002-04662 Rev. *F
Page 195 of 280
MB91520 Series
13. Ordering Information MB91F52xxxB*1
Part Number
Sub Clock
MB91F526LWBPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526LYBPMC
OFF
MB91F526LLBPMC
ON
MB91F525LYBPMC
MB91F525LJBPMC
OFF
ON
MB91F524LYBPMC
MB91F524LJBPMC
OFF
ON
MB91F523LYBPMC
OFF
MB91F523LLBPMC
ON
MB91F522LYBPMC
OFF
MB91F522LLBPMC
ON
OFF
LQP・176 pin,
Plastic
ON
OFF
ON
MB91F525LUBPMC
ON
OFF
OFF
MB91F525LKBPMC
ON
OFF
ON
MB91F524LUBPMC
ON
OFF
OFF
MB91F524LKBPMC
ON
OFF
ON
MB91F523LUBPMC
ON
OFF
OFF
MB91F523LKBPMC
ON
OFF
ON
MB91F522LUBPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526LKBPMC
MB91F522LKBPMC
ON
OFF
None
MB91F526LUBPMC
MB91F522LHBPMC
ON
OFF
MB91F522LJBPMC
MB91F522LSBPMC
ON
OFF
MB91F522LWBPMC
MB91F523LHBPMC
ON
OFF
MB91F523LJBPMC
MB91F523LSBPMC
ON
OFF
MB91F523LWBPMC
MB91F524LHBPMC
ON
OFF
MB91F524LLBPMC
MB91F524LSBPMC
ON
OFF
MB91F524LWBPMC
MB91F525LHBPMC
ON
OFF
MB91F525LLBPMC
MB91F525LSBPMC
ON
OFF
MB91F525LWBPMC
MB91F526LHBPMC
ON
OFF
MB91F526LJBPMC
MB91F526LSBPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 196 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWBPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526KYBPMC
OFF
MB91F526KLBPMC
ON
MB91F525KYBPMC
OFF
MB91F525KLBPMC
ON
MB91F524KYBPMC
OFF
MB91F524KLBPMC
ON
MB91F523KYBPMC
MB91F523KJBPMC
OFF
ON
MB91F522KYBPMC
OFF
MB91F522KLBPMC
None
ON
OFF
ON
OFF
ON
MB91F525KUBPMC
ON
OFF
OFF
MB91F525KKBPMC
ON
OFF
ON
MB91F524KUBPMC
ON
OFF
OFF
MB91F524KKBPMC
ON
OFF
ON
MB91F523KUBPMC
ON
OFF
OFF
MB91F523KKBPMC
ON
OFF
ON
MB91F522KUBPMC
Document Number: 002-04662 Rev. *F
ON
LQS・144 pin,
(Lead pitch 0.5 mm)
Plastic
OFF
MB91F526KKBPMC
MB91F522KKBPMC
ON
OFF
MB91F526KUBPMC
MB91F522KHBPMC
ON
OFF
MB91F522KJBPMC
MB91F522KSBPMC
ON
OFF
MB91F522KWBPMC
MB91F523KHBPMC
ON
OFF
MB91F523KLBPMC
MB91F523KSBPMC
ON
OFF
MB91F523KWBPMC
MB91F524KHBPMC
ON
OFF
MB91F524KJBPMC
MB91F524KSBPMC
ON
OFF
MB91F524KWBPMC
MB91F525KHBPMC
ON
OFF
MB91F525KJBPMC
MB91F525KSBPMC
ON
OFF
MB91F525KWBPMC
MB91F526KHBPMC
ON
OFF
MB91F526KJBPMC
MB91F526KSBPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 197 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWBPMC1
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526KYBPMC1
OFF
MB91F526KLBPMC1
ON
MB91F525KYBPMC1
OFF
MB91F525KLBPMC1
ON
MB91F524KYBPMC1
OFF
MB91F524KLBPMC1
ON
MB91F523KYBPMC1
MB91F523KJBPMC1
OFF
ON
MB91F522KYBPMC1
OFF
MB91F522KLBPMC1
None
ON
OFF
ON
OFF
ON
MB91F525KUBPMC1
ON
OFF
OFF
MB91F525KKBPMC1
ON
OFF
ON
MB91F524KUBPMC1
ON
OFF
OFF
MB91F524KKBPMC1
ON
OFF
ON
MB91F523KUBPMC1
ON
OFF
OFF
MB91F523KKBPMC1
ON
OFF
ON
MB91F522KUBPMC1
Document Number: 002-04662 Rev. *F
ON
LQN・144 pin,
(Lead pitch 0.4 mm)
Plastic
OFF
MB91F526KKBPMC1
MB91F522KKBPMC1
ON
OFF
MB91F526KUBPMC1
MB91F522KHBPMC1
ON
OFF
MB91F522KJBPMC1
MB91F522KSBPMC1
ON
OFF
MB91F522KWBPMC1
MB91F523KHBPMC1
ON
OFF
MB91F523KLBPMC1
MB91F523KSBPMC1
ON
OFF
MB91F523KWBPMC1
MB91F524KHBPMC1
ON
OFF
MB91F524KJBPMC1
MB91F524KSBPMC1
ON
OFF
MB91F524KWBPMC1
MB91F525KHBPMC1
ON
OFF
MB91F525KJBPMC1
MB91F525KSBPMC1
ON
OFF
MB91F525KWBPMC1
MB91F526KHBPMC1
ON
OFF
MB91F526KJBPMC1
MB91F526KSBPMC1
Package*2
ON
OFF
OFF
ON
OFF
Page 198 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526JWBPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526JYBPMC
OFF
MB91F526JLBPMC
ON
MB91F525JYBPMC
OFF
MB91F525JLBPMC
ON
MB91F524JYBPMC
OFF
MB91F524JLBPMC
ON
MB91F523JYBPMC
MB91F523JJBPMC
OFF
ON
MB91F522JYBPMC
OFF
MB91F522JLBPMC
None
ON
OFF
LQM・120 pin,
Plastic
ON
OFF
ON
MB91F525JUBPMC
ON
OFF
OFF
MB91F525JKBPMC
ON
OFF
ON
MB91F524JUBPMC
ON
OFF
OFF
MB91F524JKBPMC
ON
OFF
ON
MB91F523JUBPMC
ON
OFF
OFF
MB91F523JKBPMC
ON
OFF
ON
MB91F522JUBPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526JKBPMC
MB91F522JKBPMC
ON
OFF
MB91F526JUBPMC
MB91F522JHBPMC
ON
OFF
MB91F522JJBPMC
MB91F522JSBPMC
ON
OFF
MB91F522JWBPMC
MB91F523JHBPMC
ON
OFF
MB91F523JLBPMC
MB91F523JSBPMC
ON
OFF
MB91F523JWBPMC
MB91F524JHBPMC
ON
OFF
MB91F524JJBPMC
MB91F524JSBPMC
ON
OFF
MB91F524JWBPMC
MB91F525JHBPMC
ON
OFF
MB91F525JJBPMC
MB91F525JSBPMC
ON
OFF
MB91F525JWBPMC
MB91F526JHBPMC
ON
OFF
MB91F526JJBPMC
MB91F526JSBPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 199 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526FWBPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526FYBPMC
OFF
MB91F526FLBPMC
ON
MB91F525FYBPMC
OFF
MB91F525FLBPMC
ON
MB91F524FYBPMC
OFF
MB91F524FLBPMC
ON
MB91F523FYBPMC
MB91F523FJBPMC
OFF
ON
MB91F522FYBPMC
OFF
MB91F522FLBPMC
None
ON
OFF
LQI・100 pin,
Plastic
ON
OFF
ON
MB91F525FUBPMC
ON
OFF
OFF
MB91F525FKBPMC
ON
OFF
ON
MB91F524FUBPMC
ON
OFF
OFF
MB91F524FKBPMC
ON
OFF
ON
MB91F523FUBPMC
ON
OFF
OFF
MB91F523FKBPMC
ON
OFF
ON
MB91F522FUBPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526FKBPMC
MB91F522FKBPMC
ON
OFF
MB91F526FUBPMC
MB91F522FHBPMC
ON
OFF
MB91F522FJBPMC
MB91F522FSBPMC
ON
OFF
MB91F522FWBPMC
MB91F523FHBPMC
ON
OFF
MB91F523FLBPMC
MB91F523FSBPMC
ON
OFF
MB91F523FWBPMC
MB91F524FHBPMC
ON
OFF
MB91F524FJBPMC
MB91F524FSBPMC
ON
OFF
MB91F524FWBPMC
MB91F525FHBPMC
ON
OFF
MB91F525FJBPMC
MB91F525FSBPMC
ON
OFF
MB91F525FWBPMC
MB91F526FHBPMC
ON
OFF
MB91F526FJBPMC
MB91F526FSBPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 200 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526DWBPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526DYBPMC
OFF
MB91F526DLBPMC
ON
MB91F525DYBPMC
OFF
MB91F525DLBPMC
ON
MB91F524DYBPMC
OFF
MB91F524DLBPMC
ON
MB91F523DYBPMC
MB91F523DJBPMC
OFF
ON
MB91F522DYBPMC
OFF
MB91F522DLBPMC
None
ON
OFF
LQH・80 pin,
Plastic
ON
OFF
ON
MB91F525DUBPMC
ON
OFF
OFF
MB91F525DKBPMC
ON
OFF
ON
MB91F524DUBPMC
ON
OFF
OFF
MB91F524DKBPMC
ON
OFF
ON
MB91F523DUBPMC
ON
OFF
OFF
MB91F523DKBPMC
ON
OFF
ON
MB91F522DUBPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526DKBPMC
MB91F522DKBPMC
ON
OFF
MB91F526DUBPMC
MB91F522DHBPMC
ON
OFF
MB91F522DJBPMC
MB91F522DSBPMC
ON
OFF
MB91F522DWBPMC
MB91F523DHBPMC
ON
OFF
MB91F523DLBPMC
MB91F523DSBPMC
ON
OFF
MB91F523DWBPMC
MB91F524DHBPMC
ON
OFF
MB91F524DJBPMC
MB91F524DSBPMC
ON
OFF
MB91F524DWBPMC
MB91F525DHBPMC
ON
OFF
MB91F525DJBPMC
MB91F525DSBPMC
ON
OFF
MB91F525DWBPMC
MB91F526DHBPMC
ON
OFF
MB91F526DJBPMC
MB91F526DSBPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 201 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526BWBPMC1
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526BYBPMC1
OFF
MB91F526BLBPMC1
ON
MB91F525BYBPMC1
OFF
MB91F525BLBPMC1
ON
MB91F524BYBPMC1
OFF
MB91F524BLBPMC1
ON
MB91F523BYBPMC1
MB91F523BJBPMC1
OFF
ON
MB91F522BYBPMC1
OFF
MB91F522BLBPMC1
None
ON
ON
LQD・64 pin,
Plastic
OFF
OFF
MB91F526BKBPMC1
ON
OFF
ON
MB91F525BUBPMC1
ON
OFF
OFF
MB91F525BKBPMC1
ON
OFF
ON
MB91F524BUBPMC1
ON
OFF
OFF
MB91F524BKBPMC1
ON
OFF
ON
MB91F523BUBPMC1
ON
OFF
OFF
MB91F523BKBPMC1
ON
OFF
ON
MB91F522BUBPMC1
MB91F522BKBPMC1
ON
OFF
MB91F526BUBPMC1
MB91F522BHBPMC1
ON
OFF
MB91F522BJBPMC1
MB91F522BSBPMC1
ON
OFF
MB91F522BWBPMC1
MB91F523BHBPMC1
ON
OFF
MB91F523BLBPMC1
MB91F523BSBPMC1
ON
OFF
MB91F523BWBPMC1
MB91F524BHBPMC1
ON
OFF
MB91F524BJBPMC1
MB91F524BSBPMC1
ON
OFF
MB91F524BWBPMC1
MB91F525BHBPMC1
ON
OFF
MB91F525BJBPMC1
MB91F525BSBPMC1
ON
OFF
MB91F525BWBPMC1
MB91F526BHBPMC1
ON
OFF
MB91F526BJBPMC1
MB91F526BSBPMC1
Package*2
ON
OFF
OFF
ON
OFF
*1: It is only supported for customers who have already adopted it now. We do not recommend adopting new products.
*2: For details of the package, see Package Dimensions.
Document Number: 002-04662 Rev. *F
Page 202 of 280
MB91520 Series
14. Ordering Information MB91F52xxxC*1
Part Number
Sub Clock
MB91F526LWCPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526LYCPMC
OFF
MB91F526LLCPMC
ON
MB91F525LYCPMC
MB91F525LJCPMC
OFF
ON
MB91F524LYCPMC
MB91F524LJCPMC
OFF
ON
MB91F523LYCPMC
OFF
MB91F523LLCPMC
ON
MB91F522LYCPMC
OFF
MB91F522LLCPMC
ON
OFF
LQP・176 pin,
Plastic
ON
OFF
ON
MB91F525LUCPMC
ON
OFF
OFF
MB91F525LKCPMC
ON
OFF
ON
MB91F524LUCPMC
ON
OFF
OFF
MB91F524LKCPMC
ON
OFF
ON
MB91F523LUCPMC
ON
OFF
OFF
MB91F523LKCPMC
ON
OFF
ON
MB91F522LUCPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526LKCPMC
MB91F522LKCPMC
ON
OFF
None
MB91F526LUCPMC
MB91F522LHCPMC
ON
OFF
MB91F522LJCPMC
MB91F522LSCPMC
ON
OFF
MB91F522LWCPMC
MB91F523LHCPMC
ON
OFF
MB91F523LJCPMC
MB91F523LSCPMC
ON
OFF
MB91F523LWCPMC
MB91F524LHCPMC
ON
OFF
MB91F524LLCPMC
MB91F524LSCPMC
ON
OFF
MB91F524LWCPMC
MB91F525LHCPMC
ON
OFF
MB91F525LLCPMC
MB91F525LSCPMC
ON
OFF
MB91F525LWCPMC
MB91F526LHCPMC
ON
OFF
MB91F526LJCPMC
MB91F526LSCPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 203 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWCPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526KYCPMC
OFF
MB91F526KLCPMC
ON
MB91F525KYCPMC
OFF
MB91F525KLCPMC
ON
MB91F524KYCPMC
OFF
MB91F524KLCPMC
ON
MB91F523KYCPMC
MB91F523KJCPMC
OFF
ON
MB91F522KYCPMC
OFF
MB91F522KLCPMC
None
ON
OFF
ON
OFF
ON
MB91F525KUCPMC
ON
OFF
OFF
MB91F525KKCPMC
ON
OFF
ON
MB91F524KUCPMC
ON
OFF
OFF
MB91F524KKCPMC
ON
OFF
ON
MB91F523KUCPMC
ON
OFF
OFF
MB91F523KKCPMC
ON
OFF
ON
MB91F522KUCPMC
Document Number: 002-04662 Rev. *F
ON
LQS・144 pin,
(Lead pitch 0.5 mm)
Plastic
OFF
MB91F526KKCPMC
MB91F522KKCPMC
ON
OFF
MB91F526KUCPMC
MB91F522KHCPMC
ON
OFF
MB91F522KJCPMC
MB91F522KSCPMC
ON
OFF
MB91F522KWCPMC
MB91F523KHCPMC
ON
OFF
MB91F523KLCPMC
MB91F523KSCPMC
ON
OFF
MB91F523KWCPMC
MB91F524KHCPMC
ON
OFF
MB91F524KJCPMC
MB91F524KSCPMC
ON
OFF
MB91F524KWCPMC
MB91F525KHCPMC
ON
OFF
MB91F525KJCPMC
MB91F525KSCPMC
ON
OFF
MB91F525KWCPMC
MB91F526KHCPMC
ON
OFF
MB91F526KJCPMC
MB91F526KSCPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 204 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWCPMC1
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526KYCPMC1
OFF
MB91F526KLCPMC1
ON
MB91F525KYCPMC1
OFF
MB91F525KLCPMC1
ON
MB91F524KYCPMC1
OFF
MB91F524KLCPMC1
ON
MB91F523KYCPMC1
MB91F523KJCPMC1
OFF
ON
MB91F522KYCPMC1
OFF
MB91F522KLCPMC1
None
ON
OFF
ON
OFF
ON
MB91F525KUCPMC1
ON
OFF
OFF
MB91F525KKCPMC1
ON
OFF
ON
MB91F524KUCPMC1
ON
OFF
OFF
MB91F524KKCPMC1
ON
OFF
ON
MB91F523KUCPMC1
ON
OFF
OFF
MB91F523KKCPMC1
ON
OFF
ON
MB91F522KUCPMC1
Document Number: 002-04662 Rev. *F
ON
LQN・144 pin,
(Lead pitch 0.4 mm)
Plastic
OFF
MB91F526KKCPMC1
MB91F522KKCPMC1
ON
OFF
MB91F526KUCPMC1
MB91F522KHCPMC1
ON
OFF
MB91F522KJCPMC1
MB91F522KSCPMC1
ON
OFF
MB91F522KWCPMC1
MB91F523KHCPMC1
ON
OFF
MB91F523KLCPMC1
MB91F523KSCPMC1
ON
OFF
MB91F523KWCPMC1
MB91F524KHCPMC1
ON
OFF
MB91F524KJCPMC1
MB91F524KSCPMC1
ON
OFF
MB91F524KWCPMC1
MB91F525KHCPMC1
ON
OFF
MB91F525KJCPMC1
MB91F525KSCPMC1
ON
OFF
MB91F525KWCPMC1
MB91F526KHCPMC1
ON
OFF
MB91F526KJCPMC1
MB91F526KSCPMC1
Package*2
ON
OFF
OFF
ON
OFF
Page 205 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526JWCPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526JYCPMC
OFF
MB91F526JLCPMC
ON
MB91F525JYCPMC
OFF
MB91F525JLCPMC
ON
MB91F524JYCPMC
OFF
MB91F524JLCPMC
ON
MB91F523JYCPMC
MB91F523JJCPMC
OFF
ON
MB91F522JYCPMC
OFF
MB91F522JLCPMC
None
ON
OFF
LQM・120 pin,
Plastic
ON
OFF
ON
MB91F525JUCPMC
ON
OFF
OFF
MB91F525JKCPMC
ON
OFF
ON
MB91F524JUCPMC
ON
OFF
OFF
MB91F524JKCPMC
ON
OFF
ON
MB91F523JUCPMC
ON
OFF
OFF
MB91F523JKCPMC
ON
OFF
ON
MB91F522JUCPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526JKCPMC
MB91F522JKCPMC
ON
OFF
MB91F526JUCPMC
MB91F522JHCPMC
ON
OFF
MB91F522JJCPMC
MB91F522JSCPMC
ON
OFF
MB91F522JWCPMC
MB91F523JHCPMC
ON
OFF
MB91F523JLCPMC
MB91F523JSCPMC
ON
OFF
MB91F523JWCPMC
MB91F524JHCPMC
ON
OFF
MB91F524JJCPMC
MB91F524JSCPMC
ON
OFF
MB91F524JWCPMC
MB91F525JHCPMC
ON
OFF
MB91F525JJCPMC
MB91F525JSCPMC
ON
OFF
MB91F525JWCPMC
MB91F526JHCPMC
ON
OFF
MB91F526JJCPMC
MB91F526JSCPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 206 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526FWCPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526FYCPMC
OFF
MB91F526FLCPMC
ON
MB91F525FYCPMC
OFF
MB91F525FLCPMC
ON
MB91F524FYCPMC
OFF
MB91F524FLCPMC
ON
MB91F523FYCPMC
MB91F523FJCPMC
OFF
ON
MB91F522FYCPMC
OFF
MB91F522FLCPMC
None
ON
OFF
LQI・100 pin,
Plastic
ON
OFF
ON
MB91F525FUCPMC
ON
OFF
OFF
MB91F525FKCPMC
ON
OFF
ON
MB91F524FUCPMC
ON
OFF
OFF
MB91F524FKCPMC
ON
OFF
ON
MB91F523FUCPMC
ON
OFF
OFF
MB91F523FKCPMC
ON
OFF
ON
MB91F522FUCPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526FKCPMC
MB91F522FKCPMC
ON
OFF
MB91F526FUCPMC
MB91F522FHCPMC
ON
OFF
MB91F522FJCPMC
MB91F522FSCPMC
ON
OFF
MB91F522FWCPMC
MB91F523FHCPMC
ON
OFF
MB91F523FLCPMC
MB91F523FSCPMC
ON
OFF
MB91F523FWCPMC
MB91F524FHCPMC
ON
OFF
MB91F524FJCPMC
MB91F524FSCPMC
ON
OFF
MB91F524FWCPMC
MB91F525FHCPMC
ON
OFF
MB91F525FJCPMC
MB91F525FSCPMC
ON
OFF
MB91F525FWCPMC
MB91F526FHCPMC
ON
OFF
MB91F526FJCPMC
MB91F526FSCPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 207 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526DWCPMC
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526DYCPMC
OFF
MB91F526DLCPMC
ON
MB91F525DYCPMC
OFF
MB91F525DLCPMC
ON
MB91F524DYCPMC
OFF
MB91F524DLCPMC
ON
MB91F523DYCPMC
MB91F523DJCPMC
OFF
ON
MB91F522DYCPMC
OFF
MB91F522DLCPMC
None
ON
OFF
LQH・80 pin,
Plastic
ON
OFF
ON
MB91F525DUCPMC
ON
OFF
OFF
MB91F525DKCPMC
ON
OFF
ON
MB91F524DUCPMC
ON
OFF
OFF
MB91F524DKCPMC
ON
OFF
ON
MB91F523DUCPMC
ON
OFF
OFF
MB91F523DKCPMC
ON
OFF
ON
MB91F522DUCPMC
Document Number: 002-04662 Rev. *F
ON
OFF
MB91F526DKCPMC
MB91F522DKCPMC
ON
OFF
MB91F526DUCPMC
MB91F522DHCPMC
ON
OFF
MB91F522DJCPMC
MB91F522DSCPMC
ON
OFF
MB91F522DWCPMC
MB91F523DHCPMC
ON
OFF
MB91F523DLCPMC
MB91F523DSCPMC
ON
OFF
MB91F523DWCPMC
MB91F524DHCPMC
ON
OFF
MB91F524DJCPMC
MB91F524DSCPMC
ON
OFF
MB91F524DWCPMC
MB91F525DHCPMC
ON
OFF
MB91F525DJCPMC
MB91F525DSCPMC
ON
OFF
MB91F525DWCPMC
MB91F526DHCPMC
ON
OFF
MB91F526DJCPMC
MB91F526DSCPMC
Package*2
ON
OFF
OFF
ON
OFF
Page 208 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526BWCPMC1
Yes
CSV Initial Value LVD Initial Value
ON
MB91F526BYCPMC1
OFF
MB91F526BLCPMC1
ON
MB91F525BYCPMC1
OFF
MB91F525BLCPMC1
ON
MB91F524BYCPMC1
OFF
MB91F524BLCPMC1
ON
MB91F523BYCPMC1
MB91F523BJCPMC1
OFF
ON
MB91F522BYCPMC1
OFF
MB91F522BLCPMC1
None
ON
ON
LQD・64 pin,
Plastic
OFF
OFF
MB91F526BKCPMC1
ON
OFF
ON
MB91F525BUCPMC1
ON
OFF
OFF
MB91F525BKCPMC1
ON
OFF
ON
MB91F524BUCPMC1
ON
OFF
OFF
MB91F524BKCPMC1
ON
OFF
ON
MB91F523BUCPMC1
ON
OFF
OFF
MB91F523BKCPMC1
ON
OFF
ON
MB91F522BUCPMC1
MB91F522BKCPMC1
ON
OFF
MB91F526BUCPMC1
MB91F522BHCPMC1
ON
OFF
MB91F522BJCPMC1
MB91F522BSCPMC1
ON
OFF
MB91F522BWCPMC1
MB91F523BHCPMC1
ON
OFF
MB91F523BLCPMC1
MB91F523BSCPMC1
ON
OFF
MB91F523BWCPMC1
MB91F524BHCPMC1
ON
OFF
MB91F524BJCPMC1
MB91F524BSCPMC1
ON
OFF
MB91F524BWCPMC1
MB91F525BHCPMC1
ON
OFF
MB91F525BJCPMC1
MB91F525BSCPMC1
ON
OFF
MB91F525BWCPMC1
MB91F526BHCPMC1
ON
OFF
MB91F526BJCPMC1
MB91F526BSCPMC1
Package*2
ON
OFF
OFF
ON
OFF
*1: It is only supported for customers who have already adopted it now. We do not recommend adopting new products.
*2: For details of the package, see Package Dimensions.
Document Number: 002-04662 Rev. *F
Page 209 of 280
MB91520 Series
15. Ordering Information MB91F52xxxD
Part Number
Sub Clock
MB91F526LWDPMC
MB91F526LJDPMC
MB91F525LWDPMC
MB91F525LJDPMC
MB91F524LWDPMC
MB91F524LJDPMC
MB91F523LWDPMC
MB91F523LJDPMC
MB91F522LWDPMC
MB91F522LJDPMC
Yes
MB91F526LSDPMC
MB91F526LHDPMC
MB91F525LSDPMC
MB91F525LHDPMC
MB91F524LSDPMC
MB91F524LHDPMC
MB91F523LSDPMC
MB91F523LHDPMC
MB91F522LSDPMC
MB91F522LHDPMC
MB91F526KWDPMC
MB91F526KJDPMC
MB91F525KWDPMC
MB91F525KJDPMC
MB91F524KWDPMC
MB91F524KJDPMC
MB91F523KWDPMC
MB91F523KJDPMC
MB91F522KWDPMC
MB91F522KJDPMC
MB91F526KSDPMC
MB91F526KHDPMC
MB91F525KSDPMC
MB91F525KHDPMC
MB91F524KSDPMC
MB91F524KHDPMC
MB91F523KSDPMC
MB91F523KHDPMC
MB91F522KSDPMC
MB91F522KHDPMC
None
Document Number: 002-04662 Rev. *F
Yes
None
CSV Initial Value LVD Initial Value
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQP・176 pin,
Plastic
LQS・144 pin,
(Lead pitch 0.5 mm)
Plastic
Page 210 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWDPMC1
MB91F526KJDPMC1
MB91F525KWDPMC1
MB91F525KJDPMC1
MB91F524KWDPMC1
MB91F524KJDPMC1
MB91F523KWDPMC1
MB91F523KJDPMC1
MB91F522KWDPMC1
MB91F522KJDPMC1
MB91F526KSDPMC1
MB91F526KHDPMC1
MB91F525KSDPMC1
MB91F525KHDPMC1
MB91F524KSDPMC1
MB91F524KHDPMC1
MB91F523KSDPMC1
MB91F523KHDPMC1
MB91F522KSDPMC1
MB91F522KHDPMC1
MB91F526JWDPMC
MB91F526JJDPMC
MB91F525JWDPMC
MB91F525JJDPMC
MB91F524JWDPMC
MB91F524JJDPMC
MB91F523JWDPMC
MB91F523JJDPMC
MB91F522JWDPMC
MB91F522JJDPMC
MB91F526JSDPMC
MB91F526JHDPMC
MB91F525JSDPMC
MB91F525JHDPMC
MB91F524JSDPMC
MB91F524JHDPMC
MB91F523JSDPMC
MB91F523JHDPMC
MB91F522JSDPMC
MB91F522JHDPMC
Yes
Document Number: 002-04662 Rev. *F
None
Yes
None
CSV Initial Value LVD Initial Value
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQN・144 pin,
(Lead pitch 0.4 mm)
Plastic
LQM・120 pin,
Plastic
Page 211 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526FWDPMC
MB91F526FJDPMC
MB91F525FWDPMC
MB91F525FJDPMC
MB91F524FWDPMC
MB91F524FJDPMC
MB91F523FWDPMC
MB91F523FJDPMC
MB91F522FWDPMC
MB91F522FJDPMC
MB91F526FSDPMC
MB91F526FHDPMC
MB91F525FSDPMC
MB91F525FHDPMC
MB91F524FSDPMC
MB91F524FHDPMC
MB91F523FSDPMC
MB91F523FHDPMC
MB91F522FSDPMC
MB91F522FHDPMC
MB91F526DWDPMC
MB91F526DJDPMC
MB91F525DWDPMC
MB91F525DJDPMC
MB91F524DWDPMC
MB91F524DJDPMC
MB91F523DWDPMC
MB91F523DJDPMC
MB91F522DWDPMC
MB91F522DJDPMC
MB91F526DSDPMC
MB91F526DHDPMC
MB91F525DSDPMC
MB91F525DHDPMC
MB91F524DSDPMC
MB91F524DHDPMC
MB91F523DSDPMC
MB91F523DHDPMC
MB91F522DSDPMC
MB91F522DHDPMC
Yes
Document Number: 002-04662 Rev. *F
None
Yes
None
CSV Initial Value LVD Initial Value
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQI・100 pin,
Plastic
LQH・80 pin,
Plastic
Page 212 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526BWDPMC1
MB91F526BJDPMC1
MB91F525BWDPMC1
MB91F525BJDPMC1
MB91F524BWDPMC1
MB91F524BJDPMC1
MB91F523BWDPMC1
MB91F523BJDPMC1
MB91F522BWDPMC1
MB91F522BJDPMC1
MB91F526BSDPMC1
MB91F526BHDPMC1
MB91F525BSDPMC1
MB91F525BHDPMC1
MB91F524BSDPMC1
MB91F524BHDPMC1
MB91F523BSDPMC1
MB91F523BHDPMC1
MB91F522BSDPMC1
MB91F522BHDPMC1
Yes
CSV Initial Value LVD Initial Value
None
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQD・64 pin,
Plastic
*: For details of the package, see Package Dimensions.
Document Number: 002-04662 Rev. *F
Page 213 of 280
MB91520 Series
16. Ordering Information MB91F52xxxE
Part Number
Sub Clock
MB91F526LWEPMC
MB91F526LJEPMC
MB91F525LWEPMC
MB91F525LJEPMC
MB91F524LWEPMC
MB91F524LJEPMC
MB91F523LWEPMC
MB91F523LJEPMC
MB91F522LWEPMC
MB91F522LJEPMC
Yes
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
MB91F526LSEPMC
MB91F526LHEPMC
MB91F526LKEPMC
MB91F525LSEPMC
MB91F525LHEPMC
MB91F524LSEPMC
MB91F524LHEPMC
MB91F523LSEPMC
MB91F523LHEPMC
MB91F522LSEPMC
MB91F522LHEPMC
MB91F526KWEPMC
MB91F526KJEPMC
MB91F525KWEPMC
MB91F525KJEPMC
MB91F524KWEPMC
MB91F524KJEPMC
MB91F523KWEPMC
MB91F523KJEPMC
MB91F522KWEPMC
MB91F522KJEPMC
MB91F526KSEPMC
MB91F526KHEPMC
MB91F525KSEPMC
MB91F525KHEPMC
MB91F524KSEPMC
MB91F524KHEPMC
MB91F523KSEPMC
MB91F523KHEPMC
MB91F522KSEPMC
MB91F522KHEPMC
None
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Document Number: 002-04662 Rev. *F
Yes
None
CSV Initial Value LVD Initial Value
Package*
LQP・176 pin,
Plastic
LQS・144 pin,
(Lead pitch 0.5 mm)
Plastic
Page 214 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526KWEPMC1
MB91F526KJEPMC1
MB91F525KWEPMC1
MB91F525KJEPMC1
MB91F524KWEPMC1
MB91F524KJEPMC1
MB91F523KWEPMC1
MB91F523KJEPMC1
MB91F522KWEPMC1
MB91F522KJEPMC1
MB91F526KSEPMC1
MB91F526KHEPMC1
MB91F525KSEPMC1
MB91F525KHEPMC1
MB91F524KSEPMC1
MB91F524KHEPMC1
MB91F523KSEPMC1
MB91F523KHEPMC1
MB91F522KSEPMC1
MB91F522KHEPMC1
MB91F526JWEPMC
MB91F526JJEPMC
MB91F525JWEPMC
MB91F525JJEPMC
MB91F524JWEPMC
MB91F524JJEPMC
MB91F523JWEPMC
MB91F523JJEPMC
MB91F522JWEPMC
MB91F522JJEPMC
MB91F526JSEPMC
MB91F526JHEPMC
MB91F525JSEPMC
MB91F525JHEPMC
MB91F524JSEPMC
MB91F524JHEPMC
MB91F523JSEPMC
MB91F523JHEPMC
MB91F522JSEPMC
MB91F522JHEPMC
Yes
Document Number: 002-04662 Rev. *F
None
Yes
None
CSV Initial Value LVD Initial Value
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQN・144 pin,
(LeaE pitch 0.4 mm)
Plastic
LQM・120 pin,
Plastic
Page 215 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526FWEPMC
MB91F526FJEPMC
MB91F525FWEPMC
MB91F525FJEPMC
MB91F524FWEPMC
MB91F524FJEPMC
MB91F523FWEPMC
MB91F523FJEPMC
MB91F522FWEPMC
MB91F522FJEPMC
MB91F526FSEPMC
MB91F526FHEPMC
MB91F525FSEPMC
MB91F525FHEPMC
MB91F524FSEPMC
MB91F524FHEPMC
MB91F523FSEPMC
MB91F523FHEPMC
MB91F522FSEPMC
MB91F522FHEPMC
MB91F526DWEPMC
MB91F526DJEPMC
MB91F525DWEPMC
MB91F525DJEPMC
MB91F524DWEPMC
MB91F524DJEPMC
MB91F523DWEPMC
MB91F523DJEPMC
MB91F522DWEPMC
MB91F522DJEPMC
MB91F526DSEPMC
MB91F526DHEPMC
MB91F525DSEPMC
MB91F525DHEPMC
MB91F524DSEPMC
MB91F524DHEPMC
MB91F523DSEPMC
MB91F523DHEPMC
MB91F522DSEPMC
MB91F522DHEPMC
Yes
Document Number: 002-04662 Rev. *F
None
Yes
None
CSV Initial Value LVD Initial Value
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQI・100 pin,
Plastic
LQH・80 pin,
Plastic
Page 216 of 280
MB91520 Series
Part Number
Sub Clock
MB91F526BWEPMC1
MB91F526BJEPMC1
MB91F525BWEPMC1
MB91F525BJEPMC1
MB91F524BWEPMC1
MB91F524BJEPMC1
MB91F523BWEPMC1
MB91F523BJEPMC1
MB91F522BWEPMC1
MB91F522BJEPMC1
MB91F526BSEPMC1
MB91F526BHEPMC1
MB91F525BSEPMC1
MB91F525BHEPMC1
MB91F524BSEPMC1
MB91F524BHEPMC1
MB91F523BSEPMC1
MB91F523BHEPMC1
MB91F522BSEPMC1
MB91F522BHEPMC1
Yes
CSV Initial Value LVD Initial Value
None
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Package*
LQE・64 pin,
Plastic
*: For details of the package, see Package Dimensions.
Document Number: 002-04662 Rev. *F
Page 217 of 280
MB91520 Series
17. Package Dimensions
Document Number: 002-04662 Rev. *F
Page 218 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 219 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 220 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 221 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 222 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 223 of 280
MB91520 Series
Document Number: 002-04662 Rev. *F
Page 224 of 280
MB91520 Series
18. Errata
This section describes the errata for the MB91520 Series. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
MB91F522B/D/F/J/K/L
MB91F523B/D/F/J/K/L
MB91F524B/D/F/J/K/L
MB91F525B/D/F/J/K/L
MB91F526B/D/F/J/K/L
MB91F522/3/4/5/6 Qualification Status
Product Status: Production
Errata Summary
The following table defines the errata applicability to available MB91520 Series devices.
Items
[1]. Power-on Conditions is not enough
in the Datasheet Specification
[2]. Limitation for Watch mode (power
off)
1.
Part Number
MB91F522B/D/F/J/K/L
MB91F523B/D/F/J/K/L
MB91F524B/D/F/J/K/L
MB91F525B/D/F/J/K/L
MB91F526B/D/F/J/K/L
Silicon
Revision
Fix Status
B, C
Will be fixed in production
silicon version D, E
B, C, D, E
-
Power-on Conditions is not enough in the Datasheet Specification
■ Problem Definition
If the Power-On-Reset and Internal Low Voltage Detection are not generated, some port functions will not be available.
■ Parameters Affected
tOFF for Power off time on Power-on Conditions
VCC Power ramp rate on Power-on Conditions
■ Trigger Condition
When the power supply voltage to the MCU has been turned off but has not reached 0 V when the power supply voltage
is turned on again, MCU does not generate an internal power-on-reset signal (Power-On reset or Internal LVD reset).
Then, some port functions will not be available.
If below condition (1) or (2) or (3) is satisfied, Power-On Reset (Initialization-Reset signal) is generated and no problem
occurs.
(1) The VCC voltage is less than 200 mV for 50 ms or longer (t OFF)
(2) VCC Power ramp rate less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached
(3) C-pin voltage is below 60 mV when VCC is turned on again
Document Number: 002-04662 Rev. *F
Page 225 of 280
MB91520 Series
■ Scope of Impact
For the affected parts, when the Power-On Reset and Internal Low Voltage Detection are not generated, the MCU may
set invalid package and sub clock option information. Therefore, the MCU may operate with an invalid pin configuration.
■ Workaround
For the affected parts, it is necessary to satisfy at least one of the Power-On Reset requirements for any Power-On event
as given below:
(1) The VCC voltage is less than 200 mV for 50 ms or longer (tOFF)
(2) VCC Power ramp rate is less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached
(3) C-pin voltage is below 60 mV when VCC is turned on again
If the customer system does not satisfy the condition above-mentioned, Cypress will releases new version D, so Cypress
recommends the version D for MB91F52x. The new version prevents the limitation when an external reset signal is
asserted at pin RSTX anytime the supply voltage (VCC) is turned on.
■ Fix Status
Will be fixed in production silicon version D, E
2.
Limitation for Watch mode (power off)
■ Problem Definition
If the below all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from
watch mode (power off).
■ Trigger Conditions
(1) Using the watch mode (power off)
(2) Interrupt levels that are used as sources for recovering from the watch mode (power off) are ‘16’ to ‘30’, or using
NMIX pin as source for recovering from the watch mode (power off)
(3) The sources for recovering from the watch mode (power off) are generated between PCLK 1 cycle and PMUCLK
3 cycles (*), after CPU state changes to the watch mode (power off)
(*): In case of PCLK = 0.5 MHz and PMUCLK = 32 kHz, it is approx. 2 µs to 100 µs
■ Scope of Impact
If the all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch
mode (power off).
WTCRH, WTCRM, WTCRL
CSELR.SCEN
CMONR.SCRDY
CCRTSELR.CST
CCRTSELR.CSC
Document Number: 002-04662 Rev. *F
Page 226 of 280
MB91520 Series
■ Workaround
It is necessary to satisfy the below both conditions of (1) and (2).
(1) Interrupt levels that are used as sources for recovering from the watch mode (power off) are ‘31’, before CPU state
changes to the watch mode (power off)
(2) Don’t use NMIX pin as source for recovering from the watch mode (power off)
■ Fix Status
Will not be planned
Document Number: 002-04662 Rev. *F
Page 227 of 280
MB91520 Series
19. Major Changes
Spansion Publication Number: MB91F526L_DS705-00011
Page
Section
Revision 1.0
Revision 2.0
-
3
■FEATURES
33 to 36
■I/O CIRCUIT TYPE
44 to 49
■BLOCK DIAGRAM
138
■ELECTRICAL
CHARACTERISTICS
2. Recommended operating
conditions
139,140
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
139
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
140,141
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
141
141
141
141
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
■ELECTRICAL
CHARACTERISTICS
3.DC characteristics
Document Number: 002-04662 Rev. *F
Change Results
Initial release
Corrected the following description.
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 Automotive input
↓
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input
Corrected the following description to "Type F, G, I, J, K, M".
Schmitt input → CMOS hysteresis input
Corrected the following description to "Type D, E".
I2C Schmitt input → I2C hysteresis input
Corrected the following description.
●MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
●MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
●MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
●MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
●MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
●MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
Added the following description.
*1：When it is used outside recommended operation guarantee range (range of
the operation guarantee),contact your sales representative. Moreover,
minimum value with an effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection reset
Corrected the value of "ICCT5 When using sub clock 32kHz TA=+25°C
". Max 1420µA → Max 2000µA
Corrected the value of "Power supply voltage range".
(TA:-40°C to +105°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +105°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of "Power supply voltage range".
(TA:-40°C to +125°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +125°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of " Pull-up resistance RUP1".
Vcc=3.3V±0.3V Min 49 Max 140 →Min 45 Max 140
Corrected the following description.
Pull-up resistance RUP2
Port pin other than P035,041,093,122 → P073,074,076,077
Corrected the value of " Pull-up resistance RUP2".
VCC=5.0V±10% Min 25 Max 100 →Min 25 Max 60
VCC=3.3V±0.3V Min 49 Max 140 →Min 33 Max 90
Added the value of " Pull-up resistance RUP3".
Pin name : Port pin other than P035,041,073,074,076,077,093,122
VCC=5.0V±10% Min 25 Max 100
VCC=3.3V±0.3V Min 45 Max 140
Page 228 of 280
MB91520 Series
Page
Section
150,152,
154,156
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
150,152,
154,156
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
150,152,
154,156
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
150,152,
154,156
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
Document Number: 002-04662 Rev. *F
Change Results
(4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVI
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVI
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min -30 Max 30
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min -30 Max 30
Pin name: SCK3,SCK4
SOT3,SOT4
Value: Min -300 Max 300
(4-1-1),(4-1-4)Valid SIN⇒SCK↑ setup time tIVSHI
(4-1-2),(4-1-3)Valid SIN⇒SCK↓ setup time tIVSLI
Corrected the following description.
Pin name: SCK0 to SCK11 SIN0 to SIN11
Value: Min 34 Max ↓
Pin name: SCK0 to SCK2,SCK5 to SCK11 SIN0 to SIN2,SIN5 to SIN11
Value: Min 34 Max Pin name: SCK3,SCK4,SIN3,SIN4
Value: Min 300 Max (4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVE
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVE
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min - Max 33
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min - Max 33
Pin name: SCK3,SCK4 SOT3,SOT4
Value: Min - Max 300
(4-1-1),(4-1-2),(4-1-3),(4-1-4)SCK fall time tF
Corrected the following description.
Pin name: SCK0 to SCK2,SCK5 to SCK11
Value: Min - Max 5
Pin name: SCK3,SCK4
Value: Min - Max 250
↓
Pin name: SCK0 to SCK11
Value: Min - Max 5
Page 229 of 280
MB91520 Series
Page
Section
158,161,
164,167
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
158,161,
164,167
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
158,161,
164,167
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
Document Number: 002-04662 Rev. *F
Change Results
(4-1-5)SCS↓⇒SCK↓ setup time tCSSI
(4-1-6)SCS↓⇒SCK↑ setup time tCSSI
(4-1-7)SCS↑⇒SCK↓ setup time tCSSI
(4-1-8)SCS↑⇒SCK↑ setup time tCSSI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSSU+0 Max tCSSU+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min tCSSU-50 Max tCSSU+0
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSSU-50 Max tCSSU+300
(4-1-5)SCK↑⇒SCS↑hold time tCSHI
(4-1-6)SCK↓⇒SCS↑hold time tCSHI
(4-1-7)SCK↑⇒SCS↓hold time tCSHI
(4-1-8)SCK↓⇒SCS↓hold time tCSHI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSHD-50 Max tCSHD+0
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min tCSHD-10 Max tCSHD+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSHD-300 Max tCSHD+50
(4-1-5),(4-1-6)SCS↓⇒SOT delay time tDSE
(4-1-7),(4-1-8)SCS↑⇒SOT delay time tDSE
Corrected the following description.
Pin name: SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,SCS8 to SCS11
SOT1 to SOT11
Value: Min - Max 40
↓
Pin name: SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,
SCS8 to SCS11
SOT1,SOT2,SOT5 to SOT11
Value: Min - Max 40
Pin name: SCS3,SCS40 to SCS43
SOT3,SOT4
Value: Min - Max 300
Page 230 of 280
MB91520 Series
Page
159,162,
165,168
159,162,
165,168
184
184
184
184
188
187
Section
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
■ELECTRICAL
CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
■ELECTRICAL
CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter
Electrical Characteristics
■ELECTRICAL
CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter
Electrical Characteristics
■ELECTRICAL
CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter
Electrical Characteristics
■ELECTRICAL
CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter
Electrical Characteristics
■ELECTRICAL
CHARACTERISTICS
7.D/A Converter
■ELECTRICAL
CHARACTERISTICS
6.Flash memory
Document Number: 002-04662 Rev. *F
Change Results
(4-1-5)SCK↓⇒SCS↓ clock switch time tSCC
(4-1-6)SCK↑⇒SCS↓ clock switch time tSCC
(4-1-7)SCK↓⇒SCS↑ clock switch time tSCC
(4-1-8)SCK↑⇒SCS↑ clock switch time tSCC
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min 3tCPP+0 Max 3tCPP+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min 3tCPP-10 Max 3tCPP+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min 3tCPP-300 Max 3tCPP+50
Added the following description.
Regardless of the deselect time setting, once after the serial chip select pin
becomes inactive, it will take at least five peripheral bus clock cycles to be active
again
Added the value of "Total error".
Total error value Min – Typ –
Max ±12 LSB
Corrected the value of "Zero transition voltage".
Min AVRL+0.5LSB-20mV Max AVRL+0.5LSB+20mV
↓
Min AVRL-11.5LSB Max AVRL+12.5LSB
Corrected the value of "Full-scale transition voltage".
Min AVRH-1.5LSB-20mV Max AVRH-1.5LSB+20mV
↓
Min AVRH-13.5LSB Max AVRH+10.5LSB
Added the following description.
Parameter : Power supply current IA AVCC*3
*3: The power supply current described only current value on A/D converter. The
total AVcc current value must be calculated the power supply current for A/D
converter and D/A converter.
Added the following description.
Parameter : Power supply current *1
*1: The power supply current described only current value on D/A converter.The
total Avcc current value must be calculated the power supply current for D/A
converter and A/D converter.
Parameter: Erase cycle*2/Data retain time
Deleted the following description.
Remarks :
"Temperature at writing/erasing Tj<+105°C"
Page 231 of 280
MB91520 Series
Page
Section
188
■ELECTRICAL
CHARACTERISTICS
7.D/A Converter
190
■EXAMPLE
CHARACTERISTICS
192
■ORDERING INFORMATION
198
■ORDERING INFORMATION
198
■ORDERING INFORMATION
199 to
205
-
■ORDERING INFORMATION
-
Document Number: 002-04662 Rev. *F
Change Results
Corrected the following description.
Parameter : Power supply current
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
↓
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
Corrected the following description.
Watch mode
Corrected the following description.
■ORDERING INFORMATION
↓
■ORDERING INFORMATION MB91F52xxxB*1
Package
↓
Package*2
Added the following description.
*1: It is only supported for customers who have already adopted it now. We do
not recommend adopting new products.
Corrected the following description.
For details of the package, see "■ PACKAGE DIMENSIONS ".
↓
*2: For details of the package, see "■ PACKAGE DIMENSIONS ".
Added the following description.
■ORDERING INFORMATION MB91F52xxxC
Company name and layout design change
Page 232 of 280
MB91520 Series
Page
Section
Change Results
Cypress Document Number: 002-04662
Rev *B
1
■Features
2
■Features
6
■Product Lineup
Corrected the following description.
∙ Clock generation (equipped with SSCG function)
∙ Main oscillation (4MHz to 16MHz)
∙ Sub oscillation (32kHz to 100kHz) or none sub oscillation
∙ PLL multiplication rate : 1 to 20 times
↓
∙ Clock generation (equipped with SSCG function)
∙ Main oscillation (4MHz to 16MHz)
∙ Sub oscillation (32kHz) or no sub oscillation
∙ PLL multiplication rate : 1 to 20 times
∙ Equipped with a 100kHz CR oscillator
Corrected the following description.
∙ Base timer : Max. 2 channels
∙16-bit timer
∙ Any of four PWM/PPG/PWC/reload timer functions can be selected and used
∙ A 32-bit timer can be used in 2 channels of cascade mode
↓
∙ Base timer : Max. 2 channels
∙ 16-bit timer
∙ Any of four PWM/PPG/PWC/reload timer functions can be selected and used
∙ As for the PWC function and the reload timer function, a pair of 16-bit timers
can be used as one 32-bit timer in the cascaded mode
Corrected the following description for Product lineup comparison(64 pin).
Multi-Function
Serial Interface
↓
Multi-Function
Serial Interface
6
■Product Lineup
7
■Product Lineup
7
■Product Lineup
8
■Product Lineup
8
■Product Lineup
Document Number: 002-04662 Rev. *F
8ch
8ch*1
Added the following sentences under Product lineup comparison(64 pin)
*1: Only channel 5, channel 6 and channel 11 support the I 2C (standard mode).
Corrected the following description for Product lineup comparison(80 pin).
Multi-Function
9ch
Serial Interface
↓
Multi-Function
9ch*1
Serial Interface
Added the following sentences under Product lineup comparison(80 pin)
*1: Only channel 5, channel 6 and channel 11 support the I 2C (standard mode).
Corrected the following description for Product lineup comparison(100 pin).
Multi-Function
12ch
Serial Interface
↓
Multi-Function
12ch*1
Serial Interface
Added the following sentences under Product lineup comparison(100 pin)
*1: Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the
I2C (standard mode).
Page 233 of 280
MB91520 Series
Page
Section
9
■Product Lineup
9
■Product Lineup
10
■Product Lineup
10
■Product Lineup
11
■Product Lineup
11
■Product Lineup
Document Number: 002-04662 Rev. *F
Change Results
Corrected the following description for Product lineup comparison(120 pin).
Multi-Function
12ch
Serial Interface
↓
Multi-Function
12ch*1
Serial Interface
Added the following sentences under Product lineup comparison(120 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed mode/standard
mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the
I2C (standard mode).
Corrected the following description for Product lineup comparison(144 pin).
Multi-Function
12ch
Serial Interface
↓
Multi-Function
12ch*1
Serial Interface
Added the following sentences under Product lineup comparison(144 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed mode/standard
mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11
support the I2C (standard mode).
Corrected the following description for Product lineup comparison(176 pin).
Multi-Function
12ch
Serial Interface
↓
Multi-Function
12ch*1
Serial Interface
Added the following sentences under Product lineup comparison(176 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed mode/standard
mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11
support the I2C (standard mode).
Page 234 of 280
MB91520 Series
Page
Section
Change Results
Signals indicated by the shading below deleted in Figure.
- Left side
13
■Pin Assignment MB91F52xB
Document Number: 002-04662 Rev. *F
↓
VSS
1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
2
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
3
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
4
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
5
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
6
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
7
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
8
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0
9
P036/OCU7_1/TOT5_0/BIN0_0
10
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
11
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
12
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
13
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
14
P047/AN45/TRG8_0/TIN3_2/SOT0_1
15
P053/AN44/PPG35_0/INT14_1/SCK0_1
16
Page 235 of 280
MB91520 Series
Page
Section
Change Results
- Right side
13
■Pin Assignment MB91F52xB
Document Number: 002-04662 Rev. *F
↓
48
P122/SIN6_0/AN31/OCU8_0/INT9_1
47
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
46
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
45
P110/TX1(64)/SCS63_0/AN22
44
NM IX
43
P105/AN17/PPG13_0
42
P104/AN16/PPG12_0
41
P103/AN15/PPG11_0
40
P102/AN14/PPG10_0/INT10_0
39
AVCC0
38
AVRH0
37
AVS S 0/AVRL0
36
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
35
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
34
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
33
VSS
Page 236 of 280
MB91520 Series
Page
Section
Change Results
- Top
13
■Pin Assignment MB91F52xB
13
■Pin Assignment MB91F52xB
Document Number: 002-04662 Rev. *F
MD1
MD0
P126/SIN0_0/INT6_0
DEBUGIF
52
51
50
49
X1
X0
54
53
X1A/P135/DTTI_0
VSS
56
55
RSTX
X0A/P136
58
57
C
VSS
60
59
P006/ADTG1_1/INT2_1/TX2(64)
P005/ADTG0_1/INT7_1/RX2(64)
62
61
VCC
P011/WOT/INT3_1
64
63
↓
The following note added on the bottom left of Figure.
* In a single clock product, pin 56 and pin 57 are the general-purpose ports.
Page 237 of 280
MB91520 Series
Page
Section
Change Results
Signals indicated by the shading below deleted in Figure.
- Left side
14
■Pin Assignment MB91F52xD
Document Number: 002-04662 Rev. *F
↓
VSS
1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1
2
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
3
P026/SCK4_1/PPG26_0/TIN3_0
4
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1
5
P031/SCS42_1/PPG29_0
6
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1
7
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
8
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
9
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
10
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0
11
P036/OCU7_1/TOT5_0/BIN0_0
12
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1
13
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0
14
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
15
P044/SCS9_0/ICU6_1/TRG2_1
16
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
17
P047/AN45/TRG8_0/TIN3_2/SOT0_1
18
P053/AN44/PPG35_0/INT14_1/SCK0_1
19
VCC
20
Page 238 of 280
MB91520 Series
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
Page 239 of 280
Document Number: 002-04662 Rev. *F
↓
■Pin Assignment MB91F52xD
14
Change Results
Section
Page
- Bottom
MB91520 Series
Page
Section
Change Results
- Right side
14
■Pin Assignment MB91F52xD
↓
Document Number: 002-04662 Rev. *F
60
VSS
59
P122/SIN6_0/AN31/OCU8_0/INT9_1
58
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
57
P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
56
P114/SCS61_0/AN26/PPG18_0/RTO2_0
55
P110/TX1(64)/SCS63_0/AN22
54
NM IX
53
P107/AN19/PPG15_0
52
P105/AN17/PPG13_0
51
P104/AN16/PPG12_0
50
P103/AN15/PPG11_0
49
P102/AN14/PPG10_0/INT10_0
48
P100/AN12/PPG8_0
47
AVCC0
46
AVRH0
45
AVS S 0/AVRL0
44
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
43
P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
42
P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
41
VSS
Page 240 of 280
MB91520 Series
Page
Section
Change Results
- Top
Document Number: 002-04662 Rev. *F
P127/SOT0_0
P126/SIN0_0/INT6_0
DEBUGIF
VCC
64
63
62
61
MD1
MD0
66
65
X1
X0
68
67
X1A/P135/DTTI_0
VSS
70
69
RSTX
X0A/P136
72
71
C
VSS
74
73
P003/SIN2_0/TIOB1_1/INT3_0
P001/TIOA1_1
76
75
P006/SCS2_0/ADTG1_1/INT2_1/TX2(64)
P005/SCK2_0/ADTG0_1/INT7_1/RX2(64)
78
77
VCC
■Pin Assignment MB91F52xD
P011/WOT/SOT2_1/INT3_1
14
↓
80
■Pin Assignment MB91F52xD
79
14
The following note added on the bottom left of Figure.
* In a single clock product, pin 71 and pin 72 are the general-purpose ports.
Page 241 of 280
MB91520 Series
50 VCC
49 P087/DAO0/PPG7_0/INT8_0
48 P086/DAO1/PPG6_0
47 P082/SIN5_0/AN1/PPG2_0
46 P081/SOT5_0/SDA5/AN0/PPG1_0
45 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
44 P152/SCS53_0
43 P073/AN33/ICU3_2
42 P072/SIN4_0/AN34/ICU2_2/INT5_0
41 P071/SCK4_2/AN35/ICU1_2/MONCLK
40 P070/ICU0_2
39 P067/AN36/FRCK5_0/AIN0_1
38 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
37 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
36 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
35 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
34 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
33 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
32 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
31 AVSS1/AVRL1
30 AVRH1
29 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
28 AVCC1
27 P055/SIN10_0/AN43/PPG37_0/TIN4_1
26 VSS
Page 242 of 280
Document Number: 002-04662 Rev. *F
↓
■Pin Assignment MB91F52xF
15
Change Results
Section
Page
Signals indicated by the shading below deleted in Figure.
(Error)
- Bottom
MB91520 Series
Page
Section
Change Results
- Top
19 to 35
■PIN Description
Document Number: 002-04662 Rev. *F
77 DEBUGIF
76 VCC
79 P127/SOT0_0
78 P126/SIN0_0/INT6_0
81 MD0
80 P130/SCK0_0
83 X0
82 MD1
85 VSS
84 X1
87 X0A/P136
86 X1A/P135/DTTI_0
89 P133/TX2(64)
88 RSTX
91 P144/SCK1_1
90 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
■Pin Assignment MB91F52xL
93 C
18
92 VSS
■Pin Assignment MB91F52xK
95 P001/SOT1_0/TIOA1_1
17
94 P000/SIN1_0/INT2_0
■Pin Assignment MB91F52xJ
97 P005/SCK2_0/ADTG0_1/INT7_1
16
96 P003/SIN2_0/TIOB1_1/INT3_0
■Pin Assignment MB91F52xF
99 P011/WOT/SOT2_1/INT3_1
15
↓
98 P006/SCS2_0/ADTG1_1/INT2_1
■Pin Assignment MB91F52xF
100 VCC
15
The following note added on the bottom left of Figure.
* In a single clock product, pin 86 and pin 87 are the general-purpose ports.
The following note added on the bottom left of Figure.
* In a single clock product, pin 102 and pin 103 are the general-purpose ports.
The following note added on the bottom left of Figure.
* In a single clock product, pin 121 and pin 122 are the general-purpose ports.
The following note added on the bottom left of Figure.
* In a single clock product, pin 149 and pin 150 are the general-purpose ports.
A List of "Pin Description" modified.
I/O
Circuit
types*1
↓
I/O
Circuit
types*8
Function*2
Function*9
Page 243 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
19
Pin no.
100 120
64
80
144
176
-
-
-
-
2
2
-
-
-
-
3
3
-
-
-
-
-
4
-
-
-
-
4
5
-
-
-
-
-
6
2
2
2
2
5
7
-
-
-
3
6
8
-
-
-
4
7
9
-
-
-
5
8
10
3
3
3
6
9
11
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P015
D29
TRG0_0
P016
D30
TRG1_0
P170
PPG36_1
P017
D31
TRG2_0
P171
PPG37_1
P020
ASX
SIN3_1
TRG3_0
TIN0_2
RTO5_1
P021
CS0X
SOT3_1
TRG6_1
TRG4_0
P022
CS1X
SCK3_1
TRG7_1
TRG5_0
P023
RDX
SCS3_1
PPG32_0
TIN0_0
P024
WR0X
SIN4_1
PPG24_0
TIN1_0
RTO4_1
INT15_0
Page 244 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
19
Pin no.
100 120
64
80
144
176
-
-
-
-
2
2
-
-
-
-
3
3
-
-
-
-
-
4
-
-
-
-
4
5
-
-
-
-
-
6
2 *1
2 *1
2 *1
2 *1
5
7
-
-
-
3 *1
6
8
-
-
-
4 *1
7
9
-
-
-
5 *1
8
10
■PIN Description
Pin
Name
P015
D29
TRG0_0
P016
D30
TRG1_0
P170
PPG36_1
P017
D31
TRG2_0
P171
PPG37_1
P020
ASX *2, *3, *4, *5
SIN3_1
TRG3_0
TIN0_2
RTO5_1
P021
CS0X *5
SOT3_1
TRG6_1
TRG4_0
P022
CS1X *5
SCK3_1
TRG7_1
TRG5_0
P023
RDX *5
SCS3_1
PPG32_0
TIN0_0
P024
WR0X *2, *3, *4,
*5
3 *1
Document Number: 002-04662 Rev. *F
3 *1
3 *1
6 *1
9
11
SIN4_1
PPG24_0
TIN1_0
RTO4_1
INT15_0
Page 245 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
20
■PIN Description
Document Number: 002-04662 Rev. *F
Pin no.
100 120
64
80
144
176
-
-
4
7
10
12
-
-
-
-
-
13
-
4
5
8
11
14
4
5
6
9
12
15
-
-
-
-
-
16
-
-
7
10
13
17
-
6
8
11
14
18
5
7
9
12
15
19
6
8
10
13
16
20
Pin
Name
P025
WR1X
SOT4_1
PPG25_0
TIN2_0
P172
PPG38_1
P026
A00
SCK4_1
PPG26_0
TIN3_0
P027
A01
SCS40_1
PPG27_0
TOT0_0
RTO3_1
P173
PPG39_1
P030
A02
SCS41_1
PPG28_0
TOT1_0
P031
A03
SCS42_1
PPG29_0
TOT2_0
P032
A04
SCS43_1
PPG30_0
TOT3_0
RTO2_1
P033
A05
PPG31_0
ICU3_3
TIN4_0
RTO1_1
SCK3_2
Page 246 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
20
■PIN Description
Document Number: 002-04662 Rev. *F
Pin no.
100 120
144
176
-
4 *1
7 *1
10
12
-
-
-
-
-
13
-
4 *1
5 *1
8 *1
11
14
4 *1
5 *1
6 *1
9 *1
12
15
-
-
-
-
-
16
-
-
7 *1
10 *1
13
17
-
6 *1
8 *1
11 *1
14
18
5 *1
7 *1
9 *1
12 *1
15
19
6 *1
8 *1
10 *1
13 *1
16
20
64
80
-
Pin
Name
P025
WR1X *4, *5
SOT4_1
PPG25_0
TIN2_0
P172
PPG38_1
P026
A00 *3, *4, *5
SCK4_1
PPG26_0
TIN3_0
P027
A01 *2, *3, *4, *5
SCS40_1
PPG27_0
TOT0_0
RTO3_1
P173
PPG39_1
P030
A02 *4, *5
SCS41_1
PPG28_0
TOT1_0
P031
A03 *3, *4, *5
SCS42_1
PPG29_0
TOT2_0 *3
P032
A04 *2, *3, *4, *5
SCS43_1
PPG30_0
TOT3_0
RTO2_1
P033
A05 *2, *3, *4, *5
PPG31_0
ICU3_3
TIN4_0
RTO1_1
SCK3_2
Page 247 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
21, 22
64
80
7
9
Pin no.
100 120
11
14
144
176
17
21
8
10
13
16
19
23
9
11
14
17
20
24
10
12
15
18
21
25
-
-
16
19
22
26
-
-
-
-
-
27
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P034
A06
OCU11_1
ICU2_3
TIN5_0
RTO0_1
SOT3_2
P151
SCK8_0/
SCL8
OCU9_1
TRG7_0
ICU0_3
TIN7_0
ZIN0_2
DTTI_1
P035
A07
SIN8_0
OCU8_1
TOT4_0
AIN0_0
INT11_0
P036
A08
SCS8_0
OCU7_1
TOT5_0
BIN0_0
P037
A09
OCU6_1
TOT6_0
ZIN0_0
P174
TRG8_1
Page 248 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
21, 22
64
80
Pin no.
100 120
144
176
7 *1
9 *1
11 *1
17
21
14 *1
8 *1
10 *1
13
16
19
23
9 *1
11 *1
14 *1
17 *1
20
24
10 *1
12 *1
15 *1
18 *1
21
25
-
-
16 *1
19 *1
22
26
-
-
-
-
-
27
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P034
A06 *2, *3, *4, *5
OCU11_1
ICU2_3
TIN5_0
RTO0_1
SOT3_2
P151
SCK8_0/
SCL8 *2, *3
OCU9_1
TRG7_0
ICU0_3
TIN7_0
ZIN0_2
DTTI_1
P035
A07 *2, *3, *4, *5
SIN8_0 *2, *3
OCU8_1
TOT4_0
AIN0_0
INT11_0
P036
A08 *2, *3, *4, *5
SCS8_0 *2, *3
OCU7_1
TOT5_0
BIN0_0
P037
A09 *4, *5
OCU6_1
TOT6_0
ZIN0_0
P174
TRG8_1
Page 249 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
22, 23
Pin no.
100 120
64
80
144
176
-
-
-
-
-
28
11
13
17
20
23
29
12
14
18
21
24
30
13
15
19
22
25
31
-
-
20
23
26
32
-
16
21
24
27
33
14
17
22
25
28
34
-
-
-
26
29
35
-
-
-
-
-
36
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P175
TRG9_1
P040
A10
PPG23_1
TOT7_0
AIN1_0
SIN0_1
P041
A11
SIN9_0
ICU9_1
BIN1_0
INT12_0
P042
A12
SOT9_0
AN47
ICU8_1
TRG0_1
ZIN1_0
P043
A13
ICU7_1
TRG1_1
P044
A14
SCS9_0
ICU6_1
TRG2_1
P045
A15
SCK9_0
AN46
ICU5_1
TRG3_1
TOT1_2
P046
A16
ICU4_1
TRG4_1
P176
TRG10_0
Page 250 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
22, 23
Pin no.
100 120
64
80
144
176
-
-
-
-
-
28
11 *1
13 *1
17 *1
20 *1
23
29
12 *1
14 *1
18 *1
21 *1
24
30
13 *1
15 *1
19 *1
22 *1
25
31
-
-
20 *1
23 *1
26
32
-
16 *1
21 *1
24 *1
27
33
14 *1
17 *1
22 *1
25 *1
28
34
-
-
-
26 *1
29
35
-
-
-
-
-
36
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P175
TRG9_1
P040
A10 *2, *3, *4, *5
PPG23_1
TOT7_0
AIN1_0
SIN0_1
P041
A11 *2, *3, *4, *5
SIN9_0
ICU9_1
BIN1_0
INT12_0
P042
A12 *2, *3, *4, *5
SOT9_0
AN47
ICU8_1
TRG0_1
ZIN1_0
P043
A13 *4, *5
ICU7_1
TRG1_1
P044
A14 *3, *4, *5
SCS9_0
ICU6_1
TRG2_1
P045
A15 *2, *3, *4, *5
SCK9_0
AN46
ICU5_1
TRG3_1
TOT1_2
P046
A16 *5
ICU4_1
TRG4_1
P176
TRG10_0
Page 251 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
23, 24
64
80
Pin no.
100 120
144
176
15
18
23
27
30
37
-
-
-
-
-
38
-
-
-
28
31
39
-
-
-
-
32
40
-
-
-
-
33
41
16
19
24
29
34
42
-
-
-
-
35
43
17
22
27
32
38
46
■PIN Description
-
Document Number: 002-04662 Rev. *F
-
-
33
39
49
Pin
Name
P047
A17
AN45
TRG8_0
TIN3_2
SOT0_1
P177
TRG11_0
P050
A18
TRG5_1
PPG33_0
P051
A19
TRG9_0
P052
A20
PPG34_0
INT14_0
P053
A21
AN44
PPG35_0
INT14_1
SCK0_1
P054
SYSCLK
PPG36_0
P055
CS2X
SIN10_0
AN43
PPG37_0
TIN4_1
P056
CS3X
ICU9_0
PPG0_1
ICU0_1
TIN5_1
DTTI_2
Page 252 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
23, 24
Pin no.
100 120
144
176
18 *1
23 *1
27 *1
30
37
-
-
-
-
-
38
-
-
-
28 *1
31
39
-
-
-
-
32
40
-
-
-
-
33
41
16 *1
19 *1
24 *1
29 *1
34
42
-
-
-
-
35
43
17 *1
22 *1
27 *1
32 *1
38
46
64
80
15 *1
■PIN Description
-
Document Number: 002-04662 Rev. *F
-
-
33 *1
39
49
Pin
Name
P047
A17 *2, *3, *4, *5
AN45
TRG8_0
TIN3_2
SOT0_1
P177
TRG11_0
P050
A18 *5
TRG5_1
PPG33_0
P051
A19
TRG9_0
P052
A20
PPG34_0
INT14_0
P053
A21 *2, *3, *4, *5
AN44
PPG35_0
INT14_1
SCK0_1
P054
SYSCLK
PPG36_0
P055
CS2X *2, *3, *4, *5
SIN10_0
AN43
PPG37_0
TIN4_1
P056
CS3X *5
ICU9_0
PPG0_1
ICU0_1
TIN5_1
DTTI_2
Page 253 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
Function*2
24
■PIN Description
General-purpose I/O port
External Bus chip select 2 output pin(0)
Multi-function serial ch.10 serial data input
pin(0)
ADC analog 43 input pin
PPG ch.37 output pin(0)
Reload timer ch.4 event input pin(1)
(Correct)
Function*9
General-purpose I/O port
External Bus chip select 2 output pin
Multi-function serial ch.10 serial data input
pin(0)
ADC analog 43 input pin
PPG ch.37 output pin(0)
Reload timer ch.4 event input pin(1)
Document Number: 002-04662 Rev. *F
Page 254 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
Function*2
24
■PIN Description
General-purpose I/O port
External Bus chip select 3 output pin(0)
Input capture ch.9 input pin(0)
PPG ch.0 output pin(1)
Input capture ch.0 input pin(1)
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input pin(2)
(Correct)
Function*9
General-purpose I/O port
External Bus chip select 3 output pin
Input capture ch.9 input pin(0)
PPG ch.0 output pin(1)
Input capture ch.0 input pin(1)
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input pin(2)
Document Number: 002-04662 Rev. *F
Page 255 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
25
64
80
Pin no.
100 120
144
176
19
24
29
35
41
51
64
80
Pin no.
100 120
144
176
19 *1
24 *1
29 *1
41
51
■PIN Description
Pin
Name
P057
RDY
SCK10_1
AN42
ICU8_0
TRG0_2
PPG1_1
ICU1_1
TIN6_1
(Correct)
35 *1
Pin
Name
P057
RDY *2, *3, *4, *5
SCK10_1
AN42
ICU8_0
TRG0_2
PPG1_1
ICU1_1
TIN6_1
A List of "Pin Description" modified.
(Error)
64
80
27
Pin no.
100 120
144
176
35
43
49
57
71
80
Pin no.
100 120
144
176
■PIN Description
Pin
Name
P073
SOT4_0/
SDA4
AN33
ICU3_2
(Correct)
64
-
Document Number: 002-04662 Rev. *F
35 *3
43 *4
49
57
71
Pin
Name
P073
SOT4_0/
SDA4 *3, *4
AN33
ICU3_2
Page 256 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
64
80
34
29
Pin no.
100 120
144
176
42
52
62
77
96
80
Pin no.
100 120
144
176
■PIN Description
Pin
Name
P093
TX0_1
SIN11_0
AN7
ICU4_2
PPG16_1
ICU3_0
TOT2_1
(Correct)
64
34 *1
Document Number: 002-04662 Rev. *F
42 *1
52
62
77
96
Pin
Name
P093
TX0_1
SIN11_0
AN7
ICU4_2
PPG16_1
ICU3_0
TOT2_1 *2, *3
Page 257 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
30
64
80
Pin no.
100 120
144
176
-
48
59
85
104
69
40
49
61
71
87
106
41
50
62
72
88
107
42
51
63
73
89
108
43
52
64
74
90
109
64
80
Pin no.
100 120
144
176
-
48 *1
59
85
104
■PIN Description
Pin
Name
P100
SCK7_0/
SCL7
AN12
PPG8_0
P102
SIN7_0
AN14
PPG10_0
INT10_0
P103
SCS73_0
AN15
PPG11_0
P104
SCS72_0
AN16
PPG12_0
P105
SCS71_0
AN17
PPG13_0
(Correct)
Document Number: 002-04662 Rev. *F
69
40 *1
49 *1
61
71
87
106
41 *1
50 *1
62
72
88
107
42 *1
51 *1
63
73
89
108
43 *1
52 *1
64
74
90
109
Pin
Name
P100
SCK7_0/
SCL7 *3
AN12
PPG8_0
P102
SIN7_0 *2, *3
AN14
PPG10_0
INT10_0
P103
SCS73_0 *2, *3
AN15
PPG11_0
P104
SCS72_0 *2, *3
AN16
PPG12_0
P105
SCS71_0 *2, *3
AN17
PPG13_0
Page 258 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
64
33
80
Pin no.
100 120
144
176
-
-
94
111
131
159
-
75
95
112
132
160
80
Pin no.
100 120
■PIN Description
Pin
Name
P000
D16
SIN1_0
TIOA0_1
INT2_0
P001
D17
SOT1_0
TIOA1_1
(Correct)
64
Document Number: 002-04662 Rev. *F
-
-
-
75 *1
94 *1
144
176
111 *1
131
159
95 *1 112 *1
132
160
Pin
Name
P000
D16 *4, *5
SIN1_0
TIOA0_1 *4
INT2_0
P001
D17 *3, *4, *5
SOT1_0 *3
TIOA1_1
Page 259 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
34, 35
Pin no.
100 120
64
80
144
176
-
-
-
113
133
161
-
76
96
114
134
162
-
-
-
-
135
163
-
-
-
-
-
164
61
77
97
115
136
165
-
-
-
-
-
166
62
78
98
116
137
167
-
-
-
117
138
168
-
-
-
-
-
169
-
-
-
118
139
170
63
79
99
119
140
171
■PIN Description
Document Number: 002-04662 Rev. *F
Pin
Name
P002
D18
SCK1_0
TIOB0_1
P003
D19
SIN2_0
TIOB1_1
INT3_0
P004
D20
SOT2_0
P164
PPG32_1
P005
D21
SCK2_0
ADTG0_1
INT7_1
(RX2(64))
P165
PPG33_1
P006
D22
SCS2_0
ADTG1_1
INT2_1
(TX2(64))
P007
D23
P166
PPG34_1
P010
D24
P011
WOT
D25
SOT2_1
TIOA0_0
INT3_1
Page 260 of 280
MB91520 Series
Page
Section
Change Results
(Continued)
(Correct)
34, 35
Pin no.
100 120
64
80
144
176
-
-
113 *1
133
161
-
76 *1
96 *1 114 *1
134
162
-
-
-
-
135
163
-
-
-
-
-
164
61 *1
77 *1
-
97 *1 115 *1 136 *1 165 *1
■PIN Description
Pin
Name
P002
D18 *5
SCK1_0
TIOB0_1
P003
D19 *3, *4, *5
SIN2_0
TIOB1_1
INT3_0
P004
D20
SOT2_0
P164
PPG32_1
P005
D21 *2, *3, *4, *5
SCK2_0 *2
ADTG0_1
INT7_1
RX2(64) *4, *5, *6,
*7
-
-
62 *1
78 *1
-
-
-
166
98 *1 116 *1 137 *1 167 *1
P165
PPG33_1
P006
D22 *2, *3, *4, *5
SCS2_0 *2
ADTG1_1
INT2_1
TX2(64) *4, *5, *6,
*7
Document Number: 002-04662 Rev. *F
-
-
-
117 *1
138
168
-
-
-
-
-
169
-
-
-
118 *1
139
170
63 *1
79 *1
99 *1 119 *1
140
171
P007
D23 *5
P166
PPG34_1
P010
D24 *5
P011
WOT
D25 *2, *3, *4, *5
SOT2_1 *2
TIOA0_0 *2, *3, *4
INT3_1
Page 261 of 280
MB91520 Series
Page
Section
Change Results
A List of "Pin Description" modified.
(Error)
Function*2
General-purpose I/O port
External bus data bit21 I/O (0)
Multi-function serial ch.2 clock I/O (0)
A/D converter external trigger input 0 (1)
INT7 External interrupt input (1)
(CAN reception data 2 input
MB91F52xB ,MB91F52xD only)
34
■PIN Description
General-purpose I/O port
External bus data bit22 I/O (0)
Serial chip select 2 I/O (0)
A/D converter external trigger input 1 (1)
INT2 External interrupt input (1)
(CAN transmission data 2 output
MB91F52xB ,MB91F52xD only)
(Correct)
Function*9
General-purpose I/O port
External bus data bit21 I/O (0)
Multi-function serial ch.2 clock I/O (0)
A/D converter external trigger input 0 (1)
INT7 External interrupt input (1)
CAN reception data 2 input
General-purpose I/O port
External bus data bit22 I/O (0)
Serial chip select 2 I/O (0)
A/D converter external trigger input 1 (1)
INT2 External interrupt input (1)
CAN transmission data 2 output
Document Number: 002-04662 Rev. *F
Page 262 of 280
MB91520 Series
Page
Section
Change Results
The following sentences modified under the Table of Pin description.
(Error)
*1: For the I/O circuit types, see "■I/O CIRCUIT TYPE".
*2: For switching, see "I/O Port" in HARDWARE MANUAL.
36
■PIN Description
(Correct)
*1: There is a restriction of pin functions. See "Pin Name" of this table.
*2: not supported in 64pin
*3: not supported in 80pin
*4: not supported in 100pin
*5: not supported in 120pin
*6: not supported in 144pin
*7: not supported in 176pin
*8: For the I/O circuit types, see "■I/O CIRCUIT TYPE".
*9: For switching, see "I/O Port" in HARDWARE MANUAL.
Remarks for Type I in "I/O Circuit Types" modified as follows:
39
■I/O Circuit Type
(Error)
- 3V pad power supply (5V tolerant),
General-purpose I/O port
- Output 4mA
- CMOS hysteresis input
(Correct)
- General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Remarks for Type J in "I/O Circuit Types" modified as follows:
40
■I/O Circuit Type
(Error)
- 3V pad power supply (5V tolerant),
Analog input,General-purpose I/O port
- Output 4mA
- CMOS hysteresis input
(Correct)
- Analog input, General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Document Number: 002-04662 Rev. *F
Page 263 of 280
MB91520 Series
Page
Section
Change Results
Remarks for Type L in "I/O Circuit Types" modified as follows:
40
■I/O Circuit Type
(Error)
- Open-drain I/O
- Output 25mA (NOD)
- TTL input
(Correct)
- Open-drain I/O
- Output 25mA (Nch open-drain)
- TTL input
Remarks for Type M in "I/O Circuit Types" modified as follows:
40
■I/O Circuit Type
(Error)
- CMOS hysteresis input
- Pull-up resistor 50kΩ (5V cont)
(Correct)
- CMOS hysteresis input
- Pull-up resistor 50kΩ
121
■Interrupt Vector Table
The following sentence deleted from Interrupt vector 64pins.
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
The interrupt factor in Interrupt vector 80pin modified as follows:
124
■Interrupt Vector Table
(Error)
Base timer
1 IRQ0
Base timer
1 IRQ1
−
−
(Correct)
Base timer
1 IRQ0
Base timer
1 IRQ1
−
−
61
3D
ICR
45
308H
000F
FF08
45*5
H
61
3D
ICR
45
308H
000F
FF08
45
H
The following sentence deleted from Interrupt vector 80pins.
125
■Interrupt Vector Table
Document Number: 002-04662 Rev. *F
(Error)
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
Page 264 of 280
MB91520 Series
Page
Section
Change Results
The interrupt factor in Interrupt vector 100pin modified as follows:
129
■Interrupt Vector Table
(Error)
Base timer 0
IRQ0
Base timer 0
IRQ1
(Correct)
−
−
60
3
C
ICR
44
30CH
000F
FF0C
44
H
60
3
C
ICR
44
30CH
000F
FF0C
44
H
The interrupt factor in Interrupt vector 100pin modified as follows:
129
■Interrupt Vector Table
(Error)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
61
3D
61
3D
ICR
45
ICR
45
308H
308H
000F
FF08H
000F
FF08
45
*5
45
H
The following sentence deleted from Interrupt vector 100pins.
129
■Interrupt Vector Table
Document Number: 002-04662 Rev. *F
(Error)
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
Page 265 of 280
MB91520 Series
Page
Section
Change Results
"42" is deleted as shown below from the interrupt factor in Interrupt vector
120pin.
131
■Interrupt Vector Table
(Error)
PPG2/3/12/13/22
/23/32/33/42/43
16-bit free-run
timer 2 (0
detection) /
(compare clear)
(Correct)
PPG2/3/12/13/22
/23/32/33/43
16-bit free-run
timer 2 (0
detection) /
(compare clear)
41
29
ICR
25
358
000F
FF58
H
25
*3
H
41
29
ICR
25
358
000F
FF58
H
25
*3
H
The interrupt factor in Interrupt vector 120pin modified as follows:
133
■Interrupt Vector Table
(Error)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
61
3D
ICR
45
308
000F
FF08
H
45
*5
H
61
3D
ICR
45
308
000F
FF08
45
H
H
The following sentence deleted from Interrupt vector 120pins.
133
■Interrupt Vector Table
Document Number: 002-04662 Rev. *F
(Error)
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
Page 266 of 280
MB91520 Series
Page
Section
Change Results
"42" is deleted as shown below from the interrupt factor in Interrupt vector
144pin.
135
■Interrupt Vector Table
(Error)
PPG2/3/12/13/22/
23/32/33/42/43
16-bit free-run
timer 2 (0
detection) /
(compare clear)
(Correct)
PPG2/3/12/13/22/
23/32/33/43
16-bit free-run
timer 2 (0
detection) /
(compare clear)
41
29
ICR
25
358
000F
FF58
H
25*
3
H
41
29
ICR
25
358
000F
FF58
H
25*
3
H
The interrupt factor in Interrupt vector 144pin modified as follows:
137
■Interrupt Vector Table
(Error)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
61
3D
ICR
45
308
000F
FF08
H
45
*5
H
61
3D
ICR
45
308
000F
FF08
45
H
H
The following sentence deleted from Interrupt vector 144pins.
137
■Interrupt Vector Table
Document Number: 002-04662 Rev. *F
(Error)
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
Page 267 of 280
MB91520 Series
Page
Section
Change Results
The interrupt factor in Interrupt vector 176pin modified as follows:
141
■Interrupt Vector Table
(Error)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
Base timer 1
IRQ1
−
−
61
3D
ICR
45
308
000F
FF08
H
45
*5
H
61
3D
ICR
45
308
000F
FF08
45
H
H
The following sentence deleted from Interrupt vector 176pins.
141
■Interrupt Vector Table
(Error)
*5: It does not support the DMA transfer by the interrupt because of the RAM
ECC bit error.
The remarks of "L" level average output current" and "H" level average output
current" modified as follows.
(Error)
Parameter
142
■Electrical Characteristics
1. Absolute Maximum Ratings
"L" level average
output current *4
"H" level average
output current *4
Rating
Sym
bol Min Max
IOLAV1
4
IOLAV2
12
IOHAV1 -4
IOHAV2 -12
Unit
Remarks
mA
mA
mA
mA
(Correct)
Rating
Sym
bol Min Max
4
"L" level average IOLAV1
output current *4 IOLAV2
12
-4
"H" level average IOHAV1 output current *4 IOHAV2 -12
The following note added.
Parameter
143
■Electrical Characteristics
1. Absolute Maximum Ratings
Document Number: 002-04662 Rev. *F
Unit
mA
mA
mA
mA
Remarks
*9
*10
*9
*10
(Correct)
*9: Corresponding pins: General-purpose ports other than those of P103,
P104, P105 and P106.
*10: Corresponding pins: General-purpose ports of P103, P104, P105 and
P106.
Page 268 of 280
MB91520 Series
Page
Section
Change Results
155
■Electrical Characteristics
AC Characteristics
(2) Reset Input
156
■Electrical Characteristics
AC Characteristics
(3) Power-on Conditions
Deleted the Slope detection undetected specification.
Added the Power ramp rate and C pin voltage at Power-on.
*1, *2: Changed the sentence.
Added *3, *4, Note, Figure at the Power off time, Power ramp rate, C pin voltage
at Power-on.
■Product lineup
■Ordering information
Package description modified to JEDEC description.
6 to 11,
203 to
216
Added the At power-on*2 condition to the remarks in Reset input time.
The following sentence modified as fdeleted from Interrupt
(Error)
To prevent a malfunction of the voltage step-down circuit built in the device, set
the voltage rising time to have 50μs or longer (between 0.2V and 2.7V) during
power-on.
47
49, 50
217 to
220
221 to
227
■During Power-on
■Block Diagram
■Ordering Information
■Package Dimensions
Document Number: 002-04662 Rev. *F
(Correct)
To prevent a malfunction of the voltage step-down circuit built in the device, the
voltage rising must be monotonic increasing during power-on.
Power-on prohibits that the voltage goes up and down and voltage rising stops
temporarily.
The following Block diagram modified as follows:
●MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
●MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
(Error)
CAN (2ch).
(Correct)
CAN (3ch)
Added the following description.
■ORDERING INFORMATION MB91F52xxxD
Package Dimensions modified to JEDEC description.
Page 269 of 280
MB91520 Series
Page
Section
Change Results
Rev *C
The following sentence modified in I2C as following:
(Error)
< I2C >
2 channels ch.3 , ch.4
2
Features
Peripheral Functions
Standard mode/high-speed mode supported.
Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported
(Correct)
< I2C >
2 channels ch.3 , ch.4
Standard mode/fast mode supported.
Standard mode (Max. 100kbps) / fast mode (Max. 400kbps) supported
The following *2 added as follows:
5,6,7,8,9
,10
1. Product Lineup
(Error)
Power supply
2.7 V to 5.5 V
(Correct)
Power supply
2.7 V to 5.5 V *2
The following sentence added as follows:
5,6,7,8,9
,10
1. Product Lineup
8, 9, 10,
1. Product Lineup
11
1. Product Lineup
Document Number: 002-04662 Rev. *F
(Correct)
*2: Detection voltage of the external low voltage detection reset (initial) is
2.8V±8% (2.576V to 3.024V).
This detection voltage (2.576V) is below the minimum operation guarantee
voltage (2.7V).
Between this detection voltage and the minimum operation guarantee voltage,
MCU functions are not guaranteed except for the low voltage detector.
Note that although the detection level is below the minimum operation guarantee
voltage, the LVD reset factor flag is set as the voltage drops below the detection
level.
The following sentence modified in the bottom of Product lineup comparison
table as following:
(Error)
*1: Only channel 3 and channel 4 support the I2C (high-speed mode/standard
mode).
(Correct)
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Added silicon version E
Page 270 of 280
MB91520 Series
Page
Section
Change Results
The following sentence modified as following:
46
■During Power-on
(Error)
To prevent a malfunction of the voltage step-down circuit built in the device, the
voltage rising must be monotonic increasing during power-on.
Power-on prohibits that the voltage goes up and down and voltage rising stops
temporarily.
(Correct)
To prevent a malfunction of the voltage step-down circuit built in the device, the
voltage rising must be monotonic during power-on.
The following sentence modified as following:
(Error)
*1: When it is used outside recommended operation guarantee range (range of
the operation guarantee), contact your sales representative. Moreover,
minimum value with an effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection reset.
142,143
11. Electrical Characteristics
Recommended operating
conditions
156, 157
11. Electrical Characteristics
AC Characteristics
(Correct)
*1: When it is used outside recommended operation guarantee range (range of
the operation guarantee), contact your sales representative.
Detection voltage of the external low voltage detection reset (initial) is
2.8V±8% (2.576V to 3.024V).
This detection voltage (2.576V) is below the minimum operation guarantee
voltage (2.7V).
Between this detection voltage and the minimum operation guarantee
voltage,
MCU functions are not guaranteed except for the low voltage detector.
Note that although the detection level is below the minimum operation
guarantee voltage,
the LVD reset factor flag is set as the voltage drops below the detection level.
Added (3-2) Power-on Conditions for MB91F52xxxE
The following sentence modified as following:
(Error)
High-speed
mode*3
Min
Max
184
11. Electrical Characteristics
AC Characteristics
(4-4) I2C timing
Unit
Remarks
Notes: Only ch.3 and ch.4 are standard mode/high-speed mode
correspondence.
*3: A high-speed mode I2C bus device can be used
(Correct)
Fast mode*3
Min
Max
Unit
Remarks
Notes: Only ch.3 and ch.4 are standard mode/fast mode correspondence.
*3: A fast mode I2C bus device can be used
Document Number: 002-04662 Rev. *F
Page 271 of 280
MB91520 Series
Page
Section
Change Results
The following sentence modified in the Detection voltage as following:
(Error)
Value
Unit
187
11. Electrical Characteristics
(8) Low voltage detection
(External low-voltage
detection)
Min
Typ
Max
2.7
-
5.5
-8%
2.8
+8%
Remarks
V
V
When power-supply
voltage falls and
detection level is set
initially
(Correct)
Value
Unit
Min
Typ
Max
2.7
-
5.5
Remarks
V
LVD5F_SEL[3:0] are
programmable. Refer
-8%
+8%
V
to the hardware
manual.
The following sentence modified as following:
LVD5F
_SEL
[3:0]
188
11. Electrical Characteristics
(9) Low voltage detection
(RAM retention low-voltage
detection)
(Error)
(9) Low voltage detection (Internal low-voltage detection)
(Correct)
220 to
223
16. Ordering Information
(9) Low voltage detection (RAM retention low-voltage detection)
Added the following description.
■ORDERING INFORMATION MB91F52xxxE
Rev *D
The following sentence should be modified as follows:
1
Features
(Error)
Conversion time : 1μs
(Correct)
Conversion time : 1.4μs
Document Number: 002-04662 Rev. *F
Page 272 of 280
MB91520 Series
Page
Section
Change Results
The following sentence should be modified as follows:
5,6,7,8,9
,10
1. Product Lineup
(Error)
*2: Detection voltage of the external low voltage detection reset (initial) is
2.8V±8% (2.576V to 3.024V). This detection voltage (2.576V) is below the
minimum operation guarantee voltage (2.7V). Between this detection voltage
and the minimum operation guarantee voltage, MCU functions are not
guaranteed except for the low voltage detector. Note that although the detection
level is below the minimum operation guarantee voltage, the LVD reset factor
flag is set as the voltage drops below the detection level.
(Correct)
*2: The initial detection voltage of the external low voltage detection is 2.8V±8%
(2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips
below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU
operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the
exception of LVD.
The following sentence should be modified as follows:
142,143
11. Electrical Characteristics
Recommended operating
conditions
(Error)
*1: When it is used outside recommended operation guarantee range (range of
the operation guarantee), contact your sales representative.
Detection voltage of the external low voltage detection reset (initial) is
2.8V±8% (2.576V to 3.024V). This detection voltage (2.576V) is below the
minimum operation guarantee voltage (2.7V). Between this detection voltage
and the minimum operation guarantee voltage, MCU functions are not
guaranteed except for the low voltage detector. Note that although the
detection level is below the minimum operation guarantee voltage, the LVD
reset factor flag is set as the voltage drops below the detection level.
(Correct)
*1: When it is used outside recommended operation guarantee range (range of
the operation guarantee), contact your sales representative.
The initial detection voltage of the external low voltage detection is 2.8V±8%
(2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage
dips below minimum guaranteed operation voltage, as these detection levels
are below the minimum guaranteed MCU operation voltage. Below the
minimum guaranteed MCU operation voltage, MCU operations are not
guaranteed with the exception of LVD.
Pin name of RUP3 should be modified as follows:
146
11. Electrical Characteristics
DC Characteristics
(Error)
Port pin other than P035,041,093,122
(Correct)
Port pin other than P035,041,073,074,076,077,093,122
Document Number: 002-04662 Rev. *F
Page 273 of 280
MB91520 Series
Page
Section
Change Results
Note of Detection voltage should be added as follows:
187
11. Electrical Characteristics
(8) Low voltage detection
(External low-voltage
detection)
188
11. Electrical Characteristics
(9) Low voltage detection
(Internal low-voltage
detection)
(Correct)
Detection voltage *3
*3: The initial detection voltage of the external low voltage detection is 2.8V±8%
(2.576V to 3.024V). This LVD setting cannot be used to reliably generate a reset
before voltage dips below minimum guaranteed MCU operation voltage, as this
detection level is below the minimum guaranteed MCU operation voltage (2.7V).
Below the minimum guaranteed MCU operation voltage, MCU operations are not
guaranteed with the exception of LVD.
The following sentence modified as following:
(Error)
(9) Low voltage detection (RAM retention low-voltage detection)
(Correct)
(9) Low voltage detection (Internal low-voltage detection)
The following symbol should be modified as follows:
(Error)
*
(Correct)
*1
Note of Detection voltage should be added as follows:
(Correct)
Detection voltage *2
*2: The detection voltage of the internal low voltage detection is 0.9V±0.1V. This
LVD cannot be used to reliably generate a reset before voltage dips below
minimum guaranteed MCU operation voltage, as this detection level is below the
minimum guaranteed MCU operation voltage. Below the minimum guaranteed
MCU operation voltage, MCU operations are not guaranteed with the exception
of LVD.
233 to
235
Rev *F
18. Errata
Limitation for Watch mode (power off) should be added in Errata.
The shading part added as below.
222
16. Ordering Information
MB91F52xxxE
Document Number: 002-04662 Rev. *F
Part number
Sub
clock
CSV
Initial
value
LVD
Initial
value
Package*
MB91F526LSEPMC
None
ON
ON
LQP・176 pin,
Plastic
MB91F526LHEPMC
OFF
ON
MB91F526LKEPMC
OFF
OFF
Page 274 of 280
MB91520 Series
Document History
Document Title: MB91520 Series 32-bit FR81S Microcontroller
Document Number: 002-04662
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
Initial release
Features:
Corrected the following description.
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 Automotive input
↓
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input
I/O CIRCUIT TYPE:
Corrected the following description to "Type F, G, I, J, K, M".
Schmitt input → CMOS hysteresis input
Corrected the following description to "Type D, E".
I2C Schmitt input → I2C hysteresis input
Block Diagram
Corrected the following description.
•
MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
•
MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
•
MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
•
MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
•
MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
•
MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
**
Electrical Characteristics
2. Recommended operating conditions:
*1：When it is used outside recommended operation guarantee range (range of the
operation guarantee),contact your sales representative. Moreover, minimum value with
an effective external low-voltage detection reset becomes a voltage until generating
low-voltage detection reset
Electrical Characteristics
3.DC characteristics
Corrected the value of "ICCT5 When using sub clock 32kHz TA=+25°C
". Max 1420µA → Max 2000µA
Corrected the value of "Power supply voltage range".
(TA:-40°C to +105°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +105°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of "Power supply voltage range".
(TA:-40°C to +125°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +125°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of " Pull-up resistance RUP1".
Vcc=3.3V±0.3V Min 49 Max 140 →Min 45 Max 140
Corrected the following description.
Pull-up resistance RUP2
Port pin other than P035,041,093,122 → P073,074,076,077
Corrected the value of " Pull-up resistance RUP2".
Document Number: 002-04662 Rev. *F
Page 275 of 280
MB91520 Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
VCC=5.0V±10% Min 25 Max 100 →Min 25 Max 60
VCC=3.3V±0.3V Min 49 Max 140 →Min 33 Max 90
Added the value of " Pull-up resistance RUP3".
Pin name : Port pin other than P035,041,073,074,076,077,093,122
VCC=5.0V±10% Min 25 Max 100
VCC=3.3V±0.3V Min 45 Max 140
Electrical Characteristics
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVI
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVI
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min -30 Max 30
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min -30 Max 30
Pin name: SCK3,SCK4
SOT3,SOT4
Value: Min -300 Max 300
(4-1-1),(4-1-4)Valid SIN⇒SCK↑ setup time tIVSHI
(4-1-2),(4-1-3)Valid SIN⇒SCK↓ setup time tIVSLI
Corrected the following description.
Pin name: SCK0 to SCK11 SIN0 to SIN11
Value: Min 34 Max ↓
Pin name: SCK0 to SCK2,SCK5 to SCK11 SIN0 to SIN2,SIN5 to SIN11
Value: Min 34 Max Pin name: SCK3,SCK4,SIN3,SIN4
Value: Min 300 Max –
(4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVE
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVE
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min - Max 33
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min - Max 33
Pin name: SCK3,SCK4 SOT3,SOT4
Value: Min - Max 300
(4-1-1),(4-1-2),(4-1-3),(4-1-4)SCK fall time tF
Corrected the following description.
Pin name: SCK0 to SCK2,SCK5 to SCK11
Value: Min - Max 5
Pin name: SCK3,SCK4
Value: Min - Max 250
↓
Pin name: SCK0 to SCK11
Document Number: 002-04662 Rev. *F
Page 276 of 280
MB91520 Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
Value: Min - Max 5
(4-1-5)SCS↓⇒SCK↓ setup time tCSSI
(4-1-6)SCS↓⇒SCK↑ setup time tCSSI
(4-1-7)SCS↑⇒SCK↓ setup time tCSSI
(4-1-8)SCS↑⇒SCK↑ setup time tCSSI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSSU+0 Max tCSSU+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min tCSSU-50 Max tCSSU+0
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSSU-50 Max tCSSU+300
(4-1-5)SCK↑⇒SCS↑hold time tCSHI
(4-1-6)SCK↓⇒SCS↑hold time tCSHI
(4-1-7)SCK↑⇒SCS↓hold time tCSHI
(4-1-8)SCK↓⇒SCS↓hold time tCSHI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSHD-50 Max tCSHD+0
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min tCSHD-10 Max tCSHD+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSHD-300 Max tCSHD+50
(4-1-5),(4-1-6)SCS↓⇒SOT delay time tDSE
(4-1-7),(4-1-8)SCS↑⇒SOT delay time tDSE
Corrected the following description.
Pin name: SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70
to SCS73,SCS8 to SCS11
SOT1 to SOT11
Value: Min - Max 40
↓
Pin name: SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,
SCS8 to SCS11
SOT1,SOT2,SOT5 to SOT11
Value: Min - Max 40
Pin name: SCS3,SCS40 to SCS43
SOT3,SOT4
Value: Min - Max 300
(4-1-5)SCK↓⇒SCS↓ clock switch time tSCC
(4-1-6)SCK↑⇒SCS↓ clock switch time tSCC
(4-1-7)SCK↓⇒SCS↑ clock switch time tSCC
(4-1-8)SCK↑⇒SCS↑ clock switch time tSCC
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Document Number: 002-04662 Rev. *F
Page 277 of 280
MB91520 Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
Value: Min 3tCPP+0 Max 3tCPP+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min 3tCPP-10 Max 3tCPP+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min 3tCPP-300 Max 3tCPP+50
Added the following description.
Regardless of the deselect time setting, once after the serial chip select pin becomes
inactive, it will take at least five peripheral bus clock cycles to be active again
Electrical Characteristics
5.A/D Converter
(1) 12-bit A/D Converter Electrical Characteristics:
Added the value of "Total error".
Total error value Min – Typ – Max ±12 LSB
Corrected the value of "Zero transition voltage".
Min AVRL+0.5LSB-20mV Max AVRL+0.5LSB+20mV
↓
Min AVRL-11.5LSB Max AVRL+12.5LSB
Corrected the value of "Full-scale transition voltage".
Min AVRH-1.5LSB-20mV Max AVRH-1.5LSB+20mV
↓
Min AVRH-13.5LSB Max AVRH+10.5LSB
Added the following description.
Parameter : Power supply current IA AVCC*3
*3: The power supply current described only current value on A/D converter. The total
AVcc current value must be calculated the power supply current for A/D converter and
D/A converter.
Electrical Characteristics
7.D/A Converter:
Added the following description.
Parameter : Power supply current *1
*1: The power supply current described only current value on D/A converter.The total
Avcc current value must be calculated the power supply current for D/A converter and
A/D converter.
Electrical Characteristics
6.Flash memory:
Parameter: Erase cycle*2/Data retain time
Deleted the following description.
Remarks :
"Temperature at writing/erasing Tj<+105°C"
Electrical Characteristics
7.D/A Converter:
Corrected the following description.
Parameter : Power supply current
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
↓
Symbol IA Pin name AVCC
Document Number: 002-04662 Rev. *F
Page 278 of 280
MB91520 Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
Symbol IAH Pin name AVCC
Example Characteristics
Corrected the following description.
Watch mode
Ordering Information
Corrected the following description.
• ORDERING INFORMATION
↓
• ORDERING INFORMATION MB91F52xxxB*1
Package
↓
Package*2
Added the following description.
*1: It is only supported for customers who have already adopted it now. We do not
recommend adopting new products.
Corrected the following description.
For details of the package, see "■ PACKAGE DIMENSIONS ".
↓
*2: For details of the package, see "■ PACKAGE DIMENSIONS ".
Added the following description.
• ORDERING INFORMATION MB91F52xxxC
Company name and layout design change
Updated to Cypress template.
*A
4999456
JHMU
11/13/2015
Added the following note to the remarks of ""L" level average output current"
and ""H" level average output current" in “Absolute Maximum Ratings” of
“ELECTRICAL CHARACTERISTICS”.
*9: Corresponding pins: General-purpose ports other than those of P103, P104,
P105 and P106.
*10: Corresponding pins: General-purpose ports of P103, P104, P105 and P106.
Added Errata section.
Fixed some clerical errors.
*B
5112138
KUME
01/28/2016
*C
5196285
KUME
04/28/2016 For details, please see the chapter 19. Major Changes.
*D
5318862
KUME
06/23/2016 For details, please see the chapter 19. Major Changes.
*E
5711679 AESATMP7 04/25/2017 Updated Cypress Logo and Copyright.
*F
5984090
KUME
Document Number: 002-04662 Rev. *F
For details, please see the chapter 18. Major Changes.
12/05/2017 For details, please see the chapter 19. Major Changes.
Page 279 of 280
MB91520 Series
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Document Number: 002-04662 Rev. *F
December 5, 2017
Page 280 of 280