Intersil ISL8010 Monolithic 600ma step-down regulator with low quiescent current Datasheet

ISL8010
®
Data Sheet
September 27, 2005
Monolithic 600mA Step-Down Regulator
with Low Quiescent Current
The ISL8010 is a synchronous, integrated FET 600mA stepdown regulator with internal compensation. It operates with
an input voltage range from 2.5V to 5.5V, which
accommodates supplies of 3.3V, 5V, or a Li-Ion battery
source. The output can be externally set from 0.8V to VIN
with a resistive divider.
The ISL8010 features automatic PFM/PWM mode control, or
PWM mode only. The PWM frequency is typically 1.4MHz
and can be synchronized up to 12MHz. The typical no load
quiescent current is only 120µA. Additional features include
a Power-Good output, <1µA shutdown current, short-circuit
protection, and over-temperature protection.
FN6191.0
Features
• Less than 0.18in2 footprint for the complete 600mA
converter
• Components on one side of PCB
• Max height 1.1mm MSOP10
• Power-Good (PG) output
• Internally-compensated voltage mode controller
• Up to 95% efficiency
• <1µA shutdown current
• 120µA quiescent current
• Hiccup mode overcurrent and over-temperature protection
The ISL8010 is available in the 10 Ld MSOP package,
making the entire converter occupy less than 0.18in2 of PCB
area with components on one side only. The 10 Ld MSOP
package is specified for operation over the full -40°C to
+85°C temperature range.
• External synchronizable up to 12MHz
Ordering Information
• Bar code readers
PART
NUMBER
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
ISL8010IUZ
(Note)
8010Z
-
10 Ld MSOP MDP0043
(Pb-free)
ISL8010IUZ-T7
(Note)
8010Z
7”
10 Ld MSOP MDP0043
(Pb-free)
ISL8010IUZ-T13 8010Z
(Note)
13”
10 Ld MSOP MDP0043
(Pb-free)
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDA and pocket PC computers
• Cellular phones
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
Pinout and Typical Application Diagram
ISL8010
TOP VIEW
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
C1
10µF
VO (1.8V@600mA)
VS (2.5V-6V)
C2
10µF
L1
1.8µH
R3
100Ω
C3
0.1µF
R2*
100kΩ
R1*
124kΩ
1 SGND
FB 10
2 PGND
VO 9
3 LX
PG 8
PG
4 VIN
EN 7
EN
C4
470pF
5 VDD
SYNC 6
R4
100kΩ
R5
100kΩ
SYNC
R6
100kΩ
* VO = 0.8V * (1 + R1 / R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8010
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA
Thermal Resistance (Typical)
θJA (°C/W)
MSOP10 Package (Note 1) . . . . . . . . . . . . . . . . . . .
130
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in Typical Application Diagram),
TA = -40°C to 85°C unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
790
800
810
mV
100
nA
2.5
5.5
V
2
2.2
V
2.2
2.4
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
TA = 25°C only
VIN,OFF
Minimum Voltage for Shutdown
VIN falling, TA = 25°C only
VIN,ON
Maximum Voltage for Start-up
VIN rising
IS
Input Supply Quiescent Current
PWM Mode
Active - PFM Mode
VSYNC = 0V
120
145
µA
Active - PWM Mode
VSYNC = 3.3V
6.5
7.5
mA
Supply Current
PWM, VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
3
µA
PMOS FET Resistance
VDD = 5V, TA = 25°C
70
100
mΩ
RDS(ON)-NMOS NMOS FET Resistance
VDD = 5V, TA = 25°C
45
75
mΩ
IDD
RDS(ON)-PMOS
ILMAX
Current Limit
TOT,OFF
Over-temperature Threshold
TOT,ON
1.2
A
T rising
145
°C
Over-temperature Hysteresis
T falling
130
°C
IEN, ISYNC
EN, SYNC Current
VEN, VRSI = 0V and 3.3V
VEN1, VSYNC1
EN, SYNC Rising Threshold
VDD = 3.3V
VEN2, VSYNC2
EN, SYNC Falling Threshold
VDD = 3.3V
VPG
Minimum VFB for PG, WRT Targeted VFB VFB rising
Value
VFB falling
VOLPG
PG Voltage Drop
-1
1
µA
2.4
V
0.8
V
95
86
ISINK = 3.3mA
%
%
35
70
mV
1.4
1.6
MHz
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tSS
Soft-start Time
1.25
650
2
µs
FN6191.0
September 27, 2005
ISL8010
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
SYNC
7
EN
Enable
8
PG
Power-Good open drain output
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto
PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz
Block Diagram
100Ω
0.1µF
VDD
INDUCTOR SHORT
VO
+
CURRENT
SENSE
10pF
C4 124K
470pF
FB
5M
+
PWM
COMPENSATION
100K
SYNC
SYNC
CLOCK
RAMP
GENERATOR
EN
EN
SOFTSTART
10µF
5V +
–
BANDGAP
REFERENCE
+
PWM
COMPARATOR
PFM
ON-TIME
CONTROL
+
PWM
COMPARATOR
UNDERVOLTAGE
LOCKOUT
P-DRIVER
LX
CONTROL
LOGIC
1.8µH
1.8V
0 TO 600mA
10µF
N-DRIVER
PGND
TEMPERATURE
SENSE
SGND
VIN
+
SYNCHRONOUS
RECTIFIER
100K
PG
PG
POWER
GOOD
3
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
100
100
VO=3.3V
95
85
80
75
VO=1.8V
VO=1.5V
70
VO=1.0V
65
VO=0.8V
60
VO=1.2V
55
45
VO=1.8V
60
VO=1.5V
50
VO=1.2V
40
VO=1.0V
30
VO=0.8V
10
VIN=5V
1
VO=2.5V
70
20
50
40
VO=3.3V
80
EFFICIENCY (%)
EFFICIENCY (%)
90
VO=2.5V
90
10
100
VIN=5V
0
600
1
10
100
IO (mA)
FIGURE 1. EFFICIENCY vs IO (PFM/PWM MODE)
VO=2.5V
VO=1.8V
95
90
VO=1.8V
80
85
80
VO=1.5V
VO=1.2V
VO=1.0V
75
70
65
VO=0.8V
60
VO=1.5V
70
VO=1.2V
60
VO=1.0V
50
40
30
55
20
50
VO=0.8V
10
45
VIN=3.3V
1
10
IO (mA)
100
1
600
1.4
VIN=3.3V IO=0A
1.38
1.36
1.34
1.32
-50
600
0.1
VIN=5V IO=0A
1.42
100
FIGURE 4. EFFICIENCY vs IO (PWM MODE)
VIN=3.3V IO=600mA
VIN=5V IO=600mA
10
IO (mA)
VO CHANGES (%)
1.44
VIN=3.3V
0
FIGURE 3. EFFICIENCY vs IO (PFM/FWM MODE)
FS (MHz)
VO=2.5V
90
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 2. EFFICIENCY vs IO (PWM MODE)
100
100
40
600
IO (mA)
0.0
-0.1
VIN=3.3V
-0.2
VIN=5V
-0.3
-0.4
-0.5
0
50
100
150
TA (°C)
FIGURE 5. FS vs JUNCTION TEMPERATURE (PWM MODE)
4
0
0.2
0.4
0.6
0.8
1
IO (A)
FIGURE 6. LOAD REGULATIONS (PWM MODE)
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
0.1
12
VIN=5V IO=0A
10
VIN=3.3V IO=0A
-0.1
8
-0.2
IS (mA)
VO CHANGES (%)
0.0
VIN=3.3V IO=600mA
-0.3
-0.4
6
4
-0.5
-0.6
-0.7
2
VIN=5V IO=600mA
-50
0
50
100
0
150
2.5
3.5
3
TJ (°C)
4
4.5
5
VS (V)
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs
JUNCTION TEMPERATURE
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)
140
130
VO=1.8V
VO=3.3V
120
IS (µA)
110
100
90
VO=1.5V
VO=1.2V VO=1.0V
VO=0.8V
80
70
60
50
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VS (V)
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)
2
1
VIN
(2V/DIV)
EN
IIN
(0.25A/DIV)
IIN
(0.25A/DIV)
VO
(2V/DIV)
VO
(2V/DIV)
PG
PG
200µs/DIV
FIGURE 10. START-UP AT IO = 600mA
5
500µs/DIV
FIGURE 11. ENABLE AND SHUTDOWN
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
LX
(2V/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
IL
(0.5A/DIV)
∆VO
(10mV/DIV)
∆VO
(50mV/DIV)
0.5µs/DIV
2µs/DIV
FIGURE 12. PFM STEADY-STATE OPERATION WAVEFORM
(IO = 100mA)
FIGURE 13. PWM STEADY-STATE OPERATION (IO = 600mA)
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 14. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 15. EXTERNAL SYNCHRONIZATION TO 12MHz
IO
(200mA/DIV)
IO
(200mA/DIV)
∆VO
(100mV/DIV)
∆VO
(100mV/DIV)
100µs/DIV
FIGURE 16. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
6
50µs/DIV
FIGURE 17. PWM LOAD TRANSIENT RESPONSE (30mA TO
600mA)
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
100
1.4MHz
IO
(200mA/DIV)
EFFICIENCY (%)
80
∆VO
(50mV/DIV)
5MHz
12MHz
60
40
20
0
0
200
400
50µs/DIV
600
800
1K
1.2K
IO (mA)
FIGURE 18. PWM LOAD TRANSIENT RESPONSE (100mA TO
500mA)
FIGURE 19. EFFICIENCY vs IO (PWM MODE)
0.5
1
12MHz
0.3
VO CHANGES (%)
VO CHANGES (%)
0.6
1.4MHz
0.2
5MHz
0
12MHz
0.1
1.4MHz
-0.1
5MHz
-0.3
-0.2
-0.5
-0.6
0
200
400
600
800
1K
1.2K
0
200
400
600
800
1K
1.2K
VIN (V)
IO (mA)
FIGURE 20. LOAD REGULATION (PWM MODE)
FIGURE 21. LINE REGULATION @ 500mA (PWM MODE)
IO=50mA
IO=150mA
2µs/DIV
FIGURE 22. PFM-PWM TRANSITION TIME
7
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
LX
(2V/DIV)
2µs/DIV
FIGURE 23. PFM-PWM TRANSITION TIME
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
3
PG
VO CHANGES (%)
2
1
IO
0
-1
PFM
PWM
-2
VO
-3
0
200
400
600
800
1000
1200
IOUT (mA)
FIGURE 24. PFM-PWM TRANSITION
FIGURE 25. PFM-PWM LOAD TRANSIENT
PG
PG
IO
IO
VO
VO
FIGURE 26. PFM TO PWM TRANSITION
FIGURE 27. PWM TO PFM TRANSITION
PG
PG
IL
IL
VO
VO
FIGURE 28. OVERCURRENT SHUTDOWN
8
FIGURE 29. OVERCURRENT HICCUP MODE
FN6191.0
September 27, 2005
ISL8010
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
1
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
870mW
0.9
486mW
0.5
0.4
θ
M
JA
=
0.3
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.6
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
SO
P8
/1
20
0
6°
C/
W
0.2
0.1
0.8
0.7
θ
M
SO
P8
/1
11
0
5°
C/
W
JA
=
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
75 85
50
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
9
0
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6191.0
September 27, 2005
ISL8010
Applications Information
Product Description
The ISL8010 is a synchronous, integrated FET 600mA stepdown regulator which operates from an input of 2.5V to 5.5V.
The output voltage is user-adjustable with a pair of external
resistors.
When the load is very light, the regulator automatically
operates in the PFM mode, thus achieving high efficiency at
light load (>70% for 1mA load). When the load increases,
the regulator automatically switches over to a voltage-mode
PWM operating at nominal 1.4MHz switching frequency. The
efficiency is up to 95%.
It can also operate in a fixed PWM mode or be synchronized
to an external clock up to 12MHz for improved EMI
performance.
PFM Operation
The heart of the ISL8010 regulator is the automatic
PFM/PWM controller.
If the SYNC pin is connected to ground, the regulator
operates automatically in either the PFM or PWM mode,
depending on load. When the SYNC pin is connected to VIN,
the regulator operates in the fixed PWM mode. When the pin
is connected to an external clock ranging from 1.6MHz to
12MHz, the regulator is in the fixed PWM mode and
synchronized to the external clock frequency.
In the automatic PFM/PWM operation, when the load is light,
the regulator operates in the PFM mode to achieve high
efficiency. The top P-channel MOSFET is turned on first. The
inductor current increases linearly to a preset value before it
is turned off. Then the bottom N-channel MOSFET turns on,
and the inductor current linearly decreases to zero current.
The N-channel MOSFET is then turned off, and an antiringing MOSFET is turned on to clamp the LX pin to VO.
Both MOSFETs remain off until VFB drops below the internal
reference voltage of 0.8V. The inductor current looks like
triangular pulses. The frequency of the pulses is mainly a
function of output current. The higher the load, the higher the
frequency of the pulses until the inductor current becomes
continuous. At this point, the controller automatically
changes to PWM operation.
PWM Operation
The regulator operates the same way in the forced PWM or
synchronized PWM mode. In this mode, the inductor current
is always continuous and does not stay at zero.
In this mode, the P-channel MOSFET and N-channel
MOSFET always operate complementary. When the
P-channel MOSFET is on and the N-channel MOSFET off,
the inductor current increases linearly. The input energy is
transferred to the output and also stored in the inductor.
When the P-channel MOSFET is off and the N-channel
MOSFET on, the inductor current decreases linearly, and
10
energy is transferred from the inductor to the output. Hence,
the average current through the inductor is the output
current. Since the inductor and the output capacitor act as a
low pass filter, the duty cycle ratio is approximately equal to
VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic and
inductor is 1.5µH to 2.2µH.
Forced PWM Mode/SYNC Input
Pulling the SYNC pin HI (>2.5V) forces the converter into
PWM mode in the next switching cycle regardless of output
current. The duration of the transition varies depending on the
output current. Figures 22 and 23 (under two different loading
conditions) show the device goes from PFM to PWM mode.
Start-Up and Shutdown
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the ISL8010 is
in the shutdown mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.2A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop as load demand
increases. When the output voltage drops 30mV below the
reference voltage, the converter will shutdown for a period of
time, approximated by Equation 1, and then restart. If the
overcurrent condition still exists, it will repeat the shutdownwait-restart event. This is called a “hiccup” event. The
average power dissipation is reduced, thereby reducing the
likelihood of damage current and thermal conditions in the IC.
700u ⋅ VIN
tHICCUP ≈  ----------------------------- + 216u


3
(EQ. 1)
Thermal Shutdown
Once the junction reaches about 145°C, the regulator shuts
down. Both the P-channel and the N-channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will cool down. Once the
junction temperature drops to about 130°C, the regulator will
perform a normal restart.
FN6191.0
September 27, 2005
ISL8010
Thermal Performance
Layout Considerations
The ISL8010 is available in a fused-lead MSOP10.
Compared with regular MSOP10 package, the fused-lead
package provides lower thermal resistance. The θJA is
100°C/W on a 4-layer board and 125°C/W on 2-layer board.
Maximizing the copper area around the pins will further
improve the thermal performance.
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to VIN and PGND pins
as possible
3. Make the following PC traces as small as possible:
4. from LX pin to L
5. from CO to PGND
6. If used, connect the trace from the FB pin to R1 and R2
as close as possible
R 

V O = 0.8 ×  1 + ------2-
R

1
7. Maximize the copper area around the PGND pin
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required. It
is recommended to use between 10µF and 22µF multilayer
ceramic capacitors with X5R or X7R rating for both the input
and output capacitors, and 1.5µH to 2.2µH for the inductor.
8. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the ISL8010 Application Brief.
The RMS current present at the input capacitor is decided by
the following formula:
V O × ( V IN – V O )
I INRMS = ----------------------------------------------- × I O
V IN
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
( V IN – V O ) × V O
∆I IL = ------------------------------------------L × V IN × f S
L is the inductance
fS the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
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ISL8010
MSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
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