UMS CHK015A-SMA26 15w power packaged transistor Datasheet

CHK015A-SMA
15W Power Packaged Transistor
GaN HEMT on SiC
Description
The CHK015A-SMA is an unmatched
packaged Gallium Nitride High Electron
Mobility Transistor. It offers general purpose
and broadband solutions for a variety of RF
power applications. It is well suited for multipurpose applications such as radar and
telecommunication
The CHK015A-SMA is developed on a
0.5µm gate length GaN HEMT process. It
requires an external matching circuitry.
The CHK015A-SMA is available in a
ceramic-metal
flange
power
package
providing low parasitic and low thermal
resistance.
VDS = 50V, ID_Q = 100mA, Freq = 5.6GHz
CW mode
Main Features
Gain (dB), Pout (dBm) & PAE (%)
55
1.1
PAE
50
1.0
45
0.9
Pout
40
0.8
35
0.7
30
0.6
Id
25
0.5
20
0.4
Gain
15
0.3
10
0.2
5
0.1
0
Drain Current (A)
■ Wide band capability: up to 6GHz
■ Pulsed and CW operating modes
■ High power: > 15W
■ High Efficiency: up to 70%
■ DC bias: VDS = 50V @ ID_Q = 100mA
■ MTTF > 106 hours @ Tj = 200°C
■ RoHS Flange Ceramic package
0.0
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34
Input Power (dBm)
Intrinsic performances of the packaged device
Main Electrical Characteristics
Tcase= +25°C, CW mode, F = 5.6GHz, VDS=50V, ID_Q=100mA
Symbol
Parameter
Min
GSS
Small Signal Gain
PSAT
Saturated Output Power
15
Max Power Added Efficiency
PAE
45
GPAE_MAX Associated Gain at Max PAE
Ref. : DSCHK015ASMA3021 - 21 Jan 13
1/12
Typ
15
18
50
Max
-
Unit
dB
W
%
11
-
dB
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Recommended DC Operating Ratings
Tcase= +25°C
Symbol
Parameter
VDS
Drain to Source Voltage
VGS_Q
Gate to Source Voltage
ID_Q
Quiescent Drain Current
ID_MAX
Drain Current
Gate Current (forward
mode)
Tj_MAX
Junction temperature
(1)
Limited by dissipated power
IG_MAX
Min
20
Typ
Max
50
Unit
V
V
A
A
-1.9
0.1
0.65
0.35
0
8
mA
200
°C
(1)
Conditions
VD = 50V, ID_Q = 100mA
VD = 50V
VD = 50V,
Compressed mode
Compressed mode
DC Characteristics
Tcase= +25°C
Symbol
Parameter
Min
Typ
Max Unit
Conditions
VP
Pinch-Off Voltage
-3
-2
-1
V
VD = 50V, ID =IDSS/100
ID_SAT
Saturated Drain Current
2.7 (1)
A
VD = 7V, VG = 2V
Gate Leakage Current
IG_leak
-1
mA VD = 50V, VG = -7V
(reverse mode)
Drain-Source
VBDS
200
V
VG = -7V, ID = 20mA
Break-down Voltage
°C/W
RTH
Thermal Resistance
6.4
(1)
For information, limited by ID_MAX , see on Absolute Maximum Ratings
RF Characteristics
Tcase= +25°C, CW mode, F = 5.6GHz, VDS=50V, ID_Q=100mA
Symbol
Parameter
Min
GSS
Small Signal Gain
13
PSAT
Saturated Output Power
15
Max Power Added Efficiency
PAE
45
GPAE_MAX Associated Gain at Max PAE
Typ
15
18
50
11
Max
-
Unit
dB
W
%
dB
These values are the intrinsic performance of the packaged device. They are deduced from
measurements and simulations. They are considered in the reference plane defined by the
leads of the package, at the connection interface with the PCB.
The typical performance achievable in more than 10% frequency band around 5.5GHz was
demonstrated using the reference board 61499546 presented hereafter.
Ref. : DSCHK015ASMA3021 - 21 Jan 13
2/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Absolute Maximum Ratings
Tcase= +25°C(1), (2), (3)
Symbol
Parameter
VDS
Drain-Source Voltage
VGS_Q
Gate-Source Voltage
IG_MAX
Maximum Gate Current in forward mode
IG_MIN
Maximum Gate Current in reverse mode
ID_MAX
Maximum Drain Current
PIN
Maximum Input Power (typical)
Tj
Junction Temperature
TSTG
Storage Temperature
TCase
Case Operating Temperature
Rating
60
-10, +2
25
-4
2
34
220
-55 to +150
See note
Unit
V
V
mA
mA
A
dBm
°C
°C
°C
Note
(6)
(4)
(5)
(4)
(1)
Operation of this device above anyone of these parameters may cause permanent
damage.
(2)
Duration < 1s.
(3)
The given values must not be exceeded at the same time even momentarily for any
parameter, since each parameter is independent from each other, otherwise deterioration or
destruction of the device may occur.
(4)
Max junction temperature must be considered
(5)
@6GHz - Linked to and limited by IG_MAX & IG_MIN values
(6)
VGS_Q max limited by ID_MAX and IG_MAX values
Ref. : DSCHK015ASMA3021 - 21 Jan 13
3/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Simulated Source and Load Impedance
VDS = 50V, ID_Q = 100mA
Zload
Zsource
Frequency (MHz)
1000
Source
1.82 + j9.58
Load
42 + j48.6
2000
0.84 – j1.53
13.8 + j25.7
3000
1.02 – j8.5
6.6 + j12.8
4000
1.86 – j15.82
5.1 + j2.6
5000
2.72 – j25.4
5.4 – j7.3
6000
2.87 – j41.14
6.7 – j17.2
These values are given in the reference plane defined by the connection between the
package leads and the PCB. A gap of 200µm is considered between the edge of the
package and the PCB.
Ref. : DSCHK015ASMA3021 - 21 Jan 13
4/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Typical S-parameters
Tcase= +25°C, CW mode, VD=50V, ID_Q=100mA, Phase S(i,j) in °
Freq
(GHz)
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
Mag
S(1,1)
0.912
0.868
0.854
0.851
0.852
0.855
0.859
0.863
0.866
0.870
0.872
0.874
0.875
0.876
0.876
0.875
0.873
0.870
0.867
0.863
0.858
0.853
0.847
0.841
0.835
0.829
0.824
0.820
0.817
0.818
0.821
0.828
0.851
0.883
0.915
0.940
0.956
0.966
0.973
0.976
0.979
0.980
0.98
0.979
0.977
0.976
Phase
S(1,1)
-82.5
-123.0
-143.5
-156.0
-164.9
-171.9
-177.9
176.8
171.8
167.1
162.5
157.9
153.3
148.7
144.0
139.1
134.0
128.8
123.3
117.4
111.3
104.7
97.7
90.2
82.2
73.6
64.5
54.7
44.3
33.4
22.0
10.3
-13.5
-36.8
-58.3
-77.5
-93.8
-107.7
-119.4
-129.5
-138.2
-145.9
-152.7
-158.8
-164.3
-169.4
Ref. : DSCHK015ASMA3021 - 21 Jan 13
Mag
S(2,1)
30.268
19.526
13.768
10.431
8.291
6.814
5.739
4.928
4.298
3.800
3.401
3.076
2.809
2.590
2.408
2.257
2.131
2.027
1.942
1.872
1.815
1.770
1.734
1.707
1.687
1.672
1.660
1.649
1.638
1.625
1.605
1.577
1.486
1.334
1.124
0.887
0.663
0.481
0.346
0.249
0.182
0.135
0.101
0.078
0.061
0.049
Phase
S(2,1)
129.4
102.4
85.8
73.3
62.9
53.6
45.1
37.2
29.9
22.8
16.2
9.7
3.4
-2.7
-8.7
-14.7
-20.6
-26.6
-32.7
-38.8
-45.2
-51.7
-58.5
-65.5
-73.0
-80.7
-89.0
-97.6
-106.8
-116.5
-126.8
-137.7
-160.9
174.1
148.5
123.9
101.6
82.4
66.3
52.7
41.4
31.9
23.9
17.1
11.5
6.7
5/12
Mag
S(1,2)
0.014
0.017
0.017
0.017
0.015
0.013
0.012
0.010
0.008
0.007
0.008
0.009
0.011
0.014
0.017
0.020
0.024
0.027
0.032
0.036
0.040
0.045
0.050
0.056
0.061
0.067
0.073
0.079
0.086
0.092
0.097
0.102
0.109
0.109
0.102
0.088
0.072
0.057
0.045
0.035
0.028
0.023
0.019
0.016
0.014
0.012
Phase
S(1,2)
42.4
18.4
5.2
-3.6
-9.6
-13.3
-14.3
-11.7
-4.0
9.6
26.2
39.8
47.8
51.4
52.2
51.2
49.0
45.9
42.3
38.1
33.4
28.4
22.9
17.1
10.8
4.1
-3.1
-10.8
-19.0
-27.8
-37.1
-47.0
-68.4
-91.5
-115.2
-138.1
-158.8
-176.8
167.7
154.0
141.6
130.1
119.0
108.5
98.7
90.0
Mag
S(2,2)
0.649
0.542
0.517
0.527
0.551
0.581
0.612
0.641
0.668
0.692
0.714
0.733
0.750
0.764
0.776
0.786
0.794
0.801
0.807
0.811
0.814
0.816
0.818
0.818
0.818
0.817
0.815
0.814
0.811
0.809
0.806
0.803
0.799
0.802
0.819
0.849
0.885
0.916
0.94
0.956
0.966
0.972
0.975
0.975
0.975
0.974
Phase
S(2,2)
-38.3
-58.0
-71.6
-83.4
-93.9
-103.5
-112.2
-120.2
-127.6
-134.5
-140.9
-146.9
-152.6
-158.1
-163.4
-168.5
-173.5
-178.5
176.6
171.6
166.6
161.5
156.2
150.7
144.9
138.8
132.3
125.2
117.4
108.9
99.4
88.9
64.3
34.9
2.6
-29.2
-57.4
-80.6
-99.4
-114.6
-127.0
-137.3
-146.0
-153.5
-160.1
-165.9
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Maximum Gain & Stability Characteristics
Tcase= +25°C, CW mode, VD=50V, ID_Q=100mA
40
4.0
35
Maximum Gain
3.0
25
20
2.0
15
10
K Factor
Max. Gain (dB)
30
1.0
K Factor
5
0
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Frequency (GHz)
Ref. : DSCHK015ASMA3021 - 21 Jan 13
6/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Typical Performance on Demonstration Board (Ref. 61499546)
Calibration and measurements are done on the connector reference accesses of the
demonstration boards.
Tcase = +25°C, CW mode
Measured Id, Pout, Gain & PAE
F = 5.6GHz, VDS = 50V, ID_Q = 100mA
50
1.0
PAE
40
0.9
0.8
Pout
35
0.7
Id
30
0.6
25
0.5
20
0.4
15
0.3
10
Drain Current (A)
Gain (dB), Pout (dBm) & PAE (%)
45
0.2
Gain
5
0.1
0
0.0
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Input Power (dBm)
Measured Pout, Gain & PAE
Pin=33dBm, VDS = 50V, ID_Q = 100mA
Gain (dB), Pout (dBm) & PAE (%)
50
45
Pout
40
35
PAE
30
25
20
15
Gain
10
5
0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Frequency (GHz)
Ref. : DSCHK015ASMA3021 - 21 Jan 13
7/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Demonstration Amplifier Low Frequency Equivalent Schematic
(Ref. 61499546)
+
+
Vd
Vg
J2
J3
Demonstration Amplifier / Bill of Materials (Ref. 61499546)
Designator
C1
C2
C3
C4
C5
C6
C7
C8
R1
R2
J1
J2, J3
Q1
-
Type
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Connector
Connector
Packaged Transistor
PCB
Ref. : DSCHK015ASMA3021 - 21 Jan 13
Value - Description
0.2pF, +/- 0.05pF, 0603
1.2pF, +/- 0.1pF, 0603
2pF, +/- 0.1pF, 0603
18pF, +/- 5%, 0603
39pF, +/- 5%, 0805
180nF, +/- 5%, 0805
10nF, +/- 5%, 0805
1µF, +/- 10%, 1204
360Ω, +/- 1%, 0603
220Ω +/- 1%, 0603
CMS 3cts
N
CHK015A-SMA
RO4003, Er=3.55, h=0.508mm
8/12
Qty
1
1
1
2
2
2
2
1
1
1
2
2
1
-
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Demonstration Amplifier Circuit (Ref. 61499546)
Ref. : DSCHK015ASMA3021 - 21 Jan 13
9/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Package outline
Tcase
(A)
(°C)
Tcase
(A)
(°C)
(A)
Tcase locates the reference point used to monitor the device temperature. This point has
been taken at the device / system interface to ease system thermal design.
(B)
Chamfered lead indicates the gate access of the packaged transistor.
Ref. : DSCHK015ASMA3021 - 21 Jan 13
10/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Recommended Assembly Procedure
CHK015A-SMA is available has a flange package to be bolt down onto a thermal heat sink
also used as main electrical ground. Use preferably screw M2 and flat washers.
Thermal and electrical resistance at the package to heat sink interface has to be as low as
possible. Thermal electrically conductive grease or conductive thin layer like indium sheets
are recommended between the package and the heat sink.
In case a thermal grease is selected, we recommend to use material offering thermal
conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness
should be about 25µm (1 mil).
Contact interface quality can be improved by cleaning process prior device mounting on the
heat-sink. Such operation will enhance the thermal and electrical contact by oxide removal at
each interface.
Package leads can be soldered on printed circuit board’s traces by using RoHS solder past.
Cavity depth and width to be performed into the heat-sink where the device will be mounted
are important to achieve the best performances. These dimensions have to be optimized in
order to minimize the distance between device and signal traces made on the printed circuit
board (PCB). But they also have to be calculated in order to accommodate device variations
in height. The following drawing gives the relationship between device dimensions (Hpack &
Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed
circuit-board configuration (HPCB)
Ref. : DSCHK015ASMA3021 - 21 Jan 13
11/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK015A-SMA
15W Power Packaged Transistor
Recommended environmental management
UMS products are compliant with the regulation in particular with the directives RoHS
N°2011/65 and REACh N°1907/2006. More environmental data are available in the
application note AN0019 also available at http://www.ums-gaas.com.
Recommended ESD management
Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD
sensitivity and handling recommendations for the UMS package products.
Ordering Information
Package:
CHK015A-SMA/XY
Tray: XY = 26
Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors
S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use
as critical components in life support devices or systems without express written approval from United
Monolithic Semiconductors S.A.S.
Ref. : DSCHK015ASMA3021 - 21 Jan 13
12/12
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
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