LINER LT4430ES6 Secondary-side optocoupler driver Datasheet

LT4430
Secondary-Side
Optocoupler Driver
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FEATURES
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DESCRIPTIO
600mV Reference (1.25% Over Temperature)
Wide Input Supply Range: 3V to 20V
Overshoot Control Function Prevents Output
Overshoot on Startup and Short-Circuit Recovery
High Bandwidth Error Ampliﬁer Permits Simple Loop
Frequency Compensation
Ground-Referenced OptoCoupler Drive
10mA OptoCoupler Drive with Current Limiting
Low Proﬁle (1mm) ThinSOTTM Package
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APPLICATIO S
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48V Input Isolated DC/DC Converters
Isolated Telecommunication Power Systems
Distributed Power Step-Down Converters
Ofﬂine Isolated Power Supplies
Industrial Control Systems
Automotive and Heavy Equipment
The LT®4430 drives the optocoupler that crosses the
galvanic barrier in an isolated power supply. The IC contains a precision-trimmed reference, a high bandwidth
error ampliﬁer, an inverting gain of 6 stage to drive the
optocoupler and unique overshoot control circuitry.
The LT4430’s 600mV reference provides ±0.75% initial
accuracy and ±1.25% tolerance over temperature. A high
bandwidth 9MHz error ampliﬁer permits simple frequency
compensation and negligible phase shift at typical loop
crossover frequencies. The optocoupler driver provides
10mA of output current and is short-circuit protected.
A unique overshoot control function prevents output
overshoot on startup and short-circuit recovery with a
single capacitor.
The LT4430 is available in the low proﬁle 6-lead SOT-23
package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
Simpliﬁed Isolated Synchronous Forward Converter
ISOLATION
BARRIER
VIN
•
+
•
+
Isolated Flyback Telecom Converter
Startup with Overshoot Control
(See Schematic on Page 20)
VOUT
VIN
50V/DIV
LT1952
FG
CG
SYNC
LTC3900
•
VCC
•
VCC
VIN
GND
OC
VOUT
5V/DIV
OVERSHOOT CONTROL
IMPLEMENTED
OPTO
LT4430
t = 5ms/DIV
COMP
4430 TA01b
FB
4430 TA01
4430f
1
LT4430
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Supply Voltage
VIN ........................................................................20V
FB Voltage .................................................... –0.3V to 6V
OPTO Short-Circuit Duration ............................ Indeﬁnite
Operating Junction Temperature Range (Note 2)
.......................................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
VIN 1
6 OPTO
GND 2
5 COMP
LT4430ES6
S6 PART
MARKING
4 FB
OC 3
S6 PACKAGE
6-LEAD PLASTIC SOT-23
TJMAX = 125°C, θJA = 250°C/W
LTBFY
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
SYMBOL
PARAMETER
VIN
Input Voltage Range
CONDITIONS
IIN
Supply Current
3V ≤ VIN ≤ 20V
●
VUVLO
Undervoltage Lockout Threshold
OC Held Low for VIN < VUVLO
●
VFB
Feedback Reference Voltage
3V ≤ VIN ≤ 20V
IFB
IOC
VFB Line Regulation
3V ≤ VIN ≤ 20V
FB Input Bias Current
FB = VFB
Overshoot Control Charging Current
MIN
●
VOC = 0V
●
●
1.9
MAX
V
3.9
mA
1.95
2.2
2.5
V
0.6
0.6045
V
0.6
0.6075
V
0.02
0.1
%
0.5925
–150
–75
–15
–8.5
nA
–5
0.93
OC Ampliﬁer Offset Voltage
FB = 0.3V
Error Ampliﬁer Open-Loop DC Gain
VCOMP = 0.8V to 1V
Error Ampliﬁer Unity-Gain Bandwidth
No Load (Note 4)
●
UNITS
20
0.5955
OC Clamp Voltage
AVOL
TYP
3
60
µA
V
48
mV
80
dB
9
MHz
Error Ampliﬁer Output Swing Low
FB = 1V
●
0.1
0.35
0.55
V
Error Ampliﬁer Output Swing High
FB = 0V
●
1.2
1.33
1.5
V
Error Ampliﬁer Output Source Current
FB = 0V, COMP = 1V
●
–800
–450
–225
Error Ampliﬁer Output Sink Current
FB = 1V, COMP = 1V
25
Opto Driver Inverting DC Gain
–6.4
Opto Driver –3dB Bandwidth
No Load (Note 4)
Opto Driver Output Swing Low
FB = 0V, COMP = Open
●
Opto Driver Output Swing High
VIN = 3V, FB = 1V, COMP = Open,
IOPTO = 10mA
●
VIN = 20V, FB = 1V, COMP = Open,
IOPTO = 10mA
●
–6
–5.6
600
0.5
5.6
V/V
kHz
0.85
VIN – 1.25 VIN – 1.05
4.2
µA
mA
V
V
7.5
V
4430f
2
LT4430
ELECTRICAL CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
ISC
Opto Driver Output
FB = 1V, COMP = Open, OPTO = 0V
●
10.5
22
45
UNITS
mA
FB = 0V, OPTO = 1.5V
●
150
350
650
µA
Short-Circuit Current (Sourcing)
Opto Driver Output Sink Current
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT4430 is guaranteed to meet performance speciﬁcations
from 0°C to 125°C. Speciﬁcations over the –40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
speciﬁed.
Note 4: This parameter is guaranteed by correlation and is not tested.
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TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout Threshold
vs Temperature
Quiescent Current vs Temperature
Feedback Reference Voltage vs
Temperature
0.606
3.0
4.0
0.605
0.604
0.603
2.5
3.0
2.5
VIN = 3V
2.0
VFB (V)
VUVLO (V)
0.602
VIN = 20V
2.0
0.601
0.600
0.599
0.598
0.597
1.5
1.5
0.596
0.595
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.0
–50 –25
0
4430 G01
0
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G02
4430 G03
FB Input Bias Current vs
Temperature
FB Voltage Line Regulation
0.6010
0.594
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
50
TA = 25°C
25
FB INPUT BIAS CURRENT (nA)
1.0
–50 –25
0.6005
VFB (V)
QUIESCENT CURRENT (mA)
3.5
0.6000
0.5995
0
–25
–50
–75
–100
–125
–150
–175
0.5990
0
2
4
6
8
10 12 14 16 18 20
VIN (V)
4430 G04
–200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G07
4430f
3
LT4430
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TYPICAL PERFOR A CE CHARACTERISTICS
OC Charging Current vs Input
Voltage
15
11
9
7
11
9
15
5
–50 –25
20
0
80
90
70
60
50
60
40
GAIN (dB)
80
70
Error Ampliﬁer Output Swing Low
vs Temperature
180
135
PHASE
90
30
GAIN
20
45
PHASE (°)
VOC – VFB (mV)
100
40
10
30
20
0
10
–10
0
–20
25 50 75 100 125 150
TEMPERATURE (°C)
1k
10k
1M
100k
FREQUENCY (Hz)
1.5
1.4
1.3
1.2
1.1
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G14
ERROR AMPLIFIER OUTPUT SOURCE CURRENT (µA)
ERROR AMPLIFIER OUTPUT SWING HIGH (V)
0.5
0.4
0.3
0.2
0.1
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G12
Error Ampliﬁer Output Swing High
vs Temperature
0
–45
50M
10M
4430 G11
1.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G10
Error Ampliﬁer Open Loop Gain
and Phase vs Frequency
50
0
4430 G09
OC Ampliﬁer Offset Voltage vs
Temperature
0
0.9
0.5
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G08
0
–50 –25
1.1
0.7
7
ERROR AMPLIFIER OUTPUT SWING LOW (V)
10
VIN (V)
1.3
13
5
5
1.5
VIN = 5V
OC CLAMP VOLTAGE (V)
13
OC CHARGING CURRENT (µA)
OC CHARGING CURRENT (µA)
15
0
OC Clamp Voltage vs
Temperature
OC Charging Current vs
Temperature
4430 G13
Error Ampliﬁer Output Source
Current vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G16
4430f
4
LT4430
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TYPICAL PERFOR A CE CHARACTERISTICS
Opto Driver Inverting DC Gain vs
Temperature
30
20
10
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
35
6.3
6.2
135
25
6.1
6.0
5.9
20
90
15
GAIN
10
5.8
0
5.7
0
–5
5.6
–50 –25
–10
0
8.0
1.3
1.2
VIN – VOPTO (V)
0.8
1.1
1.0
0.9
0.3
0.8
0.2
0.7
0.1
0.6
25 50 75 100 125 150
TEMPERATURE (°C)
0.5
–50 –25
0
7.0
6.5
6.0
5.5
5.0
4.5
0
25 50 75 100 125 150
TEMPERATURE (°C)
900
800
700
600
500
400
300
200
100
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G23
4430 G21
Opto Driver Output Short-Circuit
Current (Sourcing) vs Temperature
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
1000
0
VIN = 20V
IOPTO = 10mA
4430 G20
Opto Driver Output Sink Current
vs Temperature
0
–50 –25
7.5
4.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G19
OPTO DRIVER OUTPUT SINK CURRENT (µA)
0
OPTO DRIVER OUTPUT SWING HIGH (V)
VIN = 3V
1.4 IOPTO = 10mA
0.7
–45
10M
Opto Driver Output Swing High vs
Temperature
1.5
0.4
1M
100k
FREQUENCY (Hz)
4430 G18
Opto Driver Output Swing High vs
Temperature
0.9
0.5
10k
1k
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G17
1.0
0.6
45
5
Opto Driver Output Swing Low vs
Temperature
0
–50 –25
PHASE
30
GAIN (dB)
OPTO DRIVER INVERTING DC GAIN (V/V)
40
180
40
6.4
50
4430 G15
OPTO DRIVER OUTPUT SWING LOW (V)
Opto Driver Inverting Closed Loop
Gain and Phase vs Frequency
PHASE (°)
ERROR AMPLIFIER OUTPUT SINK CURRENT (mA)
Error Ampliﬁer Output Sink
Current vs Temperature
40
30
20
10
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4430 G22
4430f
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LT4430
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PI FU CTIO S
VIN (Pin 1): This is the input supply that powers all internal circuitry. The input supply range is 3V minimum
to 20V maximum and the typical input quiescent current
is 1.9mA. Connect a 1µF bypass capacitor directly from
VIN to GND.
GND (Pin 2): Analog Ground Pin. It is also the negative
sense terminal for the internal 0.6V reference. Connect the
external feedback divider network that terminates to ground
directly to this pin for best regulation and performance.
OC (Pin 3): Overshoot Control Pin. A typical 8.5µA current
source and a capacitor placed from this pin to GND controls
output voltage overshoot on startup and recovery from
short-circuit. The typical ramp time is (COC • 0.6V)/8.5µA.
If VIN is below VUVLO (its undervoltage lockout threshold),
the OC pin is actively held low. The OC pin also ties to the
overshoot control ampliﬁer output. This ampliﬁer monitors
the FB pin voltage and the error ampliﬁer output. If FB is
low due to a short-circuit fault condition, the COMP pin
goes high. Logic detects the error ampliﬁer COMP pin high
state and activates the overshoot control ampliﬁer. The
ampliﬁer responds by discharging the OC capacitor down
to the FB voltage plus a built-in offset voltage of 48mV. If
the short-circuit condition persists, the ampliﬁer maintains
the voltage on OC. If the short-circuit condition goes away,
the FB pin recovers under the control of the OC pin.
FB (Pin 4): This is the inverting input of the error ampliﬁer. The non-inverting input is tied to the internal 0.6V
reference. Input bias current for this pin is typically 75nA
ﬂowing out of the pin. This pin normally ties to a resistor
divider network to set output voltage. Tie the top of the
external resistor divider directly to the output voltage for
best regulation performance.
COMP (Pin 5): This is the output of the error ampliﬁer. The
error ampliﬁer is a true voltage-mode error ampliﬁer and
frequency compensation is performed around the ampliﬁer.
Typical LT4430 compensation schemes use series R-C in
parallel with C networks from the COMP pin to the FB pin.
COMP also ties to the overshoot control ampliﬁer logic
that detects if the COMP pin is at its high clamp level. The
logic activates the overshoot control ampliﬁer if COMP is
at its clamp level for longer than 1µs.
OPTO (Pin 6): This is the output of the ampliﬁer that
drives the optocoupler. The opto driver ampliﬁer uses an
inverting gain of six conﬁguration to drive the optocoupler
referenced to ground. Driving the optocoupler referenced
to GND accommodates low output voltages and eases
loop frequency compensation as the secondary feedback
path with a traditional “431” topology is eliminated. The
opto driver ampliﬁer sources a maximum of 10mA, sinks
350µA typically and is short-circuit protected.
4430f
6
LT4430
W
BLOCK DIAGRA
VIN
+
I1
12.5µA
VIN
STARTUP
BIAS AND
REFERENCE
GENERATOR
Q2
R3
15k
ERROR
AMP
Q3
OUT
–
+
1.1V
0.6V
OPTO
DRIVER
COMP
–
R4
90k
VIN
I2
12.5µA
Q7
GND
Q1
VIN
R1
2k
IOC
8.5µA
Q4
FB
R2
2k
Q5
V1
0.2V
V2
0.6V
–
DFB
+
–
LOGIC
AND
DELAY
OC
AMP
Q6
S1
NORMALLY
OPEN
+
–
+
UVLO
+
–
VOS
48mV
OC
4430 BD01
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APPLICATIO S I FOR ATIO
Block Diagram Operation
A precision voltage reference, a high-bandwidth error
ampliﬁer, an inverting optocoupler driver and an overshoot
control ampliﬁer comprise the LT4430. Referring to the
block diagram, a start-up circuit establishes all internal
current and voltage biasing for the IC. A precision-trimmed
bandgap generates the 600mV reference voltage and a
1.1V bias voltage for the optocoupler driver. Room temperature reference voltage accuracy is speciﬁed at ±0.75%
and operating temperature range tolerance is speciﬁed at
±1.25%. The 600mV reference ties to the non-inverting
input of the error ampliﬁer.
The LT4430 error ampliﬁer senses the output voltage
through an external resistor divider and regulates the
FB pin to 600mV. The FB pin ties to the inverting input
of the error ampliﬁer. The error ampliﬁer’s open loop DC
gain is 80dB and its unity-gain crossover frequency of
9MHz provides negligible phase shift at typical feedback
loop crossover frequencies. The error ampliﬁer is a true
voltage-mode ampliﬁer and frequency compensation connects around the ampliﬁer. Typical LT4430 compensation
schemes use series R-C in parallel with C networks from
the COMP pin to the FB pin.
The optocoupler driver ampliﬁes the voltage difference
between the COMP pin and the 1.1V bias potential applied
to its non-inverting terminal with an inverting gain of 6. This
signal drives the optocoupler referenced to GND. Driving
the optocoupler referenced to GND accommodates low
output voltages and simpliﬁes loop frequency compensation as the secondary feedback path with a traditional
“431” topology is eliminated. A resistor in series with the
optocoupler sets the optocoupler’s DC bias current. The
opto driver ampliﬁer sources a guaranteed maximum of
10mA, sinks 350µA typically and is short-circuit protected.
The optocoupler driver ampliﬁer’s typical –3dB bandwidth
is 600kHz. The optocoupler’s output crosses the galvanic
isolation barrier and closes the feedback loop to the primary-side controller.
4430f
7
LT4430
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APPLICATIO S I FOR ATIO
The LT4430 incorporates a unique overshoot control
function that allows the user to ramp the output voltage
on startup and recovery from short-circuit conditions,
preventing overshoot. A capacitor, connected from the OC
pin to GND and charged by internal 8.5µA current source
IOC, sets the ramp rate. On startup, Q1 actively holds the
OC capacitor low until VIN of the LT4430 reaches its typical undervoltage lockout threshold of 2.2V. Q1 then turns
off and the OC capacitor charges linearly. Q2 and Q3 OR
the OC pin voltage and the 600mV reference voltage at
the non-inverting terminal of the error ampliﬁer. The OC
pin voltage is the reference voltage for the error ampliﬁer
until it increases above 600mV. If the feedback loop is in
control, the FB pin voltage follows and regulates to the OC
pin voltage. As the OC pin voltage increases past 600mV,
the reference voltage takes control of the error ampliﬁer
and the FB pin regulates to 600mV. The OC pin voltage
increases until it is internally clamped by R2, Q6 and V1.
The OC pin’s typical clamp voltage of 0.93V ensures that
Q3 turns off. All of I1’s current ﬂows in Q2, matching I2’s
current in Q4.
In a short-circuit condition, the output voltage decreases to
something well below the regulated level. The error ampliﬁer reacts by increasing the COMP pin voltage, thereby
decreasing the drive to the optocoupler. The decreased
optocoupler bias signals the primary-side controller to
increase the amount of power it delivers in an attempt
to raise the output voltage back to its regulated value. As
long as the fault persists, the output voltage remains low.
The error ampliﬁer’s COMP pin voltage increases until it
reaches a clamp level set by Q7 and V2. Q7’s resultant
collector current drives internal logic that closes normally
open switch S1. This action activates the overshoot control
ampliﬁer which employs a unity-gain follower conﬁguration. The overshoot control ampliﬁer monitors the FB pin
voltage and, on S1’s closing, pulls the OC pin voltage
down to the FB pin voltage plus a built-in offset voltage
of typically 48mV. The built-in offset voltage serves two
purposes. First, the offset voltage prevents the overshoot
control ampliﬁer from interfering with normal transient
operating conditions. Second, the offset voltage biases
the feedback loop so that if the short-circuit condition
ends, the feedback loop immediately starts to increase
the output voltage to its regulated value.
If the fault condition ceases, the output voltage increases.
In response, the error ampliﬁer COMP pin’s voltage
decreases. This action opens switch S1, deactivates the
overshoot control ampliﬁer and allows the OC pin capacitor
to charge. The FB pin voltage increases quickly until the
FB pin voltage exceeds the OC pin voltage. The feedback
loop increases the drive to the optocoupler until the FB
pin follows and regulates to the OC pin voltage. Again, as
the OC pin voltage increases past 600mV, the reference
voltage takes control of the error ampliﬁer and the FB pin
regulates to 600mV.
Generating a VIN Bias Supply
Biasing an LT4430 is crucial to proper operation. If the
overshoot control (OC) function is not being used and the
output voltage is greater than 3.3V, the IC may be biased
from VOUT. In these cases, it is the user’s responsibility to
verify large-signal startup and fault recovery behavior.
If the overshoot control function is being used or the
output voltage is below the LT4430’s minimum operating voltage of 3V, employing an alternate bias method is
necessary. The LT4430’s undervoltage lockout (UVLO)
circuitry, controlled by VIN, resets and holds the OC pin
capacitor low for VIN less than 2.2V. When VIN increases
above 2.2V, the circuit releases the OC pin capacitor. The
LT4430’s supply voltage must come up faster than the
ouput voltage to assert loop control and limit output voltage overshoot. In most cases, a few simple components
accomplish this task. Adding a few biasing components
to control overshoot is advantageous. Let’s examine bias
circuits for different topologies.
4430f
8
LT4430
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APPLICATIO S I FOR ATIO
Figures 1a to 1e illustrate bias supply circuits for the
ﬂyback converter. Figure 1a shows the typical ﬂyback
output connection. Figures 1b and 1c exhibit equivalent
circuit performance but rotate the rectiﬁer connection to
the ground-referred side. This connection permits the user
to take advantage of the transformer secondary’s forward
behavior when the primary-side switch is on.
Figures 1d to 1e illustrate the bias generator circuit.
VIN • N volts appear across the secondary winding when
the primary-side switch is on. D2 forward biases and C1
charges. During this time, the secondary-voltage is in
series with VOUT and C1 ultimately charges to (VIN • N +
VOUT – VF). VF is the forward voltage of D2. When VOUT
is zero at startup, VIN • N volts exists to charge C1. C1 is
generally much smaller in value than COUT and the bias
supply starts up ahead of VOUT. R1 in Figures 1d and
1e limits peak charging currents, lowering D2’s current
rating. R1 also ﬁlters C1 from peak-charging to the voltage spikes induced by the secondary winding’s leakage
inductance. Between 1Ω to 10Ω is generally sufﬁcient. R1
is usually necessary if C1 is a low ESR ceramic capacitor
or if the transformer has high leakage inductance. It may
be possible to eliminate R1 if C1 is a low cost, high ESR,
surface-mount tantalum.
VIN variation changes the bias supply in Figure 1d. Depending on VOUT, the transformer turns ratio N and VIN range,
the bias supply may exceed the LT4430’s 20V VIN absolute
maximum rating. If this occurs, two solutions exist. One
is to tap the secondary-side inductor to create a lower
voltage from which to rectify as illustrated in Figure 2a.
The bias voltage decreases to (VIN • N1/N + VOUT – VF).
This solution relies on secondary-side pins being available
for the tap point.
The second solution is to make a preregulator as shown
in Figure 2b. In this example, the bias supply equals (VZ1
– VBE). Select R2 to bias zener diode Z1 and to supply
base current to QBS. Resistor R3 (on the order of a few
hundred ohms), in series with Q5’s base, suppresses
possible high frequency oscillations depending on QBS’s
selection. The preregulator circuit has additional value for
fully synchronous converters. Fully synchronous converters require gate drivers to control the secondary-side
MOSFETs turn on and turnoff. The gate driver circuitry
requires supply current in the range of 10mA to 100mA
depending on the gate driver supply voltage, MOSFET size
and switching frequency. The preregulator bias supply is
ideal for powering both the LT4430 and the gate driver
T1
T1
VIN
VIN
T1
VOUT
•
D1
VIN
COUT
VOUT
•
COUT
•
COUT
•
1:N
4430 F01a
Figure 1a. Typical Flyback
Converter Connection
Q1
1:N
•
1:N
VOUT
•
SYNC
D1
4430 F01b
4430 F01c
Figure 1c. Synchronous Flyback
Converter Connection
Figure 1b. Equivalent Flyback
Converter Connection
T1
T1
VIN
VIN
VOUT
•
VOUT
•
COUT
COUT
•
1:N
1:N
D1
D2
*OPTIONAL SEE TEXT
•
Q1
SYNC
R1*
LT4430
VBIAS
C1
4430 F01d
Figure 1d. Flyback Converter with
Bias Generator
D2
*OPTIONAL SEE TEXT
R1*
LT4430
VBIAS
C1
4430 F01e
Figure 1e. Synchronous Flyback with
Bias Generator
4430f
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circuitry, especially since the gate drivers typically use a
supply voltage between 5V to 12V. The preregulator circuit
ﬁnds wide use in fully synchronous forward converters,
push-pull converters and full-bridge converters.
single-switch forward converter. In the ﬂyback converter
of Figure 1d, the bias supply is proportional to VIN and
VOUT. However, in the forward converter, L1’s presence
decouples the bias supply from VOUT. In Figure 3a, the
bias supply equals (VIN • N – VF). In Figure 3b, the bias
supply equals (VIN • N1/N – VF). In Figure 3c, the bias
supply equals (VZ1 – VF).
Generate a bias supply for a forward converter using similar
techniques to that of the ﬂyback converter. Figure 3a to 3c
detail the three common bias circuits for the synchronous
T1
T1
VIN
VOUT
VOUT
•
N1
VIN
•
•
•
1:N
COUT
D2
N2
•
R1*
R2
D1
QBS
C1
1:N
N = N1 + N2
*OPTIONAL SEE TEXT
COUT
D1
D2
Z1
LT4430
VBIAS
C1
R1*
R3*
LT4430
VBIAS
C2
*OPTIONAL SEE TEXT
4430 F02a
4430 F02b
Figure 2a. Flyback Converter with Tapped Secondary Bias
Figure 2b. Flyback Converter with Preregulator Bias
D1
LT4430
VBIAS
C1
R1*
T1
VIN
•
•
1:N Q1
VOUT
L1
FG
Q2
COUT
CG
*OPTIONAL SEE TEXT
4430 F03a
Figure 3a. Typical Single-Switch Synchronous Forward
Converter with Bias Generator
D1
R1*
LT4430
VBIAS
C1
D1
R1*
R2
QBS
T1
•
L1
N2
VIN
C1
VOUT
COUT
R3*
Z1
C2
LT4430
VBIAS
•
T1
VIN
•
•
•
L1
N1
1:N
Q1
N = N1 + N2
FG Q2
CG
*OPTIONAL SEE TEXT
4430 F03b
Figure 3b. Single-Switch Synchronous Forward Converter
with Tapped Secondary Bias Generator
10
1:N Q1
FG
Q2
VOUT
COUT
CG
*OPTIONAL SEE TEXT
4430 F03c
Figure 3c. Single-Switch Synchronous Forward Converter
with Preregulator Bias Generator
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straints such as a very wide input voltage range may force
employment of other biasing circuits. Other methods of
generating the bias supply may include an additional
transformer or output inductor winding, low-cost linear
regulators, discrete or monolithic charge pumps and
buck/boost regulators. However, if the bias supply gets this
complicated, a quick chat with your local LTC applications
engineer may result in a simpler solution.
Figures 4a to 4d demonstrate bias supply circuits for the
fully-synchronous push-pull topology. Biasing for fullbridge schemes is identical to the push-pull circuits with
the obvious difference in the primary-side drive. In Figure
4a, the bias supply equals (VIN • N – VF). In Figure 4b and
4d, the bias supply equals (2 • VIN • N – VF). In Figure 4c
and 4e, the bias supply equals (VZ1 – VF).
In general, one of the simple, low-cost biasing schemes
sufﬁces for LT4430 applications. However, design conT1
T1
Q2
•
R1*
D1
•
•
ME
•
VIN
L1
•
•
LT4430
VBIAS
C1
LT4430
VBIAS
C1
R1*
D1
Q2
VOUT
ME
VIN
COUT
VOUT
L1
COUT
•
Q1
•
1:N
Q1
1:N
*OPTIONAL SEE TEXT
MF
*OPTIONAL SEE TEXT
MF
4430 F04a
4430 F04b
Figure 4a. Typical Synchronous Push-Pull Converter
with Bias Generator
D1
R1*
Figure 4b. Typical Synchronous Push-Pull Converter
with 2x Bias Generator
D1
R2
R1*
R2
QBS
C1
R3*
Z1
C2
QBS
C1
LT4430
VBIAS
R1*
D1
T1
•
ME
•
VOUT
COUT
Q2
VOUT
VIN
COUT
•
COUT
•
•
1:N
*OPTIONAL SEE TEXT
•
L1
Q1
1:N
MF
*OPTIONAL SEE TEXT
4430 F04c
Figure 4c. Typical Synchronous Push-Pull
Converter with Preregulator Bias
ME
•
VOUT
VIN
Q1
1:N
MF
L2
ME
•
L1
•
•
L2
Q2
•
LT4430
VBIAS
C2
T1
•
VIN
Z1
LT4430
VBIAS
C1
T1
Q2
R3*
L1
Q1
MF
*OPTIONAL SEE TEXT
4430 F04e
4430 F04d
Figure 4d. Typical Synchronous
Push-Pull Current-Doubler Converter
with Bias Generator
Figure 4e. Typical Synchronous
Push-Pull Current-Doubler Converter
with Preregulator Bias
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Setting Output Voltage
Figure 5 shows how to program the power supply output
voltage with a resistor divider feedback network. Connect
the top of R1 to VOUT, the tap point of R1/R2 to FB and
the bottom of R2 directly to GND of the LT4430. The FB
pin regulates to 600mV and has a typical input pin bias
current of 75nA ﬂowing out of the pin.
The output voltage is set by the formula:
VOUT = 0.6V • (1 + R1/R2) – (75nA) • R1
VOUT
R1
75nA
Most optocoupler datasheets loosely specify the gain,
or current transfer ratio (CTR), between the input diode
and the output transistor. CTR is a strong function of the
input diode current, temperature and time (aging). Aging degrades the LED’s brightness and accelerates with
higher operating current. CTR variation directly affects the
overall system loop gain and the design must account for
total variation. To make an effective optical detector, the
output transistor design maximizes the base area to collect light energy. This constraint yields a transistor with a
large collector-to-base capacitance. This capacitance can
inﬂuence the circuit’s performance based on the output
transistor’s hookup.
The two most common topologies for the output transistor of the optocoupler are the common-emitter and
common-collector conﬁgurations. Figure 6a illustrates
the common-emitter design with the output transistor’s
collector connected to the output of the primary-side
controller’s error ampliﬁer.
FB
R2
4430 F05
Figure 5. Setting Output Voltage
OptoCoupler Feedback and Frequency Compensation
An isolated power supply with good line and load regulation generally employs the following strategy. Sense and
compare the output voltage with an accurate reference
potential. Amplify and feed back the error signal to the
supply’s control circuitry to correct the sensed error. Have
the error signal cross the isolation barrier if the control
circuitry resides on the primary-side. Coupling this signal
requires an element that withstands the isolation potentials
and still transfers the loop error signal.
Optocouplers remain in prevalent use because of their
ability to couple DC signals. Optocouplers typically consist of an input infrared light emitting diode (LED) and an
output phototransistor separated by an insulating gap.
In this example, the error ampliﬁer is typically a transconductance ampliﬁer with high output impedance and
RC dominates the impedance at the VC node. Frequency
compensation for this feedback loop is directly affected by
the output transistor’s collector-to-base capacitance as it
introduces a pole into the feedback loop. This pole varies
considerably with the transistor’s operating conditions. In
many cases, this pole limits the achievable loop bandwidth.
Cascoding the output transistor signiﬁcantly reduces the
effects of this capacitance and increases achievable loop
bandwidth. However, not all designs have the voltage
headroom required for the cascode connection or can
tolerate the additional circuit complexity. The open loop
transfer function from the output voltage to the primary-
ISOLATION
BARRIER
VCC
PRIMARY-SIDE
ERROR AMP
RC
+
VREF
FB
–
LT4430
OPTO
+
OPTO
DRIVER
+
ERROR
AMP
–
RK
R4
15k
CK
VC
VOUT
1.1V
–
COMP
0.6V
R1
R5
90k
CC
OPTO
C1
FB
R2
C3
R3
C2
4430 F06a
Figure 6a. Frequency Compensation with Optocoupler Common-Emitter Conﬁguration
12
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APPLICATIO S I FOR ATIO
side error ampliﬁer’s output is:
VC
VOUT
⎛ R2 ⎞
–A • ⎜
⎟ • (1 + s • R1• C1)• (1 + s • R3 • C 3)
⎝ R1 + R2⎠
=
•
⎛
(C 2 • C 3) ⎞
[s • A • R1• (C 2 + C 3)]• ⎜ 1 + s • R3 •
⎟
⎝
(C 2 + C 3)⎠
CTR • RC
(1 + s • RK • C K )
•
•
6•
⎛
⎞ (RK + RD )
(RK • RD )
• CK⎟
⎜ 1+ s •
⎝
(RK + RD )
⎠
1
•
⎛
⎡ (CTR • RC )
⎤⎞
⎜ 1 + s • rπ • ⎢ (R + R ) • C CB + C BE ⎥⎟
⎝
D
⎣ K
⎦⎠
1
(1+ s • RC • C C )
where:
the poles and zeroes are used. Also, different combinations
of poles and zeroes can result in the same small signal
gain-phase characteristics but demonstrate dramatically
different large-signal behavior.
The common-collector conﬁguration eliminates the miller
effect of the output transistor’s collector-to-base capacitance and generally increases achievable loop bandwidth.
Figure 6b illustrates the common-collector design with the
output transistor’s emitter connected to the inverting input
of the primary-side controller’s error ampliﬁer.
In this example, the error ampliﬁer is typically a voltage
error ampliﬁer conﬁgured as a transimpedance ampliﬁer.
The optocoupler transistor’s emitter provides feedback
information directly to the FB pin and the resistor RE from
FB to GND sets the DC bias condition for the optocoupler.
The open loop transfer function from the output voltage
to the primary-side error ampliﬁer’s output is:
A = LT4430 open loop DC Gain
VC
VOUT
RD = Optocoupler diode equivalent small-signal
resistance
CTR = Optocoupler AC current transfer ratio
CCB = Optocoupler non-linear collector-to-base
capacitor
CBE = Optocoupler non-linear base-to-emitter
capacitor
rπ = Optocoupler small-signal base-to-emitter
resistor
Figure 6a and its transfer function illustrate most of the
possible poles and zeroes that can be set and are shown
for the sake of completeness. In a practical application, the
transfer function simpliﬁes considerably because not all
Figure 6b and its transfer function illustrate most of the
possible poles and zeroes that can be set and are shown
for the sake of completeness. In a practical application,
the transfer function simpliﬁes considerably because not
all the poles and zeroes are used.
ISOLATION
BARRIER
PRIMARY-SIDE
ERROR AMP
+
VC
LT4430
VCC
OPTO
RK
VREF
+
+
ERROR
AMP
–
R4
15k
FB
OPTO
VOUT
1.1V
OPTO
DRIVER
CK
–
⎛ R2 ⎞
–A • ⎜
⎟ • (1 + s • R1• C1)• (1 + s • R3 • C 3)
⎝ R1 + R2⎠
=
•
⎛
(C 2 • C 3) ⎞
[s • A • R1• (C 2 + C 3)]• ⎜ 1 + s • R3 •
⎟
⎝
(C 2 + C 3)⎠
CTR • RC
(1 + s • RK • C K )
•
•
6•
⎛
⎞ (RK + RD )
(RK • RD )
• CK⎟
⎜ 1+ s •
⎝
⎠
(RK + RD )
1
1
•
(1+ s • rπ • C BE ) (1+ s • RC • C C )
–
COMP
0.6V
R1
C1
FB
R5
90k
R2
C3
R3
RC
CC
RE
C2
4430 F06b
Figure 6b. Frequency Compensation with Optocoupler Common-Collector Conﬁguration
4430f
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In both conﬁgurations, the terms RD, CTR, rπ, CCB and CBE.
vary from part to part and also change with bias current.
For most optocouplers, RD is 50Ω at a DC bias of 1mA,
and 25Ω at a DC bias of 2mA. CTR is the small signal
AC current transfer ratio. As an example, the Fairchild
MOC207 optocoupler has an AC CTR around 1, even
though the DC CTR is much lower when biased at 1mA
or 2mA. Most optocoupler datasheets do not specify the
terms CCB, CBE and rπ and values must be obtained from
empirical measurements.
This frequency compensation discussion only addresses
the transfer function from the output back to the control
node on the primary-side. Compensation of the entire
feedback loop must combine this transfer function with
the transfer function of the power processing circuitry,
commonly referred to as the modulator. In an isolated
power supply, the modulator’s transfer function depends
on topology (ﬂyback, forward, push-pull, bridge), current
or voltage mode control, operation in discontinuous or
continuous mode, input/output voltage, transformer turns
ratio and output load current. It is beyond this datasheet’s
scope to detail the transfer functions for all of the various combinations. However, the power supply designer
must fully characterize and understand the modulator’s
transfer function to successfully frequency compensate
the feedback loop for all operating conditions.
OptoCouplers
Optocouplers are available in a wide variety of package
styles and performance criteria including isolation rating,
CTR, output transistor breakdown voltage, output transistor
current capability, and response time. Table 1 lists several
manufacturers of optocoupler devices, although this is by
no means a complete list.
Table 1. Optocoupler Vendors
VENDOR
PHONE
URL
Agilent Technologies
800-235-0312
www.agilent.com
Fairchild Semiconductor
207-775-8100
www.fairchildsemi.com
Isocom
214-495-0755
www.isocom.com
Kodenshi Korea Corp.
82-63-839-2111
www.kodenshi.co.kr
NEC
81-44-435-1588
www.ncsd.necel.com
Sharp Microelectronics
877-343-2181
www.sharpsma.com
Toshiba
949-455-2000
www.toshiba.com
Vishay
402-563-6866
www.vishay.com
Setting Overshoot Control Time
Figure 7 shows how to calculate the overshoot time by
connecting a capacitor from the OC pin to GND.
The overshoot control time, tOC, is set by the formula:
tOC = (COC • 0.6V)/8.5µA
The OC pin requires a minimum capacitor of 100pF due to
stability requirements with the overshoot control ampliﬁer.
This yields a minimum time of 7µs which is generally on
the order of a few cycles of the switching regulator. Using the minimum capacitor value results in no inﬂuence
on startup characteristics. Larger OC capacitor values
increase the overshoot control time and only increase the
ampliﬁer stability. Do not modulate the overshoot control
time by externally increasing the OC charging current or
by externally driving the OC pin.
Choosing the Overshoot Control (OC) Capacitor Value
As discussed in the frequency compensation section,
the designer enjoys considerable freedom in setting the
feedback loop’s pole and zero locations for stability. Different pole and zero combinations can produce the same
gain-phase characteristics, but result in noticeably different
large-signal responses. Choosing frequency compensation
values that optimize both small-signal and large-signal
responses is difﬁcult. Compromise values often result.
Power supply startup and short-circuit recovery are the
worst-case large signal conditions. Input voltage and
output load characteristics heavily inﬂuence power supply
behavior as it attempts to bring the output voltage into
regulation. Frequency compensation values that provide
stable response under normal operating conditions can
allow severe output voltage overshoot to occur during
startup and short-circuit recovery conditions. Large overshoot often results in damage or destruction to the load
circuitry being powered, not a desirable trait.
VIN
IOC
8.5µA
OC
COC
4430 F07
Figure 7. Setting Overshoot Control Time
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The LT4430’s overshoot control circuitry plus one external
capacitor (COC) provide independent control of startup
and short-circuit recovery response without compromising small-signal frequency compensation. Choosing
the optimum COC value is a straightforward laboratory
procedure. The following description and set of pictures
explain this procedure.
Before choosing a value for the OC pin capacitor, complete
the remainder of the power supply design. This process
includes evaluating the chosen VIN bias generator topology
(please consult prior applications information section)
and optimizing frequency compensation under all normal
operating conditions. During this design phase, set COC
to its minimum value of 100pF. This ensures negligible
interaction from the overshoot control circuitry. Once these
steps are complete, construct a test setup that monitors
startup and short-circuit recovery waveforms. Perform this
testing with the output lightly loaded. Light load, following
full slew operation, is the worst-case as the feedback loop
transitions from full to minimal power delivery.
As an example, refer to the schematic on the last page
illustrating the 5V, 2A isolated ﬂyback converter. All of
the following photos are taken with VIN = 48V and ILD =
20mA. Figure 8a demonstrates the power supply startup
and short-circuit recovery behavior with no overshoot
control compensation (COC = 100pF minimum). The 5V
output overshoots by several volts on both startup and
short-circuit recovery due to the conservative nature of
the small-signal frequency compensation values.
Next, increase COC’s value. Either use a capacitor substitution box or solder each new value into the circuit. Monitor
the startup and short-circuit recovery waveforms. Note
any changes. Figures 8b to 8e illustrate what happens as
COC increases. In general, overshoot decreases as COC
increases.
COC = 0.0168µF in Figure 8b begins to affect loop dynamics, but startup still exhibits about 1.5V of overshoot.
Short-circuit recovery is considerably more damped. COC
= 0.022µF in Figure 8c damps startup overshoot to 0.5V
and short-circuit recovery remains similar to that of Figure
8b. COC = 0.033µF in Figure 8d provides under 100mV
of overshoot and short-circuit recovery is slightly more
damped. COC = 0.047µF in Figure 8e achieves zero over-
shoot at the expense of additional damping and delay time
in short-circuit recovery. In this example, COC = 0.033µF
provides the best value for both startup and short-circuit
recovery. Figure 8f provides an expanded scale of the
waveforms. After a COC value is selected, check startup
and short-circuit recovery over the VIN supply range and
with higher output load conditions. Modify the value as
necessary.
Startup and short-circuit recovery waveforms for various
designs will differ from the photos shown in this example.
Factors affecting these waveforms include the isolated
topology chosen, the primary-side and secondary-side
bias circuitry and input/output conditions. For instance,
in many isolated power supplies, a winding on the main
power transformer bootstraps the supply voltage for the
primary-side control circuitry. Under short-circuit conditions, the primary-side control circuitry’s supply voltage
collapses, generating a restart cycle. Recovery from
short-circuit is therefore identical to startup. In the ﬂyback
example discussed, the primary-side control circuitry is
always active. Switching never stops in short-circuit. The
LT4430 error ampliﬁer COMP pin changes from its low
clamp level to its higher regulating value during startup
and changes from its high clamp level to its lower regulating point during short-circuit recovery. This large-signal
behavior explains the observed difference in the startup
versus short-circuit recovery waveforms.
A ﬁnal point of discussion involves the chosen COC value.
LTC recommends that the designer use a value that controls overshoot to the acceptable level, but is not made
overly large. The temptation arises to use the overshoot
control function as a power supply “soft-start” feature.
Larger values of COC, above what is required to control
overshoot, do result in smaller dV/dt rates and longer
startup times. However, large values of COC may stall the
feedback loop during startup or short-circuit recovery,
resulting in an extended period of time that the output
voltage “ﬂatspots”. This voltage shelf may occur at an
intermediate value of output voltage, promoting anomalous
behavior with the powered load circuitry. If this situation
occurs with the desired COC value, solutions may require
circuit modiﬁcations. In particular, bias supply holdup
times are a prime point of concern as switching stops
during these output voltage ﬂatspots. As a reminder,
4430f
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the purpose of this LT4430 circuitry is to control and
prevent excessive output voltage overshoot that would
otherwise induce damage or destruction, not to control
power supply timing, sequencing, etc. It is ultimately the
STARTUP
VOUT
5V/DIV
user’s responsibility to deﬁne the acceptance criteria for
any waveforms generated by the power supply relative to
overall system requirements.
STARTUP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV
t = 5ms/DIV
COC = 0.0168µF = 0.01µF + 6.8nF
4430 F08a
COC = 100pF
Figure 8a. Startup and Short-Circuit Recovery Waveforms
Figure 8b. Startup and Short-Circuit Recovery Waveforms
STARTUP
VOUT
5V/DIV
STARTUP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV
4430 F08b
t = 5ms/DIV
4430 F08c
COC = 0.022µF
4430 F08d
COC = 0.033µF
Figure 8c. Startup and Short-Circuit Recovery Waveforms
Figure 8d. Startup and Short-Circuit Recovery Waveforms
STARTUP
VOUT
5V/DIV
STARTUP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV
t = 5ms/DIV
4430 F08e
COC = 0.047µF
Figure 8e. Startup and Short-Circuit Recovery Waveforms
4430 F08f
COC = 0.033µF
Figure 8f. Zoom In of Waveforms with Selected COC = 0.033µF
4430f
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C6
0.1µF
R7
33k
C5
0.47µF
R5
114k
R8
33k
R6
33k
R4
13.2k
R11
1.2k
R10
22k
36V TO 72V
VIN
NC
R9
33k
R3
370k
4
2
1
6
5
9
3
7
C1
2.2µF
100V
GND
BLANK
SYNC
FB
COMP
SOUT
ISENSE
OC
LT1952
VREF
DELAY
SS_MAXDC PGND
VIN
SOUT
ROSC
SD_VSEC
D1
12V
R1
82k
R12
39k
C3
2.2µF
VU1
VU1
D2
18V
Q1
BCX55
C7
220pF
D4
BAT760
C2
1µF
R26
10Ω
R14
0.008Ω
C4
1nF
Q2
PH21NQ15
x2
D3
BAS516
COUT = TDK
D1, D2, D7 = PHILIPS
Q1, Q2 = PHILIPS
L1 = PULSE ENGINEERING PB2020.103
T1 = PULSE ENGINEERING
T2 = COILCRAFT Q4470-B
16
10
11 R13
680Ω
12
13
8
15
14
R2
47k
VU1
4
2
4
2
•
T2
R21
330Ω
NEC
PS2701
R22
330Ω
C11
1µF
VBS
Q4
PH20100
8, 11
• 7, 10
C17
2200pF
250V
•
•
•
PA0741
T1
ISOLATION
BARRIER
8
6
4
5
C14
33nF
C13
1µF
VBS
SYNC
GND
CG
CS–
TIMER
CS
3
2
1
7
2
1
3
OC
GND
VIN
R19
10k
R18
10k
R17
10k
OPTO
FB
COMP
LT4430
C9
10nF
100V
D6
B0540W
Q5
PH20100
CS+
D5
B0540W
C8
6.8nF
100V
LTC3900
VCC
FG
R15
2.2Ω
200W, 26V, 95% Efﬁcient Base Station Converter
4
5
6
COUT
22µF
50V
X7R
4430 TA03a
C15
R23 2.2nF
8.2k
C16
10pF
C12
1nF
C10
1µF
VBS
Q3
BCX55
R20
15k
VBS
L1
10µH
D7
8.2V
R16
1k
R25
6.04k
1%
R24
26.1k
1%
26V
8A
LT4430
TYPICAL APPLICATIO S
4430f
17
U
+VIN
93
94
95
96
97
–VIN
6
8
66.5k
1.5nF
1µF
15
5
13 7
8
UVLO
FB GND CT
10k
270pF 33k
16
12 14
68nF
0.47µF
1
VREF
9
150k
SPRG RLEB SS DPRG
SDRB
VCC
DRVB
ISNS
DRVA
LTC3723EGN-1
R2
0.03Ω
1.5W
1.5k
2
B
R1
0.03Ω
1.5W
Si7852DP
4
4
A
2
B
243k
330pF
11
22nF
6
0.1µF
D6
D5
6
1
5
3
4
2
8
5
C4
2.2nF
250V
MOC207
1.1k
5
2
1
7
SYNC
CSF+
4.7nF
6
5
OPTO
14 15
6
CSE+
VIN
1
8
2
GND
10
OC
FB
3
4
470pF
1.5k
4
VE
VF
L6
1.25µH
CSE–
5
VOUT
1k
1/4W
16
C1, C2
47µF
16V
x2
3
PVCC
1
–VOUT
1µF
42.2k
1µF
VOUT
1µF
MMBT3904
100Ω
–VOUT
12V/20A
VOUT
1µF, 100V TDK C3225X7R2A105M
C1, C2: SANYO 16TQC47M
C3: AVX TPSE686M020R0150
C4: MURATA GHM3045X7R222K-GC
D1: DIODES INC. ES1B
D3-D6: BAS21
D7: MMBZ5240B
L4: COILCRAFT DO1608C-105
L5: COILCRAFT DO1813P-561HC
L6: PULSE PA1294.132 OR
PANASONIC ETQP1H1R0BFA
R1, R2: IRC LRC2512-R03G
T1: PULSE PA0805.004
T2: PULSE PA0785
470pF
7
TIMER
–VOUT
604Ω
1%
11.5k
1%
4430 TA03b
22nF
13
2
+
1nF
100V
10
1W
ME ME2 VCC
866Ω
GND PGND GND2 PGND2
LTC3901EGN
MF MF2
LT4430ES6
COMP
15nF
CSF–
12
1k
1%
VE
Si7370DP
x2
1k
1/4W
1k
1%
866Ω
1µF
100V
D1
6.19k
1/4W
1%
VF
VE
6.19k
1/4W
1%
11
VF
Si7370DP
x2
220pF
100Ω
9
11
9
T1
4T:6T(65µHMIN):6T:2T:2T
T2
1(1.5mH):0.5
1
4
Si7852DP
Si7852DP
L4
1mH
ISNS
22Ω
10
+
12V
750Ω
COMP
CS
SDRA
3
C3
68µF
20V
0.1µF
VCC
6
INP BOOST
LTC4440ES6
5 4.7Ω
TG
GND TS
6
A
0.1µF
20
200Ω
1/4W
4
3
D3
•
30k
1/4W
12V
2
Si7852DP
A
1
12V
•
464k
D4
VCC
6
INP BOOST
LTC4440ES6
5 4.7Ω
TG
GND TS
VIN
3
1
12V
18
56VIN
48VIN
42VIN
B
1µF
100V
x3
VIN
10
12
14
16
LOAD CURRENT (A)
1µF
100V
L5
0.56µH
•
•
42V TO 56V
EFFICIENCY (%)
•
•
•
18
•
LTC3723-1 240W 42VIN to 56VIN to 12V/20A Isolated 1/4 Brick (2.3" × 1.45")
D7
10V
1k
LT4430
TYPICAL APPLICATIO S
4430f
U
LT4430
U
PACKAGE DESCRIPTIO
S6 Package
6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1634)
0.62
MAX
2.80 – 3.10
(NOTE 4)
0.95
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.60 – 3.00 1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.25 – 0.50
TYP 6 PLCS
NOTE 3
0.95 BSC
0.90 – 1.30
0.20 BSC
0.90 – 1.45
DATUM ‘A’
0.35 – 0.55 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. PACKAGE EIAJ REFERENCE IS SC-74A (EIAJ)
1.90 BSC
0.09 – 0.15
NOTE 3
S6 SOT-23 0502
ATTENTION: ORIGINAL SOT23-6L PACKAGE.
MOST SOT23-6L PRODUCTS CONVERTED TO THIN SOT23
PACKAGE, DRAWING # 05-08-1636 AFTER APPROXIMATELY
APRIL 2001 SHIP DATE
4430f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT4430
U
TYPICAL APPLICATIO
5V, 2A Isolated Flyback Telecom Converter Startup Waveforms with and without Overshoot Control Implemented
ISOLATION
BARRIER
36V TO 72V
VIN
R1
220k
C1
1µF
100V
D1
PDZ-9.1B
9.1V
–VIN
ITH/SHDN
Q2
MMBTA42
ITH/RUN
GND
R2
100k
CTX-02-15242
T1
8.5V
2
D2
BAS516
4
Q1
FDC2512
NGATE
LTC3803
FB
SENSE
C2
1µF
10V
CO1
100µF
6.3V
• 11, 12
CO2
100µF
6.3V
5V
2A
CO3
100µF
6.3V
D4
UPS840
R4
220Ω
R7
11k
1%
D5
MBR0530
RCS
0.068Ω
8.5V
R5
6.8k
D3
BAS516
C1 = TDK, X7R
CO1, C02, C03 = TDK, X5R
D1, D2, D3 = PHILIPS
D4 = MICROSEMI
Q1 = FAIRCHILD
Q2 = DIODES, INC.
T1 = COOPER
MOC207 = FAIRCHILD
9, 10
C3
150pF
200V
R3
4.7k
VCC
•
R10
680Ω
C8
0.047µF
C5
1µF
VIN
C6
0.033µF
GND
MOC207
OC
C7
OPTO R9
0.1µF
1k
LT4430
COMP
R8
1500Ω
1%
FB
R6
470k
4430 TA02
C4
2200pF
250V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1693
High Speed Single/Dual N-Channel MOSFET Drivers
CMOS Compatible Input, VCC Range: 4.5V to 13.2V
LTC1698
Isolated Secondary Synchronous Rectiﬁer Controller
Pulse Transformer Synchronization, Optocoupler Driver
LT1950
Forward Controller
Programmable Volt-Second Clamp and Slope Compensation
LT1952
Single-Switch Synchronous Forward Controller
Synchronous Output Driver, Precision Current Limit, Programmable
Volt-Second Clamp and Slope Compensation
LT3710
Secondary Side Synchronous Post Regulator
Generates Regulated Auxiliary Output in Isolated DC/DC Converters,
Dual N-Channel MOSFET Synchronous Drivers
LTC3722-1/
LTC3722-2
Synchronous Dual Mode Phase Modulated Full-Bridge
Controllers
50W to 2kW Power Supply Design, Adaptive Direct Sense ZVS
LTC3723-1/
LTC3723-2
Synchronous Push-Pull PWM Controllers
LTC3723-1: Peak Current Mode Control, Programmable Slope Compensation,
Leading Edge Blanking
LTC3723-2: Voltage Mode Control with Voltage Feedforward
LT3781
Dual Transistor Synchronous Forward Controller
Operation up to 72V Maximum
LTC3803
Constant Frequency Current Mode Flyback DC/DC
Controller in ThinSOT
Adjustable Slope Compensation, Internal Soft-Start, 200kHz
LT3804
Secondary Side Dual Output Controller with Opto Driver Regulates Two Outputs, OptoCoupler Feedback Driver and Second Output
Synchronous Driver Controller
LTC3900
Synchronous Rectiﬁer Driver for Forward Converters
Programmable Timeout, Synchronization Sequence Monitor, Reverse
Inductor Current Sense
LTC3901
Synchronous Rectiﬁer Driver for Push-Pull and FullBridge Converters
Programmable Timeout, Synchronization Sequence Monitor, Reverse
Inductor Current Sense
4430f
20
Linear Technology Corporation
LT/TP 0804 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004

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