MAS MAS9081A5TC00 Dual band receiver ic high sensitivity Datasheet

DA9081.006
1 August, 2005
MAS9081
• Dual Band Receiver IC
• High Sensitivity
• Very Low Power Consumption
• Wide Supply Voltage Range
• Power Down Control
• Control for AGC On
• High Selectivity by Crystal Filter
• Fast Startup Feature
DESCRIPTION
The MAS9081 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to
receive time signals in the frequency range from 40
kHz to 100 kHz. Only a few external components are
required for time signal receiving. The circuit has
preamplifier, wide range automatic gain control,
demodulator and output comparator built in. The
output signal can be processed directly by an
additional digital circuitry to extract the data from the
received signal. The control for AGC (automatic gain
control) can be used to switch AGC on or off if
necessary. MAS9081 supports dual band operation
by switching between two crystal filters and an
additional antenna tuning capacitor.
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Dual Band Receiver IC
Highly Sensitive AM Receiver, 0.4 µVRMS typ.
Wide Supply Voltage Range from 1.1 V to 5 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
MAS9081 has differential input and different internal
compensation capacitor options for compensating
shunt capacitances of different crystals (See ordering
information on page 12).
•
Dual Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
QO2
QO1
AON
QI
RFIP
RFIM
AGC Amplifier
RFI2
Power Supply/Biasing
VDD
VSS PDN1 PDN2
Demodulator
&
Comparator
AGC
OUT
DEC
1 (12)
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1 August, 2005
MAS9081 PAD LAYOUT
VDD
VSS
QO2
RFI2
QO1
RFIM
QI
RFIP
AGC
PDN1
PDN2
AON
OUT
DEC
1688 µm
9081Ax,
x=1, 3, 4 or 5
1494 µm
DIE size = 1.49 x 1.69 mm; PAD size = 80 x 80 µm
Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or
left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component
assembly are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Name
X-coordinate
Y-coordinate
Power Supply Voltage
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
Quartz Filter Input for Crystals
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
VDD
QO2
QO1
QI
AGC
PDN2
OUT
DEC
AON
PDN1
RFIP
RFIM
RFI2
VSS
174 µm
174 µm
174 µm
174 µm
174 µm
174 µm
175 µm
1318 µm
1318 µm
1318 µm
1318 µm
1318 µm
1318 µm
1318 µm
1452 µm
1247 µm
1043 µm
839 µm
633 µm
430 µm
224 µm
240 µm
444 µm
648 µm
853 µm
1057 µm
1262 µm
1466 µm
Note
3
1
2
3
4
4
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
3) PDN1 = VDD and PDN2 = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down controlled to power up
4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistances against ground
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1 August, 2005
FREQUENCY SELECTION
The frequency selection and power down control is
accomplished via two digital control pins PDN1 and
PDN2. The control logic is presented in table 1.
Table 1 Frequency selection and power down control
PDN1
PDN2
RFI2 Switch
Selected Crystal
Output
High
High
Low
High
Low
High
Open
Open
Closed
QO1
QO2
Low
Low
Closed
QO2
The internal antenna tuning capacitor switch (RFI2)
and crystal filter output switches (QO1, QO2) are
controlled according table 1. See switch in block
diagram on page 1.
If frequency 1 is selected the RFI2 switch is open
and only crystal output QO1 is active. Antenna
frequency is determined by antenna inductor LANT
(see Typical Application on page 5), antenna
capacitor CANT1 and parasitic capacitances related
to antenna inputs RFI1, RFI2 and RFI3 (see
Antenna Tuning Considerations below). Frequency
1 is the higher frequency of two selected
frequencies.
Description
Power down
Frequency 1
Frequency 2, RFI2 capacitor connected in
parallel with antenna
Frequency 2, RFI2 capacitor connected in
parallel with antenna
If frequency 2 is selected then RFI2 switch is closed
to connect CANT2 in parallel with ferrite antenna and
tune it to frequency 2. Then only crystal output QO2
is active. Frequency 2 is lower frequency of the two
selected frequencies.
It is recommended to switch the device to power
down for 50ms before switching to another
frequency. This guarantees fast startup in switching
to another frequency. The 50ms power down period
is used to discharge AGC capacitor and to initialize
fast startup conditions.
ANTENNA TUNING CONSIDERATIONS
The ferrite bar antenna having inductance LANT and
parasitic coil capacitance CCOIL is tuned to two
reception frequencies f1 and f2 by parallel capacitors
CANT1 and CANT2. The receiver input stage and
internal antenna capacitor switch have capacitances
(CRFI1, COFF2) which affect the resonance
frequencies. COFF2 is switch capacitance when
switch is open. When the switch is closed this
capacitance is shorted by on resistance of the
switch and is effectively eliminated. Following
relationships can be written into two tuning
frequencies.
Frequency f1 (higher frequency):
CTOT1=CCOIL+CANT1+CRFI1+COFF2=CCOIL+CANT1+6.5pF+37pF=CCOIL+CANT1+ 43.5pF, f 1 =
1
2π L ANT ⋅ C TOT 1
Frequency f2 (lower frequency):
CTOT2=CCOIL+CANT1+CANT2+CRFI1=CCOIL+CANT1+CANT2+ 6.5pF, f 2 =
1
2π L ANT ⋅ C TOT 2
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DA9081.006
1 August, 2005
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature
Storage Temperature
VDD-VSS
VIN
PMAX
TOP
TST
Conditions
Min
Max
Unit
-0.3
VSS-0.3
6
VDD+0.3
100
+85
+150
V
V
mW
o
C
o
C
-40
-55
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25°C
Parameter
Operating Voltage
Current Consumption
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
RFI2 Switch On Resistance
RFI2 Switch Off Resistance
RFI2 Switch Off
Capacitance
Input Levels |lIN|<0.5 µA
Output Current
VOL<0.2 VDD;VOH >0.8 VDD
Output Pulse
Symbol
VDD
IDD
IDDoff
fIN
VIN min
VIN max
RRFI
CRFI
RON2
ROFF2
COFF2
Conditions
T200ms
T500ms
T800ms
Startup Time
TStart
Output Delay Time
TDelay
Typ
1.10
VDD=1.4 V, Vin=0 µVrms
VDD=1.4 V, Vin=20 mVrms
VDD=3.6 V, Vin=0 µVrms
VDD=3.6 V, Vin=20 mVrms
31
27
64
37
67
40
40
0.4
Max
Unit
5
V
µA
91
65
0.1
100
1
20
f=40kHz..77.5 kHz
270
6.5
3.8
VDD=1.4 V
37
0.2 VDD
0.8 VDD
5
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
Fast Start-up, Vin=0.4 µVrms
Fast Start-up, Vin=20 mVrms
µA
kHz
µVrms
mVrms
kΩ
pF
Ω
MΩ
pF
10
VIL
VIH
|IOUT|
T100ms
Min
V
µA
50
140
ms
150
230
ms
400
500
600
ms
700
800
900
ms
1.3
3.5
50
s
100
ms
4 (12)
DA9081.006
1 August, 2005
TYPICAL APPLICATION
Note 1
X2
X1
QO2
QO1
Optional
Control
for AGC on/hold
AON
QI
RFIP
LANT
CANT1
CANT2
Demodulator
&
Comparator
AGC Amplifier
RFIM
Ferrite
Antenna
OUT
Receiver
Output
Power Supply/Biasing
RFI2
VDD
VSS PDN1 PDN2
DEC
AGC
+
VBATTERY
Power Down /
Fast Startup /
Frequency Selection
Figure 1
CAGC
CDEC
Note 2
Application circuit of dual band receiver MAS9081
X2
40.003kHz
X1
60.003kHz
QO2
QO1
Optional
Control
for AGC on/hold
AON
QI
RFIP
LANT
4.40 mH
CANT1
1.5 nF
CANT2
2.0 nF
AGC Amplifier
RFIM
Demodulator
&
Comparator
OUT
Receiver
Output
Ferrite
Antenna
RFI2
Power Supply/Biasing
VDD
VSS PDN1 PDN2
AGC
DEC
+ CAGC
10 µF
1.4 V
CDEC
47 nF
Power Down /
Fast Startup /
Frequency Selection
Figure 2
Example circuit of dual band receiver MAS9081 for MSF/WWVB/JJY frequencies
5 (12)
DA9081.006
1 August, 2005
TYPICAL APPLICATION (Continued)
Note 1: Crystals
The crystals as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 2).
The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance
compensation capacitor CC of MAS9081. See Compensation Capacitance Options on table 3.
Table 2 Time-Signal System Frequencies
Time-Signal System
Location
Antenna Frequency
Recommended Crystal Frequency
DCF77
HGB
MSF
WWVB
JJY
BPC
77.5 kHz
75 kHz
60 kHz
60 kHz
40 kHz and 60 kHz
68.5 kHz
77.503 kHz
75.003 kHz
60.003 kHz
60.003 kHz
40.003 kHz and 60.003 kHz
68.505 kHz
Germany
Switzerland
United Kingdom
USA
Japan
China
Table 3 Compensation Capacitance Options
Device
CC
Crystal Description
MAS9081A1
MAS9081A3
MAS9081A4
MAS9081A5
0.75 pF
1.25 pF
1.5 pF
3.875 pF
For low C0 crystal
For high C0 crystal
For high C0 crystal
For any crystal (over compensated, requires external capacitors)
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of
floating crystal shunt capacitance. For example crystal with 1pF floating package shunt capacitance can have
0.85pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance
should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance
mismatching.
Highest frequency crystal is connected to crystal output pin 1 (QO1). Lowest frequency crystal is connected to
crystal output pin 2 (QO2). The other pin of both crystals is connected to common crystal input pin QI.
Table 4 below presents some crystal manufacturers having suitable crystals for timesignal receiver application.
Table 4. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application
Manufacturer
Crystal Type
Dimensions
Web Link
Citizen
Epson
KDS Daishinku
Microcrystal
Seiko
Instruments
CFV-206
C-2-Type
C-4-Type
DT-261
MX1V-L2N
MX1V-T1K
VTC-120
ø 2.0 x 6.0
ø 1.5 x 5.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 8.1
ø 1.2 x 4.7
http://www.citizen.co.jp/tokuhan/quartz/
http://www.epsondevice.com/e/
http://www.kdsj.co.jp/english.html
http://www.microcrystal.com/
http://speed.sii.co.jp/pub/compo/quartz/topE.jsp
Note 2: AGC Capacitor
The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the
capacitors. The insulation resistance of these capacitors should be at minimum 100 MΩ. Also probes with at
least several 100 MΩ impedance should be used for voltage probing of AGC and DEC pins. DEC capacitor can
be low leakage chip capacitor.
6 (12)
DA9081.006
1 August, 2005
MAS9081 SAMPLES IN SBDIL 20 PACKAGE
NC 1
20 VSS
19 RFI2
18 RFIM
VDD 2
QO2 3
NC 6
QI 7
AGC 8
17 RFIP
9081Az
YYWW
XXXXX.X
QO1 4
NC 5
16 NC
15 NC
14 PDN 1
13 AON
PDN2 9
12 DEC
11 NC
OUT 10
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
z = Sample Version Number
PIN DESCRIPTION
Pin Name
Pin
NC
VDD
QO2
QO1
NC
NC
QI
AGC
PDN2
OUT
NC
DEC
AON
PDN1
NC
NC
RFIP
RFIM
RFI2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AO
Function
Note
Positive Power Supply
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
1
1
AI
AO
DI
DO
Quartz Filter Input for Crystals
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
AO
DI
DI
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
AI
AI
AI
G
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
2
3
4
4
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pins 5 and 6 between QO and QI must be connected to VSS to eliminate DIL package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing MOSFET-transistors towards ground
7 (12)
DA9081.006
1 August, 2005
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VSS
RFI2
RFIM
RFIP
NC
PDN1
AON
DEC
9081Az
YYWW
VDD
QO2
QO1
NC
QI
AGC
PDN2
OUT
Top Marking Definitions:
z = Version Number
YYWW = Year Week
PIN DESCRIPTION
Pin Name
Pin
Type
Function
VDD
QO2
QO1
NC
QI
1
2
3
4
5
P
AO
AO
Positive Power Supply
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
AI
AGC
PDN2
OUT
DEC
AON
PDN1
NC
RFIP
RFIM
RFI2
VSS
6
7
8
9
10
11
12
13
14
15
16
AO
DI
DO
AO
DI
DI
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
AI
AI
AI
G
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
Note
1
2
3
4
4
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pin 4 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up (to AGC on) with current < 1 µA which is switched off at power down
4) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
8 (12)
DA9081.006
1 August, 2005
PACKAGE (TSSOP-16) OUTLINES
C
E
D
Seating Plane
B
F
G
H
A
O
Pin 1
B
Detail A
B
L
I
I1
K
P
Section B-B
J1
M
J
Dimension
N
Min
A
B
C
D
E
F
G
H
I
I1
J
J1
K
L
M
(The length of a terminal for
soldering to a substrate)
N
O
P
Detail A
Max
6.40 BSC
4.30
4.50
5.00 BSC
0.05
0.15
1.10
0.30
0.19
0.65 BSC
0.18
0.09
0.09
0.19
0.19
0°
0.24
0.50
0.28
0.20
0.16
0.30
0.25
8°
0.26
0.75
1.00 REF
12°
12°
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Dimensions do not include mold flash, protrusions, or gate burrs.
All dimensions are in accordance with JEDEC standard MO-153.
9 (12)
DA9081.006
1 August, 2005
SOLDERING INFORMATION
◆ For Pb-Free, RoHS Compliant TSSOP-16
Resistance to Soldering Heat
Maximum Temperature
Maximum Number of Reflow Cycles
Reflow profile
According to RSH test IEC 68-2-58/20
260°C
3
Thermal profile parameters stated in IPC/JEDEC J-STD-020
should not be exceeded. http://www.jedec.org
max 0.08 mm
Solder plate 7.62 - 25.4 µm, material Matte Tin
Seating Plane Co-planarity
Lead Finish
EMBOSSED TAPE SPECIFICATIONS
Tape Feed Direction
P0
D0
P2
A
E1
F1
W
D1
A
A0
P
Tape Feed Direction
T
Section A - A
B0
S1
K0
Pin 1 Designator
Dimension
Min
Max
Unit
A0
B0
D0
D1
E1
F1
K0
P
P0
P2
S1
T
W
6.50
5.20
6.70
5.40
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
1.50 +0.10 / -0.00
1.50
1.65
7.20
1.20
11.90
1.85
7.30
1.40
12.10
4.0
1.95
0.6
0.25
11.70
2.05
0.35
12.30
10 (12)
DA9081.006
1 August, 2005
REEL SPECIFICATIONS
W2
A
D
C
Tape Slot for Tape Start
N
B
W1
2000 Components on Each Reel
Reel Material: Conductive, Plastic Antistatic or Static Dissipative
Carrier Tape Material: Conductive
Cover Tape Material: Static Dissipative
Carrier Tape
Cover Tape
End
Start
Trailer
Dimension
A
B
C
D
N
W1
(measured at hub)
W2
(measured at hub)
Trailer
Leader
Weight
Leader
Components
Min
1.5
12.80
20.2
50
12.4
Max
Unit
330
14.4
mm
mm
mm
mm
mm
mm
18.4
mm
13.50
160
390,
of which minimum 160
mm of empty carrier tape
sealed with cover tape
mm
mm
1500
g
11 (12)
DA9081.006
1 August, 2005
ORDERING INFORMATION
Product Code
Product
Description
Capacitance Option
MAS9081A1TC00
Dual Band AM-Receiver IC
with Differential Input
Dual Band AM-Receiver IC
with Differential Input
Dual Band AM-Receiver IC
with Differential Input
Dual Band AM-Receiver IC
with Differential Input
Dual Band AM-Receiver IC
with Differential Input
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
TSSOP-16, Pb-free, RoHS
compliant, Tape & Reel
CC = 0.75 pF
MAS9081A3TC00
MAS9081A4TC00
MAS9081A5TC00
MAS9081A1UC06
CC = 1.25 pF
CC = 1.5 pF
CC = 3.875 pF
CC = 0.75 pF
Contact Micro Analog Systems Oy for other wafer thickness options.
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits
shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no
claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and
Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or
modification.
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