Hynix HYMD264726B8J-J Unbuffered ddr sdram dimm Datasheet

64Mx72 bits
Unbuffered DDR SDRAM DIMM
HYMD264726B(L)8J-J
DESCRIPTION
Hynix HYMD264726B(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264726B(L)8J-Jseries
consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD264726B(L)8J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD264726B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264726B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
512MB (64M x 72) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
•
JEDEC Standard 184-pin dual in-line memory module (DIMM)
•
Data inputs on DQS centers when write (centered
DQ)
•
Error Check Correction (ECC) Capability
•
•
2.5V +/- 0.2V VDD and VDDQ Power supply
Data strobes synchronized with output data for read
and input data for write
•
All inputs and outputs are compatible with SSTL_2
interface
•
Programmable CAS Latency 2 / 2.5 supported
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
tRAS Lock-out function supported
•
Internal four bank operations with single pulsed RAS
•
Auto refresh and self refresh supported
•
8192refresh cycles / 64ms
•
•
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
ORDERING INFORMATION
Part No.
HYMD264726B(L)8J-J
Power Supply
Clock Frequency
Interface
Form Factor
VDD=2.5V
VDDQ=2.5V
166MHz (*DDR333)
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Oct. 02
1
HYMD264726B(L)8J-J
PIN DESCRIPTION
Pin
Pin Description
Pin
CK0,/CK0,CK1,/CK1,CK2,/CK2
Differential Clock Inputs
VDDQ
Pin Description
DQs Power Supply
CS0, CS1
Chip Select Input
VSS
Ground
CKE0, CKE1
Clock Enable Input
VREF
Reference Power Supply
/RAS, /CAS, /WE
Commend Sets Inputs
VDDSPD
Power Supply for SPD
A0 ~ A12
Address
SA0~SA2
E2PROM Address Inputs
BA0, BA1
Bank Address
SCL
E2PROM Clock
DQ0~DQ63
Data Inputs/Outputs
SDA
E2PROM Data I/O
CB0~CB7
Check Bit
WP
Write Protect Flag
DQS0~DQS7
Data Strobe Inputs/Outputs
VDDID
VDD Identification Flag
DM0~8
Data-in Mask
DU
Do not Use
VDD
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
1
VREF
32
A5
62
VDDQ
93
VSS
124
VSS
154
Name
/RAS
2
DQ0
33
DQ24
63
/WE
94
DQ4
125
A6
155
DQ45
VDDQ
3
VSS
34
VSS
64
DQ41
95
DQ5
126
DQ28
156
4
DQ1
35
DQ25
65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5
DQS0
36
DQS3
66
VSS
97
DM0
128
VDDQ
158
/CS1
6
DQ2
37
A4
67
DQS5
98
DQ6
129
DM3
159
DM5
7
VDD
38
VDD
68
DQ42
99
DQ7
130
A3
160
VSS
8
DQ3
39
DQ26
69
DQ43
100
VSS
131
DQ30
161
DQ46
DQ47
9
NC
40
DQ27
70
VDD
101
NC
132
VSS
162
10
NC
41
A2
71
NC
102
NC
133
DQ31
163
NC
11
VSS
42
Vss
72
DQ48
103
A13*
134
CB4
164
VDDQ
12
DQ8
43
A1
73
DQ49
104
VDDQ
135
CB5
165
DQ52
13
DQ9
44
CB0
74
VSS
105
DQ12
136
VDDQ
166
DQ53
14
DQS1
45
CB1
75
/CK2
106
DQ13
137
CK0
167
NC
15
VDDQ
46
VDD
76
CK2
107
DM1
138
/CK0
168
VDD
16
CK1
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
/CK1
48
A0
78
DQS6
109
DQ14
140
DM8
170
DQ54
18
VSS
49
CB2
79
DQ50
110
DQ15
141
A10
171
DQ55
19
DQ10
50
VSS
80
DQ51
111
CKE1
142
CB6
172
VDDQ
20
DQ11
51
CB3
81
VSS
112
VDDQ
143
VDDQ
173
NC
21
CKE0
52
BA1
82
VDDID
113
BA2*
144
CB7
174
DQ60
22
VDDQ
83
DQ56
114
DQ20
175
DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12
145
VSS
176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146
DQ36
177
DM7
25
DQS2
55
DQ33
86
DQS7
117
DQ21
147
DQ37
178
DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179
DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180
VDDQ
28
DQ18
58
VSS
89
VSS
120
VDD
150
DQ38
181
SA0
29
A7
59
BA0
90
WP
121
DQ22
151
DQ39
182
SA1
30
VDDQ
60
DQ35
91
SDA
122
A8
152
VSS
183
SA2
31
DQ19
61
DQ40
92
SCL
123
DQ23
153
DQ44
184
VDDSPD
Key
key
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.1/Oct. 02
2
HYMD264726B(L)8J-J
FUNCTIONAL BLOCK DIAGRAM
/CS1
/CS0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ7
I/O7
/CS
DQS
D0
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D9
I/O7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ39
I/O7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ47
I/O7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ55
I/O7
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D4
/CS
DQS
D13
D12
I/O7
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ15
I/O7
/CS
DQS
D1
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D10
I/O7
DQS2
DM2
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D5
/CS
DQS
D14
I/O7
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ23
I/O7
/CS
DQS
D2
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D11
I/O7
DQS3
DM3
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D6
/CS
DQS
D15
I/O7
DQS7
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ31
I/O7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
CB7
I/O7
/CS
DQS
D3
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D12
I/O7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ63
I/O7
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D7
/CS
DQS
D16
I/O7
DQS8
DM8
/CS
DQS
D8
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
SPD
VDD SPD
DQS
D17
VDD /VDDQ
DO-D17
VREF
DO-D17
DO-D17
VSS
Strap:see Note 4
VDDID
I/O7
*Clock Wiring
Serial PD
SDA
SCL
WP
A0
A1
SA0 SA1
A2
SA2
Clock Input
SDRAMs
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Note :
BA0-BA1
A0-A13
CKE1
BA0-BA1 : SDRAMs D0-D17
A0-A13 : SDRAMs D0-D17
CKE : SDRAMs D9-D17
/RAS
/RAS : SDRAMs D0-D17
/CAS
/CAS : SDRAMs D0-D17
CKE0
CKE : SDRAMs D0-D8
/WE
/WE : SDRAMs D0-D17
Rev. 0.1/Oct. 02
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%
3
HYMD264726B(L)8J-J
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
o
Storage Temperature
TSTG
-55 ~ 125
oC
Voltage on Any Pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
18
W
Soldering Temperature Þ Time
TSOLDER
260 Þ 10
oC
C
Þ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
VDDQ
2.3
2.5
2.7
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51VDDQ
V
Note
1
2
3
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
VID(AC)
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
Max
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1/Oct. 02
4
HYMD264726B(L)8J-J
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
W
Series Resistor (RS)
25
W
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Input Timing Measurement Reference Level Voltage
Rev. 0.1/Oct. 02
5
HYMD264726B(L)8J-J
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A12, BA0, BA1
CIN1
TBD
TBD
pF
Input Capacitance
/RAS, /CAS, /WE
CIN2
TBD
TBD
pF
Input Capacitance
CKE0, CKE1
CIN3
TBD
TBD
pF
Input Capacitance
CS0, CS1
CIN4
TBD
TBD
pF
Input Capacitance
CK0, /CK0, CK1, /CK1, CK2,/CK2
CIN5
TBD
TBD
pF
Input Capacitance
DM0 ~ DM8
CIN6
TBD
TBD
pF
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
TBD
TBD
pF
Data Input / Output Capacitance
CB0 ~ CB7
CIO2
TBD
TBD
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
V TT
R T =50 Ω
Output
Zo=50 Ω
V REF
C L =30pF
Rev. 0.1/Oct. 02
6
HYMD264726B(L)8J-J
DC CHARACTERISTICS I (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Input Leakage
Current
Symbol
Add, CMD, /CS, /CKE
Min.
Max
-36
36
-12
12
ILI
CK, /CK
Unit
Note
uA
1
Output Leakage Current
ILO
-10
10
uA
2
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Note :
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Rev. 0.1/Oct. 02
7
HYMD264726B(L)8J-J
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Speed
Unit
Symbol
Test Condition
Operating Current
IDD0
One bank; Active Precharge; tRC=tRC(min); tCK=
tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1620
mA
Operating Current
IDD1
One bank; Active-Read-Precharge; Burst Length
=2; tRC=tRC(min); tCK=tCK(min); address and
control inputs changing once per clock cycle
1620
mA
-J
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
180
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once per
clock cycle. VIN=VREF for DQ, DQS and DM
900
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
270
mA
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK (min); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle
1080
mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2070
mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
2160
2160
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Operating Current Four Bank Operation
Rev. 0.1/Oct. 02
IDD7
Normal
54
mA
Low Power
27
mA
2970
mA
Four bank interleaving with B=4 Refer to the
following page for detailed test condition
Note
8
HYMD264726B(L)8J-J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
DDR333
Parameter
Symbol
Unit
Min
Max
Row Cycle Time
tRC
60
-
ns
Auto Refresh Row Cycle Time
tRFC
72
-
ns
Row Active Time
tRAS
42
70K
ns
Active to Read with Auto Precharge Delay
tRAP
18
-
ns
Row Address to Column Address Delay
tRCD
18
-
ns
Row Active to Row Active Delay
tRRD
12
-
ns
Column Address to Column Address Delay
tCCD
1
-
CK
Row Precharge Time
tRP
18
-
ns
Write Recovery Time
tWR
15
-
ns
Last Data-In to Read Command
tDRL
1
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
CK
6
12
ns
7.5
12
ns
CL = 2.5
System Clock Cycle Time
Note
16
15
tCK
CL = 2
Clock High Level Width
tCH
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.6
0.6
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.45
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
ns
1, 10
Clock Half Period
tHP
min
(tCL,tCH)
-
ns
1,9
tQHS
-
0.55
ns
10
Data Hold Skew Factor
Valid Data Output Window
tDV
Data-out high-impedance window from CK, /CK
tHZ
-0.7
0.7
ns
17
Data-out low-impedance window from CK, /CK
tLZ
-0.7
0.7
ns
17
Input Setup Time (fast slew rate)
tIS
0.75
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.75
-
ns
2,3,5,6
Input Setup Time (slow slew rate)
tIS
0.8
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
tIH
0.8
-
ns
2,4,5,6
Rev. 0.1/Oct. 02
tQH-tDQSQ
ns
9
HYMD264726B(L)8J-J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
DDR333
Parameter
Symbol
Min
Input Pulse Width
Unit
Note
ns
6
Max
tIPW
2.2
Write DQS High Level Width
tDQSH
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.45
-
ns
6,7, 11~13
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.45
-
ns
6,7, 11~13
DQ & DM Input Pulse Width
tDIPW
1.75
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
us
8
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Rev. 0.1/Oct. 02
10
HYMD264726B(L)8J-J
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11.
This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12.
13.
14.
15.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
17.
tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.1/Oct. 02
11
HYMD264726B(L)8J-J
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
X
X
H
X
X
1
L
H
H
H
Device Deselect
No Operation
Bank Active
H
X
L
L
H
H
H
X
L
H
L
H
ADDR
RA
Read
BA
V
L
CA
Read with Autoprecharge
1
1,3
L
H
X
L
H
L
L
CA
Write with Autoprecharge
1
V
H
Precharge All Banks
H
X
L
L
H
L
Precharge selected Bank
1
V
H
Write
Note
1,4
H
X
1,5
L
V
1
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
H
X
X
X
Exit
L
H
L
H
H
H
H
X
X
X
L
H
H
H
Self Refresh
Precharge
Power Down
Mode
Active Power
Down Mode
(Clock Suspend)
Entry
H
1
X
1
1
L
1
X
Exit
Entry
Exit
L
H
L
H
X
X
X
1
L
H
H
H
1
H
X
X
X
1
L
V
V
V
H
L
H
X
X
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.1/Oct. 02
12
HYMD264726B(L)8J-J
PACKAGE DIMENSIONS
Front
133.35
5.25
131.35
128.95
5.077
(2X)4.00
.157
5.171
2.30
0.91
(2) 0
2.5
0.098
17.80
0.700
10.0
.394
31.75
1.250
Side
Back
4.00
0.157MAX
(Front)
1.27+/-0.10
0.050+/-0.004
Rev. 0.1/Oct. 02
13
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(64Mx72 Unbuffered DDR DIMM)
Rev. 0.1/Oct. 02
14
HYMD264726B(L)8J-J
SERIAL PRESENCE DETECT
Bin Sort : J(DDR333@CL=2.5)
Byte#
Function Description
Function Supported
Hexa Value
0
Number of Bytes written into serial memory at module manufacturer
128 Bytes
80h
1
Total number of Bytes in SPD device
2
Fundamental memory type
3
4
5
Note
256 Bytes
08h
DDR SDRAM
07h
Number of row address on this assembly
13
0Dh
1
Number of column address on this assembly
10
0Ah
1
Number of physical banks on DIMM
2Bank
02h
6
Module data width
72 Bits
48h
7
Module data width (continued)
-
00h
8
Module voltage Interface levels(VDDQ)
9
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10
DDR SDRAM access time from clock at CL=2.5 (tAC)
11
Module configuration type
SSTL 2.5V
04h
6.0ns
60h
2
+/-0.7ns
70h
2
ECC
02h
12
Refresh rate and type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
x8
08h
15
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
01h
16
Burst lengths supported
2,4,8
0Eh
17
Number of banks on each DDR SDRAM
18
CAS latency supported
4 Banks
04h
2, 2.5
0Ch
01h
19
CS latency
0
20
WE latency
1
02h
21
DDR SDRAM module attributes
Differential Clock Input
20h
22
DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
C0h
23
DDR SDRAM cycle time at CL=2.0(tCK)
24
DDR SDRAM access time from clock at CL=2.0(tAC)
7.5ns
75h
2
+/-0.7ns
70h
2
25
DDR SDRAM cycle time at CL=1.5(tCK)
-
00h
2
26
DDR SDRAM access time from clock at CL=1.5(tAC)
-
00h
2
27
Minimum row precharge time(tRP)
18ns
48h
28
Minimum row activate to row active delay(tRRD)
12ns
30h
29
Minimum RAS to CAS delay(tRCD)
18ns
48h
30
Minimum active to precharge time(tRAS)
42ns
2Ah
31
Module row density
256MB
40h
32
Command and address signal input setup time(tIS)
0.75ns
75h
33
Command and address signal input hold time(tIH)
0.75ns
75h
34
Data signal input setup time(tDS)
0.45ns
45h
35
Data signal input hold time(tDH)
0.45ns
45h
36~40 Reserved for VCSDRAM
Undefined
00h
41
Minimum active / auto-refresh time ( tRC)
60ns
3Ch
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
72ns
48h
43
Maximum cycle time (tCK max)
44
Maximim DQS-DQ skew time(tDQSQ)
45
Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62
SPD Revision code
63
Checksum for Bytes 0~62
64
12ns
30h
0.45ns
2Dh
0.55ns
55h
Undefined
00h
Initial release
00h
-
13h
Manufacturer JEDEC ID Code
Hynix JEDEC ID
ADh
65~71 --------- Manufacturer JEDEC ID Code
-
00h
Rev. 0.1/Oct. 02
15
HYMD264726B(L)8J-J
SERIAL PRESENCE DETECT
Byte #
- continued -
Function Description
Function Supported
Hexa Value
Note
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
Asia Area
0*h
1*h
2*h
3*h
4*h
5*h
6
48h
72
Manufacturing location
73
Manufacture part number(Hynix Memory Module)
H
74
-------- Manufacture part number(Hynix Memory Module)
Y
59h
75
-------- Manufacture part number(Hynix Memory Module)
M
4Dh
76
Manufacture part number (DDR SDRAM)
D
44h
77
Manufacture part number(Memory density)
2
32h
78
Manufacture part number(Module Depth)
6
36h
79
------- Manufacture part number(Module Depth)
4
34h
80
Manufacture part number(Module type)
Blank
20h
81
Manufacture part number(Data width)
7
37h
82
-------Manufacture part number(Data width)
2
32h
83
Manufacture part number(Refresh, # of Bank.)
6(8K refresh,4Bank)
36h
84
Manufacture part number(Component Generation)
B
42h
85
Manufacture part number(Component configuration)
8
38h
86
Manufacture part number(Module Type)
J
4Ah
87
Manufacture part number(Hyphen)
‘-’
2Dh
88
Manufacture part number(Minimum cycle time)
J
4Ah
Blank
20h
-
89~90
Manufacture part number(T.B.D)
91
Manufacture revision code(for Component)
-
92
Manufacture revision code (for PCB)
-
-
93
Manufacturing date(Year)
-
-
94
Manufacturing date(Week)
-
-
3
95~98
Module serial number
-
-
4
99~127
Manufacturer specific data (may be used in future)
Undefined
00h
5
Undefined
00h
5
128~255 Open for customer use
3
Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number system
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix web site
Byte 85~86, Low power part
Byte #
85
86
Function Description
Manufacture part number(Low power part)
Manufacture part number(Component configuration)
Rev. 0.1/Oct. 02
Function
Supported
Hexa Value
L
8
4Ch
38h
Note
16
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