Holt HI-1581PCI 3.3v monolithic dual transceiver Datasheet

HI-1579, HI-1581
MIL-STD-1553 / 1760
3.3V Monolithic Dual Transceivers
October 2009
DESCRIPTION
PIN CONFIGURATIONS
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer.
FEATURES
· Compliant
to MIL-STD-1553A and B,
MIL-STD-1760 and ARINC 708A
· 3.3V single supply operation
44 pin plastic chip-scale package (QFN)
· Less
than 0.5W maximum power
dissipation
and extended temperature
44 Pin Plastic 7mm x 7mm
Chip-scale package
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
1579PSI
1579PST
1579PSM
1581PSI
1581PST
1581PSM
20
19
18
17
16
15
14
13
12
11
TXA
TXA
TXINHA
RXA
RXA
TXB
TXB
TXINHB
RXB
RXB
VDDA 1
20 TXA
BUSA 2
19 TXA
BUSA 3
RXENA 4
BUSB 7
Industry standard pin configurations
1579CDI
1579CDT
1579CDM
BUSB 8
18 TXINHA
17 RXA
16 RXA
GNDA 5
VDDB 6
ranges
·
1581PCI
1581PCT
1581PCM
20 Pin Plastic ESOIC - WB package
· Smallest footprint available in 7mm x 7mm
· Industrial
33 32 31 TXINHA
30 RXA
29 RXA
28 27 26 TXB
25 TXB
24 TXINHB
23 -
1579PCI
1579PCT
1579PCM
12
13
14
15
16
17
18
19
20
21
22
The receiver section of the each bus converts the 1553 bus
bi-phase differential data to complementary CMOS / TTL
data suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic "0" (HI-1579) or
logic 1 (HI-1581).
- 1
RXENA 2
GNDA 3
GNDA 4
GNDA 5
VDDB 6
VDDB 7
BUSB 8
BUSB 9
BUSB 10
BUSB 11
RXENB
GNDB
GNDB
GNDB
RXB
RXB
-
The transmitter section of each bus takes complementary
CMOS / TTL Manchester II bi-phase data and converts it to
differential voltages suitable for driving the bus isolation
transformer. Separate transmitter inhibit control signals are
provided for each transmitter.
44 43 BUSA
42 BUSA
41 BUSA
40 BUSA
39 VDDA
38 VDDA
37 TXA
36 TXA
35 34 -
The HI-1579 and HI-1581 are low power CMOS dual
transceivers designed to meet the requirements of the
MIL-STD-1553 specification.
1581CDI
1581CDT
1581CDM
15 TXB
14 TXB
13 TXINHB
RXENB 9
12 RXB
GNDB 10
11 RXB
20 Pin Ceramic DIP package
(DS1579 Rev. G)
HOLT INTEGRATED CIRCUITS
www.holtic.com
10/09
HI-1579, HI-1581
PIN DESCRIPTIONS
PIN
(DIP & SOIC)
1
SYMBOL
FUNCTION
DESCRIPTION
VDDA
power supply
+3.3 volt power for transceiver A
2
BUSA
analog output
MIL-STD-1533 bus driver A, positive signal
3
BUSA
analog output
MIL-STD-1553 bus driver A, negative signal
4
RXENA
digital input
5
GNDA
power supply
Ground for transceiver A
6
VDDB
power supply
+3.3 volt power for transceiver B
7
BUSB
analog output
MIL-STD-1533 bus driver B, positive signal
8
BUSB
analog output
MIL-STD-1553 bus driver B, negative signal
Receiver A enable. If low, forces RXA and RXA low
9
RXENB
digital input
10
GNDB
power supply
Ground for transceiver B
11
RXB
digital output
Receiver B output, inverted
12
RXB
digital output
Receiver B output, non-inverted
13
TXINHB
digital input
Transmit inhibit, bus B. If high BUSB, BUSB disabled
14
TXB
digital input
Transmitter B digital data input, non-inverted
15
TXB
digital input
Transmitter B digital data input, inverted
16
RXA
digital output
Receiver A output, inverted
17
RXA
digital output
Receiver A output, non-inverted
18
TXINHA
digital input
Transmit inhibit, bus A. If high BUSA, BUSA disabled
19
TXA
digital input
Transmitter A digital data input, non-inverted
20
TXA
digital input
Transmitter A digital data input, inverted
Receiver B enable. If low, forces RXB and RXB low
FUNCTIONAL DESCRIPTION
The HI-1579 family of dual data bus transceivers contains
differential voltage source drivers and differential receivers. It is intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
TRANSMITTER
Data input to the device’s transmitter section is from the
complementary CMOS inputs TXA/B and TXA/B. The
transmitter accepts Manchester II bi-phase data and converts it to differential voltages on BUSA/B and BUSA/B.
The transceiver outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling
methods produce a nominal voltage on the bus of 7.5 volts
peak to peak.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are either at a logic “1” or logic “0” simultaneously. A logic “1” applied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
TXA/B.
RECEIVER
The receiver accepts bi-phase differential data from the
MIL-STD-1553 bus through the same direct or transformer
coupled interface as the transmitter. The receiver’s differential input stage drives a filter and threshold comparator
that produces CMOS data at the RXA/B and RXA/B output
pins. When the MIL-STD-1553 bus is idle and RXENA or
RXENB are high, RXA/B will be logic “0” on HI-1579 and
logic “1” on HI-1581.
Each set of receiver outputs can also be independently
forced to the bus idle state (logic "0” on HI-1579 or logic “1”
on HI-1581) by setting RXENA or RXENB low.
MIL-STD-1553 BUS INTERFACE
A direct coupled interface (see Figure 2) uses a 1:2.5 ratio
isolation transformer and two 55 ohm isolation resistors
between the transformer and the bus.
In a transformer coupled interface (see Figure 3), the
transceiver is also connected to a 1:2.5 isolation
transformer which in turn is connected to a 1:1.4 coupling
transformer. The transformer coupled method also
requires two coupling resistors equal to 75% of the bus
characteristic impedance (Zo) between the coupling
transformer and the bus.
HOLT INTEGRATED CIRCUITS
2
HI-1579, HI-1581
Data Bus
Each Bus
TRANSMITTER
Isolation
Transformer
Coupler
Network
BUSA/B
TXA/B
Transmit
Logic
Direct or
Transformer
Slope
Control
TXA/B
BUSA/B
TXINHA/B
RECEIVER
RXA/B
Input
Filter
Receive
Logic
RXA/B
Comparator
RXENA/B
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
Vin
(Line to Line)
tDR
tDR
tDR
RXA/B (HI-1579)
tRG
tRG
tRG
tRG
RXA/B (HI-1579)
RXA/B (HI-1581)
RXA/B (HI-1581)
HOLT INTEGRATED CIRCUITS
3
tDR
HI-1579, HI-1581
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Supply Voltage
-0.3 V to +5 V
Logic input voltage range
VDD....................................... 3.3V... ±5%
-0.3 V dc to +3.6 V
Receiver differential voltage
Temperature Range
10 Vp-p
Driver peak output current
+1.0 A
Power dissipation at 25°C
ceramic DIL, derate
1.0 W
7mW/°C
Solder Temperature
Industrial ........................ -40°C to +85°C
Hi-Temp ....................... -55°C to +125°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
275°C for 10 sec.
Junction Temperature
175°C
Storage Temperature
-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
3.15
3.30
3.45
V
Operating Voltage
VDD
Total Supply Current
ICC1
Not Transmitting
4
10
mA
ICC2
Transmit one bus @
50% duty cycle
225
300
mA
ICC3
Transmit one bus @
100% duty cycle
425
600
mA
0.06
W
0.5
W
Power Dissipation
PD1
Not Transmitting
PD2
Transmit one bus @
100% duty cycle
0.3
Min. Input Voltage
(HI)
VIH
Digital inputs
Max. Input Voltage
(LO)
VIL
Digital inputs
Min. Input Current
(HI)
IIH
Digital inputs
Max. Input Current
(LO)
IIL
Digital inputs
-20
µA
Min. Output Voltage
(HI)
VOH
IOUT = -1.0mA, Digital outputs
90%
VDD
(LO)
VIH
IOUT = 1.0mA, Digital outputs
Max. Output Voltage
RECEIVER
70%
VDD
30%
VDD
20
µA
10%
VDD
(Measured at Point “AD“ in Figure 2 unless otherwise specified)
Input resistance
RIN
Differential (at chip BUS pins)
Input capacitance
CIN
Differential
Common mode rejection ratio
CMRR
Input Level
VIN
Input common mode voltage
Detect
VTHD
No Detect
VTHND
Kohm
5
40
Differential
VICM
Threshold Voltage - Direct-coupled
20
1 MHz Sine Wave
(Measured at Point “AD“ in Figure 2)
pF
dB
9
Vp-p
-5.0
5.0
V-pk
0.65
20.0
Vp-p
0.45
Vp-p
14.0
Vp-p
0.45
Vp-p
(RX pulse width 70 ns)
Theshold Voltage - Transformer-coupled
Detect
VTHD
No Detect
VTHND
1 MHz Sine Wave
(Measured at Point “AT“ in Figure 3)
(RX pulse width 70 ns)
HOLT INTEGRATED CIRCUITS
4
0.65
HI-1579, HI-1581
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
TRANSMITTER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
6.1
9.0
Vp-p
20.0
27.0
Vp-p
10.0
mVp-p
-90
90
mV
-250
250
mV
(Measured at Point “AD” in Figure 2 unless otherwise specified)
Output Voltage
Direct coupled
VOUT
Transformer coupled
VOUT
Output Noise
35 ohm load
(Measured at Point “AD“ in Figure 2)
70 ohm load
(Measured at Point “AT“ in Figure 3)
VON
Output Dynamic Offset Voltage
Direct coupled
VDYN
Transformer coupled
VDYN
Differential, inhibited
35 ohm load
(Measured at Point “AD“ in Figure 2)
70 ohm load
(Measured at Point “AT“ in Figure 3)
Output resistance
ROUT
Differential, not transmitting
Output Capacitance
COUT
1 MHz sine wave
10
Kohm
15
pF
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
RECEIVER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
450
ns
365
ns
40
ns
(Measured at Point “AD” in Figure 2)
Receiver Delay
tDR
From input zero crossing to RXA/B or RXA/B
Receiver gap time
tRG
Spacing between RXA/B and RXA/B pulses
Receiver Enable Delay
90
From RXENA/B rising or falling edge to
tREN
RXA/B or RXA/B
TRANSMITTER
(Measured at Point “AD” in Figure 2)
Driver Delay
tDT
TXA/B, TXA/B to BUSA/B, BUSA/B
150
ns
Rise time
tr
35 ohm load
100
300
ns
Fall Time
tf
35 ohm load
100
300
ns
tDI-H
Inhibited output
100
ns
tDI-L
Active output
150
ns
Inhibit Delay
TRANSMITTER
1:2.5
55 W
BUSA/B
TXA/B
35 W
TXA/B
BUSA/B
TXINHA/B
55 W
Isolation
Transformer
Point “AD“
55 W
RECEIVER
2.5:1
RXA/B
Point “AD“
35 W
55 W
RXA/B
Isolation
Transformer
RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS
5
HI-1579, HI-1581
TRANSMITTER
Point
“AT”
1:2.5
1:1.4
BUSA/B
TXA/B
52.5 W
(.75 Zo)
35 W (.5 Zo)
TXA/B
BUSA/B
TXINHA/B
52.5 W
(.75 Zo)
Isolation
Transformer
1.4:1
Coupling
Transformer
Point
“AT” 2.5:1
52.5 W
(.75 Zo)
RECEIVER
RXA/B
35 W (.5 Zo)
52.5 W
(.75 Zo)
RXA/B
Coupling
Transformer
Isolation
Transformer
RXENA/B
Figure 3. Transformer Coupled Test Circuits
HEAT SINK - ESOIC & CHIP-SCALE
PACKAGE
The HI-1579PSI/T/M and HI-1581PSI/T/M use a 20-pin
thermally enhanced SOIC package. The HI-1579PCI/T/M
and HI-1581PCI/T/M use a plastic chip-scale package
(QFN). These packages include a metal heat sink located
on the bottom surface of the device. This heat sink
should be soldered down to the printed circuit board for
optimum thermal dissipation. The heat sink is electrically
isolated and may be soldered to any convenient power or
ground plane.
APPLICATIONS NOTE
Holt Applications Note AN-500 provides circuit design
notes regarding the use of Holt's family of MIL-STD-1553
transceivers. Layout considerations, as well as
recommended interface and protection components are
included.
THERMAL CHARACTERISTICS
PART NUMBER
PACKAGE STYLE
HI-1579PSI / T / M
20-pin Thermally
enhanced plastic
SOIC (ESOIC)
HI-1581PSI / T / M
HI-1579CDI / T / M
HI-1581CDI / T / M
HI-1579PCI / T / M
HI-1581PCI / T / M
JUNCTION TEMPERATURE
CONDITION
ØJA
Heat sink
unsoldered
54°C/W
52°C
112°C
152°C
Heat sink
soldered
47°C/W
49°C
109°C
149°C
20-pin Ceramic
side-brazed DIP
Socketed
62°C/W
56°C
116°C
156°C
44-pin Plastic chipscale package (QFN)
Heat sink
unsoldered
49°C/W
50°C
110°C
150°C
TA=25°C
TA=85°C TA=125°C
Data taken at VDD=3.3V, continuous transmission at 1Mbit/s, single transmitter enabled.
HOLT INTEGRATED CIRCUITS
6
HI-1579, HI-1581
ORDERING INFORMATION
HI - 15xx xx x x (Plastic)
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
PC
44 PIN PLASTIC CHIP-SCALE PACKAGE QFN (44PCS)
PS
20 PIN PLASTIC ESOIC, Thermally Enhanced Wide SOIC w/Heat Sink (20HWE)
PART
NUMBER
RXENA = 0
RXA
RXA
RXENB = 0
RXB
RXB
1579
0
0
0
0
1581
1
1
1
1
HI - 15xxCD x (Ceramic)
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
Gold (Pb-free, RoHS compliant)
T
-55°C TO +125°C
T
No
Gold (Pb-free, RoHS compliant)
M
-55°C TO +125°C
M
Yes
Tin / Lead (Sn / Pb) Solder
PART
NUMBER
RXENA = 0
RXA
RXA
RXENB = 0
RXB
RXB
LEAD
FINISH
PACKAGE
DESCRIPTION
1579
0
0
0
0
20 PIN CERAMIC SIDE BRAZED DIP (20C)
1581
1
1
1
1
20 PIN CERAMIC SIDE BRAZED DIP (20C)
RECOMMENDED TRANSFORMERS
The HI-1579 and HI-1581 transceivers have been
characterized for compliance with the electrical requirements of MIL-STD-1553 when used with the following
transformers. Holt recommends the Premier Magnetics
parts as offering the best combination of electrical
performance, low cost and small footprint.
MANUFACTURER
PART NUMBER
APPLICATION
TURNS RATIO(S)
DIMENSIONS
Premier Magnetics
PM-DB2725EX
Isolation
Dual tapped 1:1.79, 1:2.5
.500 x .500 x .375 inches
TL1553-45
Isolation
Dual tapped 1:1.79, 1:2.5
.630 x 630 x .155 inches
PM-DB2702
Stub coupling
1:1.4
.625 x .500 x .250 inches
TQ-1553-2
Stub coupling
1:1.4
.625 x .625 x .250 inches
Technotrol
Premier Magnetics
Technotrol
HOLT INTEGRATED CIRCUITS
7
HI-1579, HI-1581
REVISION HISTORY
Document Rev. Date
Description of Change
DS1579
F
07/24/09
Correct typographical errors in package dimensions. Clarified available temperature
ranges.
G
10/5/09
Clarified status of RXA/B and RXA/B pins in bus idle state when RXENA or RXENB are
high (logic “1”).
Clarified nomenclature of chip-scale package as QFN. Added ’M’ flow option for QFN
package (’PCM’ package option).
Updated datasheet to include HI-1581 variant.
HOLT INTEGRATED CIRCUITS
8
PACKAGE DIMENSIONS
20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB
(Wide Body, Thermally Enhanced)
Package Type: 20HWE
.0105 ± .0015
(.267 ± .038)
.504 ± .008
(12.79 ± .19)
.407 ± .013
(10.325 ± .32)
inches (millimeters)
.290 typ
(7.37)
Bottom
View
.205 typ
(5.21)
.295 ± .002
(7.493 ± .05)
Top View
See Detail A
.0165 ± .0035
(.419 ± .089)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.090 ± .01
(2.29 ± .25)
.050
BSC
(1.27)
0° to 8°
.0075 ± .004
(.191 ± .089)
.033 ± .017
(.838 ± .432)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
20-PIN CERAMIC SIDE-BRAZED DIP
inches (millimeters)
Package Type: 20C
1.000 ±.010
(25.400 ±.254)
.310 ±.010
(7.874 ±.254)
.050 TYP.
(1.270 TYP.)
.125 min
(3.175)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.300 ± .010
(7.620 ± .254)
.085 ±.009
(2.159 ± .229)
.200
max
(5.080)
.100
BSC
(2.54)
.017 ±.002
(.432 ±.051)
HOLT INTEGRATED CIRCUITS
9
.010 + 0. 02/-.001
(.254 ±.051/-.025)
PACKAGE DIMENSIONS
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
inches (millimeters)
Package Type: 44PCS
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
.020 BSC
(0.50)
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
Top View
Bottom
View
.010
(0.25) typ
.039
max
(1.00)
.008 typ
(0.2)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
10
.016 ± .002
(0.40 ± .05)
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