MP1230A/31A/32A CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter FEATURES • • • • • • Superior Ruggedized 1230 Series: 2 KV ESD • Four Quadrant Multiplication • Stable, More Accurate Segmented DAC Approach – 0.2 ppm/°C Linearity Tempco – 2 ppm/°C Max Gain Error Tempco – Lowest Sensitivity to Amplifier Offset – Lowest Output Capacitance (COUT = 80pF) – Lower Glitch Energy • Monotonic over Temperature Range Lower Data Bus Feedthrough @ CS = 1 VDD from +11 V to +16 V Latch-Up Free CMOS Technology 12-Bit Bus Version: MP1208/1209/1210 16-Bit Upgrade: MP7636A GENERAL DESCRIPTION temperature ranges. Scale factor tempco is a low 2 ppm/°C maximum. The MP1230A series are superior pin for pin replacements for the 1230 series. The MP1230A series is manufactured using advanced thin film resistors on a double metal CMOS process which promotes significant improvements in reliability, latch-up free performance and ESD protection. The MP1230A series incorporates a unique decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 12-bit linearity is achieved without trimming. Outstanding features include: – Stability: integral and differential linearity tempcos are rated at 0.2 ppm/°C typical. Monotonicity is guaranteed over all – Low Output Capacitance: Due to smaller MOSFET switch geometries allowed by decoding, the output capacitance at IOUT1 and IOUT2 is a low 80pF / 40pF and 25pF / 65 pF. This less than half the competitive DAC 1230 series. Lower capacitance allows the MP1230A series to achieve settling times faster than 1 µs for a 10 V step. – Low Sensitivity to Output Amplifier Offset: The linearity error caused by amplifier offset is reduced by a factor of 2 in the MP1230A series over conventional R-2R DACs. The MP1230A series uses a circuit which reduces transients in the supplies caused by DATA bus transitions at CS = 1. SIMPLIFIED BLOCK DIAGRAM VDD INPUT LATCH DB11-DB4 DB3-DB0 D 8 BYTE1/BYTE2 D 8 D RFB Q VREF 12 LE 4 CS WR1 DAC LATCH Q 8 VREF IOUT2 LE Q 12 4 LE XFER WR2 DGND Rev. 2.00 1 IOUT1 AGND MP1230A/31A/32A ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) Plastic Dip –40 to +85°C MP1230ABN +1/2 +3/4 +0.4 Plastic Dip –40 to +85°C MP1231ABN –40 to +85°C +1 +1 +0.4 Plastic Dip MP1232ABN +2 +2 +0.4 SOIC –40 to +85°C MP1230ABS +1/2 +3/4 +0.4 SOIC –40 to +85°C MP1231ABS +1 +1 +0.4 SOIC –40 to +85°C MP1232ABS +2 +2 +0.4 PIN CONFIGURATIONS CS WR1 AGND DB7 DB6 DB5 DB4 VREF RFB DGND See Packaging Section for Package Dimensions 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDD BYTE1/BYTE2 CS WR1 AGND DB7 DB6 DB5 DB4 VREF RFB DGND WR2 XFER DB8 (DB0, LSB) DB9 (DB1) DB10 (DB2) DB11 MSB (DB3) IOUT2 IOUT1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDD BYTE1/BYTE2 WR2 XFER DB8 (DB0, LSB) DB9 (DB1) DB10 (DB2) DB11 MSB (DB3) IOUT2 IOUT1 20 Pin SOIC (Jedec, 0.300”) S20 20 Pin PDIP (0.300”) N20 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 CS Chip Select (Active Low) 12 IOUT2 Current Output 2 2 WR1 Write 1 (Active Low) 13 DB11 (DB3) 3 AGND Analog Ground Data Input Bit 11 (MSB) Data Input Bit 3 4 DB7 Data Input Bit 7 14 DB10 (DB2) Data Input Bit 10 Data Input Bit 2 5 DB6 Data Input Bit 6 15 DB9 (DB1) 6 DB5 Data Input Bit 5 Data Input Bit 9 Data Input Bit 1 7 DB4 Data Input Bit 4 16 DB8 (DB0) Data Input Bit 8 Data Input Bit 0 (LSB) 8 VREF Reference Input Voltage 17 XFER Transfer Control Signal (Active Low) 9 RFB Feedback Resistor 18 WR2 Write 2 (Active Low) 10 DGND Digital Ground 19 IOUT1 Current Output 1 BYTE1/ BYTE2 Byte Sequence Control 11 20 VDD Positive Power Supply Rev. 2.00 2 MP1230A/31A/32A ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) FSR = Full Scale Range N Integral Non-Linearity (Relative Accuracy) MP1230ABN/ATD/ABS MP1231ABN/ATD/ABS MP1232ABN/ATD/ABS INL Differential Non-Linearity MP1230ABN/ATD/ABS MP1231ABN/ATD/ABS MP1232ABN/ATD/ABS DNL Gain Error 12 12 Bits LSB +1/2 +1 +2 +3/4 +1 +2 +3/4 +1 +2 +0.4 +0.4 % FSR Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature ppm/% |∆Gain/∆VDD| ∆VDD = + 0.25V LSB GE TCGE 0.5 Power Supply Rejection Ratio PSRR 5 +20 +20 IOUT 1 +10 +200 nA DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1 Best Fit Straight Line Spec. (Max INL – Min INL) / 2 +1/2 +1 +2 Gain Temperature Coefficient2 Output Leakage Current Test Conditions/Comments RL=100Ω, CL=13pF tS FT µsec mV p-p 1.0 1.0 Full Scale Change to 1/2 LSB VREF=100kHz, 20Vp-p, sinewave REFERENCE INPUT Input Resistance RIN 5 10 VIH VIL 3.0 2.4 20 5 20 kΩ 0.8 +1 0.8 +1 V V µA pF 80 40 65 25 100 60 85 45 100 60 85 45 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s 1.2 +16 2.0 +16 2.0 V mA All digital inputs = 0 V or all = 5 V DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 ILKG 3.0 10 VIN = 0, 5 V ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 POWER SUPPLY Functional Voltage Range4 Supply Current VDD IDD +4.5 Rev. 2.00 3 +4.5 MP1230A/31A/32A ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min 25°C Typ tCS tCH tDS tDH tWR 200 10 100 90 100 100 0 50 70 50 Max Tmin to Tmax Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS2, 3 Chip Select to Write Set-Up Time Chip Select to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width, ns ns ns ns ns NOTES: 1 2 3 4 Full Scale Range (FSR) is 10V. Guaranteed but not production tested. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . GND –0.5 to +6.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND. Rev. 2.00 4 MP1230A/31A/32A TIMING DIAGRAM CS, BYTE1/BYTE2 VIH tCS t CH 50% 50% VIL tWR VIH 50% WR VIL VIH DATA BITS 50% tDS tDH 50% 50% VIL tS SETTLED TO +0.01% IOUT1, IOUT2 DEFINITION OF CONTROL SIGNALS: CS: Chip Select.(Active low) It will enable WR1. WR1: DAC Current Output 2 Bus. IOUT2 is a complement of IOUT1. RFB: Feedback Resistor. This internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the DAC and tracks these resistors over temperature. VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal DAC. The VREF can be selected over the range of +25V to –25V or the analog signal for a 4-quadrant multiplying mode application. VDD: Power Supply Voltage. This is the power supply pin for the part. The VDD can be from +5 V DC to +15 V DC, however optimum voltage is +12 to +15 V DC. Write 1 (Active low) The WR1 is used to load the digital data bits (DB) into the input latch. BYTE1/BYTE2: Byte sequence control. The BYTE1/BYTE2 control pin is used to select both MSB and LSB input latches. WR2: Write 2 (Active low) It will enable XFER. XFER: Transfer control signal (Active low) This signal in combination with WR2 causes the 16-bit data which is available in the input latches to transfer to the DAC register DB0 to DB11: Digital Inputs. DB0 is the least significant digital input (LSB) and DB11 is the most significant digital input (MSB). IOUT1: IOUT2: AGND: Analog Ground Back gate of the DAC N-channel current steering switches. DAC Current Output 1 Bus. IOUT1 is a maximum for a digital code of all 1’s in the DAC register, and is zero for all 0’s in the DAC register. DGND: Digital Ground Rev. 2.00 5 MP1230A/31A/32A THEORY OF OPERATION VDD DB11 (MSB) (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0) DB7 DB6 DB5 DB4 MSB Q D Q D Q D Q D Q D Q D D 12-Bit Q D DAC Q Register Q D Q D Q D D LE Q Q D Q D Q D D 8-Bit Q Input Q D D Latch Q Q D D LE Q D 4-Bit Q D Input Q D Latch Q D LE Q VREF RFB 12-Bit Multiplying D/A Converter IOUT1 IOUT2 LSB BYTE1/BYTE2 CS WR1 XFER WR2 DGND AGND When LE = 1, Q Outputs Follow D Inputs When LE = 0, Q Outputs are Latched Figure 1. Functional Diagram Digital Interface Transferring Data to the DAC Latches Figure 1. shows the internal control logic that controls the writing of the input latches. It is easy to understand how the MP1230A/31A/32A works by understanding each basic operation. Once one or all the input latches have been loaded, the condition XFER= WR2= low transfers the content of the input latches in the DAC latch. The outputs of the DAC latch change and the DAC current (IOUT) will reach a new stable value within the settling time tS (Figure 3.). Writing to Input Latches The condition BYTE1/BYTE2= high, CS = WR1 = 0 loads the data bus DB11-DB4 into both input latches. A second cycle with BYTE1/BYTE2 = low (Figure 2.) loads the pins DB11-DB8 (DB3-DB0) into the 4-bit input latch. Timing diagrams show the inputs CS and DB11-DB0 to be stable during the entire writing cycle. In reality all the above signals can change (Figure 2.) as long as they meet the timing conditions specified in the Electrical Characteristic Table. XFER WR2 or or DB11-0 CS IOUT tS BYTE1/BYTE2 DATA Figure 3. Transfer Cycles from Input Latches to DAC Latches WR1 Figure 2. Write Cycles to Input Latches Rev. 2.00 6 MP1230A/31A/32A PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 7 MP1230A/31A/32A 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20 D 20 11 E H 10 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 8 MP1230A/31A/32A 20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20 S 20 11 1 10 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN MAX –– 0.200 –– 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 9 C MP1230A/31A/32A Notes Rev. 2.00 10 MP1230A/31A/32A Notes Rev. 2.00 11 MP1230A/31A/32A NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12