Fairchild FXMAR2104UMX Dual-supply, 4-bit voltage translator / isolator for open-drain Datasheet

FXMAR2104
Dual-Supply, 4-Bit Voltage Translator / Isolator for
Open-Drain and Push-Pull Applications
Features
Description

Bi-Directional Interface between Any Two Levels:
1.65V to 5.5V



Direction Control Not Needed
The FXMAR2104 is a 4-bit high-performance,
configurable dual-voltage supply, open-drain translator
for bi-directional voltage translation over a wide range of
input and output voltages levels. The FXMAR2104 also
works in a push-pull environment.


I2C-Bus® Isolation
Internal 10KΩ Pull-Up Resistors
System GPIO Resources Not Required when OE
Tied to VCCA
A/B Port VOL = 175mV (Typical), VIL = 150mV,
IOL = 6mA



Open-Drain Inputs / Outputs



Supports I2C Clock Stretching & Multi-Master



Outputs Switch to 3-State if Either VCC is at GND

ESD Protection Exceeds:
- 5kV HBM (per JESD22-A114)
- 2kV CDM (per JESD22-C101)
Works in a Push-Pull Environment
Accommodates Standard-Mode and Fast-Mode
I2C-Bus Devices
Fully Configurable: Inputs and Outputs Track VCC
Non-Preferential Power-Up; Either VCC May Be
Powered-Up First
Intended for use as a voltage translator in applications
using the I2C-Bus® interface, the input and output
2
voltage levels are compatible with I C device
specification voltage levels. Eight internal 10KΩ pull-up
resistors are integrated.
The device is designed so that the A port tracks the
VCCA level and the B port tracks the VCCB level. This
allows for bi-directional A/B port voltage translation
between any two levels from 1.65V to 5.5V. VCCA can
equal VCCB from 1.65V to 5.5V.
Non-preferential power-up means VCC can be poweredup first. Internal power-down control circuits place the
device in 3-state if either VCC is removed.
The two ports of the device have automatic directionsense capability. Either port may sense an input signal
and transfer it as an output signal to the other port.
Tolerant Output Enable: 5V
Packaged in 12-Lead Ultrathin MLP
(1.8mm x 1.8mm)
Ordering Information
Part Number
Operating
Temperature Range
Top
Mark
Package
Packing
Method
FXMAR2104UMX
-40 to +85°C
BY
12-Lead, Ultrathin MLP, 1.8mm x 1.8mm
5000 Units on
Tape and Reel
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator for Open-Drain and Push-Pull Applications
July 2012
OE
VCCB
Dynamic
Driver (with
Time Out)
10K
Internal Direction
Generator &
Control
VbiasB
Vbias A
B
A
VCCA
10K
Internal Direction
Generator &
Control
Dynamic Driver
(with Time Out)
Figure 1. Block Diagram, 1 of 4 Channels
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Block Diagram
www.fairchildsemi.com
2
Figure 2. UMLP (Top-Through View)
Pin Definitions
Pin #
Name
Description
1
VCCB
B-Side Power Supply
2
VCCA
A-Side Power Supply
3, 4, 5, 6
A0, A1, A2, A3
7
GND
8
OE
9, 10, 11, 12
B3, B2, B1, B0
A-Side Inputs or 3-State Outputs
Ground
Output Enable Input
B-Side Inputs or 3-State Outputs
Truth Table
Control
Outputs
OE
LOW Logic Level
3-State
HIGH Logic Level
Normal Operation
Note:
1. If the OE pin is driven LOW, the FXMAR2104 is disabled and the A0, A1, A2, A3, B0, B1, B2 and B3 pins (including
dynamic drivers) are forced into 3-state. Also, if the OE pin is driven LOW, all eight 10KΩ internal pull-up
resistors are decoupled from their respective VCCs.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Pin Configuration
www.fairchildsemi.com
3
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
-0.5
7.0
A Port
-0.5
7.0
B Port
-0.5
7.0
Control Input (OE)
-0.5
7.0
An Outputs 3-State
-0.5
7.0
Bn Outputs 3-State
-0.5
7.0
An Outputs Active
-0.5
VCCA + 0.5V
Bn Outputs Active
-0.5
VCCB + 0.5V
VCCA, VCCB Supply Voltage
VIN
VO
IIK
IOK
IOH / IOL
DC Input Voltage
Output Voltage(2)
DC Input Diode Current
DC Output Diode Current
At VIN < 0V
-50
At VO < 0V
-50
At VO > VCC
+50
DC Output Source/Sink Current
-50
+50
Unit
V
V
mA
mA
mA
ICC
DC VCC or Ground Current per Supply Pin
±100
mA
PD
Power Dissipation
0.129
mW
+150
°C
TSTG
ESD
At 400KHz
Storage Temperature Range
Electrostatic Discharge
Capability
-65
Human Body Model, B-Port
(vs. GND & vs. VCCB)
8
Human Body Model, All Pins,
JESD22-A114
5
Charged Device Mode, JESD22-C101
2
kV
Note:
2. IO absolute maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
1.65
5.50
V
A Port
0
5.5
B Port
0
5.5
Control Input (OE)
0
VCCA
VCCA, VCCB Power Supply Operating
VIN
Input Voltage
ΘJA
Thermal Resistance
TA
Free Air Operating Temperature
-40
V
301.5
C°/W
+85
°C
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Absolute Maximum Ratings
Note:
3. All unused I/O pins should be disconnected.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
4
Power-Up/Power-Down Sequencing
FXM translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (OE) is
designed to track the VCCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up/power-down. The size of the pulldown resistor is based upon the current-sinking
capability of the device driving the OE pin.
The recommended power-up sequence is:
1. Apply power to the first VCC.
2. Apply power to the second VCC.
3. Drive the OE input HIGH to enable the device.
The recommended power-down sequence is:
1. Drive OE input LOW to disable the device.
2. Remove power from either VCC.
3. Remove power from other VCC.
Note:
4. Alternatively, the OE pin can be hardwired to VCCA
to save GPIO pins. If OE is hardwired to VCCA,
either VCC can be powered up or down first.
Application Circuit
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Functional Description
Figure 3. Application Circuit
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
5
C = the bus capacitance. If the FXMAR2104 is attached
to the master [on the A port] and there is a slave on the
B port, the Npassgates act as a low resistive short
between the ports until either of the port’s VCC/2
thresholds are reached. After the RC time constant has
reached the VCC/2 threshold of either port, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the LOW-to-HIGH (LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 4. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
The FXMAR2104 has four bi-directional, open-drain
I/Os and includes a total of eight internal 10K pull-up
resistors (RPUs) on each port of all four data I/O pins. If
a pair of data I/O pins (An/Bn) is not used, these pins
should be left unconnected, eliminating unwanted
current flow through the internal RPUs. External RPUs
can be added to the I/Os to reduce the total RPU value,
depending on the total bus capacitance. The user is free
to lower the total pull-up resistor value to meet the
maximum I2C edge rate per the I2C specification
(UM10204 rev. 03, June 19, 2007). For example,
2
according to the I C specification, the maximum edge
rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns.
If the bus capacitance is approaching the maximum
400pF, a lower total RPU value helps keep the rise time
below 300ns (Fast Mode). Likewise, the I2C
specification also specifies a minimum SCL high time of
600ns during Fast Mode (400KHz). Lowering the total
RPU also helps increase the SCL high time. If the bus
capacitance
approaches
400pF,
consider
the
FXMA2102, which does not contain internal RPUs.
Then the user can calculate the ideal external RPU
2
value. Section 7.1 of the I C specification provides an
excellent guideline for pull-up resistor sizing.
If both the A and B ports of the translator are HIGH, a
high-impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master
or slave device decides to pull SCL or SDA LOW, that
device’s driver pulls down (Isink) SCL or SDA until the
edge reaches the A or B port VCC/2 threshold. When
either the A or B port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the HIGH-to-LOW (HL)
direction, accelerating the falling edge.
Theory of Operation
The FXMAR2104 is designed for high-performance level
shifting and buffer / repeating in an I2C application.
Figure 1 shows that each bi-directional channel contains
two series-Npassgates and two dynamic drivers. This
2
hybrid architecture is highly beneficial in an I C
application where auto-direction is a necessity.
For example, during the following three I2C protocol
events:



Clock Stretching
th
Slave’s ACK Bit (9 bit = 0) following a Master’s
Write Bit (8th bit = 0)
Clock Synchronization and Multi Master
Arbitration
the bus direction needs to change from master-to-slave
to slave to master without the occurrence of an edge. If
there is an I2C translator between the master and slave
in these examples, the I2C translator must change
direction when both A and B ports are LOW. The
Npassgates can accomplish this task very efficiently
because, when both A and B ports are LOW, the
Npassgates act as a low resistive short between the two
(A and B) ports.
Figure 4. Waveform C: 600pF, Total RPU: 2.2KΩ
2
2
Due to I C’s open-drain topology, I C masters and
slaves are not push-pull drivers. Logic LOWs are “pulled
down” (Isink), while logic HIGHs are “let go” (3-state). For
example, when the master lets go of SCL (SCL always
comes from the master), the rise time of SCL is largely
determined by the RC time constant, where R = RPU and
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Application Information
www.fairchildsemi.com
6
2
The I C specification mandates a maximum VIL (IOL of
3mA) of VCC • 0.3 and a maximum VOL of 0.4V. If there
is a master on the A port of an I2C translator with a VCC
2
of 1.65V and a slave on the I C translator B port with a
VCC of 3.3V, the maximum VIL of the master is (1.65V x
0.3) 495mV. The slave could legally transmit a valid
logic LOW of 0.4V to the master.
If the I2C translator’s channel resistance is too high, the
voltage drop across the translator could present a VIL to
Figure 5. VOL vs. IOL
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
the master greater than 495mV. To complicate matters,
2
the I C specification states that 6mA of IOL is
recommended for bus capacitances approaching
400pF. More IOL increases the voltage drop across the
I2C translator. The I2C application benefits when I2C
translators exhibit low VOL performance. Figure 5
depicts typical FXMAR2104 VOL performance vs. a
competitor, given a 0.4V VIL.
VOL vs. IOL
www.fairchildsemi.com
7
2
The FXMAR2104 supports I C-Bus
following conditions:


®
isolation for the
Bus isolation if bus clear
Either VCC to GND
If slave #2 is a camera that is suddenly removed from
2
the I C bus, resulting in VCCB transitioning from a valid
VCC (1.65V – 5.5V) to 0V; the FXMAR2104
automatically forces all I/Os on both its A and B ports
into 3-state. Once VCCB has reached 0V, full I2C
communication between the master and slave #1
remains undisturbed.
Bus isolation if either VCC goes to ground
Bus Clear
Because the I2C specification defines the minimum SCL
frequency of DC, the SCL signal can be held LOW
2
forever; however, this condition shuts down the I C bus.
The I2C specification refers to this condition as Bus
Clear. In Figure 6, if slave #2 holds down SCL forever,
the master and slave #1 are not able to communicate
because the FXMAR2104 passes the SCL stuck-LOW
condition from slave #2 to slave #1 as well as the
Figure 6. Bus Isolation
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
master. However, if the OE pin is pulled LOW
(disabled), both ports (A and B) are 3-stated. This
results in the FXMAR2104 isolating slave #2 from the
master and slave #1, allowing full communication
between the master and slave #1.
2
I C Bus Isolation
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8
TA = –40°C to +85°C.
Symbol
Parameter
VIHA
High Level Input
Voltage A
VIHB
High Level Input
Voltage B
VILA
Low Level Input
Voltage A
VILB
Low Level Input
Voltage B
VOL
Low Level
Output Voltage
IL
IOFF
IOZ
ICCA/B
Input Leakage
Current
Condition
Min.
Typ.
Max.
Unit
Data Inputs An
1.65-5.50 1.65-5.50 VCCA – 0.4
Control Input OE
1.65-5.50 1.65-5.50 0.7 x VCCA
Data Inputs Bn
1.65-5.50 1.65-5.50 VCCB – 0.4
Data Inputs An
1.65-5.50 1.65-5.50
0.4
Control Input OE
1.65-5.50 1.65-5.50
0.3 x
VCCA
V
Data Inputs Bn
1.65-5.50 1.65-5.50
0.4
V
1.65-5.50 1.65-5.50
0.4
V
1.65-5.50 1.65-5.50
±1
µA
V
V
VIL = 0.15V
IOL = 6mA
Control Input OE,
VIN = VCCA or GND
Power-Off
Leakage Current
3-State Output
Leakage(6)
Quiescent
Supply
(7,8)
Current
VCCA (V) VCCB (V)
An
VIN or VO = 0V
to 5.5V
0
5.50
±2
Bn
VIN or VO = 0V
to 5.5V
5.50
0
±2
An,
Bn
VO = 0V to
5.5V,
OE = VIL
5.50
5.50
±2
An
VO = 0V to
5.5V,
OE = Don’t
Care
5.50
0
±2
Bn
VO = 0V to
5.5V,
OE = Don’t
Care
0
5.50
±2
VIN = VCCI or
Floating, IO = 0
µA
1.65-5.50 1.65-5.50
5
µA
1.65-5.50 1.65-5.50
5
µA
ICCZ
Quiescent
VIN = VCCI or GND,
Supply Current(7) IO = 0, OE = VIL
ICCA
VIN = 5.5V or GND,
Quiescent
(6) IO = 0, OE = Don’t
Supply Current
Care, Bn to An
ICCB
VIN = 5.5V or GND, IO 1.65-5.50
0
Quiescent
(6) = 0, OE = Don’t
Supply Current
0
1.65-5.50
Care, An to Bn
RPU
Resistor Pull-up
Value
VCCA & VCCB Sides
µA
0
1.65-5.50
-2
1.65-5.50
0
2
1.65-5.50 1.65-5.50
µA
-2
2
10
µA
KΩ
Notes:
5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic
Output Electrical Characteristics.
6. “Don’t Care” indicates any valid logic level.
7. VCCI is the VCC associated with the input side.
8. Reflects current per supply, VCCA or VCCB.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
DC Electrical Characteristics
www.fairchildsemi.com
9
Output Rise / Fall Time
Output load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
VCCO(10)
Symbol
Parameter
4.5 to 5.5V 3.0 to 3.6V
2.3 to 2.7V
1.65 to
1.95V
Unit
Typical
trise
tfall
(11)
Output Rise Time; A Port, B Port
(12)
Output Fall Time; A Port, B Port
3
4
5
7
ns
11
8
6
4
ns
Notes:
9. Output rise and fall times guaranteed by design simulation and characterization; not production tested.
10. VCCO is the VCC associated with the output side.
11. See Figure 11.
12. See Figure 12.
( )
Maximum Data Rate 13
Output load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
VCCB
VCCA
Direction
4.5 to 5.5V
3.0 to 3.6V
2.3 to 2.7V
1.65 to 1.95V
Unit
Minimum
4.5V to 5.5V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
A to B
26
20
16
9
B to A
26
20
16
9
A to B
26
20
16
9
B to A
26
20
16
9
A to B
26
20
16
9
B to A
26
20
16
9
A to B
26
20
16
9
B to A
26
20
16
9
Note:
13. F-toggle guaranteed by design simulation; not production tested.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
MHz
MHz
MHz
MHz
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Dynamic Output Electrical Characteristics
www.fairchildsemi.com
10
Output Load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
VCCB
Symbol
Parameter
VCCA = 4.5 to 5.5V
A to B
tPLH
B to A
A to B
tPHL
B to A
OE to A
tPZL
OE to B
OE to A
tPLZ
OE to B
tskew
A Port, B Port(14)
VCCA = 3.0 to 3.6V
A to B
tPLH
B to A
A to B
tPHL
B to A
OE to A
tPZL
OE to B
OE to A
tPLZ
OE to B
tskew
A Port, B Port(14)
VCCA = 2.3 to 2.7V
A to B
tPLH
B to A
A to B
tPHL
B to A
OE to A
tPZL
OE to B
OE to A
tPLZ
OE to B
tskew
A Port, B Port(14)
VCCA = 1.65 to 1.95V
A to B
tPLH
B to A
A to B
tPHL
B to A
OE to A
tPZL
OE to B
OE to A
tPLZ
OE to B
tskew
A Port, B Port(14)
4.5 to 5.5V
3.0 to 3.6V
2.3 to 2.7V
1.65 to 1.95V
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
1
1
2
2
4
3
65
5
0.5
3
3
4
4
5
5
100
9
1.5
1
2
3
2
6
4
65
6
0.5
3
4
5
5
10
7
105
10
1.0
1
3
4
2
5
5
65
7
0.5
3
5
6
6
9
8
105
12
1.0
1
4
6
5
7
10
65
9
0.5
3
7
7
7
15
15
105
16
1.0
2.0
1.5
2.0
2.0
4.0
4.0
100
5
0.5
5.0
3.0
4.0
4.0
8.0
8.0
115
10
1.5
1.5
1.5
2.0
2.0
5.0
6.0
100
4
0.5
3.0
4.0
4.0
4.0
9.0
9.0
115
8
1.0
1.5
2.0
2.0
2.0
6.0
8.0
100
5
0.5
3.0
6.0
5.0
5.0
11.0
11.0
115
10
1.0
1.5
3.0
6.0
3.0
7.0
10.0
100
9
0.5
3.0
9.0
7.0
5.0
15.0
14.0
115
15
1.0
2.5
1.5
2
2
5.0
4.0
100
65
0.5
5.0
3.0
5
5
10.0
8.0
115
110
1.5
2.5
2.0
2
2
5.0
4.5
100
65
0.5
5.0
4.0
5
5
10.0
9.0
115
110
1.0
2.0
3.0
2
2
6.0
5.0
100
65
0.5
4.0
6.0
5
5
12.0
10.0
115
115
1.0
1.0
5.0
5
3
90.0
9.0
100
12
0.5
3.0
10.0
6
6
18.0
18.0
115
25
1.0
4.0
1.0
5
4
11
6
75
75
0.5
7.0
2.0
8
8
15
14
115
115
1.5
4.0
1.0
3
3
11
6
75
75
0.5
7.0
2.0
7
7
14
14
115
115
1.0
5.0
1.5
3
3
14
6
75
75
0.5
8.0
3.0
7
7
28
14
115
115
1.0
5.0
5.0
8
3
14
9
75
75
0.5
10.0
10.0
9
7
23
19
115
115
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
AC Characteristics(17)
Note:
14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 14). Skew is
guaranteed, but not tested.
15. AC Characteristic is guaranteed by Design and Characterization
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
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11
TA = +25°C.
Symbol
Parameter
Condition
CIN
Input Capacitance Control Pin (OE)
CI/O
Input/Output Capacitance, An, Bn
Typical
Unit
VCCA = VCCB = GND
2.2
pF
VCCA = VCCB = 5.0V, OE = GND
13.0
pF
Figure 7. AC Test Circuit
Table 1.
Propagation Delay Table(16)
Test
Input Signal
Output Enable Control
tPLH, tPHL
Data Pulses
VCCA
tPZL (OE to An, Bn)
0V
LOW to HIGH Switch
tPLZ (OE to An, Bn)
0V
HIGH to LOW Switch
Note:
16. For tPZL and tPLZ testing, an external 2.2KΩ pull-up resistor to VCCO is required to force the I/O pins HIGH while
OE is LOW. When OE is low, the internal 10KΩ RPUs are decoupled from their respective VCC’s.
Table 2.
AC Load Table
VCCO
CL
RL
1.8 ± 0.15V
50pF
NC
2.5 ± 0.2V
50pF
NC
3.3 ± 0.3V
50pF
NC
5.0 ± 0.5V
50pF
NC
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Capacitance
www.fairchildsemi.com
12
DATA
IN
VCCI
Vmi
OUTPUT
CONTROL
GND
DATA
OUT
tPZL
Vmo
DATA
OUT
VCCO
VCCA
Symbol
Vmi
GND
tPLZ
DATA
OUT
Figure 10.
Vx
VOL
VY
VOL
Figure 9. 3-STATE Output Low Enable Time(17)
Figure 8. Waveform for Inverting and Non-Inverting
Functions(17)
OUTPUT
CONTROL
GND
tpxx
tpxx
VCCA
Vmi
VCC
Vmi
VCCI / 2
Vmo
VCCO / 2
VX
0.5 x VCCO
VY
0.1 x VCCO
(17)
3-STATE Output High Enable Time
Figure 11. Active Output Rise Time
Figure 12. Active Output Fall Time
VCCO
DATA
OUTPUT
Vmo
Vmo
GND
tperiod
DATA
IN
tskew
VCCI
VCCI / 2
tskew
VCCI / 2
GND
DATA
OUTPUT
F-toggle rate, f = 1 / tperiod
VCCO
Vmo
Vmo
GND
tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin)
Figure 13. F-Toggle Rate
Figure 14. Output Skew Time
Notes:
17. Input tR = tF = 2.0ns, 10% to 90% at VIN = 1.65V to 1.95V;
Input tR = tF = 2.0ns, 10% to 90% at VIN = 2.3 to 2.7V;
Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 3.6V only;
Input tR = tF = 2.5ns, 10% to 90%, at VIN = 4.5V to 5.5 only.
18. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Timing Diagrams
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13
1.80
0.10 C
A
(11X)
2.10
B
0.563
0.588
2X
1
1.80
0.40
2.10
PIN#1 IDENT
TOP VIEW
0.55 MAX.
0.10 C
0.10 C
(12X) 0.20
2X
RECOMMENDED
LAND PATTERN
0.152
0.45
0.35
0.08 C
0.05
0.00
0.10
SEATING C
PLANE
SIDE VIEW
0.10
0.10
DETAIL A
SCALE : 2X
NOTES:
0.35
(11X)
0.45
3
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
6
0.40
DETAIL A
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
1
PIN#1 IDENT
12
9
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
0.25
0.15 (12X)
BOTTOM VIEW
0.10 C A B
0.05 C
E. DRAWING FILENAME: MKT-UMLP12Arev4.
PACKAGE
EDGE
LEAD
OPTION 1
SCALE : 2X
LEAD
OPTION 2
SCALE : 2X
Figure 15. 12-Lead Ultrathin MLP, 1.8mm x 1.8mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
Physical Dimensions
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14
FXMAR2104 — Dual-Supply, 4-Bit Voltage Translator / Isolator / for Open-Drain and Push-Pull Applications
15
www.fairchildsemi.com
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1