Renesas M38D59G7XXXHP Single-chip 8-bit cmos microcomputer Datasheet

38D5 Group
REJ03B0158-0304
Rev.3.04
May 20, 2008
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 38D5 Group is the 8-bit microcomputer based on the 740
Family core technology.
The 38D5 Group is pin-compatible with the 38C5 Group.
The 38D5 Group has an LCD drive control circuit, an A/D
converter, a serial interface, and a ROM correction function as
additional functions.
The QzROM version and the flash memory version are available.
The flash memory version does not have a selection function for
the oscillation start mode. Only the on-chip oscillator starts
oscillating.
The various microcomputers include variations of memory size,
and packaging. For details, refer to the section on part
numbering.
FEATURES
• Power source voltage (QzROM version)
[In frequency/2 mode]
f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 2 MHz................................................... 1.8 to 5.5 V
[In frequency/4 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V
[In frequency/8 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V
[In low-speed mode].............................................. 1.8 to 5.5 V
Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
• Basic machine-language instructions ................................. 71
• The minimum instruction execution time ................... 0.32 µs
(at 12.5 MHz oscillation frequency)
• Memory size (QzROM version)
ROM ........................................................ 32 K to 60 K bytes
RAM ......................................................... 1536 to 2048 bytes
• Memory size (Flash memory version)
ROM ...................................................................... 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports .. 59 (common to SEG: 36)
• Interrupts ............................................. 17 sources, 16 vectors
(Key input interrupt included)
• Timers ..................................................... 8-bit × 4, 16-bit × 2
• Serial interface
Serial I/O1 ...............8-bit × 1 (UART or Clock-synchronized)
Serial I/O2 .............................. 8-bit × 1 (Clock-synchronized)
• PWM .......... 10-bit × 2, 16-bit × 1 (common to IGBT output)
• A/D converter .......................................... 10-bit × 8 channels
(A/D converter can be operated in low-speed mode.)
• Watchdog timer ......................................................... 8-bit × 1
• ROM correction function ....................... 32 bytes × 2 vectors
• LED direct drive port ............................................................ 6
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
• LCD drive control circuit
Bias ............................................................................ 1/2, 1/3
Duty ............................................................... Static, 2, 3, 4, 8
Common output ................................................................. 4/8
Segment output .............................................................. 32/36
• Main clock generating circuit ............................................... 1
(connect to external ceramic resonator or on-chip oscillator)
• Sub-clock generating circuit ..................................................1
(connect to external quartz-crystal oscillator)
• Power source voltage (Flash memory version)
[In frequency/2 mode]
f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 2.7 to 5.5 V
[In frequency/4 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V
[In frequency/8 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V
[In low-speed mode].............................................. 2.7 to 5.5 V
Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
• Power dissipation (QzROM version)
• In frequency/2 mode ..................................... Typ. 32 mW
(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ........................................ Typ. 18 µW
(VCC = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
• Power dissipation (Flash memory version)
• In frequency/2 mode ..................................... Typ. 20 mW
(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ...................................... Typ. 1.1 mW
(VCC = 2.7 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
• Operating temperature range ............................... −20 to 85°C
Flash Memory Mode
• Program/Erase voltage ............................. VCC = 2.7 to 5.5 V
• Program method ....................... Programming in unit of byte
• Erase method .................................................... Block erasing
• Program/Erase control by software command
APPLICATION
Household products, Consumer electronics, etc.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 1 of 134
Rev.3.04 May 20, 2008
REJ03B0158-0304
Fig. 1 Pin configuration (QFP Package)
Page 2 of 134
21
22
23
24
V L2
V L1
20
19
18
17
P7 1/C 2 /INT 11
P7 0/C 1/INT 01
P7 2/T 2OUT/CKOUT
V L3
P7 4/PWM 1 /T 4OUT
P7 3/PWM 0/T 3OUT
16
15
14
13
74
12
73
11
72
10
71
9
8
7
6
5
4
3
2
1
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
P43/SRDY1
P42/SCLK1
P41/TXD
P40/RXD
AVSS
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
RESET
P6 1/X COUT
P6 0/X CIN
V SS
X IN
X OUT
V CC
P5 1/AN 1/RTP 1
P5 0/AN 0/RTP 0
P6 7/CNTR 1/(LED 5)
P6 6/INT 10/CNTR 0/(LED 4)
P6 5/T XOUT1 /(LED 3)
P6 4/INT 2/(LED 2)
P6 3/T XOUT2/(LED 1)
P6 2 /INT 00/(LED 0)
OSCSEL (Note 1)
Package type : PRQP0080GB-A(80P6N-A)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P1 5/SEG 21
P1 6/SEG 22
P17/SEG 23
P1 3/SEG 19
P1 4/SEG 20
P12/SEG 18
P2 0/SEG 0/(KW 4)
P2 1/SEG 1/(KW 5)
P2 2/SEG 2/(KW 6)
P2 3/SEG 3/(KW 7)
P2 4/SEG 4
P2 5/SEG 5
P2 6/SEG 6
P2 7/SEG 7
P0 0/SEG 8
P0 1/SEG 9
P0 2/SEG 10
P0 3/SEG 11
P0 4/SEG 12
P0 5/SEG 13
P0 6/SEG 14
P0 7/SEG 15
P10/SEG 16
P11/SEG 17
38D5 Group
PIN CONFIGURATION
(TOP VIEW)
65
40
66
39
67
38
68
37
69
36
70
35
M38D5XGXFP
M38D59FFFP
34
32
33
31
75
76
30
29
77
28
78
27
79
26
80
25
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
Note 1: CNVSS in flash
memory version
P1 3 /SEG 19
P1 4 /SEG 20
P1 5 /SEG 21
43
42
41
45
44
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
M38D5XGXHP
M38D59FFHP
70
71
72
31
30
29
73
28
74
27
75
26
18
19
20
V L3
V L2
P7 1/C 2/INT 11
17
P7 2/T 2OUT /CKOUT
15
14
13
12
11
10
9
8
16
P6 4/INT 2/(LED 2)
P6 3/T XOUT2/(LED 1)
P6 2/INT 00 /(LED 0)
OSCSEL (Note 1)
P6 7/CNTR 1/(LED 5)
P6 6/INT 10/CNTR 0/(LED 4)
P6 5/T XOUT1/(LED 3)
RESET
P6 1/X COUT
P6 0/X CIN
V SS
X IN
X OUT
V CC
P7 4/PWM 1/T 4OUT
P7 3 /PWM 0/T 3OUT
21
7
22
80
6
23
79
5
78
4
24
3
25
77
2
76
1
P21/SEG1/(KW5)
P20/SEG0/(KW4)
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
P43/SRDY1
P42/SCLK1
P41/TXD
P40/RXD
AVSS
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1/RTP1
P50/AN0/RTP0
59
60
PIN CONFIGURATION
(TOP VIEW)
P2 2/SEG 2/(KW 6)
P2 3/SEG 3/(KW 7)
P2 4/SEG 4
P2 5/SEG 5
P2 6/SEG 6
P2 7/SEG 7
P0 0/SEG 8
P0 1/SEG 9
P0 2/SEG 10
P0 3/SEG 11
P0 4/SEG 12
P0 5/SEG 13
P0 6/SEG 14
P0 7/SEG 15
P1 0/SEG 16
P1 1/SEG 17
P1 2/SEG 18
38D5 Group
Package type : PLQP0080KB-A(80P6Q-A)
Fig. 2 Pin configuration (LQFP package)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 3 of 134
P16/SEG22
P17/SEG23
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
VL1
P70/C1/INT01
Note 1: CNVSS in flash
memory version
38D5 Group
Table 1
Performance overview (1)
Parameter
Function
Number of basic instructions
71
Instruction execution time
0.32 µs (Minimum instruction, Oscillation frequency 12.5 MHz)
Oscillation frequency
16 MHz (Maximum)(1)
Memory sizes
(QzROM version)
ROM
32 K to 60 K bytes
RAM
1536 to 2048 bytes
ROM
Memory sizes
(Flash memory version) RAM
60 K bytes
2048 bytes
2-bit × 1
Input port
P70, P71
I/O port
P0-P6, P72-P74
8-bit × 7, 3-bit × 1 (36 pins sharing SEG)
Interrupt
17 sources, 16 vectors (includes key input interrupt)
Timer
8-bit × 4, 16-bit × 2
Serial I/O1
8-bit × 1 (UART or Clock-synchronized)
Serial I/O2
8-bit × 1 (Clock-synchronized)
PWM
10-bit × 2, 16-bit × 1 (common to IGBT output)
A/D converter
10-bit × 8 (operated in low-speed mode)
Watchdog timer
8-bit × 1
ROM correction function
32 bytes × 2 vectors
LED direct drive port
6 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)
LCD drive control
circuit
Bias
1/2, 1/3
Duty
Static, 2, 3, 4, 8
Common output
4/8
Segment output
32/36
Main clock generating circuits
Built-in (connect to external ceramic resonator or on-chip oscillator)
Sub-clock generating circuits
Power source voltage
(QzROM version)
Built-in (connect to external quartz-crystal oscillator)
In frequency/2 mode
f(XIN) ≤ 12.5 MHz 4.5 to 5.5 V
(1)
f(XIN) ≤ 8 MHz
4.0 to 5.5 V
f(XIN) ≤ 4 MHz
2.0 to 5.5 V
In frequency/4 mode
In frequency/8 mode
f(XIN) ≤ 2 MHz
1.8 to 5.5 V
f(XIN) ≤ 16 MHz
4.5 to 5.5 V
f(XIN) ≤ 8 MHz
2.0 to 5.5 V
f(XIN) ≤ 4 MHz
1.8 to 5.5 V
f(XIN) ≤ 16 MHz
4.5 to 5.5 V
f(XIN) ≤ 8 MHz
2.0 to 5.5 V
f(XIN) ≤ 4 MHz
1.8 to 5.5 V
In low-speed mode
Power source voltage In frequency/2 mode
(Flash memory version) (1)
1.8 to 5.5 V
f(XIN) ≤ 12.5 MHz 4.5 to 5.5 V
f(XIN) ≤ 8 MHz
4.0 to 5.5 V
f(XIN) ≤ 4 MHz
2.7 to 5.5 V
In frequency/4 mode
f(XIN) ≤ 16 MHz
4.5 to 5.5 V
f(XIN) ≤ 8 MHz
2.7 to 5.5 V
In frequency/8 mode
f(XIN) ≤ 16 MHz
4.5 to 5.5 V
f(XIN) ≤ 8 MHz
2.7 to 5.5 V
In low-speed mode
NOTE:
2.7 to 5.5 V
1. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 4 of 134
38D5 Group
Table 2
Performance overview (2)
Parameter
Function
Power dissipation
(QzROM version)
In frequency/2 mode
Std. 32 mW (Vcc = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
In low-speed mode
Std. 18 µW (Vcc = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
Power dissipation
(Flash memory version)
In frequency/2 mode
Std. 20 mW (Vcc = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
In low-speed mode
Std. 1.1 mW (Vcc = 2.7 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
Input/Output withstand voltage
VCC
Input/Output characteristics
Output current
Operating temperature range
10 mA
-20 to 85°C
Device structure
CMOS silicon gate
Package
80-pin plastic molded LQFP/QFP
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 5 of 134
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
Fig. 3 Functional block diagram
Page 6 of 134
8
8
Port P5 (8)
4 COM × 36 SEG
8 COM × 32 SEG or
LCD drive control circuit
ROM correction
Serial I/O2
(Clock synchronous)
8
8
Timer
3
2
Port P7 (5)
Watchdog timer
PWM1 (10 bits)
Timer 4 (8 bits)
PWM0 (10 bits)
Timer 3 (8 bits)
Timer 2 (8 bits)
Timer 1 (8 bits)
Timer Y (16 bits)
IGBT output
PWM (16 bits)
CPU core
Port P3 (8)
Timer X (16 bits)
Port P6 (8)
Serial I/O1
(UART or Clock synchronous)
Serial I/O
A/D converter
10-bits × 8-channels
8
Port P2 (8)
Internal peripheral function
Port P1 (8)
8
On-chip
oscillator
RAM
RAM for LCD display
(36 bytes)
ROM
Memory
X IN –X OUT
(Main clock)
X CIN –X COUT
(Sub-clock)
System clock φ generation
---------------------------------------------------------------------------------------------------------------------------------------------
Rev.3.04 May 20, 2008
REJ03B0158-0304
Port P4 (8)
Port P0 (8)
8
---------------------------------------------------------------------------------------------------------------------------------------------
FUNCTIONAL BLOCK DIAGRAM
38D5 Group
38D5 Group
PIN DESCRIPTION
Table 3
Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
• Apply power source voltage to VCC, and 0 V to VSS.
RESET
Reset input
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to
set the oscillation frequency. When an external clock is used, connect the clock source to
XIN, and leave XOUT pin open.
• Feedback resistor is built in between XIN pin and XOUT pin.
XIN
Clock input
XOUT
Clock output
VL1, VL2, VL3
LCD power
source
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
• Input 0 − VL3 voltage to LCD.
COM0−
COM3
Common output
• LCD common output pins.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
COM4/SEG35−
COM7/SEG32
Common output
Segment output
• LCD common/segment output pins.
P00/SEG8−
P07/SEG15
I/O port P0
•
•
•
•
P10/SEG16−
P17/SEG23
I/O port P1
•
•
•
•
P20/SEG0/(KW4)−
P23/SEG3/(KW7)
I/O port P2
•
•
•
•
P30/SEG24−
P37/SEG31
I/O port P3
•
•
•
•
P40/RXD
P41/TXD
P42/SCLK1
P43/SRDY1
I/O port P4
•
•
•
•
P24/SEG4−
P27/SEG7
P44/SIN2/(KW0)
P45/SOUT2/(KW1)
P46/SCLK2/(KW2)
P47/SRDY2/(KW3)
Rev.3.04 May 20, 2008
REJ03B0158-0304
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
programmed as either input or output.
• Pull-up control is enabled in 4-bit unit.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• Key input interrupt
input pins
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in 4-bit unit.
• Serial I/O1 function pins
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output. • Serial I/O2
• Key input interrupt
• Pull-up control is enabled in 4-bit unit.
function pins
input pins
Page 7 of 134
38D5 Group
Table 4
Pin description (2)
Pin
P50/AN0/RTP0
P51/AN1/RTP1
Name
Function
•
•
•
•
P52/AN2−
P56/AN6
P57/AN7/ADKEY0
P60/XCIN
P61/XCOUT
Function except a port function
• AD converter
8-bit I/O port.
input pins
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
I/O port P5
I/O port P6
P65/TXOUT1/(LED3)
P66/INT10/CNTR0/
(LED4)
• ADKEY input pin
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• P62 to P67 (6 bits) are enabled to output large
current for LED drive.
• Sub clock generating I/O pins
(oscillator connected)
• Timer X, Timer Y
output pins
• External interrupt
pins
• External interrupt
pins
• External
capacitor connect
pins for a voltage
multiplier of LCD.
•
•
•
•
P62/INT00/(LED0)
P63/TXOUT2/(LED1)
P64/INT2/(LED2)
• Real time port
function pins
• External interrupt pin
• Timer X output pin
• External interrupt pin
• Timer X output pin
P67/CNTR1/(LED5)
P70/C1/INT01
P71/C2/INT11
Input port P7
• 2-bit input port.
• CMOS input level.
P72/T2OUT/CKOUT
I/O port P7
•
•
•
•
• Clock output pin
3-bit I/O port.
CMOS compatible input level.
• PWM output pins
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in 3-bit unit.
P73/PWM0/T3OUT
P74/PWM1/T4OUT
OSCSEL
(Only QzROM
version)
Oscillation start
selection pin
CNVSS
CNVSS
(Only flash memory
version)
• Timer 4 output pin
• Whether oscillation starts by an oscillator between the XIN and XOUT pins or an on-chip
oscillator is selected.
• VPP power source input pin in the QzROM writing mode.
• Pin for controlling the operating mode of the chip. Connect to VSS.
VREF
Analog reference • Reference voltage input pin for A/D converter.
voltage
AVSS
Analog power
source
Rev.3.04 May 20, 2008
REJ03B0158-0304
• Timer 2 output pin
• Timer 3 output pin
• Analog power source input pin for A/D converter. Connect to VSS.
Page 8 of 134
38D5 Group
PART NUMBERING
Product M38D5 8 G 8 - XXX FP
Package type
FP: PRQP0080GB-A package
HP: PLQP0080KB-A package
ROM number
Omitted in the shipped in blank version.
ROM memory size
1 : 4096 bytes
9 : 36864 bytes
2 : 8192 bytes
A : 40960 bytes
3 : 12288 bytes B : 45056 bytes
4 : 16384 bytes C : 49152 bytes
5 : 20480 bytes D : 53248 bytes
6 : 24576 bytes E : 57344 bytes
7 : 28672 bytes F : 61440 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
G : QzROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 4 Part numbering
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 9 of 134
38D5 Group
GROUP EXPANSION
Renesas plans to expand the 38D5 Group as follows.
Packages
• PRQP0080GB-A ................. 0.8 mm-pitch plastic molded QFP
• PLQP0080KB-A ...............0.5 mm-pitch plastic molded LQFP
Memory Size
<QzROM version>
• ROM size ................................................... 32 K to 60 K bytes
• RAM size .................................................. 1536 to 2048 bytes
<Flash memory version>
• ROM size ................................................................ 60 K bytes
• RAM size ............................................................... 2048 bytes
Memory Expansion Plan
M38D59GF/FF
ROM size 60K
(bytes)
56K
M38D59GC
48K
40K
M38D58G8
32K
28K
24K
20K
16K
12K
8K
4K
192 256
384
512
640
768
896
1,024
1,536
2,048
RAM size (bytes)
Fig. 5 Memory expansion plan
Currently supported products are listed below.
Table 5
Support products
Part No.
M38D58G8-XXXFP
As of Apr. 2008
ROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Package
32768 (32638)
1536
PRQP0080GB-A
M38D58G8-XXXHP
M38D58G8FP
32768 (32638)
1536
49152 (49022)
2048
49152 (49022)
2048
61440 (61310)
2048
61440 (61310)
PRQP0080GB-A
QzROM version (blank)
PRQP0080GB-A
QzROM version
2048
PRQP0080GB-A
QzROM version (blank)
PLQP0080KB-A
61440 (61310)
M38D59FFHP
Rev.3.04 May 20, 2008
REJ03B0158-0304
QzROM version
PLQP0080KB-A
M38D59GFHP
M38D59FFFP
PRQP0080GB-A
PLQP0080KB-A
M38D59GF-XXXHP
M38D59GFFP
QzROM version (blank)
PLQP0080KB-A
M38D59GCHP
M38D59GF-XXXFP
PRQP0080GB-A
PLQP0080KB-A
M38D59GC-XXXHP
M38D59GCFP
QzROM version
PLQP0080KB-A
M38D58G8HP
M38D59GC-XXXFP
Remarks
2048
PRQP0080GB-A
PLQP0080KB-A
Page 10 of 134
Flash memory version
38D5 Group
Table 6
Differences between QzROM and flash memory versions
QzROM version
Flash memory version
Main clock XIN or on-chip oscillator selectable
Oscillation circuit at reset and at returning from stop mode
by OSCSEL pin
On-chip oscillator
Termination of OSCEL/CNVSS pin
OSCSEL = “H”
OSCSEL = “L”
CNVSS = “L”
Main clock oscillation at reset and at returning from
stop mode
Oscillation on
Stop
Stop
On-chip oscillator oscillation at reset and at returning
from stop mode
Stop
Oscillation on
Oscillation on
f(XIN)/8
f(OCO)/32
f(OCO)/32
Required
Optional
System clock φ oscillation at reset and at returning
from stop mode
Mounting of main clock oscillation circuit
Optional
On-chip oscillator oscillation in low speed-mode
Stop
Stop by setting the on-chip
oscillator stop bit because it
is not stopped.
Writing “1” to on-chip oscillator stop bit in on-chip
oscillator mode
On-chip oscillator is stopped
On-chip oscillator is not
stopped
Reset input “L” pulse width
Absolute maximum rating: OSCSEL/CNVSS pin
2 µs or more
2 ms or more
−0.3 to 8.0
−0.3 to VCC + 0.3
Minimum operating power source voltage
1.8 V
2.7 V
A/D converter minimum operating power source voltage
2.0 V
2.7 V
NOTE:
1. For detailed specifications, confirm the descriptions in the Datasheet.
Notes on Differences between QzROM and Flash Memory Versions
(1) The memory map, the writing modes and programming
circuits vary because of the differences in their internal
memories.
(2) The oscillation parameters of XIN-XOUT and XCIN-XCOUT
may vary.
(3) The QzROM version and the flash memory version MCUs
differ in their manufacturing processes, built-in ROM, and
layout patterns. Because of these differences, characteristic
values, operation margins, A/D conversion accuracy, noise
immunity, and noise radiation may vary within the specified
range of electrical characteristics.
(4) When switching from the flash memory version to the
QzROM version, implement system evaluations equivalent
to those implemented in the flash memory version.
(5) The both operations except the electrical characteristics are
same at the emulator (emulator MCU board: M38D59TRLFS).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 11 of 134
38D5 Group
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38D5 Group uses the standard 740 Family instruction set.
Refer to the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
The central processing unit (CPU) has six registers. Figure 6
shows the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as
arithmetic data transfer, etc., are executed mainly through the
accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y
and specifies the real address.
b7
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and
interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0”, the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Table 7 shows the push and pop instructions of accumulator or
processor status register.
Store registers other than those described in Figure 7 with
program when the user needs them during interrupts or
subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b0
A
b7
Accumulator
b0
X
b7
Index register X
b0
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
PCL
Program counter
b7
b0
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 12 of 134
38D5 Group
On-going Routine
Interrupt request (1) →
M(S) ← (PCH)
Push return address
on stack
(S) ← (S) − 1
Execute JSR
M(S) ← (PCL)
M(S) ← (PCH)
(S) ← (S) − 1
M(S) ← (PCL)
------------
Push return address
on stack
(S) ← (S) − 1
(S) ← (S) − 1
M(S) ← (PS)
(S) ← (S) − 1
Push contents of processor
status register on stack
Interrupt Service
Routine
I Flag is set from “0” to “1”
Fetch the jump vector
Subroutine
.....
Execute RTI
Execute RTS
(S) ← (S) + 1
(S) ← (S) + 1
(PS) ← M(S)
POP return address
from stack
(PCL) ← M(S)
POP contents of
processor status
register from stack
(S) ← (S) + 1
(S) ← (S) + 1
(PCL) ← M(S)
(PCH) ← M(S)
(S) ← (S) + 1
POP return
address
from stack
(PCH) ← M(S)
Note1: Condition for acceptance of an interrupt request here → Interrupt disable flag is “0” and
Interrupt enable bit corresponding to each interrupt source is “1”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 7
Push and pop instructions of accumulator or processor status register
Push instruction to stack
PHA
PHP
Accumulator
Processor status register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 13 of 134
Pop instruction from stack
PLA
PLP
38D5 Group
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
• Bit 1: Zero flag (Z)
The Z flag is set to “1” if the result of an immediate arithmetic
operation or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal arithmetic.
Table 8
• Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. When the BRK instruction
is generated, the B flag is set to “1” automatically. When the
other interrupts are generated, the B flag is set to “0”, and the
processor status register is pushed onto the stack.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
• Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to -128.
When the BIT instruction is executed, bit 6 of the memory
location operated on by the BIT instruction is stored in the
overflow flag.
• Bit 7: Negative flag (N)
The N flag is set to “1” if the result of an arithmetic operation
or data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the BIT
instruction is stored in the negative flag.
Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Rev.3.04 May 20, 2008
REJ03B0158-0304
Z flag
−
−
Page 14 of 134
I flag
SEI
CLI
D flag
SED
CLD
B flag
−
−
T flag
SET
CLT
V flag
−
CLV
N flag
−
−
38D5 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
This register is allocated at address 003B16.
After the system is released from reset, the mode depends on the
OSCSEL pin state in the QzROM version.
When the OSCSEL pin state is GND level, only the on-chip
oscillator starts oscillation. The XIN -X OUT oscillation stops
oscillating, and XCIN and XCOUT pins function as I/O ports. The
operating mode is the on-chip oscillator mode.
When the OSCSEL pin state is Vcc level, the X IN -X OUT
oscillation divided by 8 starts oscillation. The on-chip oscillator
stops oscillating, and the XCIN and XCOUT pins function as I/O
ports. The operating mode is the frequency/8 mode.
In the flash memory version, only the on-chip oscillator starts
oscillating. The XIN-XOUT oscillation stops oscillating, and the
XCIN and XCOUT pins function as I/O ports. The operating mode
is the on-chip oscillator mode.
When the main clock or sub-clock is used, after the XIN-XOUT
oscillation and the XCIN-XCOUT oscillation are enabled, wait in
the on-chip oscillator mode etc. until the oscillation stabilizes,
and then switch the operation mode.
When the main clock is not used (XIN-XOUT oscillation and an
external clock input are not used), connect the XIN pin to VCC
through a resistor and leave XOUT open.
[CPU Mode Register 2 (CPUM2)] 001116
The CPU mode register 2 contains the control bits for the on-chip
oscillator.
The CPU mode register 2 is allocated at address 001116.
CPU mode register 2
CPUM2
CM8 (address 001116, QzROM version, OSCSEL=L, initial value: 0016)
(
QzROM version, OSCSEL=H, initial value: 0116)
(
Flash memory version,
initial value: 0016)
b7
b0
On-chip oscillator stop bit (1)
0 : Oscillating
1 : Stopped
Not used (do not write “1”)
Not used (returns “0” when read)
Not used (do not write “1”)
CPU mode register
CPUM
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 (address 003B16, QzROM version, OSCSEL=L, initial value: E016)
(
QzROM version, OSCSEL=H, initial value: 4016)
(
Flash memory version,
initial value: E016)
b7
b0
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Internal system clock selection bit
0 : Main clock selected
(includes OCO, XIN)
1 : XCIN–XCOUT selected
Port Xc switch bit (2)
0 : I/O port function (Oscillation stop)
1 : XCIN–XCOUT oscillating function
XIN–XOUT oscillation stop bit (3)
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(Valid only when CM3=0)(4)
b7 b6
0
0
1
1
0 : f(XIN)/2 (frequency/2 mode)
1 : f(XIN)/8 (frequency/8 mode)
0 : f(XIN)/4 (frequency/4 mode)
1 : On-chip oscillator
Notes 1: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2 (bit
5 of watchdog timer control register (address 002916)), the on-chip oscillator does not stop
even when the on-chip oscillator stop bit is set to “1”.
Also, when the low-speed mode is set, the on-chip oscillator stops regardless of the value of
this bit in the QzROM version. The on-chip oscillator does not stop in the flash memory
version, so set this bit to “1” to stop the oscillation.
In on-chip oscillator mode, even if this bit is set to “1”, the on-chip oscillator does not stop in
the flash memory version, but stops in the QzROM version.
2: In low-speed mode, the XCIN-XCOUT oscillation stops if the port XC switch bit is set to “0”.
3: In XIN mode, the XIN-XOUT oscillation does not stop even if the XIN-XOUT oscillation stop bit is
set to “1”.
4: 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
Fig. 8 Structure of CPU mode register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 15 of 134
38D5 Group
<QzROM version>
Reset
OSCSEL ?
H
L
Wait by operation until establishment
Start with an on-chip oscillator.
Initial value of CPUM is E016.
Initial value of CPUM2 is 0016.
As for the details of condition for
transition among each mode,
refer to the state transition of system clock.
After releasing reset
N
Low-speed/XIN mode ?
After releasing reset
The CPU starts its operation
in the built-in XIN mode.
Initial value of CPUM is 4016.
Initial value of CPUM2 is 0116.
Y
Oscillator starts oscillation.
Do not change bit 3, bit 6 and bit 7 of CPUM until
oscillation stabilizes.
Start the oscillation
(bits 4 and 5 of CPUM)
Wait by on-chip oscillator operation until
establishment of oscillator clock
System can operate in on-chip oscillator mode until
oscillation stabilize.
Select internal system clock
(bit 3 of CPUM or bit 7, 6 = “01”)
Select internal system clock.
Do not change bit 3, bit 6 and bit 7 of CPUM at the
same time.
Switch the main clock division ratio
selection bit (bit 7, 6 = “00” or “10”)
Select main clock division ratio.
Switch to frequency/2 or frequency/4 mode here,
if necessary.
Main routine
<Flash memory version>
Reset
Start with an on-chip oscillator.
Initial value of CPUM is E016.
Initial value of CPUM2 is 0016.
As for the details of condition for
transition among each mode,
refer to the state transition of system clock.
After releasing reset
N
Low-speed/XIN mode ?
Y
Oscillator starts oscillation.
Do not change bit 3, bit 6 and bit 7 of CPUM until
oscillation stabilizes.
Start the oscillation
(bits 4 and 5 of CPUM)
Wait by on-chip oscillator operation until
establishment of oscillator clock
System can operate in on-chip oscillator mode until
oscillation stabilize.
Select internal system clock
(bit 3 of CPUM or bit 7, 6 = “01”)
Select internal system clock.
Do not change bit 3, bit 6 and bit 7 of CPUM at the
same time.
Switch the main clock division ratio
selection bit (bit 7, 6 = “00” or “10”)
Select main clock division ratio.
Switch to frequency/2 or 4 mode here, if necessary.
Main routine
Fig. 9 Switch procedure of CPU mode register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 16 of 134
38D5 Group
MEMORY
• Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
• RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
• ROM
In the QzROM version, the first 128 Kbytes and the last 2 bytes
are reserved for device testing and the rest is the user area. Also,
1 byte of address FFDB16 is reserved.
In the flash memory version, programming and erase operations
can be performed to reserved ROM areas.
• Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
• Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
• Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
• ROM Code Protect Address in QzROM Version (Address
FFDB16)
Address FFDB16 as reserved ROM area in the QzROM version
is ROM code protect address. “0016” or “FE16” is written into
this address when selecting the protect bit write by using a serial
programmer and selecting protect enabled for writing shipment
by Renesas Technology Corp. When “0016” or “FE16” is set to
the ROM code protect address, the protect function is enabled, so
that reading or writing from/to the corresponding area is disabled
by a serial programmer.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
The protect can be performed, dividing twice. The protect area 1
is from the beginning address of ROM to address “EFFF16”.
As for the QzROM product shipped after writing, “0016” (protect
enabled to all area), “FE16” (protect enabled to the protect area 1)
or “FF16” (protect disabled) is written into the ROM code protect
address when Renesas Technology Corp. performs writing. The
writing of “0016”, “FE16” or “FF16 ” can be selected as ROM
option setup (“MASK option” written in the mask file converter)
when ordering.
For the ROM code protect in the flash memory version, refer to
the “FLASH MEMORY MODE”.
<Notes>
• After a reset, the contents of RAM are undefined. Make sure to
set the initial value before use.
• When Renesas ships QzROM write products, we write ROM
option data* specified by the mask file converter MM to the
ROM code protect address. Therefore, set FF16 to the ROM
code protect address in ROM data regardless of the presence
or absence of a protect. When data other than FF16 is set, we
may ask that the ROM data be submitted again.
* ROM option data: mask option noted in MM
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 17 of 134
38D5 Group
000016
SFR area
004016
Zero page
010016
(2)
RAM area
RAM size
(bytes)
192
256
384
512
640
768
896
1024
1536
2048
Address
XXXX16
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
RAM
XXXX16
Reserved area
084016
086316
0FE016
0FEF16
0FF016
LCD display RAM area
Not used
SFR area (1)
SFR area
100016
ROM area
ROM size
(bytes)
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
Address
YYYY16
Address
ZZZZ16
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
Reserved ROM area
(128 bytes)
Protect area 1
ZZZZ16
EFFF16
(2)
ROM
FF0016
FFD416
Reserved ROM area(1)
FFDB16
Reserved ROM area
(ID code)
(ROM code protect)
FFDC16
FFFE16
FFFF16
Special page
Interrupt vector area
Reserved ROM area
Note 1: This area is available in the flash memory version only.
2: ROM correction vectors are assigned. As for the details, refer to the “ROM CORRECTION FUNCTION”.
3: In the flash memory version, programming and erase operations can be performed to reserved ROM areas.
Note that their areas are different from those in the QzROM version.
Fig. 10 Memory map diagram
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 18 of 134
38D5 Group
000016
Port P0 (P0)
002016
Timer 1 (T1)
000116
Port P0 direction register (P0D)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
000316
Port P1 direction register (P1D)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
PWM01 register (PWM01)
000516
Port P2 direction register (P2D)
002516
Timer 12 mode register (T12M)
000616
Port P3 (P3)
002616
Timer 34 mode register (T34M)
000716
Port P3 direction register (P3D)
002716
Timer 1234 mode register (T1234M)
000816
Port P4 (P4)
002816
Timer 1234 frequency division selection register (PRE1234)
000916
Port P4 direction register (P4D)
002916
Watchdog timer control register (WDTCON)
000A16
Port P5 (P5)
002A16 Timer X (low-order) (TXL)
002B16 Timer X (high-order) (TXH)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
000F16
Port P7 direction register (P7D)
002C16 Timer X (extension) (TXEX)
002D16 Timer X mode register (TXM)
002E16 Timer X control register 1 (TXCON1)
002F16 Timer X control register 2 (TXCON2)
003016
Compare register 1 (low-order) (COMP1L)
001116
CPU mode register 2 (CPUM2)
003116
Compare register 1 (high-order) (COMP1H)
001216
RRF register (RRFR)
003216
Compare register 2 (low-order) (COMP2L)
001316
LCD mode register1 (LM1)
003316
Compare register 2 (high-order) (COMP2H)
001416
LCD mode register2 (LM2)
003416
Compare register 3 (low-order) (COMP3L)
001516
AD control register (ADCON)
003516
Compare register 3 (high-order) (COMP3H)
001616
AD conversion register (low-order) (ADL)
003616
Timer Y (low-order) (TYL)
001716
AD conversion register (high-order) (ADH)
003716
Timer Y (high-order) (TYH)
001816
Transmit/receive buffer register 1 (TB1/RB1)
003816
Timer Y mode register (TYM)
001916
Serial I/O1 status register (SIO1STS)
003916
Timer Y control register (TYCON)
001016
001A16 Serial I/O1 control register (SIO1CON)
001B16 UART control register (UARTCON)
003A16 Interrupt edge selection register (INTEDGE)
001C16 Baud rate generator (BRG)
003C16 Interrupt request register 1 (IREQ1)
001D16 Serial I/O2 control register (SIO2CON)
003D16 Interrupt request register 2 (IREQ2)
001E16 Reserved (1)
003E16 Interrupt control register 1 (ICON1)
001F16
Serial I/O2 register (SIO2)
003F16 Interrupt control register 2 (ICON2)
0FE016
Flash memory control register 0 (FMCR0)
0FF016 PULL register 1 (PULL1)
0FE116
Flash memory control register 1 (FMCR1)
0FF116 PULL register 2 (PULL2)
0FE216
Flash memory control register 2 (FMCR2)
0FF216 PULL register 3 (PULL3)
0FE316
Reserved (1)
0FF316 Clock output control register (CKOUT)
0FE416
Reserved
(1)
0FF416 Segment output disable register 0 (SEG0)
0FE516
Reserved (1)
0FF516 Segment output disable register 1 (SEG1)
0FE616
Reserved (1)
0FF616 Segment output disable register 2 (SEG2)
0FE716
Reserved (1)
0FF716 Key input control register (KIC)
0FE816
Reserved (1)
0FF816 ROM correction address 1 high-order register (RCA1H)
0FE916
Reserved (1)
0FF916 ROM correction address 1 low-order register (RCA1L)
0FEA16
Reserved (1)
0FFA16 ROM correction address 2 high-order register (RCA2H)
0FEB16
Reserved (1)
0FFB16 ROM correction address 2 low-order register (RCA2L)
003B16 CPU mode register (CPUM)
0FEC16 Reserved (1)
0FED16 Reserved (1)
0FFC16 ROM correction enable register (RCR)
0FEE16
Reserved (1)
0FFE16 Reserved (1)
0FEF16
Reserved (1)
0FFF16 Reserved (1)
0FFD16 Reserved (1)
Note 1: The blanks are reserved. Do not write data to these areas.
2: No memory access is allowed to the blank areas within the SFRs.
3: Addresses 0FE016 to 0FEF16 are available in the flash memory version only.
Fig. 11 Memory map of special function register (SFR)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 19 of 134
38D5 Group
I/O PORTS
• Direction Registers (Ports P0-P6, P72-P74)
The I/O ports P0-P6, P7 2-P74 have direction registers which
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input port or output port.
When “0” is written to the bit of the direction register, the
corresponding pin becomes an input pin. As for ports P0−P3,
when “1” is written to the bit of the direction register and the
segment output disable register, the corresponding pin becomes
an output pin. As for ports P4−P6, P72-P74 when “1” is written to
the bit of the direction register, the corresponding pin becomes
an output pin.
If data is read from a pin set to output, the value of the port latch
is read, not the value of the pin itself. However, when peripheral
output (RTP 1 , RTP 0 , T XOUT1 , T XOUT2 , T 4OUT, T 3OUT and
T2OUT/CKOUT) is selected, the output value is read. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
• Ports P70, P71
These are input ports which are shared with the voltage
multiplier. When these are read out at using the voltage
multiplier, the contents are “1”.
• Pull-up Control
Each individual bit of ports P0−P3 can be pulled up with a
program by setting direction registers and segment output disable
registers 0 to 2 (addresses 0FF416 to 0FF616).
The pin is pulled up by setting “0” to the direction register and
“1” to the segment output disable register.
By setting the PULL registers (addresses 0FF016 to OFF216),
ports P4−P7 can control pull-up with a program.
However, the contents of PULL register do not affect ports
programmed as the output ports.
b7
Direction
register
“0”
b7
b0
b7
b0
Input port
No pull-up
“1”
0 : No pull-up
1 : Pull-up
PULL register 3
(PULL3 : address 0FF216))
P40-P43 pull-up
0 : No pull-up
P44-P47 pull-up
1 : Pull-up
P72-P74 pull-up
Not used (do not write “1”)
Not used (return “0” when read)
b7
b0
Segment output disable register 0
(SEG0 : address 0FF416)
P00 pull-up
P01 pull-up
P02 pull-up
P03 pull-up
P04 pull-up
P05 pull-up
P06 pull-up
P07 pull-up
b0
0 : No pull-up
1 : Pull-up
Segment output disable register 1
(SEG1 : address 0FF516)
P20 pull-up
P21 pull-up
P22 pull-up
P23 pull-up
“1”
P24 pull-up
P25 pull-up
P26 pull-up
P27 pull-up
Input port
Pull-up
b7
Segment
output
0 : No pull-up
1 : Pull-up
PULL register 2
(PULL2 : address 0FF116))
P60 pull-up
P61 pull-up
P62 pull-up
P63 pull-up
P64 pull-up
P65 pull-up
P66 pull-up
P67 pull-up
Initial state
“0”
PULL register 1
(PULL1 : address 0FF0 16)
P50 pull-up
P51 pull-up
P52 pull-up
P53 pull-up
P54 pull-up
P55 pull-up
P56 pull-up
P57 pull-up
b7
Segment output
disable register
b0
Port output
Fig. 12 Structure of ports P0 to P3
b0
0 : No pull-up
1 : Pull-up
Segment output disable register 2
(SEG2 : address 0FF616)
P10-P13 pull-up
P14-P17 pull-up
0 : No pull-up
P30-P33 pull-up
1 : Pull-up
P34-P37 pull-up
Not used (do not write “1”)
Note1: The PULL register and segment output disable register affect only ports
programmed as the input ports.
Fig. 13 Structure of PULL register and segment output
disable register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 20 of 134
38D5 Group
Table 9
List of I/O port function
Pin
Name
P00/SEG8−
P07/SEG15
Port P0
P10/SEG16−
P17/SEG23
P20/SEG0/(KW4)−
P23/SEG3/(KW7)
Input/Output
I/O format
Non-port function
Related SFRs
Ref.
No.
Input/Output, CMOS compatible input level LCD segment output
individual bits CMOS 3-state output
Segment output disable register 0
(1)
Port P1
Input/Output, CMOS compatible input level
individual bits CMOS 3-state output
Segment output disable register 2
Port P2
Input/Output, CMOS compatible input level
individual bits CMOS 3-state output
Key input
(key-on
wakeup)
interrupt
input
P24/SEG4−
P27/SEG7
Segment output disable register 1
Key input control register
(2)
Segment output disable register 1
(1)
P30/SEG24−
P37/SEG31
Port P3
Input/Output, CMOS compatible input level
individual bits CMOS 3-state output
Segment output disable register 2
P40/RXD
P41/TXD
P42/SCLK1,
Port P4
Input/Output, CMOS compatible input level Serial I/O1 function I/O
individual bits CMOS 3-state output
PULL register 3
(3)
Serial I/O1 control register
(4)
P43/SRDY1
P44/SIN2/(KW0)
P45/SOUT2/(KW1)
P46/SCLK2/(KW2)
P47/SRDY2/(KW3)
P50/AN0/RTP0
P51/AN1/RTP1
Serial I/O2
function I/O
Port P5
Input/Output, CMOS compatible input level A/D
individual bits CMOS 3-state output
conversion
input
Key input
(key-on
wakeup)
interrupt
input
(5)
UART control register
(6)
PULL register 3
(7)
Serial I/O2 control register
(8)
Serial I/O2 register
(9)
Key input control register
(10)
PULL register 1
Real time
port function AD control register
Timer Y mode register
output
P52/AN2−
P56/AN6
PULL register 1
AD control register
P57/AN7/ADKEY0
P60/XCIN
P61/XCOUT
Serial I/O1 status register
Input/Output, CMOS compatible input level Sub-clock
individual bits CMOS 3-state output
oscillation circuit
(12)
(13)
ADKEY
input
Port P6
(11)
PULL register 2
CPU mode register
(14)
(15)
P62/INT00/(LED0)
External interrupt input
PULL register 2
Interrupt edge selection register
(16)
P63/TXOUT2/(LED1)
Timer X output 2
PULL register 2
Timer X mode register
Timer X control registers 1,2
(18)
P64/INT2/(LED2)
External interrupt input
PULL register 2
Interrupt edge selection
register
(17)
P65/TXOUT1/(LED3)
Timer X output 1
PULL register 2
Timer X mode register
Timer X control register 1
(18)
P66/INT10/CNTR0/
(LED4)
Timer X function input
External interrupt input
PULL register 2
Interrupt edge selection register
Timer X mode register
Timer X control registers 1,2
(19)
P67/CNTR1/(LED5)
Timer Y function input
PULL register 2
Timer Y mode register
(17)
Input,
CMOS compatible input level External interrupt input
individual bits
LCD voltage multiplier
input
Interrupt edge selection register
LCD mode registers 1,2
(20)
Input/Output CMOS compatible input level Timer 2
individual bits CMOS 3-state output
output
clock
output
(21)
Timer 3
output
Timer 4
output
PWM
output
PULL register 3
Timer 1234 mode register
Timer 1234 frequency division
register
Clock output control register
LCD mode register 1,2
(22)
P70/C1/INT01
P71/C2/INT11
Port P7
P72/T2OUT/
CKOUT
P73/PWM0/T3OUT
P74/PWM1/T4OUT
COM0 −COM3
Common Output
LCD common output
COM4/SEG35−
COM7/SEG32
Common
/Segment
LCD common/Segment
output
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 21 of 134
LCD common output
LCD
Segment
output
(23)
38D5 Group
(1) Ports P0, P1, P24-P27, P3
(2) Ports P20-P23
VL3/VL2
VL3/VL2
Segment data
Segment data
VL1/VSS
Segment output disable bit
VL1/VSS
Segment output disable bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Key-on wakeup
interrupt input
Key input control
(4) Port P41
(3) Port P40
Pull-up control
Pull-up control
Serial I/O enable bit
Receive enable bit
P41/TxD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Serial I/O input
Port latch
Serial I/O output
(5) Port P42
(6) Port P43
Serial I/O1 synchronous clock
selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Pull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Serial I/O1 ready output
Serial I/O1 clock output
Serial I/O1 clock input
Fig. 14 Port block diagram (1)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 22 of 134
Pull-up control
38D5 Group
(7) Port P44
(8) Port P45
P45/SOUT2 P-channel output disable bit
Serial I/O2 transmit end signal
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
Pull-up control
Direction
register
Data bus
Pull-up control
Direction
register
Data bus
Port latch
Port latch
Serial I/O2 input
Serial I/O2 input
Key input control
Key-on wakeup interrupt input
(9) Port P46
Key input control
Key-on wakeup interrupt input
(10) Port P47
Pull-up control
Pull-up control
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
SRDY2 output selection bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Serial I/O2 clock output
Port latch
Serial I/O2 ready output
Serial I/O2 input
Key input control
Key-on wakeup interrupt input
(11) Ports P50, P51
(12) Ports P52-P56
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Key input control
Key-on wakeup interrupt input
Port latch
Data bus
Port latch
Real time port control bit
Data for real time port
ADKEY enable bit
Analog input pin selection bit
A/D conversion input
Fig. 15 Port block diagram (2)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 23 of 134
ADKEY enable bit
Analog input pin selection bit
A/D conversion input
38D5 Group
(13) Port P57
(14) Port P60
Pull-up control
Pull-up control
Port Xc switch bit
Port Xc switch bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
ADKEY selection bit
Sub-clock oscillation circuit input
ADKEY enable bit
Analog input pin selection bit
A/D conversion input
(15) Port P61
(16) Port P62
Pull-up control
Pull-up control
Port Xc switch bit
Port Xc switch bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Sub-clock oscillation circuit
Port P60
INT0 interrupt input
INT0 input port switch bit
Xc oscillation enable
(17) Ports P64, P67
(18) Ports P63, P65
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
CNTR1 interrupt input
INT2 interrupt input
Fig. 16 Port block diagram (3)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 24 of 134
Port latch
Pulse output mode
Timer X output 1
Timer X output 2
38D5 Group
(20) Ports P70, P71
(19) Port P66
Pull-up control
C1,C2
Direction
register
Voltage multiplier
control bit
Data bus
Data bus
Port latch
INT0 interrupt
INT1 interrupt
INT0 input port switch bit
INT1 input port switch bit
CNTR0 interrupt input
INT1 interrupt input
INT1 input port switch bit
(22) COM0 to COM3
(21) Ports P72, P73, P74
VL3
Pull-up control
Data bus
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
VL2
Direction
register
VL1
Port latch
VSS
Port/Timer output selected
Timer output/PWM output
Timer output/system clock φ output/XCIN output
(23) COM4/SEG35 to COM7/SEG32
VL3
VL2
VL1
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
VL2/VL3
VSS
Duty ratio selection bits
Segment data
VL1/VSS
Fig. 17 Port block diagram (4)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 25 of 134
38D5 Group
• Termination of unused pins
• Termination of common pins
I/O ports:
Select an input port or an output port and follow
each processing method.
In addition, it is recommended that related
registers be overwritten periodically to prevent
malfunctions, etc.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply
current may increase.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 26 of 134
Especially, when expecting low consumption
current (at STP or WIT instruction execution etc.),
pull-up or pull-down input ports to prevent
through current (built-in resistor can be used).
We recommend processing unused pins through a
resistor which can secure IOH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation
etc.
38D5 Group
Table 10 Termination of unused pins
Pin
P00/SEG8−P07/SEG15
Termination 1
Termination 2
Termination 3
When selecting SEG output, open.
−
P40/RXD
When selecting RxD function, perform
termination of input port.
−
P41/TXD
When selecting TxD function, perform
termination of output port.
−
P42/SCLK1
When selecting external clock input,
perform termination of input port.
P43/SRDY1
When selecting SRDY1 function, perform
termination of output port.
−
P44/SIN2/(KW0)
When selecting SIN2 function, perform
termination of input port.
−
P45/SOUT2/(KW1)
When selecting SOUT2 function, perform
termination of output port.
−
P46/SCLK2/(KW2)
When selecting external clock input,
perform termination of output port.
P47/SRDY2/(KW3)
When selecting SRDY2 function, perform
termination of output port.
−
P50/AN0/RTP0
P51/AN1/RTP1
When selecting AN function, these pins
can be opened. (A/D conversion result
cannot be guaranteed.)
When selecting RTP function,
perform termination of output port.
I/O port
P10/SEG16−P17/SEG23
P20/SEG0/(KW4)−
P27/SEG7
P30/SEG24−P37/SEG31
P52/AN2−P56/AN6
P57/AN7/ADKEY0
When selecting internal clock output,
perform termination of output port.
When selecting internal clock output,
perform termination of output port.
−
When selecting ADKEY function,
pull-up this pin through a resistor.
P60/XCIN
P61/XCOUT
Do not select XCIN−XCOUT oscillation
function by program.
−
P62/INT00/(LED0)
When selecting INT function,
perform termination of input port.
−
P63/TXOUT2/(LED1)
When selecting TXOUT function, perform
termination of output port.
−
P64/INT2/(LED2)
When selecting INT function,
perform termination of input port.
−
P65/TXOUT1/(LED3)
When selecting TXOUT function, perform
termination of output port.
−
P66/INT10/CNTR0/
(LED4)
When selecting CNTR input function or INT
function, perform termination of input port.
−
P67/CNTR1/(LED5)
When selecting CNTR input function,
perform termination of input port.
−
P70/C1/INT01
P71/C2/INT11
Disable the voltage multiplier, and When selecting INT function, disable the voltage
connect to VSS through a resistor. multiplier, and connect to VSS through a resistor.
−
P72/T2OUT/CKOUT
I/O port
When selecting T2OUT function or CKOUT
function, perform termination of output port.
−
When selecting PWM, T3OUT, or T4OUT
function, perform termination of output port.
−
VL3
Set the VL3 connect bit to “1” and
Set the VL3 connect bit to “0” and leave the
apply a Vcc level voltage to VL3 pin. VL3 pin open.
−
P73/PWM0/T3OUT
P74/PWM1/T4OUT
VL2
VL3 ≥ VL2 ≥ VL1
−
−
VL1
Connect to VSS
−
−
COM0−COM3
Open
−
−
COM4/SEG35−
COM7/SEG32
Open
−
−
VREF
Connect to VCC
−
−
XIN
When only on-chip oscillator is used,
connect to VCC through a resistor.
−
−
XOUT
When external clock is input or when
only on-chip oscillator is used, open.
−
−
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 27 of 134
38D5 Group
INTERRUPTS
The 38D5 Group interrupts are vector interrupts with a fixed
priority scheme, and generated by 16 sources among 17 sources:
6 external, 10 internal, and 1 software.
The interrupt sources, vector addresses(1), and interrupt priority
are shown in Table 11.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 18 shows an interrupt control diagram.
Table 11
An interrupt requests is accepted when all of the following
conditions are satisfied:
• Interrupt disable flag ................................ “0”
• Interrupt request bit .................................. “1”
• Interrupt enable bit ................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses(1)
High
Low
Interrupt Request
Generating Conditions
Remarks
Reset(2)
1
FFFD16
FFFC16
At reset
Non-maskable
INT0 (INT00 or
INT01)(3)
2
FFFB16
FFFA16
At detection of either rising or falling
edge of INT0 input
External interrupt (active edge selectable)
INT1 (INT10 or
INT11)(3)
3
FFF916
FFF816
At detection of either rising or falling
edge of INT1 input
External interrupt (active edge selectable)
INT2
4
FFF716
FFF616
At detection of either rising or falling
edge of INT2 input
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Key input
(key-on wakeup)
5
FFF516
FFF416
At falling of ports P20−P23, P44−P47
input logical level AND
Valid when Key input interrupt is
selected External interrupt (falling valid)
Timer X
6
FFF316
FFF216
At timer X underflow
Timer 1
7
FFF116
FFF016
At timer 1 underflow
Timer 2
8
FFEF16
FFEE16
At timer 2 underflow
Timer 3
9
FFED16
FFEC16
At timer 3 underflow
Timer 4
10
FFEB16
FFEA16
At timer 4 underflow
Serial I/O1 receive
11
FFE916
FFE816
At completion of serial I/O1 data receive Valid only when serial I/O1 is selected
Serial I/O1 transmit
12
FFE716
FFE616
At completion of serial I/O1 transmit
shift or transmit buffer is empty
Serial I/O2
13
FFE516
FFE416
At completion of serial I/O2 data
transmit/receive
CNTR0
14
FFE316
FFE216
At detection of either rising or falling
edge of CNTR0 input
Timer Y
15
FFE116
FFE016
At timer Y underflow
At detection of either rising or falling
edge of CNTR1 input
CNTR1
A/D conversion
16
FFDF16
FFDE16
At completion of A/D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Valid only when serial I/O1 is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Non-maskable software interrupt
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
3. INT0, and INT1 input pins are selected by the interrupt edge selection register (INTEDGE).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 28 of 134
38D5 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt
acceptance
Fig. 18 Interrupt control
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1” until the request
is accepted . Wh en the request is accepted, th is bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 29 of 134
• Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt edge selection register (003A16).
• Timer Y or CNTR1
• External Interrupt Pin Selection
For external interrupts INT0 and INT1, the INT0, INT1 input port
switch bit in the interrupt edge selection register (bits 4 and 5 of
address 003A16) can be used to select INT00 and INT01 pin input
or INT10 and INT11 pin input.
38D5 Group
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
Timer Y/CNTR1 interrupt switch bit
0 : Timer Y interrupt
1 : CNTR1 interrupt
INT0 input port switch bit
0 : input from Port P62 (INT00)
1 : input from Port P70 (INT01)
INT1 input port switch bit
0 : input from Port P66 (INT10)
1 : input from Port P71 (INT11)
Not used (do not write to “1”)
Not used (return “0” when read)
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16)
0 : Falling edge active
1 : Rising edge active
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 4 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive/transmit interrupt request bit
CNTR0 interrupt request bit
Timer Y interrupt request bit
CNTR1 interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Key input interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Key input interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Fig. 19 Structure of interrupt-related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 30 of 134
b0
Interrupt control register 2
(ICON2 : address 003F16)
Timer 4 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive/transmit interrupt enable bit
CNTR0 interrupt enable bit
Timer Y interrupt enable bit
CNTR1 interrupt enable bit
AD conversion interrupt enable bit
Not used (do not write to “1”)
0 : Interrupts disabled
1 : Interrupts enabled
38D5 Group
• Interrupt Request Generation, Acceptance, and
Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source
(external interrupt signal input, timer underflow, etc.) and
the corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance
conditions (interrupt request bit, interrupt enable bit, and
interrupt disable flag) and interrupt priority levels for
accepting interrupt requests. When two or more interrupt
requests are generated simultaneously, the highest priority
interrupt is accepted. The value of interrupt request bit for
an unaccepted interrupt remains the same and acceptance is
determined at the next interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 20 shows the time up to execution in the interrupt routine,
and Figure 21 shows the interrupt sequence.
Figure 22 shows the timing of interrupt request generation,
interrupt request bit, and interrupt request acceptance.
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
Stack push and
Vector fetch
Main routine
*
0 to 16 cycles
Interrupt handling
routine
7 cycles
7 to 23 cycles
* When executing DIV instruction
Fig. 20 Time up to execution in interrupt routine
Push onto stack
Vector fetch
Execute interrupt
routine
φ
SYNC
RD
• Interrupt Handling Execution
When interrupt handling is executed, the following operations
are performed automatically.
(1) Once the currently executing instruction is completed, an
interrupt request is accepted.
(2) The contents of the program counters and the processor
status register at this point are pushed onto the stack area in
order from 1 to 3.
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
(3) Concurrently with the push operation, the jump address of
the corresponding interrupt (the start address of the interrupt
processing routine) is transferred from the interrupt vector to
the program counter.
(4) The interrupt request bit for the corresponding interrupt is
set to “0”. Also, the interrupt disable flag is set to “1” and
multiple interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the
registers pushed onto the stack area are popped off in the
order from 3 to 1. Then, the routine that was before running
interrupt processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each
interrupt to execute the interrupt processing routine.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 31 of 134
WR
Address bus
Data bus
PC
Not used
S,SPS
S-1,SPS S-2,SPS
PCH
PCL
PS
BL
BH
AL
AL,AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS : “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Fig. 21 Interrupt sequence
38D5 Group
<Notes>
The interrupt request bit may be set to “1” in the following cases.
• When setting the external interrupt active edge
Related bits: INT0 interrupt edge selection bit
(bit 0 of interrupt edge selection register
(address 003A16))
INT1 interrupt edge selection bit
(bit 1 of interrupt edge selection register)
INT2 interrupt edge selection bit
(bit 2 of interrupt edge selection register)
CNTR0 activate edge switch bit
(bits 6 and 7 of timer X control register 1
(address 002E16))
CNTR1 activate edge switch bit
(bits 6 of timer Y mode register
(address 003816))
• When switching the interrupt sources of an interrupt vector
address where two or more interrupt sources are assigned
Related bit: Timer Y/CNTR1 interrupt switch bit
(bit 3 of interrupt edge selection register)
• When switching the INT pins
Related bits: INT0 input port switch bit
(bit 4 of interrupt edge selection register)
INT1 input port switch bit
(bit 5 of interrupt edge selection register)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Push onto stack
Vector fetch
Instruction cycle
Instruction cycle
Internal clock φ
SYNC
1
T1
2
IR1 T2
IR2 T3
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
Fig. 22 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 32 of 134
38D5 Group
• Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by detecting the falling
edge from any pin of ports P20−P23, P44−P47 that have been set
to input mode. In other words, it is generated when AND of input
level goes from “1” to “0”. An example of using a key input
interrupt is shown in Figure 23, where an interrupt request is
generated by pressing one of the keys consisted as an active-low
key matrix which inputs to ports P44−P47.
Port PXx
“L” level output
Port P2 direction
register bit 3 = “1”
Key input control
register bit 7 = “1”
Port P23
latch
Segment output
disable register 1
Bit 3 = “1”
∗
∗∗
Key input interrupt request
P23 output
Segment output
disable register 1
Bit 2 = “1”
∗
∗∗
Port P22 direction
register bit 2 = “1”
Key input control
register bit 6 = “1”
Port P22
latch
P22 output
Port P2 direction
register bit 1 = “1”
Key input control
register bit 5 = “1”
Port P21
latch
Segment output
disable register 1
Bit 1 = “1”
∗
∗∗
Port P2
Input reading circuit
P21 output
Segment output
disable register 1
Bit 0 = “1”
∗
∗∗
Port P2 direction
register bit 0 = “1”
Key input control
register bit 4 = “1”
Port P20
latch
P20 output
∗
P47 input
∗
Port P4 direction
register bit 7 = “0”
Key input control
register bit 3 = “1”
Port P47
∗∗
latch
Port P4 direction
register bit 6 = “0”
Key input control
register bit 2 = “1”
Port P46
∗∗
latch
P46 input
Port P4 direction
register bit 5 = “0”
∗
∗∗
Port P45
latch
Key input control
register bit 1 = “1”
Port P4
Input reading circuit
P45 input
Port P4 direction
register bit 4 = “0”
∗
∗∗
Port P44
latch
Key input control
register bit 0 = “1”
P44 input
PULL register 3
Bit 1 = “1”
∗ P-channel transistor for pull-up
∗∗ CMOS output buffer
Fig. 23 Connection example when using key input interrupt
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 33 of 134
38D5 Group
A key input interrupt is controlled by the key input control
register and port direction registers. When the key input interrupt
is enabled, set “1” to the key input control register. A key input
of any pin of ports P20−P23, P44−P47 that have been set to input
mode is accepted.
b7
b0
Key input control register
(KIC : address 0FF716)
P44 key input control bit
P45 key input control bit
P46 key input control bit
P47 key input control bit
P20 key input control bit
P21 key input control bit
P22 key input control bit
P23 key input control bit
0 : Key input interrupt disabled
1 : Key input interrupt enabled
Fig. 24 Structure of key input control register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 34 of 134
38D5 Group
TIMERS
8-Bit Timer
The 38D5 Group has four built-in 8-bit timers: Timer 1, Timer 2,
Timer 3, and Timer 4.
Timer 1
Timer 2
Timer 3
Timer 4
(1)
φ SOURCE
Frequency divider
8
Each timer has the 8-bit timer latch. All timers are downcounters.
When the timer reaches “0016”, the contents of the timer latch is
reloaded into the timer with the next count pulse. In this mode,
the interrupt request bit corresponding to that timer is set to “1”.
The count can be stopped by setting the stop bit of each timer to
“1”.
Frequency division
selection bits
(2 bits for each Timer)
Data bus
Clock for Timer 4
Clock for Timer 3
Clock for Timer 2
Clock for Timer 1
XCIN
Timer 1 count
source selection
“00”
bits
“01”
Clock for
Timer 1
The following values can be selected
the clock for Timer;
1/1, 1/2, 1/16, 1/256
Timer 1 latch (8)
Timer 1 (8)
“10”
Timer Y
output
Timer 1 interrupt request
Timer 1 count stop bit
P72 clock output control bit
“10”
XCIN
System
clock φ
P72 direction
register
Timer 2 latch (8)
“01”
Clock for
Timer 2
“01”
P72/T2OUT/CKOUT
Timer 2 count
source selection
bits
“00”
Timer 2 (8)
“10”
Timer 2 output selection bit
Timer 2 write control bit
Timer 2 interrupt request
Timer 2 count stop bit
“00”
S
“0”
Q T 1/2
“1”
Q
T2OUT output
edge switch bit
P72
latch
Timer 2 output selection bit
Timer 3 count source
selection bit
“1”
Clock for
Timer 3
Timer 3 operating
mode selection bit
P73/PWM0/
T3OUT
Timer 3 latch (8)
Timer 3 (8)
Timer 3 write control bit
Timer 3 interrupt request
Timer 3 count stop bit
“0”
10 bit
PWM0
circuit
“1”
Timer 3 output selection bit
PWM01 register (2)
“0”
“0”
S
Q
P73 direction
P73
T
“1”
register
latch
Q
1/2
3OUT
output
T
Timer 3 output selection bit
edge switch bit
“01”
“10”
Clock for
Timer 4
Timer 4 operating
mode selection bit
P74/PWM1/
T4OUT
“1”
10 bit
PWM1
circuit
“00”
Timer 4 count source
selection bits
Timer 4 latch (8)
Timer 4 (8)
“11”
Timer 4 count stop bit
f(XIN)
Timer 4 output selection bit
PWM01 register (2)
“0”
“0”
S
Q
P74
P74 direction
T
“1”
latch
register
1/2
Q
T4OUT output
Timer 4 output selection bit
edge switch bit
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 25 Timer 1-4 block diagram
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 35 of 134
Timer 4 write control bit
Timer 4 interrupt request
38D5 Group
• Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider
for the count source. The count source of the frequency divider is
switched to XIN, XCIN, or the on-chip oscillator OCO divided by
4 in the on-chip oscillator mode by the CPU mode register. The
frequency divider is controlled by each timer division ratio
selection bit. The division ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4. Switch the
frequency division or count source* while the timer count is
stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
• Timer 1, Timer 2
The count source for timer 1 and timer 2 can be set using the
timer 12 mode register. X CIN may be selected as the count
source. If XCIN is selected, count operation is possible regardless
of whether or not the XIN input oscillator or the on-chip oscillator
is operating. In addition, the timer 12 mode register can be used
to output from the P72/T2OUT pin a signal to invert the polarity
every time timer 2 underflows.
At reset, all bits of the timer 12 mode register are set to “0”, timer
1 is set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time
at return.
• Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by
setting the timer 34 mode register. Also, by the timer 34 mode
register, each time timer 3 or timer 4 underflows, the signal of
which polarity is inverted can be output from P73/T3OUT pin or
P74/T4OUT pin.
• Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit
accuracy can be output from the P73/PWM0 pin and P74/PWM1
pin by setting the timer 34 mode register and PWM01 register
(refer to Figure 26).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address
002216) or the timer 4 (address 002316). The “ts” is one period of
timer 3 or timer 4 count source. “H” width of the short interval is
obtained by n × ts.
However, in the long interval, “H” width of output pulse is
extended for ts which is set by the PWM01 register (address
002416).
<Notes on Timer 1 to Timer 4>
(1) Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
• When PWM output is suspended after starting PWM output,
depending on the level of the output pulse at that time to
resume an output, the delay of the one section of the short
interval may be needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 × ts
• In the PWM mode, the follows are performed every cycle of
the long interval (4 × 256 × ts).
• Generation of timer 3, timer 4 interrupt requests
• Update of timer 3, timer 4
(2) Write to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload
latch and the underflow timing are almost the same, the value is
set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the reload latch.
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
Long interval
4 × 256 × ts
Short interval
256 × ts
PWM01 register = “002”
PWM01 register = “012”
PWM01 register = “102”
PWM01 register = “112”
Short interval
256 × ts
Short interval
256 × ts
Short interval
256 × ts
n × ts
n × ts
n × ts
n × ts
(n+1) × ts
n × ts
n × ts
n × ts
(n+1) × ts
n × ts
(n+1) × ts
n × ts
(n+1) × ts
(n+1) × ts
(n+1) × ts
n × ts
Interrupt request
Interrupt request
n: Setting value of Timer 3 or Timer 4
ts: One period of Timer 3 count source or Timer 4 count source
PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)
Fig. 26 Waveform of PWM0 and PWM1
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 36 of 134
38D5 Group
b7
b7
b0
b0
Timer 12 mode register
(T12M: address 002516)
PWM01 register
(PWM01: address 002416)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
PWM0 set bits
b1b0
0
0
1
1
Timer 2 count stop bit
0 : Count operation
1 : Count stop
PWM1 set bits
Timer 1 count source selection bits
b3b2
b3b2
0
0
1
1
0 : No extended
1 : Extended once in four periods
0 : Extended twice in four periods
1 : Extended three times in four periods
0
0
1
1
0 : Frequency divider for Timer 1
1 : f(XCIN)
0 : Underflow of Timer Y
1 : Not available
0 : No extended
1 : Extended once in four periods
0 : Extended twice in four periods
1 : Extended three times in four periods
Not used (returns “0” when read)
Timer 2 count source selection bits
b5b4
0
0
1
1
0 : Underflow of Timer 1
1 : f(X CIN)
0 : Frequency divider for Timer 2
1 : Not available
Timer 2 output selection bit (P7 2)
0 : I/O port
1 : Timer 2 output
T2OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
b7
b7
b0
Timer 1 frequency division selection bits
b1b0
Timer 4 count stop bit
0 : Count operation
1 : Count stop
(1)
0 0 : 1/16 × φ SOURCE
0 1 : 1/1 × φ SOURCE
1 0 : 1/2 × φ SOURCE
1 1 : 1/256 × φ SOURCE
Timer 2 frequency division selection bits
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Underflow of Timer 2
b3b2
0
0
1
1
Timer 4 count source selection bits
b4b3
0 0 : Frequency divider for Timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : f(XIN)
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
0 : 1/16 × φ SOURCE
1 : 1/1 × φ SOURCE
0 : 1/2 × φ SOURCE
1 : 1/256 × φ SOURCE
Timer 3 frequency division selection bits
b5b4
0
0
1
1
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
0 : 1/16 × φSOURCE
1 : 1/1 × φ SOURCE
0 : 1/2 × φ SOURCE
1 : 1/256 × φ SOURCE
Timer 4 frequency division selection bits
b7b6
0
0
1
1
Not used (returns “0” when read)
b7
b0
Timer 1234 frequency division selection register
(PRE1234: address 002816)
Timer 34 mode register
(T34M: address 002616)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
0 : 1/16 × φ SOURCE
1 : 1/1 × φ SOURCE
0 : 1/2 × φ SOURCE
1 : 1/256 × φ SOURCE
b0
Timer 1234 mode register
(T1234M: address 002716)
T3OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
T4OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Timer 3 output selection bit (P7 3)
0 : I/O port
1 : Timer 3 output
Timer 4 output selection bit (P7 4)
0 : I/O port
1 : Timer 4 output
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns “0” when read)
Fig. 27 Structure of timer 1 to timer 4 related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 37 of 134
38D5 Group
16-bit Timer
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write
the low-order byte first. The 16-bit timer cannot perform the
correct operation when reading during the write operation, or
when writing during the read operation.
XIN
φSOURCE
(1)
2
Frequency divider
Timer X frequency
division selection bits
“0”
Timer X count source selection bit
XcIN
“1”
Timer 1 interrupt
“001” Timer X count
“010”
stop bit
“011”
“101”
Latch
“00”
Timer X (low-order) latch (8) Timer X (high-order) latch (8) Extend latch (2)
CNTR0
Timer X (low-order)(8)
Both edges
detection
“000”
“001”
“011”
“100”
“101”
Timer X operating
mode bits
Timer X write
control bit
“000”
D Q
Data for control of event counter window
“01”
Timer X (high-order)(8)
Extend counter (2)
CNTR0
interrupt request
Pulse width
measurement
mode
Timer X output Timer X operating
“010”
mode bits
control bit 1
Edge
selection
Timer X output
control bit 2
Edge
detection
Compare register 1 (low-order)(8) Compare register 1 (high-order)(8)
Compare register 2 (low-order)(8) Compare register 2 (high-order)(8)
Edge
selection
INT2
Compare register 3 (low-order)(8) Compare register 3 (high-order)(8)
R
Q
T
Q
Pulse output mode
“0”
P65/TXOUT1/(LED3)
S
Q
P65
direction
register
P65
latch
Timer X output 1
selection bit
“1”
T
Timer X output 1
Q
active edge switch
bit
IGBT output mode
PWM mode
“0”
R
Q
P63/TXOUT2/(LED1)
P63
direction
register
P63
latch
“1”
Timer X output 2
active edge
switch bit
Q
Timer X output 2
selection bit
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 28 Timer X block diagram
Rev.3.04 May 20, 2008
REJ03B0158-0304
Timer X interrupt
request
“100”
“10”
“11”
CNTR0 active
edge switch bits
INT10/INT11
INT0
interrupt request
16/f(XIN) “11”
Clock for Timer X
“0”
Data bus
External trigger delay time
selection bits
“00”
0 µs
Trigger for IGBT input control bit
4/f(XIN) “01”
“1”
Timer X operating
Delay
“010” mode bits
Delay
circuit 1/2
8/f(XIN) “10”
circuit
Noise filter
(4 times same
levels judgment)
Edge
selection
INT00/INT01
Noise filter sampling
Trigger for IGBT input control bit
clock selection bit
“1”
1/4 “1”
×2
Frequency
divider
1/2 “0”
“0”
Page 38 of 134
T
Equal
38D5 Group
• Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the
count source. The count source of the frequency divider is
switched to XIN, XCIN, or the on-chip oscillator OCO divided by
4 in the on-chip oscillator mode by the CPU mode register. The
division ratio of each timer can be controlled by each timer
division ratio selection bit. The division ratio can be selected
from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4.
Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
• Timer X
The count source for timer X can be set using the timer X mode
register. XCIN may be selected as the count source. If XCIN is
selected, count operation is possible regardless of whether or not
the XIN input oscillator or the on-chip oscillator is operating.
The timer X operates as down-count. When the timer contents
reach “000016”, an underflow occurs at the next count pulse and
the timer latch contents are reloaded. After that, the timer
continues countdown. When the timer underflows, the interrupt
request bit corresponding to the timer X is set to “1”.
Six operating modes can be selected for timer X by the timer X
mode register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode
register. In this mode, timer X operates as the 18-bit counter by
setting the timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer
underflows are output from the TXOUT1 pin. Except for that, this
mode operates just as in the timer mode.
When using this mode, set the port sharing the TXOUT1 pin to
output mode.
(3) IGBT Output Mode
After dummy output from the TXOUT1 pin, count starts with the
INT0 pin input as a trigger. In the case that the timer X output 1
active edge switch bit is “0”, when the trigger is detected or the
timer X underflows, “H” is output from the TXOUT1 pin. And
then, when the count value corresponds with the compare
register 1 value, the TXOUT1 output becomes “L”.
After noise is cleared by noise filters, judging continuous 4-time
same levels with sampling clocks to be signals, the INT0 signal
can use 4 types of delay time by a delay circuit.
When using this mode, set the port sharing the INT0 pin to input
mode and set the port sharing the pin used as TXOUT1 or TXOUT2
function to output mode.
When the timer X output control bit 1 or 2 of the timer X control
register is set to “1”, the timer X count stop bit is fixed to “1”
forcibly by the interrupt signal of INT1 or INT2. And then, the
TXOUT1 output and TXOUT2 output can be set to “L” forcibly at
the same time that the timer X stops counting.
Do not write “1” to the timer X register (extension) when using
the IGBT output mode.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 39 of 134
(4) PWM Mode
IGBT dummy output, an external trigger with the INT0 pin and
output control with pins INT1 and INT2 are not used. Except for
those, this mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set
value. In the case that the timer X output 1 active edge switch bit
is “0”, the “H” interval is specified by the compare register 1 set
value. In the case that the timer X output 2 active edge switch bit
is “0”, the “H” interval is specified by the compare registers 2
and 3 set values.
When using this mode, set the port sharing the pin used as
TXOUT1 or TXOUT2 function to output mode.
Do not write “1” to the timer X register (extension) when using
the PWM mode.
(5) Event Counter Mode
The timer counts signals input through the CNTR0 pin. In this
mode, timer X operates as the 18-bit counter by setting the timer
X register (extension). When using this mode, set the port
sharing the CNTR0 pin to input mode.
In this mode, the window control can be performed by the timer
1 underflow. When the bit 5 (data for control of event counter
window) of the timer X mode register is set to “1”, counting is
stopped at the next timer 1 underflow. When the bit is set to “0”,
counting is restarted at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider
for timer. In this mode, timer X operates as the 18-bit counter by
setting the timer X register (extension). When the bit 6 of the
CNTR 0 active edge switch bits is “0”, counting is executed
during the “H” interval of CNTR0 pin input. When the bit is “1”,
counting is executed during the “L” interval of CNTR0 pin input.
When using this mode, set the port sharing the CNTR0 pin to
input mode.
Also, set to enable (“0”) the data for control of event counter
window (bit 5 of timer X mode register (address 002D16)).
38D5 Group
ts
Timer X count source
Timer X PWM mode
IGBT output mode
External trigger (INT0 source)
is generated.
INT1 or INT2 source is generated.
Level is “H” only IGBT
output mode.
TXOUT1 output
(TXCON1 bit 5 = “0”)
m × ts
TXOUT2 output
(TXCON2 bit 1 = “0”)
Level is forcibly “L” only IGBT
output mode.
q × ts
p × ts
(n+1) × ts
n : Timer X setting value
m: Compare register 1 setting value
p : Compare register 2 setting value
q : Compare register 3 setting value
ts: One period of timer X count source
The following PWM waveform is output;
Duty of TXOUT1 output :{(n+1)-m}/(n+1),
Duty of TXOUT2 output :(p-q)/(n+1),
Period :(n+1) × ts
Fig. 29 Waveform of PWM/IGBT
<Notes on Timer X>
(1) Write Order to Timer X
• In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following
registers in the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after
reset is released, setting the timer X register (extension) is not
required. In this case, write the timer X register (low-order)
first and the timer X register (high-order). However, once
writing to the timer X register (extension) is executed, note that
the value is retained to the reload latch.
• Write to the timer X register by the 16-bit unit. Do not read the
timer X register while write operation is performed. If the
write operation is not completed, normal operation will not be
performed.
• In the IGBT output and PWM modes, do not write “1” to the
timer X register (extension). Also, when “1” is already written
to the timer X register, be sure to write “0” to the register
before using.
Write to the following registers in the order as shown below;
the compare registers 1, 2, 3 (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare
registers 1, 2, 3 (high- and low-order). However, write both the
compare registers 1, 2, 3 and the timer X register at the same
time.
For the compare registers, set a value less than the setting value
in the timer X register. Also, do not set “0016”.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 40 of 134
(2) Read Order to Timer X
• In all modes, read the following registers in the order as shown
below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required,
read the timer X register (high-order) first and the timer X
register (low-order).
Read order to the compare registers 1, 2, 3 is not specified.
• Read from the timer X register by the 16-bit unit. Do not write
to the timer X register while read operation is performed. If the
read operation is not completed, normal operation will not be
performed.
(3) Write to Timer X
• Which write control can be selected by the timer X write
control bit (b3) of the timer X mode register (address 2D16),
writing data to both the latch and the timer at the same time or
writing data only to the latch. When writing a value to the
timer X address to write to the latch only, the value is set into
the reload latch and the timer is updated at the next underflow.
After reset release, when writing a value to the timer X
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the highorder reload latch and the underflow timing are almost the
same, the value is set into the timer and the timer latch at the
same time. In this time, counting is stopped during writing to
the high-order reload latch.
• Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
38D5 Group
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to “1”
(write to the latch only) when setting the IGBT output and PWM
modes.
Output waveform simultaneously reflects the contents of both
registers at the next underflow after writing to the timer X
register (high-order).
(5) Output Control Function of Timer X
• When using the output control function (INT1 and INT2) in the
IGBT output mode, set the levels of INT1 and INT2 to “H” in
the falling edge active or to “L” in the rising edge active before
switching to the IGBT output mode.
(7) When Timer X Pulse Width Measurement Mode
Used
When timer X pulse width measurement mode is used, enable the
event counter wind control data (bit 5 of timer X mode register
(address 002D16)) by setting to “0”.
<Reason>
If the event counter window control data (bit 5 of timer X mode
r egister (add ress 002 D 1 6 )) is set to “1” (disabled) to
enable/disable the CNTR0 input, the input is not accepted after
the timer 1 underflow.
(6) Switch of CNTR0 Active Edge
• When the CNTR0 active edge switch bits are set, at the same
time, the interrupt active edge is also affected.
When the pulse width is measured, set the bit 7 of the CNTR0
active edge switch bits to “0”.
b7
b7
b0
Timer X mode register
(TXM: address 002D16)
Timer X operating mode bits
b2b1b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : IGBT output mode
0 1 1 : PWM mode
1 0 0 : Event counter mode
1 0 1 : Pulse width measurement mode
1 1 0 : Not available
1 1 1 : Not available
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bit
0 : Frequency divider output
1 : f(XCIN)
Data for control of event counter window
0 : Event count enabled
1 : Event count disabled
Timer X count stop bit
0 : Count operation
1 : Count stop
Timer X output 1 selection bit (P6 5)
0 : I/O port
1 : Timer X output 1
b7
b0
Timer X control register 2
(TXCON2: address 002F16)
Timer X output 2 control bit (P6 3)
0 : I/O port
1 : Timer X output 2
Timer X output 2 active edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer X dividing frequency selection bits
b3b2
0 0 : 1/16 × φ SOURCE
0 1 : 1/1 × φ SOURCE (1)
1 0 : 1/2 × φ SOURCE
1 1 : 1/256 × φ SOURCE
Trigger for IGBT input control bit
0 : Noise filter sampling clock × 1
External trigger delay time × 1
1 : Noise filter sampling clock × 2
External trigger delay time × 1/2
Not used (returns “0” when read)
Fig. 30 Structure of Timer X related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 41 of 134
b0
Timer X control register 1
(TXCON1: address 002E16)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
b2b1
0 0 : Not delayed
0 1 : (4/f(XIN)) µs
1 0 : (8/f(XIN)) µs
1 1 : (16/f(XIN)) µs
Timer X output control bit 1 (P6 6 or P71)
0 : Not used INT1 interrupt signal
1 : INT1 interrupt signal used
Timer X output control bit 2 (P6 4)
0 : Not used INT2 interrupt signal
1 : INT2 interrupt signal used
Timer X output 1 active edge switch bit
0 : Start at “L” output
1 : Start at “H” output
CNTR0 active edge switch bits
b7b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR 0 interrupt
Measure “H” pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR 0 interrupt
Measure “L” pulse width in pulse width measurement mode
1 0 : Count at both edges in event counter mode
1 1 : Both edges active for CNTR 0 interrupt
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
38D5 Group
Data bus
(1)
φSOURCE
2
Frequency divider
Timer Y operating mode bits
Timer Y dividing frequency selection bit
“00”, “01”, “10”
“0”
“1”
Rising edge detection
XcIN
Count source selection bit
Falling edge detection
CNTR1 active
edge switch bit
“0”
“11”
Period measurement
mode
Timer Y (low-order) latch (8) Timer Y (high-order) latch (8)
“00”, “01”, “11”
Timer Y (low-order)(8)
Timer Y (high-order)(8)
“10” Timer Y operating
mode bits
“1”
Real time port 2
control bit
“1”
RTP1 data for real
time port
Q D
P51/RTP1/AN1
Timer Y
interrupt request
Real time port 2 control bit
“0”
Timer Y mode register
write signal
Latch
“0”
“1”
P51 latch
Real time port 1
control bit “1”
RTP0 data for real
time port
Q D
P50/RTP0/AN0
P50 direction
register
CNTR1
interrupt request
Timer Y write control bit
Timer Y count
stop bit
CNTR1
P51 direction
register
Pulse width HL continuous
measurement mode
“0”
Real time port 1 control bit
“0”
Timer Y mode register
write signal
Latch
“1”
P50 latch
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 31 Block diagram of Timer Y
• Timer Y
Timer Y is a 16-bit timer. The timer Y count source can be
selected by setting the timer Y mode register. X CIN can be
selected as the count source. When XCIN is selected as the count
source, counting can be performed regardless of XIN oscillation
or on-chip oscillator oscillation.
Four operating modes can be selected for timer Y by the timer Y
mode register. Also, the real time port can be controlled.
(1) Timer Mode
The timer Y count source can be selected by setting the timer Y
mode register.
(2) Period Measurement Mode
The interrupt request is generated at rising or falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y
latch is reloaded in timer Y and timer Y continues counting.
Except for that, this mode operates just as in the timer mode.
The timer value just before the reloading at rising or falling of
CNTR1 pin input is retained until the timer Y is read once after
the reload.
The rising or falling timing of CNTR1 pin input is found by
CNTR1 interrupt. When using this mode, set the port sharing the
CNTR1 pin to input mode.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 42 of 134
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for that, this mode operates just as in the timer mode.
When using this mode, set the port sharing the CNTR1 pin to
input mode.
(4) Pulse Width HL Continuously Measurement Mode
The interrupt request is generated at both rising and falling edges
of CNTR1 pin input signal. Except for that, this mode operates
just as in the period measurement mode. When using this mode,
set the port sharing the CNTR1 pin to input mode.
(5) Real Time Port Control
When the real time port function is valid, data for the real time
port is output from ports P5 0 and P5 1 each time the timer Y
underflows.(However, if the real time port control bit is changed
from “0” to “1” after the data for real time port is set, data is
output independent of the timer Y operation.) When the data for
the real time port is changed while the real time port function is
valid, the changed data is output at the next underflow of timer
Y. Before using this function, set the P50 and P51 port direction
registers to output.
38D5 Group
<Notes on Timer Y>
• CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously
measurement mode, CNTR1 interrupt request is generated at
both rising and falling edges of CNTR 1 pin input signal
regardless of the setting of CNTR1 active edge switch bit.
• Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-chip
oscillator mode, XIN mode, or low-speed mode). Be careful
when changing settings in the CPU mode register.
• Timer Y Read/Write Control
• When reading from/writing to timer Y, read from/write to both
the high-order and low-order bytes of timer Y. When the value
is read, read the high-order bytes first and the low-order bytes
next. When the value is written, write the low-order bytes first
and the high-order bytes next.
Write to or read from the timer Y register by the 16-bit unit. If
reading from the timer Y register during write operation or
writing to it during read operation is performed, normal
operation will not be performed.
• Which write control can be selected by the timer Y write
control bit (b0) of the timer Y control register (address
0039 16), writing data to both the latch and the timer at the
same time or writing data only to the latch. When writing a
value to the timer Y address to write to the latch only, the
value is set into the reload latch and the timer is updated at the
next underflow. After reset release, when writing a value to the
timer Y address, the value is set into the timer and the timer
latch at the same time, because they are set to write at the same
time.
When writing to the latch only, if the write timing to the highorder reload latch and the underflow timing are almost the
same, the value is set into the timer and the timer latch at the
same time. In this time, counting is stopped during writing to
the high-order reload latch.
b7
b7
b0
Timer Y mode register
(TYM: address 003816)
Real time port 1 control bit (P5 0)
0 : Real time port function invalid
1 : Real time port function valid
Real time port 2 control bit (P5 1)
0 : Real time port function invalid
1 : Real time port function valid
RTP0 data for real time port
RTP1 data for real time port
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuous measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure falling period in period measurement mode
Falling edge active for CNTR 1 interrupt
1 : Count at falling edge in event counter mode
Measure rising period in period measurement mode
Rising edge active for CNTR 1 interrupt
Timer Y count stop bit
0 : Count operation
1 : Count stop
Fig. 32 Structure of Timer Y related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 43 of 134
b0
Timer Y control register
(TYCON: address 003916)
Timer Y write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer Y count source selection bit
0 : Frequency divider output
1 : f(XCIN)
Timer Y frequency division selection bits
b3 b2
0
0
1
1
(1)
0 : 1/16 × φSOURCE
1 : 1/1 × φSOURCE
0 : 1/2 × φSOURCE
1 : 1/256 × φSOURCE
Not used (returns “0” when read)
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•Internal on-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
38D5 Group
SERIAL INTERFACE
• SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O mode selection bit of the serial I/O1 control register
to “1”.
For clock synchronous serial I/O1, the transmitter and the
receiver must use the same clock. If an internal clock is used,
transfer is started by a write signal to the TB/RB.
Data bus
Address 001816
Serial I/O1 control register
Receive buffer register
P40/RXD
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
Shift clock
Clock control circuit
P42/SCLK1
φSOURCE
(1)
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
1/4
P43/SRDY1
F/F
Falling-edge detector
Clock control circuit
Transmit shift completion flag (TSC)
Shift clock
P41/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Data bus
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 33 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write pulse to receive/transmit
buffer register
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or
after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 34 Operation of clock synchronous serial I/O1 function
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 44 of 134
38D5 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
P40/RXD
Serial I/O1 control register Address 001A16
OE
Receive buffer register
Character length selection bit
ST detector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P42/SCLK1
φSOURCE
(1) BRG count source selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P41/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Character length selection bit
Transmit buffer empty flag (TBE)
Address 001916
Transmit buffer register
Address 001816
Serial I/O1 status register
Data bus
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 35 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer register
write signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1∗
TBE=1
Serial output TxD
ST
D0
D1
SP
ST
D0
SP
D1
∗ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer register
read signal
RBF=0
RBF=1
RBF=1
Serial input RxD
ST
D0
D1
SP
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting
of the transmit interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC flag = “1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until
changing to TSC flag = “0”.
Fig. 36 Operation of UART serial I/O1 function
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 45 of 134
SP
38D5 Group
[Transmit Buffer Register/Receive Buffer Register
(TB1/RB1)]
The transmit buffer register and the receive buffer register are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIO1STS)]
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O1 status register sets all the error flags OE, PE, FE, and
SE (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial
I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register)
also sets all the status flags to “0”, including the error flags.
All bits of the serial I/O1 status register are set to “0” at reset, but
if the transmit enable bit (bit 4) of the serial I/O1 control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIO1CON)]
The serial I/O1 control register consists of eight control bits for
the serial I/O1 function.
[UART Control Register (UARTCON)]
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of the data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P41/TXD pin.
[Baud Rate Generator (BRG)]
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 46 of 134
<Notes on serial I/O1>
When setting transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”.
When not requiring the interrupt occurrence synchronous with
the transmission enabled, take the following sequence.
(1) Set the serial I/O1 transmit interrupt enable bit to “0”
(disabled).
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/O1 transmit interrupt request bit to “0” after
1 or more instructions have been executed.
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
38D5 Group
b7
b7
b0
b0
Serial I/O1 status register
(SIO1STS : address 001916)
b7
b0
Serial I/O1 control register
(SIO1CON : address 001A16)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
BRG count source selection bit (CSS)
0: φSOURCE (1)
1: φSOURCE/4
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY1 output enable bit (SRDY)
0: P43 pin operates as ordinary I/O pin
1: P43 pin operates as SRDY1 output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P40 to P43 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P40 to P43 operate as serial I/O pins)
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P41/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 37 Structure of serial I/O1 related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 47 of 134
38D5 Group
• Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For serial I/O2, the transmitter and the receiver must use the
same clock.
When the internal clock is selected as the operating clock, a write
signal to the serial I/O2 register initializes serial I/O2 and
transmission/reception starts.
When the external clock is selected as the operating clock, a
write signal to the serial I/O2 register initializes the serial I/O2
counter and transmission/reception is enabled. Inputting the
external clock starts transmission/reception. To write to the serial
I/O2 register when the external clock is selected as the operating
clock, perform writing while SCLK2 is set to “H”.
b7
b0
Serial I/O2 control register
(SIO2CON: address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : φSOURCE/8 (1)
1 : φSOURCE/16
0 : φSOURCE/32
1 : φSOURCE/64
0 : Not available
1 : Not available
0 : φSOURCE/128
1 : φSOURCE/256
Serial I/O2 port selection bit
0 : I/O port
1 : SOUT2, SCLK2 signal pin
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8bits which control
various serial I/O functions.
P45/SOUT2 P-channel output disable bit
0 : CMOS output (at output mode)
1 : N-channel open-drain output (at output mode)
Transfer direction selection bit
0 : LSB first
1 : MSB first
Serial I/O2 synchronous clock selection bit
0 : External clock
1 : Internal clock
SRDY2 output selection bit
0 : I/O port P47
1 : SRDY2 signal output
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 38 Structure of serial I/O2 control registers
Internal
synchronous clock
Data bus
selection bits
Frequency
divider
φSOURCE
P47 latch
(1)
Serial I/O2 synchronous
clock selection bit “1”
Synchronous circuit
“0”
S CLK2
P47/SRDY2
1/8
1/16
1/32
1/64
1/128
1/256
External clock
P46 latch
“0”
P46/SCLK2
(1)
“1”
P45 latch
“0”
Serial I/O2 counter (3)
P45/SOUT2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P44/SIN2
Address 001F16
Notes: 1: It is selected by the serial I/O2 synchronous clock selection bit, S RDY2 output
selection bit and serial I/O2 port selection bit.
2: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 39 Block diagram of serial I/O2
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 48 of 134
Serial I/O2
interrupt request
38D5 Group
[Serial I/O2 Operation]
Writing to the serial I/O2 register initializes the serial I/O2
counter to “7”.
After writing, the S OUT2 pin outputs data each time the
synchronous clock changes from “H” to “L”. The S IN2 pin
captures data each time the synchronous clock changes from “L”
to “H” and the serial I/O2 register shifts 1-bit simultaneously.
When the external clock is selected as the synchronous clock,
counting the synchronous clock eight times results the following:
• Serial I/O2 counter = “0”
• Synchronous clock is stopped at “H”
• Serial I/O2 interrupt request bit = “1”
After transfer is completed, the SOUT2 pin is placed in the highimpedance state.
Transfer clock
When the external clock is selected as the synchronous clock,
counting the synchronous clock eight times sets the serial I/O2
bit to “1” and the S OUT2 pin retains the D7 output level.
However, if the synchronous clock is continuously input, the
serial I/O2 register continues shifting and the SOUT2 pin keeps
outputting transmit data.
(1)
Serial I/O2 register
write signal
(2) (3)
Serial I/O2 output SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Reception enable signal
SRDY2
(When the internal clock
is selected)
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer, the dividing frequency of internal clock for transfer
clock can be selected by bits 0 to 2 of serial I/O2 control register.
2: When the internal clock is selected as the synchronous clock, the SOUT2 pin is placed in the high
impedance state after transfer is completed.
3: When the external clock is selected as the synchronous clock, the SOUT2 pin retains the D7 output level
after transfer is completed.
However, if the synchronous clock is continuously input, the serial I/O2 register continues shifting and the
SOUT2 pin keeps outputting transmit data.
Fig. 40 Serial I/O2 timing
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 49 of 134
38D5 Group
A/D CONVERTER
The 38D5 Group has a 10-bit A/D converter. The A/D converter
performs successive approximation conversion. The 38D5 Group
has the ADKEY function which perform A/D conversion of the
“L” level analog input from the ADKEY pin automatically.
[AD Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the AD conversion register (high-order) (address
001716), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the AD conversion register (low-order) (address
001616).
During A/D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference
voltage input pin (VREF) can be controlled by the VREF input
switch bit (bit 0 of address 001616). When “1” is written to this
bit, the resistor ladder is always connected to VREF. When “0” is
written to this bit, the resistor ladder is disconnected from VREF
except during the A/D conversion.
[AD Control Register (ADCON)]
This register controls A/D converter. Bits 2 to 0 are analog input
pin selection bits. Bit 3 is an AD conversion completion bit and
“0” during A/D conversion. This bit is set to “1” upon
completion of A/D conversion.
A/D conversion is started by setting “0” in this bit.
Bit 5 is the ADKEY enable bit. The ADKEY function is enabled
by setting “1” to this bit. When this function is valid, the analog
input pin selection bits are ignored. Also, when bit 5 is “1”, do
not set “0” to bit 3 by program.
[Channel Selector]
The channel selector selects one of the input ports P57/AN7−
P50/AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compare an analog input
voltage with the comparison voltage and store the result in the
AD conversion register. When an A/D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The
conversion accuracy may be low because the change is lost if the
conversion speed is not enough.
Accordingly, set f(X IN ) to at least 500 kHz during A/D
conversion in the XIN mode.
Also, do not execute the STP and WIT instructions during the
A/D conversion.
In the low-speed mode and on-chip oscillator mode, there is no
limit on the oscillation frequency because the on-chip oscillator
is used as the A/D conversion clock. In the low-speed mode, onchip oscillator starts oscillation automatically at the A/D
conversion is executed and stops oscillation automatically at the
A/D conversion is finished even though it is not oscillating.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF, and outputs the divided voltages.
Data bus
b7
b0
AD control register
ADKEY
control circuit
(1)
φSOURCE
1/ 2
1/ 8
A/D control circuit
Channel selector
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7/ADKEY0
Comparator
A/D interrupt request
AD conversion register (H) AD conversion register (L)
(Address 001616)
(Address 001716)
Resistor ladder
AVSS
VREF
Note 1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the low-speed and the on-chip oscillator mode
Fig. 41 Block diagram of A/D converter
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 50 of 134
38D5 Group
b7
b0
AD control register
(ADCON: address 001516)
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : P50/AN0
1 : P51/AN1
0 : P52/AN2
1 : P53/AN3
0 : P54/AN4
1 : P55/AN5
0 : P56/AN6
1 : P57/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
AD conversion clock selection bit
0 : φSOURCE/2
(1)
1 : φSOURCE/8
ADKEY enable bit (2)
0 : Disabled
1 : Enabled
10-bit or 8-bit conversion switch bit
0 : 10-bit AD
1 : 8-bit AD
ADKEY selection bit
0 : Invalid
1 : Valid
At 10bitAD
(Read address 001716 before 001616)
AD conversion register
high-order
(Address 001716)
b7
AD conversion register
low-order
(Address 001616)
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2 (high-order)
b0
b1 b0
*
(low-order)
* VREF input switch bit
0: ON only during A/D conversion
1: ON
Note : The bit 5 to bit 1 of address 001616 become “0” at reading.
Also, bit 0 is undefined at reading.
At 8bitAD
(Read only address 001716)
b7
(Address 001716)
b0
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the low-speed and the on-chip
oscillator mode
2: When the ADKEY enable bit is “1”, the analog input pin selection
bits are invalid.
Do not execute the A/D conversion by program while the ADKEY is
enabled.
Bit 0 to bit 2 of ADCON are not changed even when ADKEY is
enabled.
Fig. 42 Structure of AD control register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 51 of 134
ADKEY function
The ADKEY function is used to judge the analog input voltage
input from the ADKEY pin. When the A/D converter starts
operating after VIL (0.7 × Vcc-0.5) or less is input, the event of
analog voltage input can be judged with the A/D conversion
interrupt.
This function can be used with the STP and WIT state.
As for the ADKEY function in 38D5 Group, the A/D conversion
of analog input voltage immediately after starting ADKEY
function is not performed.
Therefore, the A/D conversion result immediately after an
ADKEY function is undefined. Accordingly, when the A/D
conversion result of the analog input voltage input from the
ADKEY pin is required, start the A/D conversion by program
after the analog input pin corresponding to ADKEY is selected.
• ADKEY Selection
When the ADKEY pin is used, set the ADKEY selection bit to
“1”. The ADKEY selection bit is “0”, just after the A/D
conversion is started.
• ADKEY Enable
The ADKEY function is enabled by writing “1” to the ADKEY
enable bit. Surely, in order to enable ADKEY function, set “1” to
the ADKEY enable bit, after setting the ADKEY selection bit to
“1”.
When the ADKEY enable bit of the AD control register is “1”,
the analog input pin selection bits become invalid. Please do not
write “0” in the AD conversion completion bit by the program
during ADKEY enabled state.
[ADKEY Control Circuit]
In order to obtain a more exact conversion result, by the A/D
conversion with ADKEY, execute the following;
• set the input to the ADKEY pin into a steep falling waveform,
• stabilize the input voltage within 8 clock cycles (1 µs at f(XIN)
= 8 MHz) after the input voltage is under VIL
The threshold voltage with an actual ADKEY pin is the voltage
between VIH-VIL.
In order not to make ADKEY operation perform superfluously in
a noise etc., in the state of the waiting for an input, set the voltage
of an ADKEY pin to VIH (0.9VCC) or more.
When the following operations are performed, the A/D
conversion operation cannot be guaranteed.
• When the CPU mode register is operated during A/D
conversion operation,
• When the AD conversion control register is operated during
A/D conversion operation,
• When the STP or WIT instruction is executed during A/D
conversion operation.
38D5 Group
LCD DRIVE CONTROL CIRCUIT
The 38D5 Group has the built-in Liquid Crystal Display (LCD)
drive control circuit consisting of the following.
• LCD display RAM
• Segment output disable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit
A maximum of 36 segment output pins and 8 common output
pins can be used.
Up to 256 pixels can be controlled for an LCD display. When the
LCD enable bit is set to “1” after data is set in the LCD mode
register, the segment output disable register, and the LCD display
RAM, the LCD drive control circuit starts reading the display
data automatically, performs the bias control and the duty ratio
control, and displays the data on the LCD panel.
b7
b0
.
Table 12
Maximum number of display pixels at each duty ratio
Duty ratio
1
2
3
4
8
b7
Maximum number of display pixels
36 dots
or 8 segment LCD 4 digits
72 dots
or 8 segment LCD 9 digits
108 dots
or 8 segment LCD 13 digits
144 dots
or 8 segment LCD 18 digits
256 dots
or 8 segment LCD 32 digits
b0
LCD mode register 1
(LM 1 : address 001316)
LCD mode register 2
(LM2 : address 001416) (4)
Duty ratio selection bits
Voltage multiplier circuit control bit
0 : Voltage multiplier circuit disabled
(Input ports P70/INT01, P71/INT11)
1 : Voltage multiplier circuit enabled (C1, C2 pins)
VL3 connection bit
0 : Connect LCD internal VL3 to VCC
1 : Connect LCD internal VL3 to VL3 pin
Not used (returns “0” when read)
b2b1b0
0 0 0 : 1 (Static)
0 0 1 : 2 (use COM0, COM1)
0 1 0 : 3 (use COM0-COM2)
0 1 1 : 4 (use COM0-COM3)
1 0 0 to 1 1 0 : Not available
1 1 1 : 8 (COM0-COM7)
Bias control bit
0 : 1/3 bias (1)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (2)
0 : f(XCIN)/32
1 : φSOURCE/8192
b7
b7
b0
b7
b0
Segment output disable register 0
(SEG0 : address 0FF416) (3)
Segment output disable register 1
(SEG1 : address 0FF516) (3)
Segment output disable bit 0
0 : Segment output SEG8
1 : Output port P00
Segment output disable bit 1
0 : Segment output SEG9
1 : Output port P01
Segment output disable bit 2
0 : Segment output SEG10
1 : Output port P02
Segment output disable bit 3
0 : Segment output SEG11
1 : Output port P03
Segment output disable bit 4
0 : Segment output SEG12
1 : Output port P04
Segment output disable bit 5
0 : Segment output SEG13
1 : Output port P05
Segment output disable bit 6
0 : Segment output SEG14
1 : Output port P06
Segment output disable bit 7
0 : Segment output SEG15
1 : Output port P07
Segment output disable bit 8
0 : Segment output SEG0
1 : Output port P20
Segment output disable bit 9
0 : Segment output SEG1
1 : Output port P21
Segment output disable bit 10
0 : Segment output SEG2
1 : Output port P22
Segment output disable bit 11
0 : Segment output SEG3
1 : Output port P23
Segment output disable bit 12
0 : Segment output SEG4
1 : Output port P24
Segment output disable bit 13
0 : Segment output SEG5
1 : Output port P25
Segment output disable bit 14
0 : Segment output SEG6
1 : Output port P26
Segment output disable bit 15
0 : Segment output SEG7
1 : Output port P27
b0
Segment output disable register 2
(SEG2 : address 0FF616) (3)
Segment output disable bit 16
0 : Segment output SEG16-SEG19
1 : Output port P10-P13
Segment output disable bit 17
0 : Segment output SEG20-SEG23
1 : Output port P14-P17
Segment output disable bit 18
0 : Segment output SEG24-SEG27
1 : Output port P30-P33
Segment output disable bit 19
0 : Segment output SEG28-SEG31
1 : Output port P34-P37
Not used (do not write “1”)
Fig. 43 Structure of LCD related registers
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 52 of 134
Notes 1: When “1” is selected as duty ratio by the duty ratio selection bits,
set “1” to the bias control bit.
2: LCDCK is a clock for the LCD timing controller.
φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
3: Only pins set to output ports by the direction register can be controlled
to switch to output ports or segment outputs by the segment output
disable register.
4: When disabling the voltage multiplier circuit, the C1 and C2 pins
function as input ports P70/INT01, P71/INT11.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Address
0841 16
Address
0842 16
Address
0843 16
Fig. 44 Block diagram of LCD controller/driver
Page 53 of 134
Level
shift
Level
shift
Level
shift
COM 7 /
SEG 32
Level
shift
COM 5 /
SEG 34
COM 4 /
SEG 35
Segment Segment
driver
driver
Level
shift
(2)
V L3
connection
bit
V SS V L1 V L2 V L3 C 1 C 2
Level
shift
Level
shift
Level
shift
Level
shift
“1”
“0”
Level
shift
LCDCK
Level
shift
LCD
divider
Timing controller
2
Level
shift
φSOURCE/8192
f(X CIN )/32
LCDCK count source
selection bit
COM 0
COM 1 COM 2 COM 3
COM 4/ COM 5 / COM 6 / COM 7 /
SEG 35 SEG 34 SEG 33 SEG 32
Common Common Common Common Common Common Common Common
driver
driver
driver
driver
driver
driver
driver
driver
V CC
Level
shift
2
Duty ratio selection bits
LCD circuit
divider division
ratio selection bits
LCD enable bit
Voltage multiplier
control bit
Bias control bit
Bias control
Address
LCD display RAM
0863 16
Selector Selector
Address
0862 16
Notes 1: LCDCK is the clock for the LCD timing controller.
φSOURCE indicates the followings:
•X IN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
2: When the voltage multiplier circuit is not used (bit 0 of LCD mode register 2
= “0”), the C 1 and C 2 pins function as input ports P7 0 /INT 01 , P7 1/INT 11.
P20 /SEG 0 P2 1 /SEG 1 P22 /SEG 2 P2 3 /SEG 3
Segment Segment Segment Segment
driver
driver
driver
driver
Level
shift
Selector Selector Selector Selector
Address
0840 16
Data bus
(1)
38D5 Group
38D5 Group
• Voltage Multiplier
The voltage multiplier performs threefold boosting. This circuit
inputs a reference voltage for boosting from LCD power input
pin VL1. Set each bit of the segment output disable registers and
the LCD mode registers in the following order for operating the
voltage multiplier.
(1) Set the segment output disable bits (bits 0 to 19) of the
segment output disable registers (SEG0, 1, 2) to “0” or “1”.
(2) Set the duty ratio selection bits (bits 0 to 2), the bias control
bit (bit 3), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register 1 to “0” or “1”.
(3) Set the VL3 connection bit (bit 1 of the LCD mode register 2
(LM2)) to “1”.
(4) Set the voltage multiplier control bit (bit0) of the LCD mode
register 2 to “1”.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
The voltage multiplier is controlled by the voltage multiplier
control bit (bit 0 of the LCD mode register 2).
In addition, when the voltage multiplier is used, set the voltage
multiplier control bit to “1” (voltage multiplier enabled) after the
voltage 1.3 V or more and 2.1 V or less.
When the voltage multiplier is not used, set the VL3 connection
bit to “1” (open), and apply the suitable voltage for the power
supply input pins for LCD (VL1-VL3).
When VL3 connection bit is set to be open, VL3 pin is in a high
impedance state.
When the voltage multiplier is used, set the LCDCK frequency to
100 Hz or more. The on-chip oscillator cannot be used for
LCDCK.
In a system where the multiplier circuit is used (a multiplier
capacitor is externally connected between the C1 and C2 pins),
set the voltage multiplier circuit control bit to “1” (voltage
multiplier circuit enabled) before executing the STP or WIT
instruction.
• Bias Control and Applied Voltage to LCD Power Input
Pins
Apply the voltage value shown in Table 13 according to the bias
value to the LCD power input pins. Apply the voltage value
shown in Table 13 according to the bias value by setting to VL3
connection bit (bit 1 of LCD mode register 1) to “1”, when the
voltage multiplier is not used.
Select a bias value by the bias control bit (bit 3 of the LCD mode
register 1).
Table 13 Bias control and applied voltage to VL1−VL3
Bias value
Voltage value
VL3 = VLCD
VL2 = 2/3 VLCD
VL1 = 1/3 VLCD
VL3 = VLCD
VL2 = VL1 = 1/2 VLCD
1/3 bias
1/2 bias
NOTE:
1. VLCD is the maximum value of supplied voltage for the LCD
panel.
• Common Pin and Duty Ratio Control
The common pins (COM0−COM7) to be used are determined by
duty ratio. Select duty ratio by the duty ratio selection bits (bits 0,
1 and 2 of the LCD mode register1). When reset is released, VCC
voltage is output from the common pin.
Table 14 Duty ratio control and common pins used
Duty ratio selection bits
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
Duty
ratio
1
2
3
4
8
VL3
1. Unused common pin outputs the unselected waveform.
• Segment Signal Output Pin
The segment signal output pins (SEG0−SEG31) are shared with
ports P0−P3. When these pins are used as the segment signal
output pins, set the direction registers of the corresponding pins
to “1”, and set the segment output disable register to “0”.
Also, these pins are set to the input port after reset, the V CC
voltage is output by the pull-up resistor.
Contrast adjust
VL3
VL3
R1
VL2
VL2
R4
VL2
VL2
C2
P71/INT11
*
C1
P70/INT01
*
P71/INT11
*
P70/INT01
*
R2
VL1
VL1
VL1
VL1
R5
R3
1/3 bias
Voltage multiplier is used.
1/3 bias: R1 = R2 = R3
1/3 bias
Voltage multiplier is not used.
R4 = R5
1/2 bias
* : When the voltage multiplier is not used, the C1 and C2 pins function as input ports P70/INT01, P71/INT11.
Fig. 45 Example of circuit at each bias (at external power supply input)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 54 of 134
COM0
COM0, COM1
COM0−COM2
COM0−COM3
COM0−COM7
NOTE:
Contrast adjust
VL3
Common pins used
1/1 bias (static)
38D5 Group
• LCD Display RAM
The 36-byte area of address 084016 to 086316 is the designated
RAM for the LCD display. When “1” is written to these
addresses, the corresponding segments of the LCD display panel
are turned on.
The LCDCK timing frequency (LCD drive timing) is generated
internally and the frame frequency can be determined with the
following equation;
f(LCDCK)=
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency=
<Notes>
(1) Executing STP Instruction
Executing the STP instruction sets the LCD enable bit (bit 4 of
LCD mode register1 (address 001316)) to “0” and the LCD panel
turns off. To turn the LCD panel on after returning from stop
mode, set the LCD enable bit to “1”.
(2) VL3 Pin
To use the LCD drive control circuit while VL3 is set to the
voltage equal to VCC, apply the VCC voltage to the VL3 pin and
write “1” to the VL3 connection bit (bit 1 of LCD mode register 2
(address 001416)).
f(LCDCK)
duty ratio
at 4COM × 36SEG
Bits
7
6
5
4
3
at 8COM × 32SEG
2
1
0
084016
084116
084216
084316
084416
084516
084616
084716
084816
084916
084A16
084B16
084C16
084D16
084E16
084F16
085016
085116
085216
085316
085416
085516
085616
085716
085816
085916
085A16
085B16
085C16
085D16
085E16
085F16
086016
086116
086216
086316
Bits
7
6
5
4
3
2
1
0
Address
Address
Not used
(This area can be used
as normal RAM.)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
COM3 COM2 COM1 COM0
Fig. 46 LCD display RAM map
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 55 of 134
084016
084116
084216
084316
084416
084516
084616
084716
084816
084916
084A16
084B16
084C16
084D16
084E16
084F16
085016
085116
085216
085316
085416
085516
085616
085716
085816
085916
085A16
085B16
085C16
085D16
085E16
085F16
086016
086116
086216
086316
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
Not used
(This area can be used as normal RAM.)
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
38D5 Group
Internal signal
LCDCK timing
1/8 duty
Voltage level
VL3
VL2 = VL1
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VL3
VSS
SEG0
OFF
ON
OFF
ON
OFF
ON
OFF
ON
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
1/4 duty
VL3
VL2 = VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
ON
OFF
ON
OFF
ON
OFF
ON
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
1/3 duty
VL3
VL2 = VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
OFF
COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0
1/2 duty
VL3
VL2 = VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0
Fig. 47 LCD drive waveform (1/2 bias)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 56 of 134
38D5 Group
Internal signal
LCDCK timing
Voltage level
1/8 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VL3
SEG0
VSS
OFF
ON
OFF
ON
OFF
ON
OFF
ON
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
1/4 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
ON
OFF
ON
OFF
OFF
ON
ON
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0 COM2 COM1 COM0
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0
Fig. 48 LCD drive waveform (1/3 bias)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 57 of 134
38D5 Group
ROM CORRECTION FUNCTION
A part of program in ROM can be corrected.
Set the start address of the corrected ROM data (i.e. an Op code
address of the beginning instruction) to the ROM correction
address high-order and low-order registers.
When the program is being executed and the value of the
program counter matches with the set address value in the ROM
correction address registers, the program is branched to the ROM
correction vectors and then the correction program can be
executed by setting it to the ROM correction vectors.
Use the JMP instruction (3-byte instruction) to return the main
program from the correction program.
The correctable area is up to two. There are two vectors for ROM
correction.
Also, ROM correction vector can be selected from the RAM area
or ROM area by the ROM correction memory selection bit.
ROM correction address 1 high-order register (RCA1H)
0FF816
ROM correction address 1 low-order register (RCA1L)
0FF916
ROM correction address 2 high-order register (RCA2H)
0FFA16
ROM correction address 2 low-order register (RCA2L)
0FFB16
Note: Do not set address other than ROM area.
Fig. 49 ROM correction address register
000016
SFR area
Zero
page
004016
Vector 1
Vector 2
RAM area
RC2 = “0”
address 010016
address 012016
ROM area
RC2 = “1”
address F10016
address F12016
RAM
010016 ROM correction vector 1
012016 ROM correction vector 2
063F16
The ROM correction function is controlled by the ROM
correction address 1 enable bit and ROM correction address 2
enable bit.
If the ROM correction function is not used, the ROM correction
vector may be used as normal RAM/ROM. When using the
ROM correction vector as normal RAM/ROM, make sure to set
bits 1 and 0 in the ROM correction enable register to “0”
(Disable).
<Notes>
1. When using the ROM correction function, set the ROM correction address registers and then enable the ROM correction with the ROM correction enable register.
2. Do not set addresses other than the ROM area in the ROM
correction address registers.
Do not set the same ROM correction addresses in both the
ROM correction address registers 1 and ROM correction
address registers 2.
3. It is necessary to contain the process for ROM correction in
the program.
b7
~
~
~
~
800016
Reserved ROM area
808016
Protect
area 1
EFFF16
F10016 ROM correction vector 1
ROM
F12016 ROM correction vector 2
FF0016
Special
page
FFDB16
FFFF16
Reserved ROM area
Interrupt vector area
Fig. 50 Memory map of M38D58G8
b0 ROM correction enable register (Address 0FFC 16)
RCR
ROM correction address 1 enable bit (RC0)
0 : Disable
1 : Enable
ROM correction address 2 enable bit (RC1)
0 : Disable
1 : Enable
ROM correction memory selection bit (RC2)
0 : Branch to the RAM area
1 : Branch to the ROM area
Not used (returns “0” when read)
Note: After ROM correction address register is set,
set the ROM correction address enable bit to be enabled.
Fig. 51 Structure of ROM correction enable register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 58 of 134
38D5 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit counter.
• Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each
watchdog timer is set to “FF16”. Instructions such as STA, LDM
and CLB to generate the write signals can be used.
The written data in bits 7, 6 or 5 are not valid, and the above
values are set.
Bits 7 to 5 can be rewritten only once after releasing reset.
After rewriting it is disable to write any data to this bit. This bit
becomes “0” after reset.
• Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the
watchdog timer control register. An internal reset occurs at an
underflow of the watchdog timer. Then, reset is released after the
reset release time is elapsed, the program starts from the reset
vector address.
Normally, writing to the watchdog timer control register before
an underflow of the watchdog timer is programmed. If writing to
the watchdog timer control register is not executed, the watchdog
timer does not operate.
When reading the watchdog timer control register is executed,
the contents of the high-order 5-bit counter, the count source
selection bit 2 (bit 5), the STP instruction function selection bit
(bit 6), and the count source selection bit (bit 7) are read out.
(1)
“0”
Data bus
“0”
1/1024
On-chip oscillator 1/4
“1”
<Notes>
1. The watchdog timer continues to count even during the wait
time set by timer 1 and timer 2 to release the stop state and
in the wait mode. Accordingly, write to the watchdog timer
control register to not underflow the watchdog timer in this
time.
2. When the on-chip oscillator is selected by the watchdog
timer count source selection bit 2, the on-chip oscillator
forcibly oscillates and it cannot be stopped. Also, in this
time, set the STP instruction function selection bit to “1” at
this time.
Select “0” (φSOURCE) the watchdog timer count source
selection bit 2 at the system which on-chip oscillator is
stopped.
Watchdog timer
count source
selection bit
Watchdog timer count
source selection bit 2
φ SOURCE
• Bit 6 of Watchdog Timer Control Register
1. When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer
restarts counting (Note 1). When executing the WIT
instruction, the watchdog timer does not stop.
2. When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
3. The time until the underflow of the watchdog timer register
after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer
control register is “0”);
4. at XIN mode (f(XIN) = 8 MHz): 32.768 ms
5. at low-speed mode (f(XCIN) = 32 KHz): 8.19s
“1”
1/4
Watchdog
timer L (3)
Watchdog
timer H (5)
“FF16” is set when
watchdog timer
control register is
written to.
Undefined instruction
Reset
STP instruction function selection bit
Reset
circuit
STP instruction
RESET
Internal reset
Wait until reset release
Note1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
Fig. 52 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 002916)
Watchdog timer H (for read-out of high-order 5 bit)
“FF16” is set to watchdog timer by writing to these bits.
Watchdog timer count source selection bit 2
0 : φSOURCE (1)
1 : On-chip oscillator/4
STP instruction function selection bit
0 : Entering stop mode by execution of STP instruction
1 : Internal reset by execution of STP instruction
Watchdog timer count source selection bit
0 : Count source/1024
1 : Count source/4
Fig. 53 Structure of Watchdog timer control register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 59 of 134
Notes 1: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4 , or 8 mode
•On-chip oscillator divided by 4 in the on-chip
oscillator mode
•Sub-clock in the low-speed mode
2: When the on-chip oscillator is selected by the
watchdog timer count source selection bit 2,
set the STP instruction function selection bit
to “1”.
Select φ(SOURCE) as the count source at the
system which on-chip oscillator is stopped.
3: Bits 7 to 5 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit.
38D5 Group
CLOCK OUTPUT FUNCTION
A system clock φ can be output from I/O port P72. The triple
function of I/O port, timer 2 output function and system clock φ
output function are controlled by the clock output control register
(address 0FF316) and the timer 2 output selection bit of the timer
12 mode register (address 002516).
In order to output a system clock φ from I/O port P72, set the
timer 2 output selection bit to “1” and P72 clock output control
bits of the clock output control register to “01”. In order to output
the same signal as oscillation frequency of sub clock XCIN, set
the P72 clock output control bits to “10”. When the clock output
function is selected, a clock is output while the direction register
of port P72 is set to the output mode.
P72 is switched to the port output or the output (timer 2 output or
the clock output) except port at the cycle after the timer 2 output
selection bit is switched.
b7
b0
Clock output control register
(CKOUT : address 0FF316)
P72 clock output control bits
b1b0
0 0: Timer 2 output
0 1: φ frequency signal output
1 0: XCIN frequency signal output
1 1: Not available
Not used (returns “0” when read)
Fig. 54 Structure of clock output control register
Timer 2 output selection bit
T2OUT output edge
switch bit
Timer 2 latch (8)
Timer 2 (8)
S
1/2
T
Q “0”
“1”
Q
P72/T2OUT/CKOUT
“00”
P72 latch
P72 direction register
System clock φ
Timer 2 output selection bit
“01”
b7
XCIN
b0
Timer 12 mode register (address 002516)
T12M
“10”
Timer 2 output selection bit
0 : I/O port
1 : Timer 2 output
P72 clock output
control bits
Fig. 55 Block diagram of Clock output function
Other function registers
[RRF register (RRFR)]
The RRF register (address 001216) is the 8-bit register and does
not have the control function.
As for the value written in this register, high-order 4 bits and
low-order 4 bits interchange.
It is initialized after reset.
b7
b0
RRF register
(RRFR : address 001216)
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
Fig. 56 Structure of RRF register
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 60 of 134
38D5 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC (min.)
and 5.5 V), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD 16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage
meets VIL spec. When a power source voltage passes VCC (min.).
In the flash memory version, input to the RESET pin in the
following procedure.
• When power source is stabilized
(1) Input “L” level for 2µs or more to RESET pin.
(2) Input “H” level to RESET pin.
• At power-on
(1) Input “L” level to RESET pin.
(2) Increase the power source voltage to 2.7 V.
(3) Wait for td(P-R) until internal power source has stabilized.
(4) Input “H” level to RESET pin.
In the QzROM version, the input level applied to the OSCSEL
pin is determined when the RESET pin changes from “L” to “H”.
VCC VCC (min.)
0V
VCC
RESET
RESET
0.2VCC or less
0V
(1)
5V
VCC
2.7 V
0V
5V
RESET
0V
VCC
RESET
td(P-R) or more
Power source
voltage detection
circuit
Note 1: QzROM version: 2 µs or more
Flash memory version: td(P-R) or more
Fig. 57 Reset circuit example
OSCSEL=L: OCO
OSCSEL=H: XIN
······
System clock φ
RESET
Internal
reset
Reset address from
vector table
Address
?
Data
?
?
?
FFFC
ADL
FFFD
ADH, ADL
ADH
SYNC
OSCSEL=L: OCO= about 32768 cycles
OSCSEL=H: XIN= about 8192 cycles
Notes 1: The frequency of system clock φ is f(OCO)/32 or f(XIN)/8.
2: The question marks (?) indicate an undefined state.
3: In the QzROM version, the input level applied to the OSCSEL pin is determined when the RESET pin changes from “L” to “H”.
Fig. 58 Reset sequence
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 61 of 134
38D5 Group
Address
000016
Register contents
0016
(36) Timer X (low-order)
Port P0 direction register
000116
0016
Port P1
000216
0016
(4)
Port P1 direction register
000316
(5)
Port P2
(6)
Address
002A16
Register contents
FF16
(37) Timer X (high-order)
002B16
FF16
(38) Timer X (extension)
002C16
0016
0016
(39) Timer X mode register
002D16
0016
000416
0016
(40) Timer X control register 1
002E16
0016
Port P2 direction register
000516
0016
(41) Timer X control register 2
002F16
0016
(7)
Port P3
000616
0016
(42) Compare register 1 (low-order)
003016
0016
(8)
Port P3 direction register
000716
0016
(43) Compare register 1 (high-order)
003116
0016
(9)
Port P4
000816
0016
(44) Compare register 2 (low-order)
003216
0016
(10) Port P4 direction register
000916
0016
(45) Compare register 2 (high-order)
003316
0016
(11) Port P5
000A16
0016
(46) Compare register 3 (low-order)
003416
0016
(12) Port P5 direction register
000B16
0016
(47) Compare register 3 (high-order)
003516
0016
(13) Port P6
000C16
0016
(48) Timer Y (low-order)
003616
FF16
(14) Port P6 direction register
000D16
0016
(49) Timer Y (high-order)
003716
FF16
(15) Port P7
000E16
0016
(50) Timer Y mode register
003816
0016
(16) Port P7 direction register
000F16
0016
(51) Timer Y control register
003916
0016
(17) CPU mode register 2
(52) Interrupt edge selection register
003A16
0016
(18) RRF register
001116 0 0 0 0 0 0 0 *
0016
001216
(53) CPU mode register
(19) LCD mode register 1
001316
0016
(54) Interrupt request register 1
003B16 * 1 * 0 0 0 0 0
0016
003C16
(20) LCD mode register 2
001416
0016
(55) Interrupt request register 2
003D16
0016
(21) AD control register
001516
0816
(56) Interrupt control register 1
003E16
0016
(22) Serial I/O1 status register
001916 1 0 0 0 0 0 0 0
0016
001A16
(57) Interrupt control register 2
003F16
0016
(58) PULL register 1
0FF016
0016
(59) PULL register 2
0FF116
0016
(25) Serial I/O2 control register
001B16 1 1 1 0 0 0 0 0
0016
001D16
(60) PULL register 3
0FF216
0016
(26) Timer 1
002016
FF16
(61) Clock output control register
0FF316
0016
(27) Timer 2
002116
0116
(62) Segment output disable register 0
0FF416
FF16
(28) Timer 3
002216
FF16
(63) Segment output disable register 1
0FF516
FF16
(29) Timer 4
002316
FF16
(64) Segment output disable register 2
0FF616
0F16
(30) PWM01 register
002416
0016
(65) Key input control register
0FF716
0016
(31) Timer 12 mode register
002516
0016
(66) ROM correction address 1(high-order) 0FF816
0016
(32) Timer 34 mode register
(33) Timer 1234 mode register
002616
0016
(67) ROM correction address 1(low-order)
0FF916
0016
002716
0016
(68) ROM correction address 2 (high-order) 0FFA16
0016
1234 frequency division
(34) Timer
selection register
002816
0016
(69) ROM correction address 2 (low-order) 0FFB16
0016
(70) ROM correction enable register
0016
(1)
Port P0
(2)
(3)
(23) Serial I/O1 control register
(24) UART control register
(35) Watchdog timer control register 002916 0 0 0 1 1 1 1 1
(71) Processor status register
(72) Program counter
0FFC16
(PS) × × × × × 1 × ×
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
×: Not fixed
*: Depends on OSCSEL setting at the QzROM version.
In the flash memory version, the CPU mode register 2 (address
001116), is set to “0016” and the CPU mode register (address 003B16) is
set to “E016”.
Since the initial values for other than above mentioned registers and RAM
contents are indefinite at reset, they must be set.
Fig. 59 Internal status at reset
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 62 of 134
38D5 Group
CLOCK GENERATING CIRCUIT
The oscillation circuit of 38D5 Group can be formed by
connecting an oscillator, capacitor and resistor between XIN and
XOUT (XCIN and XCOUT). To supply a clock signal externally,
input it to the XIN pin and make the XOUT pin open. The clocks
that are externally generated cannot be directly input to XCIN.
Use the circuit constants in accordance with the oscillator
manufacturer's recommended values. No external resistor is
needed between XIN and XOUT since a feed-back resistor exists
on-chip. (An external feed-back resistor may be needed
depending on conditions.) However, an about 10 MΩ external
feedback resistor is needed between XCIN and XCOUT.
The 38D5 Group operation mode immediately after reset
depends on the OSCSEL pin state in the QzROM version.
When the OSCSEL pin state is GND level, the only on-chip
oscillator starts oscillating. The XIN -X OUT oscillation stops
oscillating, and XCIN and X COUT pins function as I/O ports.
Flash memory version as same.
When the OSCSEL pin state is V CC level, the X IN -X OUT
oscillation divided by 8 starts oscillating. The on-chip oscillator
stops oscillating, and the XCIN and XCOUT pins function as I/O
ports.
Note the following in each mode.
• XIN Mode
The XIN-XOUT oscillation does not stop even if the XIN-XOUT
oscillation stop bit is set to “1”.
• Low-Speed Mode
The XCIN-XCOUT oscillation stops if the port XC switch bit is set
to “0”.
• On-Chip Oscillator Mode
Even if the on-chip oscillator stop bit is set to “1”, the on-chip
oscillator oscillation does not stop in the flash memory version,
but stops in the QzROM version.
• Frequency Control
(1) On-chip oscillation mode
The system clock φ is the on-chip oscillator oscillation divided
by 32.
(2) XIN mode
Frequency/2 mode, frequency/4 mode, and frequency/8 mode are
collectively referred as XIN mode.
- Frequency/8 Mode
The system clock φ is the frequency of XIN divided by 8.
- Frequency/4 Mode
The system clock φ is the frequency of XIN divided by 4.
- Frequency/2 Mode
The system clock φ is half the frequency of XIN.
(3)Low-speed Mode
The system clock φ is half the frequency of sub clock.
After reset and when system returns from the stop mode, the
operation mode depends on the OSCSEL pin state in the
QzROM version and the flash memory version operation mode is
the on-chip oscillator mode.
When the RESET pin changes from “L” to “H” and when the
STP instruction is executed, determine the input level applied to
the OSCSEL pin.
Refer to the clock state transition diagram for the setting of
transition to each mode.
The XIN-OUT oscillation is controlled by the bit 5 of CPUM, and
the sub-clock oscillation is controlled by the bit 4 of CPUM and
the on-chip oscillator oscillation is controlled by the bit 0 of
CPUM2.
In the on-chip oscillator mode, the oscillation by the oscillator
can be stopped. In the low-speed mode, the power consumption
can be reduced by stopping the XIN−XOUT oscillation.
In low-speed mode, the on-chip oscillator stops in the QzROM
version regardless of the on-chip oscillator stop bit value. The
on-chip oscillator does not stop in the flash memory version, so
set the on-chip oscillator stop bit to “1” to stop the oscillation.
Set enough time for oscillation to stabilize by programming to
restart the stopped oscillation and switch the operation mode.
Also, set enough time for oscillation to stabilize by programming
to switch the timer count source.
<Notes on Clock Generating Circuit>
If you switch the mode between on-chip oscillator mode, XIN
mode and low-speed mode, stabilize both X IN and X CIN
oscillations. Especially be careful immediately after power-on
and at returning from stop mode. Refer to the clock state
transition diagram for the setting of transition to each mode. Set
the frequency in the condition that f(XIN) > 3•f(XCIN).
When the X IN mode is not used (X IN -X OUT oscillation and
external clock input are not performed), connect XIN to VCC
through a resistor.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 63 of 134
38D5 Group
• Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock φ stops at an
“H” level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values * to
generate the wait time required for oscillation stabilization to
timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and
high-order 8 bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count
source, and the output of timer 1 is forcibly connected to timer 2. In
this time, bits 0 to 5 of the timer 12 mode register are cleared to “0”.
The values of the timer 12 frequency divider selection register
are not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to be
disabled (“0”) before executing the STP instruction.
*: Reference (Set values according to your oscillator and system.)
OSCSEL = “L” of the QzROM version and flash memory
version:
.......................................................................... 000516 or more
OSCSEL = “H” of the QzROM version:
..........................................................................01FF16 or more
When an external interrupt is received, the clock set according to
the OSCSEL pin state starts oscillating in the QzROM version.
The operation mode at returning is decided by the clock that set
according to the OSCSEL pin state.
Bits 3, 5, 6, and 7 of CPUM and bit 0 of CPUM2 are forcibly
changed by the OSCSEL pin state. In the flash memory version,
the on-chip oscillator starts oscillating and the operation mode at
returning is set to on-chip oscillator mode. The bit 3 of CPUM is
changed to “0”, bits 5, 6 and 7 of CPUM are changed to “1”, and
the bit 0 of CPUM2 is changed to “0” forcibly.
Oscillator restarts when reset occurs or an interrupt request is
received, but the system clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit
oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, only the system clock φ stops
at an “H” state. The states of main clock, on-chip oscillator and
sub clock are the same as the state before executing the WIT
instruction, and oscillation does not stop. Since supply of system
clock φ is started immediately after the interrupt is received, the
instruction can be executed immediately.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 64 of 134
XCIN XCOUT
Rf
XIN
Rd
Rd
CCOUT
CCIN
XOUT
CIN
COUT
Note : Insert a damping resistor if required.
The resistance will vary depending on the oscillator and the oscillation drive
capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet specifies that a feedback
resistor be added external to the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT following the instruction.
Fig. 60 Ceramic resonator circuit example
XCIN
XCOUT
Rf
XIN
XOUT
Open
Rd
External oscillation circuit
CCIN
CCOUT
VCC
VSS
Fig. 61 External clock input circuit
38D5 Group
On-chip oscillator
CPUM2 BIT0
On-chip oscillator stop bit
“0”
1/4
XIN
XOUT
Main clock division
ratio selection bit
CPUM BIT7, 6
(2)
“11”
“00”
“01”
“10”
XIN-XOUT
oscillation stop bit
CPUM BIT5
XCOUT
XCIN
“0”
Internal system clock
selection bit
CPUM BIT3 (1)
“1”
φSOURCE
Timer 1 count source
selection bits
“01”
(3)
Timer 1
Frequency divider
for Timer
1/2
Timer 2
“00”
“10”
1/2
1/2
“1”
“1”
Port Xc switch bit
CPUM BIT4
Timer 2 count source
selection bits
“00”
“0”
Main clock
division ratio
selection bit
“0”
CPUM BIT6
“0”
Internal system clock selection bit
“1”
System clock φ
Q S
R
S
STP instruction
WIT
instruction
R
Q
Q S
R
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Notes 1: When the XCIN-XCOUT oscillation is selected as the system clock, set the port Xc
switch bit to “1”.
2: Although a feed-back resistor exists on-chip, an external
feed-back resistor may be needed depending on conditions.
3: φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
However, when used as the A/D conversion clock by the A/D converter,
φSOURCE indicates the followings:
•XIN input in the frequency/2, 4, or 8 mode
•On-chip oscillator divided by 4 in the low-speed or the on-chip oscillator mode
Fig. 62 Clock generating circuit block diagram
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 65 of 134
38D5 Group
Low-speed mode (14)
On-chip oscillator mode
XIN stop
XCIN stop
OCO oscillation
φ =f(OCO)/32
CM7=1
CM6=1
CM5=1
CM4=0
CM3=0 CM8=0
CM5
• QzROM version
• Flash memory version
OSCSEL=L
XIN oscillation
XCIN stop
OCO oscillation
φ =f(OCO)/32
CM7=1
CM6=1
CM5=0
CM4=0
CM3=0 CM8=0
CM4
CM4
CM5
CM4
XIN stop
XCIN oscillation
OCO oscillation
φ =f(OCO)/32
CM7=1
CM6=1
CM5=1
CM4=1
CM3=0 CM8=0
CM3, CM8
(6)
XIN stop
XCIN oscillation
OCO stop
φ =f(XCIN)/2
CM7=1 (invalid)
CM6=1 (invalid)
CM5=1
CM4=1
CM3=1 CM8=1
CM5
(CM7)
CM5
XIN oscillation
XCIN oscillation
OCO oscillation
φ =f(OCO)/32
CM7=1
CM6=1
CM5=0
CM4=1
CM3=0 CM8=0
CM3, CM7,
CM8
(6)
XIN oscillation
XCIN oscillation
OCO stop
φ =f(XCIN)/2
CM7=0 (invalid)
CM6=1 (invalid)
CM5=0
CM4=1
CM3=1 CM8=1
CM6
(CM7)
CM6
Reset release
(6) CM7
(6) CM7
CM3
Frequency/8 mode
• QzROM version
OSCSEL=H
XIN oscillation (frequency/8)
XCIN stop
OCO oscillation or stop
CM4
φ =f(XIN)/8
CM7=0
CM6=1
CM5=0
CM4=0
CM3=0 CM8=∗
XIN oscillation (frequency/8)
XCIN oscillation
OCO oscillation or stop
φ =f(XIN)/8
CM7=0
CM6=1
CM5=0
CM4=1
CM3=0 CM8=∗
CM6
CM5
CM6
CM5
(CM7)
XIN oscillation
XCIN oscillation
OCO stop
φ =f(XCIN)/2
CM7=1 (invalid)
CM6=0 (invalid)
CM5=0
CM4=1
CM3=1 CM8=1
XIN oscillation
XCIN oscillation
OCO stop
φ =f(XCIN)/2
CM7=0 (invalid)
CM6=0 (invalid)
CM5=0
CM4=1
CM3=1 CM8=1
CM3
CM3
CM6
CM7
CM6
CM6
CM6
CM7
Frequency/4 mode
Frequency/2 mode
XIN oscillation (frequency/2)
XCIN stop
OCO oscillation or stop
φ =f(XIN)/2
CM7=0
CM6=0
CM5=0
CM4=0
CM3=0 CM8=∗
CM4
XIN oscillation (frequency/2)
XCIN oscillation
OCO oscillation or stop
φ =f(XIN)/2
CM7=0
CM6=0
CM5=0
CM4=1
CM3=0 CM8=∗
XIN oscillation (frequency/4)
XCIN stop
OCO oscillation or stop
φ =f(XIN)/4
CM7=1
CM6=0
CM5=0
CM4=0
CM3=0 CM8=∗
XIN oscillation (frequency/4)
XCIN oscillation
OCO oscillation or stop
φ =f(XIN)/4
CM7=1
CM6=0
CM5=0
CM4=1
CM3=0 CM8=∗
CM4
∗ : The OCO oscillating at “0”; the OCO stopped at “1”.
b7
Notes 1: Switch the mode by the arrows shown between the mode blocks.
The all modes can be switched to the stop mode or the wait mode.
2: Timer and LCD operate in the wait mode. System is returned to the
source mode when the wait mode is ended.
3: The CM4 value is retained in the stop mode. When the stop mode is
ended, the operation mode varies as follows:
In the QzROM version: Mode set by the OSCSEL pin state
In the flash memory version: On-chip oscillator mode
The input level applied to the OSCSEL pin is determined when
executing the STP instruction.
4: Before executing the STP instruction, set the values to generate the
wait time required for oscillation stabilization to timer 1 and timer 2,
and set to “0” (interrupts disabled) to the interrupt enable bits of
timer 1 and timer 2.
5: Execute the transition after the oscillation used in the destination
mode is stabilized.
6: When system goes to on-chip oscillator mode, the oscillation
stabilizing wait time is not needed.
7: The on-chip oscillator can be stopped in all kinds of state of
frequency/2,4 mode.
8: In all XIN mode, stop of on-chip oscillator is enabled.
9: The example assumes that 8 MHz is being applied to the X IN pin and
32 kHz to the XCIN pin. f(OCO) indicates the oscillation frequency of
on-chip oscillator.
10: When selecting the on-chip oscillator for the WDT clock, the on-chip
oscillator does not stop.
Also, in low-speed mode, the on-chip oscillator stops in the QzROM
version regardless of the on-chip oscillator stop bit value. The onchip oscillator does not stop in the flash memory version, so set this
bit to “1” to stop the oscillation.
In on-chip oscillator mode, even if this bit is set to “1”, the on-chip
oscillator oscillation does not stop in the flash memory version, but
stops in the QzROM version.
11: In low-speed mode, the X CIN-XCOUT oscillation stops if the port X C
switch bit is set to “0”.
12: In XIN mode, the XIN-XOUT oscillation does not stop even if the X INXOUT oscillation stop bit is set to “1”.
13: 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2
mode.
14: In the flash memory version, set the on-chip oscillator stop bit to “1”
(oscillation stops) because OCO is in the state set by the setting
value of the on-chip oscillator stop bit.
Fig. 63 State transitions of system clock
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 66 of 134
b0
CM8
CPU mode register 2
CPUM2
(address 001116,QzROM version, OSCSEL=L, initial value: 0016)
(
QzROM version, OSCSEL=H,initial value: 0116)
(
Flash memory version,
initial value: 0016)
On-chip oscillator stop bit
0 : Oscillating
1 : Stopped
Not used (do not write “1”)
Not used
(returns “0” when read)
Not used (do not write “1”)
b7
b0
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
CPU mode register
CPUM
(address 003B16, QzROM version, OSCSEL=L, initial value: E016)
(
QzROM version, OSCSEL=H, initial value: 4016)
(
Flash memory version,
initial value: E016)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Internal system clock selection bit
0 : Main clock selected
(includes OCO, XIN)
1 : XCIN–XCOUT selected
Port Xc switch bit (11)
0 : I/O port function (Oscillation stop)
1 : XCIN–XCOUT oscillating function
XIN–XOUT oscillation stop bit (12)
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(Valid only when CM3=0) (13)
b7 b8
0
0
1
1
0 : f(XIN)/2 (frequency/2 mode)
1 : f(XIN)/8 (frequency/8 mode)
0 : f(XIN)/4 (frequency/4 mode)
1 : On-chip oscillator
38D5 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be
rewritten while the microcomputer is mounted on-board by using
a serial programmer which is applicable for this microcomputer.
Table 15 lists the pin description (QzROM writing mode) and
Figure 64 and Figure 65 show the pin connections.
Refer to Figure 66 to Figure 69 for examples of a connection
with a serial programmer.
Contact the manufacturer of your serial programmer for serial
programmer. Refer to the user ’s manual of your serial
programmer for details on how to use it.
Table 15 Pin description (QzROM writing mode)
Pin
VCC, VSS
RESET
XIN
XOUT
VREF
AVSS
P00−P07
P10−P17
P20−P27
P33−P37
P40, P44−P47
P50−P57
P60−P67
P72−P74
P70, P71
OSCSEL
P41
P42
P43
Name
Power source
Reset input
Clock input
Clock output
Analog reference
voltage
Analog power source
I/O port
Input port
VPP input
ESDA input/output
ESCLK input
ESPGMB input
Rev.3.04 May 20, 2008
REJ03B0158-0304
I/O
Input
Input
Input
Output
Input
Function
• Apply 2.7 to 5.5 V to VCC, and 0 V to VSS.
• Reset input pin for active “L”. Reset occurs when RESET pin is
held at an “L” level for 16 cycles or more of XIN.
• Set the same termination as the single-chip mode.
• Input the reference voltage of A/D converter to VREF.
Input
I/O
• Connect AVss to Vss.
• Input “H” or “L” level signal or leave the pin open.
Input
Input
I/O
Input
Input
• Input “H” or “L” level signal or leave the pin open.
• QzROM programmable power source pin.
• Serial data I/O pin.
• Serial clock input pin.
• Read/program pulse input pin.
Page 67 of 134
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 68 of 134
Fig. 64 Pin connection diagram (M38D5XGXFP)
P7 3/PWM 0/T 3OUT
P7 2/T 2OUT /CKOUT
VL 3
VL 2
P7 1/C 2/INT 11
P7 0/C 1 /INT 01
VL 1
RESET
Vcc
PRQP0080GB-A(80P6N-A)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
73
9
72
8
7
6
5
4
3
2
1
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
ESPGMB
P43/SRDY1
P42/SCLK1
ESCLK
P41/TXD
ESDA
P40/RXD
AVSS
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P6 2 /INT 00/(LED 0)
OSCSEL
RESET
P6 1/X COUT
P6 0/X CIN
V SS
X IN
X OUT
V CC
P7 4/PWM 1 /T 4OUT
P5 1/AN 1/RTP 1
P5 0/AN 0/RTP 0
P6 7/CNTR 1/(LED 5)
P6 6/INT 10 /CNTR 0/(LED 4)
P6 5/T XOUT1/(LED 3)
P6 4/INT 2/(LED 2)
P6 3/T XOUT2/(LED 1)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P2 0/SEG 0/(KW 4)
P2 1/SEG 1/(KW 5)
P2 2/SEG 2 /(KW 6)
P2 3/SEG 3 /(KW 7)
P2 4/SEG 4
P2 5/SEG 5
P2 6/SEG 6
P2 7/SEG 7
P0 0/SEG 8
P0 1/SEG 9
P0 2/SEG 10
P0 3/SEG 11
P0 4/SEG 12
P0 5/SEG 13
P0 6/SEG 14
P0 7/SEG 15
P1 0/SEG 16
P1 1/SEG 17
P1 2/SEG 18
P1 3/SEG 19
P1 4/SEG 20
P1 5/SEG 21
P1 6/SEG 22
P1 7/SEG 23
38D5 Group
M38D5XGXFP
QzROM version
65
40
66
39
67
38
68
37
69
36
70
35
71
34
32
33
74
31
75
76
30
29
77
28
78
27
79
26
80
25
GND
: QzROM pin
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
*
VPP
* : Connect to oscillation circuit.
38D5 Group
41
42
43
45
44
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P2 2/SEG 2/(KW 6)
P2 3/SEG 3/(KW 7)
P2 4/SEG 4
P2 5/SEG 5
P2 6/SEG 6
P2 7/SEG 7
P0 0/SEG 8
P0 1/SEG 9
P0 2/SEG 10
P0 3/SEG 11
P0 4/SEG 12
P0 5/SEG 13
P0 6/SEG 14
P0 7/SEG 15
P1 0/SEG 16
P1 1/SEG 17
P1 2/SEG 18
P1 3/SEG 19
P1 4/SEG 20
P1 5/SEG 21
QzROM version
P21/SEG1/(KW5)
P20/SEG0/(KW4)
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
ESPGMB
P43/SRDY1
P42/SCLK1
ESCLK
P41/TXD
ESDA
P40/RXD
AVSS
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1/RTP1
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
P50/AN0/RTP0
M38D5XGXHP
70
71
31
30
72
29
73
28
74
27
75
26
20
19
18
17
16
P7 3/PWM 0/T 3OUT
P7 2 /T 2OUT/CKOUT
VL 3
VL 2
P7 1 /C 2/NT 11
15
14
13
12
11
10
9
8
P6 7/CNTR 1/(LED 5)
P6 6 /INT 10/CNTR 0/(LED 4)
P6 5/T XOUT1/(LED 3)
P6 4 /INT 2/(LED 2)
P6 3/T XOUT2/(LED 1)
P6 2/INT 00/(LED 0)
OSCSEL
RESET
P6 1/X COUT
P6 0/X CIN
V SS
X IN
X OUT
V CC
P7 4/PWM 1/T 4OUT
7
21
6
22
80
5
23
79
4
78
3
24
2
25
77
1
76
P16/SEG22
P17/SEG23
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
VL1
P70/C1/INT01
*
VPP
RESET
* : Connect to oscillation circuit.
GND
: QzROM pin
Vcc
PLQP0080KB-A(80P6Q-A)
Fig. 65 Pin connection diagram (M38D5XGXHP)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 69 of 134
38D5 Group
QzROM version
38D5 Group
Vcc
Vcc
OSCSEL
4.7 kΩ
4.7 kΩ
P41 (ESDA)
P42 (ESCLK)
P43 (ESPGMB)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESET
circuit
∗1
RESET
Vss
AVss
XIN
XOUT
Set the same termination as the
single-chip mode.
∗1 : Open-collector buffer
Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 66 When using E8 programmer, connection example (1) (OSCSEL = “L”)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 70 of 134
38D5 Group
QzROM version
38D5 Group
Vcc
VCC
*2
Jumper
switch
OSCSEL
4.7 kΩ
4.7 kΩ
P41 (ESDA)
P42 (ESCLK)
P43 (ESPGMB)
14
13
12
11
RESET
circuit
*1
10
9
8
7
RESET
6
5
Vss
4
3
2
1
AVss
XIN
XOUT
Set the same termination as the
single-chip mode.
*1 : Open-collector buffer
**2 : When programming 38D5 Group is performed, disconnect Vcc from OSCSEL by a jumper switch.
Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 67 When using E8 programmer, connection example (2) (OSCSEL = “H”)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 71 of 134
38D5 Group
QzROM version
38D5 Group
T_VDD
Vcc
T_VPP
OSCSEL
4.7kΩ
4.7kΩ
T_TXD
T_RXD
P41 (ESDA)
T_SCLK
P42 (ESCLK)
T_BUSY
N.C.
T_PGM/OE/MD
P43 (ESPGMB)
RESET circuit
RESET
T_RESET
GND
Vss
AVss
XIN
XOUT
Set the same termination as the
single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 68 When using programmer of Suisei Electronics System Co., LTD, connection example (1) (OSCSEL = “L”)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 72 of 134
38D5 Group
QzROM version
38D5 Group
T_VDD
Vcc
*1
Jumper
switch
T_VPP
OSCSEL
4.7kΩ
4.7kΩ
T_TXD
T_RXD
P41 (ESDA)
T_SCLK
P42 (ESCLK)
T_BUSY
N.C.
T_PGM/OE/MD
P43 (ESPGMB)
RESET circuit
RESET
T_RESET
GND
Vss
AVss XIN
XOUT
Set the same termination as the
single-chip mode.
*1 : When programming QzROM is performed, disconnect Vcc from OSCSEL by a jumper switch.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 69 When using programmer of Suisei Electronics System Co., LTD, connection example (2) (OSCSEL = “H”)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 73 of 134
38D5 Group
FLASH MEMORY MODE
The 38D5 Group flash memory version has the flash memory
that can be rewritten with a single power source.
For this flash memory, three flash memory modes are available
in which to read, program, and erase: the parallel I/O and
standard serial I/O modes in which the flash memory can be
manipulated using a programmer and the CPU rewrite mode in
which the flash memory can be manipulated by the Central
Processing Unit (CPU). For details of each mode, refer to the
next and after pages. Contact the manufacturer of your
programmer for the programmer. Refer to the user's manual of
your programmer for details on how to use it.
This flash memory version has some blocks on the flash memory
as shown in Figure 70 and each block can be erased.
In addition to the ordinary User ROM area to store the MCU
operation control program, the flash memory has a Boot ROM
area that is used to store a program to control rewriting in CPU
rewrite and standard serial I/O modes. This Boot ROM area has
had a standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application
system. This Boot ROM area can be rewritten in only parallel I/O
mode.
Performance overview
Table 16 lists the performance overview of the 38D5 Group flash
memory version.
Table 16 Performance overview of 38D5 Group flash memory version
Parameter
Power source voltage (Vcc)
Program/Erase VPP voltage (VPP)
Flash memory mode
Erase block division
User ROM area/Data ROM area
Boot ROM area (1)
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
ROM code protection
NOTE:
Function
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
3 modes; Parallel I/O mode, Standard serial I/O mode, CPU
rewrite mode
Refer to Figure 70.
Not divided (4K bytes)
In units of bytes
Block erase
Program/Erase control by software command
5 commands
100
Available in parallel I/O mode and standard serial I/O mode
1. The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory.
This Boot ROM area can be erased and written in only parallel I/O mode.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 74 of 134
38D5 Group
Boot Mode
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode
beforehand. (If the control program is written into the Boot ROM
area, the standard serial I/O mode becomes unusable.)
See Figure 70 for details about the Boot ROM area.
Normal microcomputer mode is entered when the
microcomputer is reset with pulling CNVSS pin low. In this case,
the CPU starts operating using the control program in the User
ROM area.
When the microcomputer is reset and the CNVSS pin high after
pulling the P41/TxD pin and CNVSS pin high, the CPU starts
operating (start address of program is stored into addresses
FFFC 16 and FFFD 16 ) using the control program in the Boot
ROM area. This mode is called the “Boot mode”. Also, User
ROM area can be rewritten using the control program in the Boot
ROM area.
CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central
Processing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure
70 can be rewritten; the Boot ROM area cannot be rewritten.
Make sure the program and block erase commands are issued for
only the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in
either User ROM or Boot ROM area. In the CPU rewrite mode,
because the flash memory cannot be read from the CPU, the
rewrite control program must be transferred to internal RAM
area before it can be executed.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
000016
User ROM area
SFR area
100016
004016
Internal RAM area
(2K bytes)
RAM
140016
Data block B:
1K bytes
Data block A:
1K bytes
180016
083F16
Block 1: 26K bytes
0FE016
SFR area
Notes1: The boot ROM area can be rewritten
in a parallel I/O mode. (Access to
except boot ROM area is disabled.)
2: To specify a block, use the maximum
address in the block.
3: The QzROM version has the reserved
ROM area. Note the difference of the
area.
800016
0FFF16
100016
Block 0: 32 K bytes
Internal flash memory area
(60K bytes)
F00016
Boot ROM area
4K bytes
FFFF16
FFFF16
Fig 70. Block diagram of built-in flash memory
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 75 of 134
FFFF16
38D5 Group
Outline Performance
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the
internal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM
area before it can be executed.
The MCU enters CPU rewrite mode by setting “1” to the CPU
rewrite mode select bit (bit 1 of address 0FE016). Then, software
commands can be accepted.
Use software commands to control program and erase
operations. Whether a program or erase operation has terminated
normally or in error can be verified by reading the status register.
Figure 71 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the
internal flash memory directly. Therefore, use the control
program in the internal RAM for write to bit 1. To set this bit 1 to
“1”, it is necessary to write “0” and then write “1” in succession
to bit 1. The bit can be set to “0” by only writing “0”.
Bit 2 of the flash memory control register 0 is the user block 1
E/W enable bit. By setting combination of bit 4 (user block 0
E/W enable bit) of the flash memory control register 2 (address
0FE216) and this bit as shown in Table 17, E/W is disabled to
user block in the CPU rewriting mode.
Bit 3 of the flash memory control register 0 is the flash memory
reset bit used to reset the control circuit of internal flash memory.
This bit is used when flash memory access has failed. When the
CPU rewrite mode select bit is “1”, setting “1” for this bit resets
the control circuit. To release the reset, it is necessary to set this
bit to “0”.
Bit 5 of the flash memory control register 0 is the User ROM
area select bit and is valid only in the boot mode. Setting this bit
to “1” in the boot mode switches an accessible area from the boot
ROM area to the user ROM area. To use the CPU rewrite mode
in the boot mode, set this bit to “1”. To rewrite bit 5, execute the
user original reprogramming control software transferred to the
internal RAM in advance.
Bit 6 of the flash memory control register 0 is the program status
flag. This bit is set to “1” when writing to flash memory is failed.
When program error occurs, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status
flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
Figure 72 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporary when block erase command
is executed can be used. In order to set this bit 0 to “1”, writing
“0” and “1” in succession to bit 0. In order to set this bit to “0”,
write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 76 of 134
b7
b0
Flash memory control register 0
(FMCR0: address : 0FE016, initial value: 0116)
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
CPU rewrite mode select bit(1)
0 : CPU rewrite mode invalid
1 : CPU rewrite mode valid
User block 1 E/W enable bit(1, 2)
0 : E/W disabled (180016-7FFF16)
1 : E/W enabled (180016-7FFF16)
Flash memory reset bit(3, 4)
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
User ROM area select bit(5)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: This bit can be written only when CPU rewrite mode select bit is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
bit to “0” when the CPU rewrite mode select bit is “0”.
4: When setting this bit to “1” (when the control circuit of flash memory
is reset), the flash memory cannot be accessed for 10 ms.
5: Write to this bit in program on RAM
Fig 71. Structure of flash memory control register 0
b7
b0
Flash memory control register 1
(FMCR1: address: 0FE116, initial value: 4016)
Erase Suspend enable bit(1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend request bit(2)
0 : Erase restart
1 : Suspend request
Not used (do not write “1” to this bit.)
Erase Suspend flag
0 : Erase active
1 : Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
Fig 72. Structure of flash memory control register 1
38D5 Group
b7
b0
Flash memory control register 2
(FMCR2: address : 0FE216, initial value: 4516)
Not used (return “1” when read)
Not used (do not write “1” to this bit.)
Not used (return “1” when read)
Not used (return “0” when read)
User block 0 E/W enable bit (1, 2)
0 : E/W disabled (800016-FFFF16)
1 : E/W enabled (800016-FFFF16)
Not used (return “0” when read)
Not used (return “1” when read)
Not used (return “0” when read)
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1”
to it in succession. For this bit to be set to “0”, write “0” only to this bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
Fig 73. Structure of flash memory control register 2
Table 17 State of E/W inhibition function
User block 0
E/W enable bit
0
0
1
1
User block 1
E/W enable bit
0
1
0
1
User block 0
Addresses 800016 to FFFF16
E/W disabled
E/W disabled
E/W enabled
E/W enabled
User block 1
Addresses 180016 to 7FFF16
E/W disabled
E/W enabled
E/W disabled
E/W enabled
Data block
Addresses 100016 to 17FF16
E/W enabled
E/W enabled
E/W enabled
E/W enabled
Figure 74 shows a flowchart for setting/releasing CPU rewrite mode.
Start
Single-chip mode or Boot mode
Set CPU mode register(1)
Transfer CPU rewrite mode control program to internal RAM
Jump to control program transferred to internal RAM
(Subsequent operations are executed by control program in
this RAM)
Set CPU rewrite mode select bit to “1” (by writing “0” and
then “1” in succession)
Set user block 0 E/W enable bit to “1” (by writing “0” and
then “1” in succession)
Set user block 1 E/W enable bit (At E/W disabled; writing
“0” , at E/W enabled;
writing “0” and then “1” in succession
Using software command executes erase, program, or other
operation
Execute read array command(2)
Set user block 0 E/W enable bit to “0”
Set user block 1 E/W enable bit to “0”
Write “0” to CPU rewrite mode select bit
End
Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16).
2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command.
Fig 74. CPU rewrite mode set/release flowchart be sure to execute
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 77 of 134
38D5 Group
<Notes on CPU Rewrite Mode>
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the main clock division ratio selection bits (bits 6 and
7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
(3) Interrupts
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
(4) Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
(5) Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVSS = “H”, so that the
program will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 78 of 134
38D5 Group
Software Commands
Table 18 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a
software command to specify an erase or program operation.
Each software command is explained below.
The RY/BY status flag is set to “0” during program operation
and “1” when the program operation is completed as is the status
register bit 7 (SR7).
At program end, program results can be checked by reading the
status register.
• Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D0 to D7).
The read array mode is retained until another command is
written.
• Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Start
Write “4016”
Write
Write address
Write data
Read status register
• Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = “1”?
or
RY/BY = “1”?
NO
YES
• Program Command (4016)
Program operation starts when the command code “40 16 ” is
written in the first bus cycle. Then, if the address and data to
program are written in the 2nd bus cycle, program operation
(data programming and verification) will start.
Whether the write operation is completed can be confirmed by
read status register or the RY/BY status flag. To read the status
register, write the read status register command “70 16 ”. The
status register bit 7 (SR7) is set to “0” at the same time the
program starts and returned to “1” upon completion of the
program. The read status mode remains active until the read
array command (“FF16”) is written.
NO
Program error
SR4 = “0”?
YES
Program completed
Fig 75. Program flowchart
Table 18 List of software commands (CPU rewrite mode)
Command
First bus cycle
Second bus cycle
cycle
number
Mode
Address
Data
(D0 to D7)
FF16
Read array
1
Write
X(4)
Read status register
2
Write
X
7016
Clear status register
1
Write
X
5016
Program
2
Write
X
4016
Block erase
2
Write
X
2016
NOTES:
1.
2.
3.
4.
SRD = Status Register Data
WA = Write Address, WD = Write Data
BA = Block Address to be erased (Input the maximum address of each block.)
X denotes a given address in the User ROM area.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 79 of 134
Mode
Address
Data
(D0 to D7)
Read
X
SRD(1)
Write
WA(2)
WD(2)
Write
BA(3)
D016
38D5 Group
• Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and
the confirmation command code “D016” and the block address in
the second bus cycle that follows, the block erase (erase and
erase verify) operation starts for the block address of the flash
memory to be specified.
Whether the block erase operation is completed can be confirmed
by read status register or the RY/BY status flag of flash memory
control register. To read the status register, write the status
register command “7016”. The status register bit 7 (SR7) is set to
“0” at the same time the block erase operation starts and returned
to “1” upon completion of the block erase operation. The read
status mode at this time remains active until the read array
command (“FF16”) is written.
The RY/BY status flag register is set to “0” during block erase
operation and “1” when the block erase operation is completed as
is the status register bit 7 (SR7).
After the block erase ends, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
Start
Write “2016”
Write “D016”
Block address
Read status register
SR7 = “1”?
or
RY/BY = “1”?
NO
YES
SR5 = “0”?
YES
Erase completed
(write read command
“FF16”)
Fig 76. Erase flowchart
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 80 of 134
NO
Erase error
38D5 Group
• Status Register
The status register shows the operating status of the flash
memory and whether erase operations and programs ended
successfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area
after writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in
the period from when the program starts or erase operation
starts to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 19 shows the status register. Each bit in this register is
explained below.
• Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase
operation and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
• Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is reset to “0”.
• Program status (SR4)
The program status indicates the operating status of write
operation.
When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the read array,
program, and block erase commands are not accepted. Before
executing these commands, execute the clear status register
command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
Table 19 Definition of each bit in status register
Each bit of
SRD bits
Status name
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 81 of 134
Definition
“1”
Ready
−
Terminated in error
Terminated in error
−
−
−
−
“0”
Busy
−
Terminated normally
Terminated normally
−
−
−
−
38D5 Group
Full Status Check
By performing full status check, it is possible to know the
execution results of erase and program operations. Figure 77
shows a full status check flowchart and the action to be taken
when each error occurs.
Read status register
SR4 = “1”
YES
Command
sequence error
and
SR5 = “1”?
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
NO
SR5 = “0”?
NO
Block erase error
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = “0”?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the read array, program,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig 77. Full status check flowchart and remedial procedure for errors
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 82 of 134
38D5 Group
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code
protect function for use in parallel I/O mode and an ID code
check function for use in standard serial I/O mode.
• ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control address (address FFDB 16 ) in
parallel I/O mode. Figure 78 shows the ROM code protect
control address (address FFDB16). (This address exists in the
User ROM area.)
If one or both of the pair of ROM code protect bits is set to “0”,
the ROM code protect is turned on, so that the contents of
internal flash memory are protected against readout and
modification. The ROM code protect is implemented in two
levels. If level 2 is selected, the flash memory is protected even
against readout by a shipment inspection LSI tester, etc. When an
attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be readout or modified. Once the ROM code
protect is turned on, the contents of the ROM code protect reset
bits cannot be modified in parallel I/O mode. Use standard serial
I/O mode or other modes to rewrite the contents of the ROM
code protect disable bits.
Rewriting of only the ROM code protect control address (address
FFDB16) cannot be performed. When rewriting the ROM code
protect reset bit, rewrite the whole user ROM area (block 0)
containing the ROM code protect control address.
b0
b7
1
1
ROM code protect control address (address FFDB16)
ROMCP (FF16 when shipped)
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2)(1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (ROMCR)(3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1)(1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level
1 and ROM code protect level 2.
However, no change can be made in parallel I/O mode. Use serial I/O mode or
other modes to change settings.
Fig 78. Structure of ROM code protect control address
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 83 of 134
38D5 Group
• ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the
programmer is compared with the ID code written in the flash
memory to see if they match. If the ID codes do not match, the
commands sent from the programmer are not accepted. The ID
code consists of 8-bit data, and its areas are FFD416 to FFDA16.
Write a program which has had the ID code preset at these
addresses to the flash memory.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM code protect control
Interrupt vector area
Fig 79. ID code store addresses
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 84 of 134
38D5 Group
Parallel I/O Mode
The parallel I/O mode is used to input/output software
commands, address and data in parallel for operation (read,
program and erase) to internal flash memory.
• User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown
in Figure 70 can be rewritten. Both areas of flash memory can be
operated on in the same way.
The Boot ROM area is 4 Kbytes in size and located at addresses
F00016 through FFFF 16 . Make sure program and block erase
operations are always performed within this address range.
(Access to any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to
only one 4 K byte block. The boot ROM area has had a standard
serial I/O mode control program stored in it when shipped from
the factory. Therefore, using the MCU in standard serial I/O
mode, do not rewrite to the Boot ROM area.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 85 of 134
38D5 Group
Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, program,
erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific
peripheral unit.
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the CNVSS pin
and “H” to the P4 1 (BOOTENT) pin, and releasing the reset
operation. (In the ordinary microcomputer mode, set CNVSS pin
to “L” level.) This control program is written in the Boot ROM
area when the product is shipped from Renesas. Accordingly,
make note of the fact that the standard serial I/O mode cannot be
used if the Boot ROM area is rewritten in parallel I/O mode. The
standard serial I/ O mode has standard serial I/O mode 1 of the
clock synchronous serial and standard serial I/O mode 2 of the
clock asynchronous serial. Tables 20 and 21 show description of
pin function (standard serial I/O mode). Figure 80 to 83 show the
pin connections for the standard serial I/O mode.
In standard serial I/O mode, only the User ROM area shown in
Figure 70 can be rewritten. The Boot ROM area cannot be
written.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, this function determines whether the
ID code sent from the peripheral unit (programmer) and those
written in the flash memory match. The commands sent from the
peripheral unit (programmer) are not accepted unless the ID code
matches.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 86 of 134
38D5 Group
Table 20 Description of pin function (Flash Memory Standard Serial I/O Mode 1)
Pin name
VCC,VSS
CNVSS
RESET
XIN
XOUT
AVSS
VREF
P00−P07, P10−P17,
P20−P27, P30−P37,
P40−P47, P50−P57,
P60−P67, P72−P74
P40
P41
P42
P43
Signal name
Power supply
CNVSS
Reset input
I/O
I
I
I
Function
Apply 2.7 to 5.5 V to the VCC pin and 0 V to the Vss pin.
After input of port is set, input “H” level.
Clock input
Clock output
Analog power supply input
Reference voltage input
I/O port
I
O
Reset input pin. To reset the microcomputer, RESET pin should be
held at an “L” level for 16 cycles or more of XIN.
Connect an oscillation circuit between the XIN and XOUT pins.
As for the connection method, refer to the “clock generating circuit”.
I
I/O
Connect AVss to VSS.
Apply reference voltage of A/D convertor to this pin.
Input “L” or “H” level, or keep open.
RxD input
TxD output
SCLK input
BUSY output
I
O
I
O
Serial data input pin.
Serial data output pin.
Serial clock input pin.
BUSY signal output pin.
Table 21 Description of pin function (Flash Memory Standard Serial I/O Mode 2)
Pin name
VCC,VSS
CNVSS
RESET
XIN
XOUT
AVSS
VREF
P00−P07, P10−P17,
P20−P27, P30−P37,
P40−P47, P50−P57,
P60−P67, P72−P74
P40
P41
P42
P43
Signal name
Power supply
CNVSS
Reset input
I/O
I
I
I
Clock input
Clock output
Analog power supply input
Reference voltage input
I/O port
I
O
Reset input pin. To reset the microcomputer, RESET pin should be
held at an “L” level for 16 cycles or more of XIN.
Connect an oscillation circuit between the XIN and XOUT pins.
As for the connection method, refer to the “clock generating circuit”.
I
I/O
Connect AVss to VSS.
Apply reference voltage of A/D convertor to this pin.
Input “L” or “H” level, or keep open.
RxD input
TxD output
SCLK input
BUSY output
I
O
I
O
Serial data input pin.
Serial data output pin.
Input “L” level.
BUSY signal output pin.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 87 of 134
Function
Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the VSS pin.
After input of port is set, input “H” level.
38D5 Group
P2 0 /SEG 0 /(KW 4)
P2 1 /SEG 1 /(KW 5)
P2 2 /SEG 2 /(KW 6)
P2 3 /SEG 3 /(KW 7)
P2 4/SEG 4
P2 5/SEG 5
P2 6/SEG 6
P2 7/SEG 7
P0 0/SEG 8
P0 1/SEG 9
P0 2/SEG 10
P0 3/SEG 11
P0 4/SEG 12
P0 5/SEG 13
P0 6/SEG 14
P0 7/SEG 15
P1 0/SEG 16
P1 1/SEG 17
P1 2/SEG 18
P1 3/SEG 19
P1 4/SEG 20
P1 5/SEG 21
P1 6/SEG 22
P1 7/SEG 23
Flash memory version
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
BUSY
SCLK
TXD
RXD
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
P43/SRDY1
P42/SCLK1
P41/TXD
P40/RXD
AVss
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
65
66
67
68
69
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
70
71
72
73
74
75
76
77
M38D59FFFP
M3822xMX-XXXFP
78
79
80
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
P5 1 /AN 1 /RTP 1
P5 0 /AN 0 /RTP 0
P6 7/CNTR 1/(LED 5 )
P6 6/INT 10/CNTR 0/(LED 4 )
P6 5/T XOUT1 /(LED 3 )
P6 4/INT 2 /(LED 2 )
P6 3/T XOUT2 /(LED 1 )
P6 2 /INT 00 /(LED 0 )
CNV SS
RESET
P6 1 /X COUT
P6 0 /X CIN
V SS
X IN
∗
X OUT
V CC
P7 4/PWM 1 /T 4OUT
P7 3/PWM 0 /T 3OUT
P7 2 /T 2OUT /CKOUT
VL3
VL2
P7 1 /C 2 /INT 11
P7 0 /C 1 /INT 01
VL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VPP
RESET
∗Connect oscillation circuit.
GND
indicates flash memory pin.
VCC
Package type: PRQP0080GB-A (80P6N-A)
Fig 80. Connection for standard serial I/O mode 1
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 88 of 134
38D5 Group
41
42
43
45
46
47
48
49
50
51
52
53
54
55
56
57
58
44
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
16
13
14
12
11
10
9
8
7
6
4
5
P16/SEG22
P17/SEG23
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM7/SEG32
COM6/SEG33
COM5/SEG34
COM4/SEG35
COM3
COM2
COM1
COM0
VL1
P70/C1/INT01
P6 7 /CNTR 1 /(LED 5 )
P6 6 /INT 10 /CNTR 0 /(LED 4)
P6 5 /T XOUT1 /(LED3)
P6 4 /INT 2 /(LED 2)
P6 3 /T XOUT2 /(LED 1 )
P6 2 /INT 00 /(LED 0 )
CNV SS
RESET
P6 1 /X COUT
P6 0 /X CIN
V SS
X IN
∗
X OUT
V CC
P7 4/PWM 1 /T 4OUT
P7 3/PWM 0 /T 3OUT
P7 2 /T 2OUT /CKOUT
V L3
V L2
P7 1 /C 2 /INT 11
1
M38D59FFHP
3
TXD
RXD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
2
BUSY
“L”INPUT
P21/SEG1/(KW5)
P20/SEG0/(KW4)
P47/SRDY2/(KW3)
P46/SCLK2/(KW2)
P45/SOUT2/(KW1)
P44/SIN2/(KW0)
P43/SRDY1
P42/SCLK1
P41/TXD
P40/RXD
AVss
VREF
P57/AN7/ADKEY0
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1/RTP1
P50/AN0/RTP0
59
60
P2 2 /SEG 2 /(KW 6 )
P2 3 /SEG 3 /(KW 7 )
P2 4 /SEG 4
P2 5 /SEG 5
P2 6 /SEG 6
P2 7 /SEG 7
P0 0 /SEG 8
P0 1 /SEG 9
P0 2 /SEG 10
P0 3 /SEG 11
P0 4 /SEG 12
P0 5 /SEG 13
P0 6 /SEG 14
P0 7 /SEG 15
P1 0 /SEG 16
P1 1 /SEG 17
P1 2 /SEG 18
P1 3 /SEG 19
P1 4 /SEG 20
P1 5 /SEG 21
Flash memory version
VPP
∗Connect oscillation circuit.
RESET
indicates flash memory pin.
GND
Vcc
Package type: PLQP0080KB-A (80P6Q-A)
Fig 81. Connection for standard serial I/O mode 2
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 89 of 134
38D5 Group
Flash memory version
38D5 Group
T_VDD
Vcc
T_VPP
N.C.
4.7 kΩ
T_RXD
P41 (TxD)
T_TXD
P40 (RxD)
T_SCLK
P42 (SCLK)
CNVSS
T_PGM/OE/MD
4.7 kΩ
T_BUSY
P43 (BUSY)
RESET circuit
RESET
T_RESET
GND
Vss
AVss
XIN
XOUT
Set the same termination as
the single-chip mode.
Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF.
Fig 82. When using programmer (in standard serial I/O mode 1) of Suisei Electronics System Co., LTD, connection
example
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 90 of 134
38D5 Group
Flash memory version
38D5 Group
Vcc
Vcc
CNVSS
4.7 kΩ
4.7 kΩ
4.7 kΩ
P41 (TxD)
P40 (RxD)
P42 (SCLK)
P43 (BUSY)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESET
circuit
∗1
RESET
Vss
AVss
XIN
XOUT
Set the same termination as
the single-chip mode.
∗ 1: Open-collector buffer
Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF.
Fig 83. When using E8 programmer (in standard serial I/O mode 1) connection example
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 91 of 134
38D5 Group
Flash memory version
td(CNVSS-RESET)
td(P41-RESET)
Power source
RESET
CNVSS
P41(TXD)
P42(SCLK)
P43(BUSY)
P40(RXD)
Symbol
Limits
Min.
Typ.
Max.
td(CNVSS-RESET)
0
-
-
td(P41-RESET)
0
Unit
ms
Note: In the standard serial I/O mode 1, input “H” to the P42 pin.
Be sure to set the CNVss pin to “H” before rising RESET.
Be sure to set the P41 pin to “H” before rising RESET.
ms
Fig 84. Operating waveform for standard serial I/O mode 1
Flash memory version
td(CNVSS-RESET)
td(P41-RESET)
Power source
RESET
CNVSS
P41(TXD)
P42(SCLK)
P43(BUSY)
P40(RXD)
Symbol
Limits
Min.
Typ.
Max.
td(CNVSS-RESET)
0
-
-
td(P41-RESET)
0
Unit
ms
Note: In the standard serial I/O mode 2, input “H” to the P42 pin.
Be sure to set the CNVss pin to “H” before rising RESET.
Be sure to set the P41 pin to “H” before rising RESET.
ms
Fig 85. Operating waveform for standard serial I/O mode 2
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 92 of 134
38D5 Group
NOTES ON USE
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”.
After a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on
calculations. Initialize these flags at beginning of the program.
Interrupt
The contents of the interrupt request bits do not change
immediately after they have been written. After writing to an
interrupt request register, execute at least one instruction before
performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After
executing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
The division ratio is 1/(n+1) when the value n (0 to 255) is
written to the timer latch.
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Direction Registers
The values of the port direction registers cannot be read. This
means, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS. It is also impossible to use bit
operation instructions such as CLB and SEB, and read-modifywrite instructions to direction registers, including calculations
such as ROR. To set the direction registers, use instructions such
as LDM or STA.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
A/D Converter
The comparator is constructed linked to a capacitor. The
conversion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at
least 500kHz during A/D conversion in the XIN mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by
the on-chip oscillator, the minimum value of f(XIN) frequency is
not limited.
LCD Drive Control Circuit
Execution of the STP instruction sets the LCD enable bit (bit 4 of
the LCD mode register) to “0” and the LCD panel turns off. To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the
frequency of the internal clock φ by the number of cycles needed
to execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less
than the recommended operating conditions and design a system
not to cause errors to the system by this unstable operation.
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (Vss pin), and between power
source pin (V CC pin) and analog power source pin (AV CC ).
Besides, connect the capacitor to as close as possible. For bypass
capacitor which should not be located too far from the pins to be
connected, a ceramic capacitor of 0.1 µF is recommended.
LCD drive power supply
Power supply capacitor may be insufficient with the division
resistance for LCD power supply, and the characteristic of the
LCD panel. In this case, there is the method of connecting the
bypass capacitor about 0.1 − 0.33 µ F to V L1 − V L3 pins. The
example of a strengthening measure of the LCD drive power
supply is shown below.
VL3
VL2
• Connect by the shortest
possible wiring.
• Connect the bypass capacitor
to the VL1 −VL3 pins as short
as possible.
(Referential value:0.1−0.33 µF)
VL1
Fig. 86 Strengthening measure example of LCD drive
power supply
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 93 of 134
38D5 Group
NOTES ON QzROM VERSION
Wiring to OSCSEL pin
1. OSCSEL = L
Connect the OSCSEL pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series
to the GND could improve noise immunity. In this case as well
as the above mention, connect the pin the shortest possible to
the GND pattern which is supplied to the V SS pin of the
microcomputer.
2. OSCSEL = H
Connect the OSCSEL pin the shortest possible to the V CC
pattern which is supplied to the VCC pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series
to the VCC could improve noise immunity. In this case as well
as the above mention, connect the pin the shortest possible to
the V CC pattern which is supplied to the V CC pin of the
microcomputer.
• Reason
The OSCSEL pin is the power source input pin for the built-in
QzROM.
When programming in the QzROM, the impedance of the
OSCSEL pin is low to allow the electric current for writing to
flow into the built-in QzROM. Because of this, noise can enter
easily. If noise enters the OSCSEL pin, abnormal instruction
codes or data are read from the QzROM, which may cause a
program runaway.
Termination of OSCSEL pin
(2) OSCSEL = H
(1) OSCSEL = L
(1)
(1)
The shortest
The shortest
VCC
OSCSEL
about 5 kΩ
about 5 kΩ
OSCSEL
VSS
(1)
The shortest
(1)
Product shipped in blank
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approximate
0.1% may occur.
Moreover, please note the contact of cables and foreign bodies on
a socket, etc. because a writing environment may cause some
writing errors.
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .msk) which is made by the
mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “00 16 ”, “FE 16 ” and “FF 16 ” can not be
accepted.
• Set “FF16” to the ROM code protect address in ROM data
regardless of the presence or absence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
Data Required For QzROM Writing Orders
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
The shortest
QzROM Receive Flow
When writing to QzROM is performed by user side, the
receiving inspection by the following flow is necessary.
Note 1: It shows the microcomputer’s pin
Fig. 87 Wiring for the OSCSEL pin
Precautions Regarding Overvoltage in QzROM Version
Make sure that voltage exceeding the VCC pin voltage is not
applied to other pins. In particular, ensure that the state indicated
by bold lines in figure below does not occur for OSCSEL pin
(VPP power source pin for QzROM) during power-on or poweroff. Otherwise the contents of QzROM could be rewritten.
QzROM product shipped after writing
Renesas
Renesas
Programming
Shipping
Verify test
Shipping
∼
∼
1.8V
(1)
QzROM product shipped in blank
“protect disabled”
“protect enabled to the protect area 1”
User
Receiving inspection
(Blank check)
User
(2)
1.8V
Receiving inspection of
unprotected area (Verify test)
Programming
Programming to unprotected area
Verify test for all area
VCC pin voltage
∼
∼
OSCSEL pin voltage
“H” input
∼
∼
OSCSEL pin voltage
“L” input
(1) Input voltage to other MCU pins rises before VCC pin voltage.
(2) Input voltage to other MCU pins falls after VCC pin voltage.
Note: The internal circuitry is unstable when VCC is below the minimum
voltage specification of 1.8 V (shaded portion), so particular care should
be exercised regarding overvoltage.
Fig. 88 Example of Overvoltage
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 94 of 134
Verify test for unprotected area
Fig. 89 QzROM receive flow
38D5 Group
NOTES ON FLASH MEMORY VERSION
CPU Rewrite Mode
(1) Operation speed
During CPU rewrite mode, set the system clock φ 4.0 MHz or
less using the main clock division ratio selection bits (bits 6 and
7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during the CPU rewrite mode.
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode
because they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the
internal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is
released, boot mode is active. So the program starts from the
address contained in address FFFC16 and FFFD16 in boot ROM
area.
CNVSS Pin
The CNVSS pin determines the flash memory mode.
Connect the CNVSS /VPP pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ. resistor in series
to the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the V S S pin of the
microcomputer.
Note. When the boot mode or the standard serial I/O mode is used, a
switch of the input level to the CNVSS pin is required.
The shortest
(1)
CNVSS
Approx. 5kΩ
VSS
(1)
The shortest
Note 1: Shows the microcomputer’s pin.
Fig 90. Wiring for the CNVSS
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 95 of 134
NOTES ON DIFFERENCES BETWEEN QzROM
VERSION AND FLASH MEMORY VERSION
The QzROM and flash memory versions differ in their
manufacturing processes, built-in ROM, and layout patterns.
Because of these differences, characteristic values, operation
margins, noise immunity, and noise radiation and oscillation
circuit constants may vary within the specified range of electrical
characteristics.
When switching to the QzROM version, implement system
evaluations equivalent to those performed in the flash memory
version.
Confirm page 11 about the differences of functions.
38D5 Group
Countermeasures against noise
Noise
(1) Shortest wiring length
1. Wiring for RESET pin
Make the length of wiring which is connected to the RESET
pin as short as possible. Especially, connect a capacitor across
the RESET pin and the V SS pin with the shortest possible
wiring (within 20 mm).
• Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is
completely initialized. This may cause a program runaway.
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 92 Wiring for clock I/O pins
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
(2) Connection of bypass capacitor across VSS line and VCC
line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
RESET
VSS
VCC
VCC
VSS
VSS
O.K.
Fig. 91 Wiring for the RESET pin
2. Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O
pins as short as possible.
• Make the length of wiring (within 20 mm) across the
grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as
possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
• Reason
If noise enters clock I/O pins, clock waveforms may be
deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 96 of 134
N.G.
O.K.
Fig. 93 Bypass capacitor across the VSS line and the VCC
line
38D5 Group
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user
system and its condition, contact the oscillator manufacturer and
select the oscillator and oscillation circuit constants. Be careful
especially when range of voltage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
1. Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the
tolerance of current value flows.
• Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise
occurs because of mutual inductance.
2. Installing oscillator away from signal lines where potential
levels change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change
frequently. Also, do not cross such signal lines over the clock
lines or the signal lines which are sensitive to noise.
• Reason
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
1. Keeping oscillator away from large current signal lines
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
2. Installing oscillator away from signal lines where potential
levels change frequently
Do not cross.
CNTR
XIN
XOUT
VSS
N.G.
Fig. 94 Wiring for a large current signal line/Wiring of
signal lines where potential levels change
frequently
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 97 of 134
(4) Analog input
The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be
obtained by the charge/discharge current at the time of A/D
conversion when the analog signal source of high-impedance is
connected to an analog input pin. In order to obtain the A/D
conversion result stabilized more, please lower the impedance of
an analog signal source, or add the smoothing capacitor to an
analog input pin.
(5) Difference of memory size
When memory size differ in one group, actual values such as an
electrical characteristics, A/D conversion accuracy, and the
amount of proof of noise incorrect operation may differ from the
ideal values.
When these products are used switching, perform system
evaluation for each product of every after confirming product
specification.
38D5 Group
QzROM VERSION
QzROM VERSION ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 22 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
P00−P07, P10−P17, P20−P27, P30−P37
P40−P47, P50−P57, P60−P67, P70−P74
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage
Input voltage
Output voltage
Output voltage
Conditions
All voltages are
based on VSS.
When an input
voltage is
measured, output
transistors are cut
off.
RESET, XIN
OSCSEL
C1, C2
P00−P07, P10−P17, P20−P27, P30−P37 At output port
At segment output
Output voltage P40−P47, P50−P57, P60−P67, P72−P74
Output voltage VL3
All voltages are
Output voltage VL2, SEG32−SEG35, COM0−COM3 based on VSS.
Output voltage XOUT
Power dissipation
Ta = 25°C
Operating temperature
Storage temperature
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 98 of 134
Ratings
−0.3 to 6.5
−0.3 to VCC+0.3
Unit
V
V
−0.3 to VL2
VL1 to VL3
VL2 to 6.5
−0.3 to 6.5
−0.3 to VCC+0.3
V
V
V
V
V
−0.3 to 8.0
−0.3 to 6.5
−0.3 to VCC+0.3
−0.3 to VL3+0.3
−0.3 to VCC+0.3
−0.3 to 6.5
−0.3 to VL3+0.3
−0.3 to VCC+0.3
300
−20 to 85
−40 to 125
V
V
V
V
V
V
V
V
mW
°C
°C
38D5 Group
QzROM VERSION
Recommended Operating Conditions
Table 23 Recommended operating conditions (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C unless otherwise noted)
Symbol
VCC
Limits
Parameter
Power source
voltage (1)
Frequency/2 mode (2)
Frequency/4 mode
Min.
Typ.
Max.
Unit
f(XIN) ≤ 12.5MHz
4.5
5.5
V
f(XIN) ≤ 8MHz
4.0
5.5
V
f(XIN) ≤ 4MHz
2.0
5.5
V
f(XIN) ≤ 2MHz
1.8
5.5
V
f(XIN) ≤ 16MHz
4.5
5.5
V
f(XIN) ≤ 8MHz
2.0
5.5
V
V
f(XIN) ≤ 4MHz
1.8
5.5
f(XIN) ≤ 16MHz
4.5
5.5
V
f(XIN) ≤ 8MHz
2.0
5.5
V
f(XIN) ≤ 4MHz
1.8
5.5
V
1.8
5.5
V
On-chip oscillator mode
1.8
5.5
V
When start oscillating (3)
0.05 × f + 1.9
Frequency/8 mode
Low-speed mode
VSS
Power source voltage
VLI
VL1 input voltage
V
0
Voltage multiplier is used
1.3
V
1.8
2.0
2.1
V
VCC
V
VCC
V
VREF
A/D converter reference voltage
AVSS
Analog power source voltage
VIA
Analog input voltage AN0−AN7
VIH
“H” input voltage P00−P07, P10−P17, P24−P27, P30−P37, P41, P43,
P50−P57, P60(CM4=0), P61, P65, P72−P74
0.7VCC
VCC
V
VIH
“H” input voltage P20−P23, P40, P42, P44−47, P62−P64, P66, P67,
P70, P71
0.8VCC
VCC
V
VIH
“H” input voltage RESET
2.2V < VCC ≤ 5.5V
0.8VCC
VCC
V
VCC ≤ 2.2V
65 × VCC - 99
VCC
V
0
V
AVSS
VCC -
100
VIH
“H” input voltage XIN
VCC
V
VIL
“L” input voltage P00−P07, P10−P17, P24−P27, P30−P37, P41, P43,
P50−P57, P60, P61, P65, P72−P74
0.8VCC
0
0.3VCC
V
VIL
“L” input voltage P20−P23, P40, P42, P44−P47, P62−P64, P66, P67,
P70, P71, OSCSEL
0
0.2VCC
V
VIL
“L” input voltage RESET
2.2V < VCC ≤ 5.5V
0
0.2VCC
V
VCC ≤ 2.2V
0
65 × VCC − 99
V
100
VIL
0
“L” input voltage XIN
0.2VCC
V
NOTES:
1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
2. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
3. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and
operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency
oscillator.
f: Oscillation frequency (1 MHz ≤ f(XIN) ≤ 8 MHz) of oscillator. When the 8 MHz oscillation is used, assign “8” to “f”.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 99 of 134
38D5 Group
QzROM VERSION
Table 24
Recommended operating conditions (2)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Parameter
Min.
Limits
Typ.
Max.
−40
Unit
ΣIOH(peak)
“H” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
ΣIOH(peak)
“H” total peak output current (1)
P40−47, P50−P57, P60−P67
−40
mA
ΣIOL(peak)
“L” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
40
mA
ΣIOL(peak)
“L” total peak output current (1)
P40−P47, P50−P57, P60, P61
40
mA
ΣIOL(peak)
“L” total peak output current (1)
P62−P67
110
mA
ΣIOH(avg)
“H” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
−20
mA
ΣIOH(avg)
“H” total average output current (1)
P40−P47, P50−P57, P60−P67
−20
mA
ΣIOL(avg)
“L” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
20
mA
ΣIOL(avg)
“L” total average output current (1)
P40−P47, P50−P57, P60, P61
20
mA
ΣIOL(avg)
“L” total average output current (1)
P62−P67
90
mA
IOH(peak)
“H” peak output current (2)
P00−P07, P10−P17, P20−P27, P30−P37
−2
mA
IOH(peak)
“H” peak output current (2)
P40−P47, P50−P57, P60−P67, P72−P74
−5
mA
IOL(peak)
“L” peak output current (2)
P00−P07, P10−P17, P20−P27, P30−P37
5
mA
IOL(peak)
“L” peak output current (2)
P40−P47, P50−P57, P60, P61, P72−P74
10
mA
IOL(peak)
“L” peak output current (2)
P62−P67
30
mA
IOH(avg)
“H” average output current (3)
P00−P07, P10−P17, P20−P27, P30−P37
−1.0
mA
IOH(avg)
“H” average output current (3)
P40−P47, P50−P57, P60−P67, P72−P74
−2.5
mA
IOL(avg)
“L” average output current (3)
P00−P07, P10−P17, P20−P27, P30−P37
2.5
mA
IOL(avg)
“L” average output current (3)
P40−P47, P50−P57, P60, P61, P72−P74
5.0
mA
IOL(avg)
“L” average output current (3)
P62−P67
15
mA
mA
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2. The peak output current is the peak current flowing in each port.
3. The average output current is average value measured over 100 ms.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 100 of 134
38D5 Group
QzROM VERSION
Table 25 Recommended operating conditions (3)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
f(CNTR0)
f(CNTR1)
Parameter
Conditions
Timer X and Timer Y
Input frequency (duty cycle 50%)
Limits
Min.
Typ.
4.5 ≤ VCC ≤ 5.5V
6.25
MHz
4.0 ≤ VCC < 4.5V
2 × Vcc −4
MHz
2.0 ≤ VCC < 4.0V
Vcc
MHz
5 × Vcc −8
MHz
4.5 ≤ VCC ≤ 5.5V
16
MHz
4.0 ≤ VCC < 4.5V
4 × Vcc −8
MHz
2.0 ≤ VCC < 4.0V
2 × Vcc
MHz
VCC < 2.0V
f(Tclk)
Timer X, Timer Y,
Timer 1, Timer 2,
Timer 3, Timer 4 clock input frequency
(Count source frequency of each timer)
f(φ)
VCC < 2.0V
10 × Vcc −16
MHz
6.25
MHz
4.0 ≤ VCC < 4.5V
4
MHz
2.0 ≤ VCC < 4.0V
Vcc
MHz
5 × Vcc −8
MHz
4.5 ≤ VCC ≤ 5.5V
System clock φ frequency (1)
VCC < 2.0V
f(XIN)
Main clock input frequency
(duty cycle 50%) (2)(3)
f(XCIN)
Unit
Max.
4.5 ≤ VCC ≤ 5.5V
1.0
16
MHz
2.0 ≤ VCC < 4.5V
1.0
8.0
MHz
VCC < 2.0V
1.0
20 × Vcc −32
MHz
80
kHz
Sub-clock oscillation frequency
(duty cycle 50%)(4)(5)
32.768
NOTES:
Relationship between system clock φ frequency and power source voltage is shown in the graph below.
When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and
operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency
oscillator.
5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
1.
2.
3.
4.
<System clock φ frequency>
<Main clock XIN frequency>
[MHz]
16
Main clock X IN frequency
System clock φ frequency
[MHz]
6.25
4.0
2.0
8.0
4.0
1.0
1.0
0
1.8 2.0
4.0 4.5
5.5 [V]
Power source voltage
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 101 of 134
0
1.8 2.0
4.5
Power source voltage
5.5 [V]
38D5 Group
QzROM VERSION
Electrical Characteristics
Table 26
Electrical characteristics (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VOL
VOL
Parameter
“H” output voltage
P00−P07, P10−P17, P20−P27,
P30−P37
Test conditions
Limits
Min.
IOH= −2.5mA
VCC−2.0
IOH= −0.6mA
VCC=2.5V
VCC−1.0
Typ.
Max.
V
“H” output voltage
P40−P47, P50−P57, P60−P67,
P72−P74 (1)
IOH= −5mA
VCC−2.0
IOH= −1.25mA
VCC−0.5
IOH= −1.25mA
VCC=2.5V
VCC−1.0
“L” output voltage
P00−P07, P10−P17, P20−P27,
P30−P37
IOL=5mA
2.0
IOL=1.25mA
0.5
IOL=1.25mA
VCC=2.5V
1.0
“L” output voltage
P40−P47, P50−P57, P60, P61
P72−P74 (1)
IOL=10mA
2.0
IOL=2.5mA
0.5
IOL=2.5mA
VCC=2.5V
1.0
IOL=15mA
2.0
IOL=3.0mA
VCC=2.5V
0.8
“L” output voltage
P62−P67
Unit
V
V
V
V
VT+ − VT-
Hysteresis
INT00, INT01, INT10, INT11, INT2,
CNTR0, CNTR1, KW0−KW7
0.5
V
VT+ − VT-
Hysteresis
SIN2, SCLK1, SCLK2, RXD
0.5
V
VT+ − VT-
Hysteresis
RESET
VCC = 2.0 V to 5.5 V
on RESET
0.5
V
IIH
“H” input current
P00−P07, P10−P17, P20−P27,
P30−P37
VI=VCC
5.0
µA
IIH
“H” input current
P40−P47, P50−P57,
P60−P67, P70−P74
VI=VCC
5.0
µA
IIH
“H” input current
RESET, OSCSEL
VI=VCC
5.0
µA
IIH
“H” input current
XIN
VI=VCC
IIL
“L” input current
P00−P07, P10−P17, P20−P27,
P30−P37
VCC=5V, VI=VSS Pull-up “ON”
“L” input current
P40−P47, P50−P57
P60−P67, P72−P74
VCC=5V, VI=VSS Pull-up “ON”
IIL
VI=VSS Pull-up “OFF”
VCC=3V, VI=VSS Pull-up “ON”
−60
−25
−120
−50
−30
−6.5
−70
−25
VI=VSS Pull-up “OFF”
VCC=3V, VI=VSS Pull-up “ON”
IIL
“L” input current
RESET, OSCSEL
VI=VSS
IIL
“L” input current
XIN
VI=VSS
f(OCO)
On-chip oscillator frequency
VCC=5V, Ta =25°C
µA
4.0
−5.0
−240
−100
−5.0
−140
−45
−5.0
−4.0
2500
5000
µA
µA
µA
µA
µA
µA
µA
µA
7500
kHz
NOTE:
1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is “1”, the drivability of P61 is different from the above.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 102 of 134
38D5 Group
QzROM VERSION
Table 27 Electrical characteristics (2)
(Vcc = 1.8 to 5.5 V, Ta = −20 to 85°C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D converter
stopped, unless otherwise noted)
Symbol
Parameter
Limits
Test conditions
VRAM
RAM hold voltage
When clock is stopped
ICC
Power source current
Frequency/2 mode
VCC=5V
VCC=2.5V
Frequency/8 mode
VCC=5.0V
VCC=2.5V
Low-speed mode
VCC=5.0V
VCC=2.5V
On-chip oscillator mode
f(XIN), f(XCIN) = stop
All oscillations stopped
(in STP state)
Current increased
at A/D converter operating
Typ.
Max.
1.8
VCC=5V
VCC=2.5V
Frequency/4 mode
Min.
Unit
5.5
V
f(XIN)=12.5MHz
6.4
13
mA
f(XIN)=12.5MHz (in WIT
state)
1.5
3.0
mA
mA
f(XIN)=4MHz
2.2
3.0
f(XIN)=4MHz
0.6
1.2
mA
f(XIN)=4MHz (in WIT state)
0.3
0.6
mA
f(XIN)=2MHz
0.4
0.8
mA
f(XIN)=12.5MHz
3.5
10
mA
f(XIN)=12.5MHz (in WIT
state)
1.5
3
mA
mA
f(XIN)=4MHz
1.5
2.5
f(XIN)=8MHz
0.8
2.5
mA
f(XIN)=8MHz (in WIT state)
0.3
0.6
mA
f(XIN)=4MHz
0.5
1.0
mA
f(XIN)=12.5MHz
2.5
5.0
mA
f(XIN)=12.5MHz (in WIT
state)
1.5
3.0
mA
mA
f(XIN)=4MHz
1.2
1.6
f(XIN)=8MHz
0.5
1.0
mA
f(XIN)=8MHz (in WIT state)
0.3
0.6
mA
f(XIN)=4MHz
0.3
0.6
mA
f(XIN)=stop
17
26
in WIT state
5.5
11
f(XIN)=stop
7.0
14
in WIT state
3.5
7.0
540
VCC=5V
270
VCC=2.5V
35
90
VCC=2.5V (in WIT state)
25
75
µA
µA
µA
µA
µA
µA
µA
Ta=25°C
0.1
1.0
µA
10
µA
Ta=85°C
f(XIN)=12.5 MHz, VCC=5 V
in frequency/2, 4 or 8 mode
0.5
mA
f(XIN)= stop, VCC = 5 V
in on-chip oscillator operating
0.5
mA
f(XIN) = stop, VCC = 5 V
in low-speed mode
0.4
mA
A/D Converter Characteristics
Table 28 A/D converter recommended operating condition
(Vcc = 2.0 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
VIH
“H” input voltage ADKEY0
VIL
“L” input voltage ADKEY0
f(φAD)
(1)
AD converter clock frequency
(Low-speed • on-chip oscillator mode excluded)
Test conditions
2.0
5.0
Max.
Unit
5.5
V
0.9VCC
VCC
V
0
0.7 × VCC−0.5
V
4.5V < VCC ≤ 5.5V
6.25
MHz
4.0
MHz
2.0V < VCC ≤ 4.0V
VCC
MHz
1. Confirm the recommended operating condition for main clock input frequency.
Page 103 of 134
Typ.
4.0V < VCC ≤ 4.5V
NOTE:
Rev.3.04 May 20, 2008
REJ03B0158-0304
Limits
Min.
38D5 Group
QzROM VERSION
Table 29 A/D converter characteristics
(Vcc = 2.0 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, low-speed • on-chip oscillator mode
included, unless otherwise noted)
Symbol
−
ABS
Parameter
Limits
Test conditions
Min.
Typ.
Max.
Unit
Resolution
10
Bits
Absolute accuracy 10bitAD 4.5V < VCC ≤ 5.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ 6.25MHz
(quantification error mode
excluded)
4.0V < VCC ≤ 4.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ 4MHz
4
LSB
2.2V ≤ VCC ≤ 4.0V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ VccMHz
2.0V ≤ VCC ≤ 5.5V,
AD conversion clock=f(OCO)/8, f(OCO)/32
4.5V < VCC ≤ 5.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ 6.25MHz
8bitAD
mode
2
4.0V < VCC ≤ 4.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ 4MHz
2.2V < VCC ≤ 4.0V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ VccMHz
2.0V ≤ VCC ≤ 2.2V,
AD conversion clock=f(XIN)/2, f(XIN)/8 ≤ (6Vcc−11)MHz
2.0V ≤ VCC ≤ 2.2V,
AD conversion clock=f(XIN)/8 ≤ VccMHz
2.0V ≤ VCC ≤ 5.5V,
AD conversion clock=f(OCO)/8, f(OCO)/32
tCONV
Conversion time(1)
10bitAD mode
tc(φAD)×61
tc(φAD)×62
8bitAD mode
tc(φAD)×49
tc(φAD)×50
RLADDER Ladder resistor
IVREF
Reference input
current
VREF=5.0V
IIA
Analog input current
µs
12
35
100
50
150
200
kΩ
µA
5.0
µA
NOTES:
1. tc(φAD): one cycle of AD conversion clock. AD conversion clock can be selected from φSOURCE/2 or φSOURCE/8. φSOURCE
represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or
the low-speed mode.
When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) ≥ 500 kHz.
Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.
AD conversion clock frequency
10bitAD=4LSB
8bitAD=2LSB
[MHz]
6.25
AD conversion clock
•frequency/2 mode,
frequency/4 and
frequency/8 mode:
f(XIN)/2 or
f(XIN)/8
4.0
f(XIN)/8
8bitAD=2LSB
2.2
2.0
f(XIN)/2 or f(XIN)/8
10bitAD=4LSB
8bitAD=2LSB
f(XIN)/2 or f(XIN)/8
8bitAD=2LSB
1.0
(Note)
0
1.8 2.0 2.2
4.0 4.5
Power source voltage V CC
Note: f(XIN) ≥ 500kHz
Rev.3.04 May 20, 2008
REJ03B0158-0304
AD conversion clock
•Low-speed mode and
on-chip oscillator mode:
f(OCO)/8 or
f(OCO)/32
Page 104 of 134
5.5 [V]
38D5 Group
QzROM VERSION
Timing Requirements And Switching Characteristics
Table 30 Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
tW(RESET)
Reset input “L” pulse width
tC(XIN)
Main clock input cycle time
tWH(XIN)
Main clock input “H” pulse
width
tWL(XIN)
Main clock input “L” pulse
width
Min.
Typ.
Max.
Unit
4.5V ≤ VCC ≤ 5.5V (1)
62.5
µs
ns
4.0V ≤ VCC < 4.5V
125
ns
25
ns
4.0V ≤ VCC < 4.5V
50
ns
4.5V ≤ VCC ≤ 5.5V (2)
25
ns
4.0V ≤ VCC < 4.5V
50
ns
2
4.5V ≤ VCC ≤ 5.5V
(2)
tC(CNTR)
CNTR0, CNTR1 input cycle time
250
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
105
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
105
ns
tWH(INT)
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
80
ns
tWL(INT)
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
80
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (3)
800
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (3)
370
ns
tWL(SCLK1)
(3)
370
ns
tsu(RXD-SCLK1) Serial I/O1 input setup time
220
ns
th(SCLK1-RXD)
Serial I/O1 input hold time
100
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
1000
ns
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
400
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
400
ns
tsu(SIN2-SCLK2) Serial I/O2 input setup time
200
ns
th(SCLK2-SIN2)
200
ns
Serial I/O1 clock input “L” pulse width
Serial I/O2 input hold time
NOTES:
1. 80 ns in the frequency/2 mode.
2. 32 ns in the frequency/2 mode.
3. When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 105 of 134
38D5 Group
QzROM VERSION
Table 31 Timing requirements (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Max.
Unit
µs
ns
VCC < 2.0V
2.0V ≤ VCC < 4.0V
VCC < 2.0V
Main clock input “L” pulse width 2.0V ≤ VCC < 4.0V
VCC < 2.0V
CNTR0, CNTR1 input cycle time 2.0V ≤ VCC < 4.0V
VCC < 2.0V
166
ns
50
ns
Main clock input cycle time
(XIN input)
tC(CNTR)
Typ.
125
Reset input “L” pulse width
tWL(XIN)
Min.
2.0V ≤ VCC < 4.0V
tW(RESET)
tC(XIN)
tWH(XIN)
Limits
Parameter
2
Main clock input “H” pulse width
70
ns
50
ns
70
ns
1000/VCC
ns
1000/(5 × VCC-8)
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
tc(CNTR)/2-20
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
tc(CNTR)/2-20
ns
tWH(INT)
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
230
ns
tWL(INT)
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
230
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (1)
2000
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (1)
950
ns
tWL(SCLK1)
(1)
950
ns
tsu(RXD-SCLK1) Serial I/O1 input setup time
400
ns
th(SCLK1-RXD)
Serial I/O1 input hold time
200
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
2000
ns
Serial I/O1 clock input “L” pulse width
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
950
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
950
ns
tsu(SIN2-SCLK2) Serial I/O2 input setup time
400
ns
th(SCLK2-SIN2)
200
ns
Serial I/O2 input hold time
NOTE:
1. When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 106 of 134
38D5 Group
QzROM VERSION
Table 32 Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2-30
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2-30
td(SCLK1-TxD)
Serial I/O1 output delay time (1)
tv(SCLK1-TxD)
Serial I/O1 output valid time (1)
tr(SCLK1)
Serial I/O1 clock output rising time
Max.
Unit
ns
ns
140
ns
30
ns
30
ns
−30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2-30
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2-30
tf(SCLK2)
Serial I/O2 clock output falling time
td(SCLK2-SOUT2)
Serial I/O2 output delay time
tv(SCLK2-SOUT2)
Serial I/O2 output valid time
ns
ns
40
140
−30
ns
ns
ns
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
Table 33 Switching characteristics (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ
tWH(SCLK1)
Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2-80
tWL(SCLK1)
Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2-80
td(SCLK1-TxD)
Serial I/O1 output delay time
tv(SCLK1-TxD)
Serial I/O1 output valid time (1)
tr(SCLK1)
Serial I/O1 clock output rising time
Max.
ns
ns
(1)
350
ns
80
ns
80
ns
-30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
tWH(SCLK2)
Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2-80
tWL(SCLK2)
Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2-80
tf(SCLK2)
Serial I/O2 clock output falling time
td(SCLK2-SOUT2)
Serial I/O2 output delay time
tv(SCLK2-SOUT2)
Serial I/O2 output valid time
ns
ns
80
350
-30
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
1kΩ
Measurement output pin
100pF
CMOS output
100pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1.”
(N-channel open-drain output mode)
Fig 95. Circuit for measuring output switching characteristics
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 107 of 134
ns
ns
ns
NOTE:
Measurement output pin
Unit
38D5 Group
QzROM VERSION
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0, CNTR1
0.8VCC
0.2VCC
tWH(INT)
INT00, INT01
INT10, INT11
INT2
tWL(INT)
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK1), tC(SCLK2)
SCLK1
SCLK2
tf
tWL(SCLK1), tWL(SCLK2)
tr
0.8VCC
0.2VCC
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)
RXD
SIN2
th(SCLK1-RXD),
th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD), td(SCLK2-SOUT2)
TXD
SOUT2
Fig 96. Timing diagram
Rev.3.04 May 20, 2008
REJ03B0158-0304
tWH(SCLK1), tWH(SCLK2)
Page 108 of 134
tV(SCLK1-TXD),
tV(SCLK2-SOUT2)
38D5 Group
FLASH MEMORY VERSION
FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 34 Absolute maximum ratings
Symbol
Parameter
Conditions
VCC
Power source voltage
VI
Input voltage
P00−P07, P10−P17, P20−P27, P30−P37,
P40−P47, P50−P57, P60−P67, P70−P74
VI
Input voltage
VL1
VI
Input voltage
VL2
VI
Input voltage
VL3
VI
Input voltage
C1, C2
VI
Input voltage
RESET, XIN, CNVSS
VO
Output voltage
C1, C2
VO
Output voltage
P00−P07, P10−P17,
P20−P27, P30−P37
All voltages are based on
VSS.
When an input voltage is
measured, output
transistors are cut off.
Ratings
−0.3 to 6.5
−0.3 to VCC+0.3
Unit
−0.3 to VL2
V
VL1 to VL3
V
V
V
VL2 to 6.5
V
−0.3 to 6.5
V
−0.3 to VCC+0.3
V
−0.3 to 6.5
V
At output port
−0.3 to VCC+0.3
V
At segment output
−0.3 to VL3+0.3
V
VO
Output voltage
P40−P47, P50−P57, P60−P67, P72−P74
−0.3 to VCC+0.3
V
VO
Output voltage VL3
Output voltage VL2, SEG32−SEG35, COM0−COM3
−0.3 to 6.5
−0.3 to VL3+0.3
V
VO
VO
Output voltage XOUT
V
Pd
Power dissipation
Topr
Operating temperature
Tstg
Storage temperature
−0.3 to VCC+0.3
300
−20 to 85
−40 to 125
Rev.3.04 May 20, 2008
REJ03B0158-0304
Ta=25°C
Page 109 of 134
V
mW
°C
°C
38D5 Group
FLASH MEMORY VERSION
Recommended Operating Conditions
Table 35 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C unless otherwise noted)
Symbol
VCC
Limits
Parameter
Power source
voltage(1)
VL1 input voltage
Unit
4.5
5.5
V
4.0
5.5
V
f(XIN) ≤ 4MHz
2.7
5.5
V
f(XIN) ≤ 16MHz
4.5
5.5
V
f(XIN) ≤ 8MHz
2.7
5.5
V
f(XIN) ≤ 16MHz
4.5
5.5
V
f(XIN) ≤ 8MHz
2.7
5.5
V
Low-speed mode
2.7
5.5
V
On-chip oscillator mode
2.7
5.5
V
2.1
V
VCC
V
AVSS
VCC
V
Frequency/8 mode
VLI
Max.
f(XIN) ≤ 12.5MHz
Frequency/4 mode
Power source voltage
Typ.
f(XIN) ≤ 8MHz
Frequency/2 mode (2)
VSS
Min.
0
Voltage multiplier is used
1.3
1.8
VREF
A/D converter reference voltage
AVSS
Analog power source voltage
VIA
Analog input voltage AN0−AN7
VIH
“H” input voltage
P00−P07, P10−P17, P24−P27, P30−P37,P41, P43,
P50−P57, P60 (CM4=0), P61, P65, P72−P74
0.7VCC
VCC
V
VIH
“H” input voltage
P20−P23, P40, P42, P44−P47, P62−P64, P66, P67,
P70, P71
0.8VCC
VCC
V
VIH
“H” input voltage
RESET
0.8VCC
VCC
V
VIH
“H” input voltage
XIN
0.8VCC
VCC
V
VIL
“L” input voltage
P00−P07, P10−P17, P24−P27, P30−P37, P41, P43,
P50−P57, P60 (CM4=0), P61, P65, P72−P74
0
0.3VCC
V
VIL
“L” input voltage
P20−P23, P40, P42, P44−P47, P62−P64, P66, P67,
P70, P71
0
0.2VCC
V
VIL
“L” input voltage
RESET
0
0.2VCC
V
XIN
0
0.2VCC
V
VIL
“L” input voltage
2.7
V
0
NOTES:
1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
2. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 110 of 134
V
38D5 Group
FLASH MEMORY VERSION
Table 36 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Parameter
Min.
Limits
Typ.
Max.
−40
Unit
ΣOH(peak)
“H” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
ΣOH(peak)
“H” total peak output current (1)
P40−P47, P50−P57, P60−P67
−40
mA
ΣOL(peak)
“L” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
40
mA
ΣOL(peak)
“L” total peak output current (1)
P40−P47, P50−P57, P60, P61
40
mA
ΣOL(peak)
“L” total peak output current (1)
P62−P67
110
mA
ΣOH(avg)
“H” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
−20
mA
ΣOH(avg)
“H” total average output current (1)
P40−P47, P50−P57, P60−P67
−20
mA
ΣOL(avg)
“L” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37, P72−P74
20
mA
ΣOL(avg)
“L” total average output current (1)
P40−P47, P50−P57, P60, P61
20
mA
ΣOL(avg)
“L” total average output current (1)
P62−P67
90
mA
IOH(peak)
“H” peak output current (2)
P00−P07, P10−P17, P20−P27, P30−P37
−2
mA
IOH(peak)
“H” peak output current (2)
P40−P47, P50−P57, P60−P67, P72−P74
−5
mA
IOL(peak)
“L” peak output current (2)
P00−P07, P10−P17, P20−P27, P30−P37
5
mA
IOL(peak)
“L” peak output current (2)
P40−P47, P50−P57, P60, P61, P72−P74
10
mA
IOL(peak)
“L” peak output current (2)
P62−P67
30
mA
IOH(avg)
“H” average output current (3)
P00−P07, P10−P17, P20−P27, P30−P37
−1.0
mA
IOH(avg)
“H” average output current (3)
P40−P47, P50−P57, P60−P67, P72−P74
−2.5
mA
IOL(avg)
“L” average output current (3)
P00−P07, P10−P17, P20−P27, P30−P37
2.5
mA
IOL(avg)
“L” average output current (3)
P40−P47, P50−P57, P60−P67, P72−P74
5.0
mA
IOL(avg)
“L” average output current (3)
P62−P67
15
mA
mA
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2. The peak output current is the peak current flowing in each port.
3. The average output current is average value measured over 100 ms.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 111 of 134
38D5 Group
FLASH MEMORY VERSION
Table 37 Recommended operating conditions (3)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
f(CNTR0)
f(CNTR1)
Parameter
Limits
Conditions
Timer X and Timer Y
Input frequency (duty cycle 50%)
Min.
Typ.
Max.
4.5V ≤ VCC ≤ 5.5V
6.25
4.0V ≤ VCC < 4.5V
2×Vcc−4
MHz
2.7V ≤ VCC < 4.0V
Vcc
MHz
Timer X, Timer Y,
4.5V ≤ VCC ≤ 5.5V
Timer 1, Timer 2,
4.0V ≤ VCC < 4.5V
Timer 3, Timer 4 clock input frequency
(Count source frequency of each timer) 2.7V ≤ VCC < 4.0V
f(Tclk)
f(φ)
System clock φ frequency
(1)
Main clock input frequency
(duty cycle 50%) (2)(3)
f(XCIN)
Sub-clock oscillation frequency
(duty cycle 50%) (4)(5)
MHz
16
MHz
4×Vcc−8
MHz
2×Vcc
MHz
4.5V ≤ VCC ≤ 5.5V
6.25
MHz
4.0V ≤ VCC < 4.5V
4
MHz
2.7V ≤ VCC < 4.0V
f(XIN)
Unit
4.5V ≤ VCC ≤ 5.5V
1.0
2.7V ≤ VCC < 4.5V
1.0
32.768
Vcc
MHz
16
MHz
8.0
MHz
80
kHz
NOTES:
Relationship between system clock φ frequency and power source voltage is shown in the graph below.
When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.
The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and
operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency
oscillator.
5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
1.
2.
3.
4.
<System clock φ frequency>
<Main clock XIN frequency>
[MHz]
16
[MHz]
Main clock XIN frequency
System clock φ frequency
6.25
4.0
2.7
8.0
1.0
0
4.0
2.7
4.5
Power source voltage
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 112 of 134
5.5 [V]
0
2.7
4.5
Power source voltage
5.5 [V]
38D5 Group
FLASH MEMORY VERSION
Electrical Characteristics
Table 38
Symbol
Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Parameter
Test conditions
IOH= −2.5mA
Limits
Min.
Typ.
Max.
VCC−2.0
V
IOH= −5mA
VCC−2.0
V
IOH= −1.25mA
VCC−0.5
V
VOH
“H” output voltage
P00−P07, P10−P17, P20−P27,
P30−P37
VOH
“H” output voltage
P40−P47, P50−P57, P60−P67,
P72−P74 (1)
“L” output voltage
P00−P07, P10−P17, P20−P27,
P30−P37
IOL=5mA
2.0
IOL=1.25mA
0.5
“L” output voltage
P40−P47, P50−P57, P60−P67,
P72−P74 (1)
IOL=10mA
2.0
IOL=2.5mA
0.5
IOL=15mA
2.0
VOL
VOL
Unit
V
V
V
VOL
“L” output voltage
P62−P67
VT+−VT−
Hysteresis
INT00, INT01, INT10, INT11, INT2,
CNTR0, CNTR1, KW0−KW7
0.5
V
VT+−VT−
Hysteresis
SIN2, SCLK1, SCLK2, RxD
0.5
V
VT+−VT−
0.5
Hysteresis RESET
V
IIH
“H” input current
P00−P07, P10−P17, P20−P27,
P30−P37
VI=VCC
5.0
µA
IIH
“H” input current
P40−P47, P50−P57,
P60−P67, P70−P74
VI=VCC
5.0
µA
IIH
“H” input current RESET, CNVSS
VI=VCC
5.0
µA
IIH
“H” input current XIN
VI=VCC
IIL
“L” input current
P00−P07, P10−P17, P20−P27,
P30−P37
VI=VSS
Pull-up “OFF”
IIL
“L” input current
P40−P47, P50−P57, P60−P67,
P72−P74
µA
4.0
−5.0
VCC=5V, VI=VSS
Pull-up “ON”
−60
−120
−240
VCC=3V, VI=VSS
Pull-up “ON”
−25
−50
−100
VI=VSS
Pull-up “OFF”
−5.0
VCC=5V, VI=VSS
Pull-up “ON”
−30
−70
−140
VCC=3V, VI=VSS
Pull-up “ON”
−6.5
−25
−45
IIL
“L” input current RESET, CNVSS
IIL
“L” input current XIN
VI=VSS
f(OCO)
On-chip oscillator frequency
VCC=5V, Ta=25°C
VI=VSS
5000
µA
µA
µA
µA
µA
−5.0
µA
7500
kHz
−4.0
2500
µA
µA
NOTE:
1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is “1”, the drivability of P61 is different from the above.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 113 of 134
38D5 Group
FLASH MEMORY VERSION
Table 39 Electrical characteristics (2)
(Vcc = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state,
A/D converter stopped, unless otherwise noted)
Symbol
Parameter
Limits
Test conditions
VRAM
RAM hold voltage
When clock is stopped
ICC
Power source current
Frequency/2 mode Vcc=5.0V
Vcc=2.7V
Frequency/4 mode Vcc=5.0V
Vcc=2.7V
Frequency/8 mode Vcc=5.0V
Vcc=2.7V
Low-speed mode
Vcc=5.0V
Min.
Typ.
2.2
Max.
5.5
V
f(XIN)=12.5MHz
4.0
7.0
mA
f(XIN)=12.5MHz (in WIT state)
2.0
3.5
mA
f(XIN)=4MHz
2.0
3.5
mA
f(XIN)=4MHz
1.5
3
mA
f(XIN)=4MHz (in WIT state)
1.0
2.5
mA
mA
f(XIN)=2MHz
1.0
2.5
f(XIN)=12.5MHz
3.2
5.6
mA
f(XIN)=12.5MHz (in WIT state)
1.6
3.2
mA
mA
f(XIN)=4MHz
1.6
3.2
f(XIN)=8MHz
1.6
3.2
mA
f(XIN)=8MHz (in WIT state)
1.0
2.5
mA
mA
f(XIN)=4MHz
1.0
2.5
f(XIN)=12.5MHz
2.5
5
mA
f(XIN)=12.5MHz (in WIT state)
1.5
3
mA
mA
f(XIN)=4MHz
1.5
3
f(XIN)=8MHz
1.5
3
mA
f(XIN)=8MHz (in WIT state)
1.0
2.5
mA
f(XIN)=4MHz
1.0
2.5
mA
f(XIN)=stop
400
800
µA
4.0
10
Ta=25°C
in WIT state
Ta=85°C
Vcc=2.7V
Unit
20
f(XIN)=stop
Ta=25°C
in WIT state
µA
300
600
µA
3.7
9
µA
Ta=85°C
18
500
1000
All oscillations stopped
(in STP state)
Ta=25°C
0.6
3.0
Ta=85°C
1.0
Current increased
at A/D converter operating
f(XIN)=12.5MHz, VCC=5V
in frequency/2, 4 or 8 mode
1.0
µA
µA
µA
µA
µA
mA
f(XIN)=stop, VCC=5V
in on-chip oscillator operating
1.0
mA
f(XIN)=stop, VCC=5V
in low-speed mode
0.8
mA
On-chip oscillator mode
f(XIN), f(XCIN), stop
Vcc=5.0V
600
1200
Vcc=2.7V
500
1000
Vcc=2.7V (in WIT state)
A/D Converter Characteristics
Table 40 A/D converter recommended operating condition
(Vcc = 2.7 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, unless otherwise noted)
Symbol
Parameter
Test conditions
VCC
Power source voltage
VIH
“H” input voltage ADKEY0
VIL
“L” input voltage ADKEY0
f(φAD)
AD converter clock frequency (1)
(Low-speed • on-chip oscillator
mode excluded)
Limits
Min.
Typ.
2.7
5.0
Unit
5.5
V
0.9VCC
VCC
V
0
0.7 × VCC − 0.5
V
6.25
MHz
4.0V < VCC ≤ 4.5V
4.0
MHz
2.7V < VCC ≤ 4.0V
VCC
MHz
4.5V < VCC ≤ 5.5V
NOTE:
1. Confirm the recommended operating condition for main clock input frequency.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Max.
Page 114 of 134
38D5 Group
FLASH MEMORY VERSION
Table 41 A/D converter characteristics
(Vcc = 2.7 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, low-speed • on-chip oscillator mode
included, unless otherwise noted)
Symbol
−
ABS
Parameter
Limits
Test conditions
Min.
Typ.
Max.
Unit
Resolution
10
Bits
Absolute accuracy 10bitAD 4.5V < VCC ≤ 5.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8≤6.25MHz
(quantification error mode
excluded)
4.0V < VCC ≤ 4.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8≤4MHz
4
LSB
2.7V ≤ VCC ≤ 4.0V,
AD conversion clock, f(XIN)/2, f(XIN)/8≤VccMHz
2.7V ≤ VCC ≤ 5.5V,
f(OCO)/8, f(OCO)/32
4.5V < VCC ≤ 5.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8≤6.25MHz
8bitAD
mode
2
4.0V < VCC ≤ 4.5V,
AD conversion clock=f(XIN)/2, f(XIN)/8≤4MHz
2.7V ≤ VCC ≤ 4.0V,
AD conversion clock=f(XIN)/2, f(XIN)/8≤VccMHz
2.7V ≤ VCC ≤ 5.5V,
f(OCO)/8, f(OCO)/32
tCONV
Conversion time(1)
10bitAD mode
tc(φAD) × 61
tc(φAD) × 62
8bitAD mode
tc(φAD) × 49
tc(φAD) × 50
RLADDER Ladder resistor
IVREF
Reference input
current
IIA
Analog input
current
VREF=5V
µs
12
35
100
50
150
200
kΩ
µA
5.0
µA
NOTE:
1. tc(φAD): one cycle of AD conversion clock. AD conversion clock can be selected from φSOURCE/2 or φSOURCE/8. φSOURCE
represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or
the low-speed mode.
When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) ≥ 500 kHz.
Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.
10bitAD=4LSB
8bitAD=2LSB
AD conversion clock
• Low-speed mode and
on-chip oscillator mode:
f(OCO)/8 or
f(OCO)/32
AD conversion clock frequency
[MHz]
6.25
4.0
AD conversion clock
• frequency/2 mode,
frequency/4 and
frequency/8 mode:
f(XIN)/2 or
f(XIN)/8
2.7
f(XIN)/2 or f(XIN)/8
10bitAD=4LSB
8bitAD=2LSB
(Note)
0
2.7
4.0
4.5
Power source voltage VCC
Note: f(XIN) ≥ 500kHz
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 115 of 134
5.5 [V]
38D5 Group
FLASH MEMORY VERSION
Timing Requirements And Switching Characteristics
Table 42 Power supply circuit characteristics
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
td(P-R)
Parameter
Test conditions
Internal power source voltage
stabilizes time at power-on
2.7 ≤ VCC ≤ 5.5V
Limits
Min.
Typ.
Unit
Max.
2
ms
Table 43 Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
Reset input “L” pulse width
tC(XIN)
Main clock input cycle time
tWH(XIN)
Main clock input “H” pulse width
tWL(XIN)
Main clock input “L” pulse width
tC(CNTR)
CNTR0, CNTR1 input cycle time
Limits
Min.
Typ.
Max.
Unit
4.5V ≤ VCC ≤ 5.5V (1)
62.5
µs
ns
4.0V ≤ VCC < 4.5V
125
ns
4.5V ≤ VCC ≤ 5.5V (2)
25
ns
4.0V ≤ VCC < 4.5V
50
ns
4.5V ≤ VCC ≤ 5.5V (2)
25
ns
2
4.0V ≤ VCC < 4.5V
50
ns
250
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
105
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
105
ns
tWH(INT)
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
80
ns
tWL(INT)
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
80
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (3)
800
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (3)
370
ns
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (3)
370
ns
tsu(RxD-SCLK1)
Serial I/O1 input setup time
220
ns
th(SCLK1-RxD)
Serial I/O1 input hold time
100
ns
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
1000
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
400
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
400
ns
tsu(SIN2-SCLK2)
Serial I/O2 input setup time
200
ns
th(SCLK2-SIN2)
Serial I/O2 input hold time
200
ns
NOTES:
1. 80 ns in the frequency/2 mode.
2. 32 ns in the frequency/2 mode.
3. When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 116 of 134
38D5 Group
FLASH MEMORY VERSION
Table 44 Timing requirements (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
Main clock input cycle time
(XIN input)
125
ns
tWH(XIN)
Main clock input “H” pulse width
50
ns
tWL(XIN)
Main clock input “L” pulse width
50
ns
tC(CNTR)
CNTR0, CNTR1 input cycle time
1000/VCC
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
tc(CNTR)/2−20
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
tc(CNTR)/2−20
ns
tWH(INT)
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
230
ns
tWL(INT)
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
230
ns
tC(SCLK1)
Serial I/O1 clock input cycle time
2000
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width
950
ns
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width
950
ns
tsu(RXD-SCLK1)
Serial I/O1 input setup time
400
ns
th(SCLK1-RXD)
Serial I/O1 input hold time
200
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
2000
ns
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
950
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
950
ns
tsu(SIN2-SCLK2)
Serial I/O2 input setup time
400
ns
th(SCLK2-SIN2)
Serial I/O2 input hold time
200
ns
NOTE:
1. When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 117 of 134
38D5 Group
FLASH MEMORY VERSION
Table 45 Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
tC(SCLK1)/2−30
tWL (SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2−30
td (SCLK1-TXD)
Serial I/O1 output delay time (1)
Serial I/O1 output valid time (1)
tr (SCLK1)
Serial I/O1 clock output rising time
tf (SCLK1)
Serial I/O1 clock output falling time
tWH (SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2−30
tWL (SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2−30
tf (SCLK2)
Serial I/O2 clock output falling time
td (SCLK2-SOUT2)
Serial I/O2 output delay time
Serial I/O2 output valid time
Max.
Unit
ns
ns
140
ns
30
ns
30
ns
−30
tV (SCLK1-TXD)
tV (SCLK2-SOUT2)
Typ
ns
ns
ns
40
ns
140
ns
−30
ns
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
Table 46 Switching characteristics (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
tC(SCLK1)/2−80
tWL (SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2−80
td (SCLK1-TXD)
Serial I/O1 output delay time (1)
tV (SCLK1-TXD)
Serial I/O1 output valid time (1)
Typ
Max.
Unit
ns
ns
350
−30
ns
ns
tr (SCLK1)
Serial I/O1 clock output rising time
80
ns
tf (SCLK1)
Serial I/O1 clock output falling time
80
ns
tWH (SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2−80
tWL (SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2−80
tf (SCLK2)
Serial I/O2 clock output falling time
80
td (SCLK2-SOUT2)
Serial I/O2 output delay time
350
tV (SCLK2-SOUT2)
Serial I/O2 output valid time
ns
ns
−30
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0”.
1kΩ
Measurement output pin
100pF
CMOS output
Fig 97. Circuit for measuring output switching characteristics
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 118 of 134
ns
ns
NOTE:
Measurement output pin
ns
100pF
N-channel open-drain output (Note)
38D5 Group
FLASH MEMORY VERSION
tc(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
0.2VCC
CNTR0, CNTR1
tWL(INT)
tWH(INT)
INT00,INT01
INT10,INT11
INT2
0.8VCC
0.2VCC
tw(RESET)
RESET
0.8VCC
0.2VCC
tc(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
0.2VCC
XIN
tC(SCLK1), tC(SCLK2)
tf
SCLK1
SCLK2
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
0.8VCC
0.2VCC
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)
RXD
SIN2
th(SCLK1-RXD),
th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD), td(SCLK2-SOUT2)
TXD
SOUT2
Fig 98. Timing diagram (in single-chip mode)
Rev.3.04 May 20, 2008
REJ03B0158-0304
tr
Page 119 of 134
tV(SCLK1-TXD),
tV(SCLK2-SOUT2)
38D5 Group
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting
information are available in the “Packages” section of the
Renesas Technology website.
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
*2
E
40
Reference
Symbol
80
25
1
ZD
24
D
E
A2
HD
HE
A
A1
bp
c
c
Index mark
A
A2
F
*3
y
bp
L
A1
e
Detail F
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 120 of 134
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.3 0.35 0.45
0.13 0.15 0.2
0°
10°
0.65 0.8 0.95
0.10
0.8
1.0
0.4 0.6 0.8
38D5 Group
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
bp
c
A
*3
A1
y
e
A2
F
L
x
L1
Detail F
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 121 of 134
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
38D5 Group
APPENDIX
Note on Programming
1. Processor Status Register
(1) Initialization of the processor status register
It is required to initialize the processor status register (PS) flags
which affect program execution. It is particularly essential to
initialize the T and D flags because of their effect on
calculations. Initialize these flags at the beginning of the
program.
<Reason>
At a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
Initialize the flags
Main program
Fig. 99 Initialization of processor status register flags
(2) How to refer the processor status register
To refer the contents of the processor status register (PS), execute
the PHP instruction once and then read the contents of (S+1). If
necessary, execute the PLP instruction to return the stored PS to
its original status.
(S)
(S) + 1
Stored PS
Fig. 100 Stack memory contents after PHP instruction
execution
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 122 of 134
2. Decimal Calculations
(1) Instructions for decimal calculations
To perform decimal calculations, set the decimal mode (D) flag
to “1” with the SED instruction and execute the ADC or SBC
instruction. In that case, after the ADC or SBC instruction,
execute another instruction before the SEC, CLC, or CLD
instruction.
Set the decimal mode (D) flag to “1”
Execute the ADC or SBC instruction
NOP
Execute the SEC, CLC, or CLD instruction
Fig. 101 Instructions for decimal calculations
(2) Status flag at decimal calculations
When the ADC or SBC instruction is executed in decimal mode
(D flag = “1”), three of the status flags (N, V, and Z) are disabled.
The carry (C) flag is set to “1” if a carry is generated and is
cleared to “0” if a borrow is generated as a result of a calculation,
so it can be used to determine whether the calculation has
generated a carry or borrow.
Initialize the C flag before each calculation.
38D5 Group
3. JMP Instruction
When using the JMP instruction (indirect addressing mode), do
not specify the address where “FF16” is allocated to the loworder 8 bits as the operand.
4. Multiplication and Division Instructions
(1) The MUL and DIV instructions are not affected by the T and
D flags.
(2) Executing these instructions does not change the contents of
the processor status register.
5. Read-Modify-Write Instruction
Do not execute any read-modify-write instruction to the read
invalid (address) SFR.
The read-modify-write instruction reads 1-byte of data from
memory, modifies the data, and writes 1-byte the data to the
original memory.
In the 740 Family, the read-modify-write instructions are the
following:
(1) Bit handling instructions:
CLB, SEB
(2) Shift and rotate instructions:
ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions:
DEC, INC
(4) Logical operation instructions (1’s complement):
COM
Although not the read-modify-write instructions, add and
subtract/logical operation instructions (ADC, SBC, AND, EOR,
and ORA) when T flag = “1” operate in the way as the readmodify-write instruction. Do not execute them to the read invalid
SFR.
<Reason>
When the read-modify-write instruction is executed to the read
invalid SFR, the following may result:
As reading is invalid, the read value is undefined. The instruction
modifies this undefined value and writes it back, so the written
value will be indeterminate.
Notes on Peripheral Functions
Notes on I/O Ports
1. Use in Stand-By State
When using the MCU in stand-by state* 1 for low-power
consumption, do not leave the input level of an I/O port
undefined. Be especially careful to the I/O ports for the Nchannel open-drain.
In this case, pull-up (connect to Vcc) or pull-down (connect to
Vss) these ports through a resistor.
When determining a resistance value, note the following:
• External circuit
• Variation in the output level during ordinary operation
When using a built-in pull-up resistor, note variations in current
values:
• When setting as an input port: Fix the input level
• When setting as an output port: Prevent current from
flowing out externally.
<Reason>
Even if a port is set to output by the direction register, when the
content of the port latch is “1”, the transistor becomes the OFF
state, which allows the port to be in the high-impedance state.
This may cause the level to be undefined depending on external
circuits.
As described above, if the input level of an I/O port is left
undefined, the power source current may flow because the
potential applied to the input buffer in the MCU will be unstable.
*1 Stand-by state: Stop mode by executing the STP instruction
Wait mode by executing the WIT instruction
2. Modifying Output Data with Bit Handling Instruction
When the port latch of an I/O port is modified with the bit
handling instruction* 1 , the value of an unspecified bit may
change.
<Reason>
I/O ports can be set to input mode or output mode in byte units.
When the port register is read or written, the following will be
operated:
• Port as input mode
Read: Read the pin level
Write: Write to the port latch
• Port as output mode
Read: Read the port latch or peripheral function output
(specifications vary depending on the port)
Write: Write to the port latch (output the content of the port
latch from the pin)
Meanwhile, the bit handling instructions are the read-modifywrite instructions*2. Executing the bit handling instruction to the
port register allows reading and writing a bit unspecified with the
instruction at the same time.
If an unspecified bit is set to input mode, the pin level is read and
the value is written to the port latch. At this time, if the original
content of the port latch and the pin level do not match, the
content of the port latch changes.
If an unspecified bit is set to output mode, the port latch is
normally read, but the peripheral function output is read in some
ports and the value is written to the port latch. At this time, if the
original content of the port latch and the peripheral function
output do not match, the content of the port latch changes.
*1 Bit handling instructions: CLB, SEB
*2 Read-modify-write instruction: Reads 1-byte of data from
memory, modifies the data, and writes 1-byte of the data to
the original memory.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 123 of 134
38D5 Group
3. Direction Registers
The values of the port direction registers cannot be read. This
means, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS. It is also impossible to use bit
operation instructions such as CLB and SEB, and read-modifywrite instructions to direction registers, including calculations
such as ROR. To set the direction registers, use instructions such
as LDM or STA.
4. Pull-Up Control
Only for the pin set to input mode, pull-up is controlled by the
PULL register and the segment output disable register.
Notes on Termination of Unused Pins
1. Termination of Unused Pins
Perform the following at the shortest possible distance (20 mm or
less) from the MCU pins.
(1) I/O ports
Set the ports to input mode and connect each pin to VCC or VSS
through a resistor of 1 k to 10 kΩ. An internal pull-up resistor can
also be used for the port where the internal pull-up resister is
selectable.
To set the ports to output mode, leave open at “L” or “H” output.
• When setting the ports to output mode and leave open,
input mode in the initial state remains until the mode of the
ports are switched to output mode by a program after a
reset. This may cause the voltage level of the pins to be
undefined and the power source current to increase while
the ports remains in input mode. For any effects on the
system, careful system evaluations should be implemented
on the user side.
• The direction registers may be changed due to a program
runaway or noise, so reset the registers periodically by a
program to increase the program reliability.
2. Termination Concerns
(1) When setting I/O ports to input mode
[1] Do not leave open
<Reason>
• The power source current may increase depending on the
first-stage circuit.
• The ports are more likely affected by noise when compared
with the termination shown on the above “1. (1) I/O ports”
[2] Do not connect to VCC or VSS directly
<Reason>
If the direction registers are changed to output mode due to a
program runaway or noise, a short circuit may occur.
[3] Do not connect multiple ports in a lump to V CC or V SS
through a resistor.
<Reason>
If the direction registers are changed to output mode due to a
program runaway or noise, a short circuit may occur between the
ports.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 124 of 134
38D5 Group
Notes on Interrupts
1. Changing Related Register Settings
If the interrupt occurrence synchronized with the following
settings is not required, take the sequence shown below.
• When selecting the external interrupt active edge
• When selecting the interrupt source of the interrupt vector
address where two or more interrupt sources are allocated
2. Checking Interrupt Request Bit
To check the interrupt request bit with the BBC or BBS
instruction immediately after this bit is set to “0”, take the
following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after the
interrupt request bit is set to “0”, the bit value before being set to
“0” is read.
Set the corresponding interrupt enable bit to
“0” (disabled).
Set the interrupt request bit to “0” (no interrupt)
Set the interrupt edge selection bit (active edge
switch bit) or interrupt (source) selection bit.
NOP (one or more instructions)
Execute the BBC or BBS instruction
NOP (one or more instructions)
Fig. 103 Sequence for setting interrupt request bit
Set the corresponding interrupt request bit to “0”
(no interrupt request).
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 102 Sequence for setting related register
<Reason>
In the following cases, the interrupt request bit of the
corresponding interrupt may be set to “1”.
<When switching the external interrupt active edge>
• INT0 interrupt edge selection bit
(bit 0 of interrupt edge selection register (address 003A16))
• INT1 interrupt edge selection bit
(bit 1 of interrupt edge selection register)
• INT2 interrupt edge selection bit
(bit 2 of interrupt edge selection register)
• CNTR0 active edge switch bits
(bits 6 and 7 of timer X control register 1 (address 002E16))
• CNTR1 active edge switch bit
(bits 6 of timer Y mode register (address 003816))
<When switching the interrupt source of the interrupt vector
address where two or more interrupt sources are allocated>
• Timer Y/CNTR1 interrupt switch bit
(bit 3 of interrupt edge selection register)
<When switching the INT pin>
• INT0 input port switch bit
(bit 4 of interrupt edge selection register)
• INT1 input port switch bit
(bit 5 of interrupt edge select register)
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 125 of 134
3. Setting Unused Interrupts
Set the interrupt enable bit of the unused interrupt to “0”
(disabled).
38D5 Group
Notes on Timers
8. Write Order to Timer X
1. Frequency Divider
All timers shares one circuit for the frequency divider to generate
the count source.
Thus the frequency divider is not initialized when each
individual timer is activated. When the frequency divider is
selected as the count source, a one-cycle delay of the maximum
count source will result between when the timer is activated and
when it starts counting or outputs the waveform.
The count source cannot be observed externally.
(1) When timer mode, pulse output mode, event counter mode,
or pulse width measurement mode is set, write to the
following registers in the order below:
The timer X register (extension)
The timer X register (low-order)
The timer X register (high-order)
Writing to only one of these registers cannot be performed.
When either of the above modes is set and timer X operates
as a 16-bit counter, if the timer X register (extension) is never
set after a reset release, setting the timer X register
(extension) is not required. In that case, write the timer X
register (low-order) first and the timer X register (high-order)
next. However, once the timer X register (extension) is
written, note that the value is retained in the reload latch.
(2) Write to the timer X register by the 16-bit unit. Do not read
the timer X register while write operation is performed. If the
write operation is not completed, normal operation will not
be performed.
(3) When IGBT output mode or PWM mode is set, do not write
“1” to the timer X register (extension). If “1” has been
already written to the timer X register, be sure to write “0” to
the register before use.
Write to the following registers in the order below:
The compare registers 1, 2, 3 (high- and low-order)
The timer X register (extension)
The timer X register (low-order)
The timer X register (high-order)
The compare registers (high- and low-order) can be written
in either order. However, be sure to write both the compare
registers 1, 2, 3 and the timer X register at the same time.
2. Division Ratio for Timer 1 to 4
The division ratio is 1/(n+1) when the value n (0 to 255) is
written to the timer latch.
3. Switching Frequency and Count Source for Timer 1
to 4, X, and Y
Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
4. Setting Timer 1 and 2 When STP Instruction
Executed
Before executing the STP instruction, first set the wait time at
return.
5. Setting Order to Timer 1 to 4
When switching the count source of timer 1 to timer 4, a narrow
pulse may be generated at the count input, which causes the timer
count value to be undefined. Also, if the timers are used in
cascade connection, a narrow pulse may be generated at the
output when writing to the pervious timer, which causes the next
timer count value to be undefined.
Thus set the value from timer 1 in order after setting the count
source of timer 1 to timer 4.
6. Write to Timer 2, 3, and 4
When writing to the latch only, if the write timing to the reload
latch and the underflow timing are almost the same, the value is
set into the timer and the timer latch at the same time. At this
time, count is stopped during write operation to the reload latch.
7. Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
(1) When PWM output is suspended once it starts, the time to
resume outputting may be delayed one section (256 × ts) of
the short interval depending on the level of the output pulse
at that time:
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 × ts
(2) When PWM mode is used, the interrupt requests and values
of timer 3 and timer 4 are updated every cycle of the long
interval (4 × 256 × ts).
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 126 of 134
9. Read Order to Timer X
(1) In all modes, read the following registers in the order below:
The timer X register (extension)
The timer X register (high-order)
The timer X register (low-order)
When reading the timer X register (extension) is not
required, read the timer X register (high-order) first and the
timer X register (low-order) next.
The read order to the compare registers 1, 2, 3 is not
specified.
(2) Read the timer X register in 16-bit units. Do not write to it
during read operation. If read operation is terminated in
progress, normal operation will not be performed.
38D5 Group
10. Write to Timer X
(1) Timer X can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
X write control bit (b3) in the timer X mode register
(address 002D16). When writing to the latch only, if a value
is written to the timer X address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer X
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(2) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
11. Setting Timer X Mode Register
When PWM mode or IGBT output mode is set, be sure to set the
write control bit in the timer X mode register to “1” (writing to
latch only). After writing to the timer X register (high-order), the
contents of both registers are simultaneously reflected in the
output waveform at the next underflow.
12. Timer X Output Control Functions
To use the output control functions (INT1 and INT2 ), set the
levels of INT1 and INT2 to “H” for the falling edge active or to
“L” for the rising edge active before switching to IGBT output
mode.
13. CNTR0 Active Edge Selection
(1) Setting the CNTR0 active edge switch bits also affects the
interrupt active edge at the same time.
(2) When the pulse width is measured, set bit 7 of the CNTR0
active edge switch bits to “0”.
14. When Timer X Pulse Width Measurement Mode
Used
When timer X pulse mode measurement mode is used, enable the
event counter wind control data (bit 5 of timer X mode register
(address 002D16)) by setting to “0”.
<Reason>
If the event counter window control data (bit 5 of timer X mode
r egister (address 002 D 1 6 )) is set to “1 ” (disabled) to
enable/disable the CNTR0 input, the input is not accepted after
the timer 1 underflow.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 127 of 134
15. CNTR1 Active Edge Selection
Setting the CNTR 1 active edge switch bits also affects the
interrupt active edge at the same time.
However, in pulse width HL continuous HL measurement mode,
the CNTR 1 interrupt request is generated at both rising and
falling edges of the pin regardless of the settings of the CNTR1
active edge switch bits.
16. Read from/Write to Timer Y
(1) When reading from/writing to timer Y, read from/write to
both the high-order and low-order bytes of timer Y. To read
the value, read the high-order bytes first and the low-order
bytes next. To write the value, write the low-order bytes first
and the high-order bytes next.
Writing/reading should be preformed in 16-bit units. If
write/read operation is changed in progress, normal
operation will not be performed.
(2) Timer Y can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
Y write control bit (b0) in the timer Y control register
(address 003916). When writing to the latch only, if a value
is written to the timer Y address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer Y
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(3) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
38D5 Group
Notes on Serial I/O1
1. Write to Baud Rate Generator
Write to the baud rate generator while transmission/reception is
stopped.
2. Setting Sequence When Serial I/O1 Transmit
Interrupt Used
To use the serial I/O1 transmit interrupt, if the interrupt
occurrence synchronized with settings is not required, take the
following sequence:
(1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of
interrupt control register 2 (address 003F 16 )) to “0”
(disabled).
(2) Set the transmit enable bit to “1”.
(3) After one or more instructions have been executed, set the
serial I/O1 transmit interrupt request bit (bit 2 of interrupt
request register 2 (address 003D16)) to “0” (no interrupt).
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag (bit 0 of serial I/O1 status register) and the transmit
shift completion flag are set to “1”.
This allows an interrupt request to be generated regardless of
which interrupt occurrence source has been selected by the
transmit interrupt source selection bit (bit 3 of serial I/O1 control
register) and the serial I/O1 transmit interrupt request bit is set to
“1”.
3. Data Transmission Control Using Transmit Shift
Completion Flag
After transmit data is written to the transmit buffer register, the
transmit shift completion flag (bit 2 of serial I/O1 status register
(address 001916)) changes from “1” to “0” after a delay of 0.5 to
1.5 cycles of the system clock. Thus, after transmit data is written
to the transmit buffer register, note this delay when controlling
data transmission by referencing the transmit shift completion
flag.
4. Setting Serial I/O1 Control Register
Before setting the serial I/O1 control register again, first set both
the transmit enable bit and the receive enable bit to “0” and
initialize the transmission and reception circuits.
Set both the transmit enable bit (TE) and the
receive enable bit (RE) to “0”
Set bits 0 to 3, and 6 of the serial I/O1 control
register.
Set both the transmit enable bit (TE) and the receive
enable bit (RE), or one of them to “1”.
Settings can be made with
the LDM instruction at the
same time
Fig. 104 Sequence of setting serial I/O1 control register
5. Pin Status After Transmission Completed
After transmission is completed, the TxD pin retains the level
when transmission is completed.
When the internal clock is selected in clock synchronous serial
I/O mode, the SCLK1 pin is set to “H”.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 128 of 134
6. Serial I/O1 Enable Bit during Transmit Operation
During transmission, if the serial I/O1 enable bit (bit 7 of serial
I/O1 control register (address 001A16 )) is set to “0”, the pin
function is set to an I/O port and the internal transmit operation
continues even though transmit data is not output externally.
Also, if the transmit buffer register is written in this state,
transmit operation starts internally. If the serial I/O1 enable bit is
set to “1” at this time, transmit data is output to the TxD pin from
that point.
7. Transmission Control When External Clock
Selected
During data transmission, if the external clock is selected as the
synchronous clock, set the transmit enable bit to “1” while SCLK1
is set to “H”. Also, write to the transmit buffer register while
SCLK1 is set to “H”.
8. Receive Operation in Clock Synchronous Serial I/O
Mode
During reception in clock synchronous serial I/O mode, set both
the transmit enable bit and the receive enable bit to “1”. Then
write dummy data to the transmit buffer register. When the
internal clock is selected as the synchronous clock, the
synchronous clock is output at this point and receive operation
starts. When the external clock is selected, reception is enabled at
this point and inputting the external clock starts transmit
operation.
The P41/TxD pin outputs dummy data written in the transmit
buffer register.
9. Transmit/Receive Operation in Clock Synchronous
Serial I/O Mode
In clock synchronous serial I/O mode, set the transmit enable bit
and the receive enable bit to “0” simultaneously to stop
transmit/receive operations. If only one of the operations is
stopped, transmission and reception cannot be synchronized,
which will cause a bit error.
Notes on Serial I/O2
1. Switching Synchronous Clock
If the synchronous clock is switched by the serial I/O2
synchronous clock selection bit (bit 6 of serial I/O2 control
register (address 001D 16 )), initialize the serial I/O2 counter
(writing to serial I/O2 register (address 001F16)).
2. Notes When External Clock Selected
When the external clock is selected as the synchronous clock, the
SOUT2 pin retains the D7 level after transfer is completed.
However, if the synchronous clock is continuously input, the
serial I/O2 register continues shifting and the SOUT2 pin keeps
outputting transmit data.
Also, write to the serial I/O2 register while SCLK2 is set to “H”.
When the internal clock is selected as the synchronous clock, the
SOUT2 pin is placed in the high-impedance state after transfer is
completed.
38D5 Group
Notes on A/D Conversion
1. Analog Input Pin
Set the signal source impedance for analog input low, or equip an
analog input pin with an external capacitor of 0.01 µF to 1 µF.
In addition, operations of application products should be verified
thoroughly on the user side.
<Reason>
An analog input pin has a built-in capacitor for analog voltage
comparison. Thus if a signal from the high impedance signal
source is input to the analog input pin, charge and discharge
noise will be generated. This may cause the A/D
conversion/comparison accuracy to drop.
2. Clock Frequency during A/D Conversion
The comparator input consists of a capacity coupling. If the
conversion rate is too low, the A/D conversion accuracy may
deteriorate due to a charge lost, so set f(XIN) 500 kHz or more for
A/D conversion in XIN mode. Also, do not execute the STP or
WIT instruction during A/D conversion.
In low-speed mode (when on-chip oscillator is selected), as A/D
conversion is performed using the internal on-chip oscillator,
there is no limit on the minimum frequency for f(XIN).
3. ADKEY Function
When the ADKEY enable bit is set to “1”, the analog input pin
selection bits are disabled. Do not execute the A/D conversion by
a program while ADKEY is enabled. Enabling ADKEY does not
change bits 0 to 2 of ADCON.
4. A/D Conversion Immediately After ADKEY Function
Started
In the ADKEY function, A/D conversion is not performed to the
analog input voltage immediately after starting the function. This
causes the A/D conversion result immediately after starting the
function to be undefined. If the A/D conversion result of the
analog input voltage applied to the ADKEY pin is required,
select the analog input pin corresponding to ADKEY before
performing A/D conversion.
5. Input Voltage Applied to ADKEY Pin
Set the input to the ADKEY pin into a steep falling waveform
and stabilize the input voltage within eight cycles (1 µs when
f(XIN) = 8 MHz) from the moment the input voltage reaches VIL
or lower.
The actual threshold voltage for the ADKEY pin is between VIH
and VIL.
To prevent unnecessary ADKEY operation due to noise or other
factors, set the ADKEY pin voltage to VIH (0.9 VCC) or more
while the input is waited.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 129 of 134
6. Register Operation during A/D Conversion
The A/D conversion operation is not guaranteed if the following
are preformed:
• The CPU mode register is operated during A/D conversion
operation
• The AD control register is operated during A/D conversion
operation
• The STP or WIT instruction is executed during A/D
conversion operation
7. A/D Converter Power Source Pin
Connect to the A/D converter power source pin to AVSS or VSS
whether the A/D conversion function is used or not.
<Reason>
If the AVSS pin is left open, the MCU may operate incorrectly
because the pin will be affected by noise or other factors.
38D5 Group
Notes on LCD Drive Control Circuit
1. Multiplier Circuit
When the multiplier circuit is used, set the multiplier circuit
control bit to “1” (multiplier circuit enabled) after applying a
voltage from 1.3 V or more to 2.1 V or less to the VL1 pin.
When the multiplier circuit is not used, set the VL3 connection bit
to “1” (open) and apply an appropriate voltage to the LCD power
source input pins (VL1 to VL3). When the VL3 connection bit is
set open, the VL3 pin is placed in the high impedance state.
When the multiplier circuit is used, set the LCDCK frequency to
100 Hz or more. The on-chip oscillator cannot be used as
LCDCK.
In a system where the multiplier circuit is used (a multiplier
capacitor is externally connected between the C1 and C2 pins),
set the multiplier circuit control bit to “1” (multiplier circuit
enabled) before executing the STP or WIT instruction.
2. Setting Data to LCD Display RAM
To write data to the LCD display RAM when the LCD enable bit
is set to “1” and while LCD is turned on, set fixed data.
Rewriting with temporary data may cause LCD to flicker. The
following shows a processing example to write data to the LCD
display RAM while LCD is turned on.
(1) Correct processing
*Content at address 0840 16: “FF16”
LCD
on
Off
LCD on or off?
On
LCD
on or
off
Set LCD display RAM data
LRAM0 (address 084016) ← “FF16”
Set LCD display RAM data
LRAM0 (address 084016) ←“0016”
• Set fixed data to LCD display RAM
(2) Incorrect processing
LCD
on
*Content at address 0840 16: “FF16”
Set LCD display RAM data
LRAM0 (address 084016) ← “0016”
LCD
off
• Set off data to LCD display RAM
Off
LCD on or off?
On
LCD
on or
off
Set LCD display RAM data
LRAM0 (address 084016) ← “FF16”
• Set fixed data to LCD display RAM
Fig. 105 Processing example when writing data to LCD display RAM While LCD Turned On
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 130 of 134
38D5 Group
3. Executing STP Instruction
Executing the STP instruction sets the LCD enable bit (bit 4 of
LCD mode register1 (address 001316)) to “0” and the LCD panel
turns off. To turn the LCD panel on after returning from stop
mode, set the LCD enable bit to “1”.
5. Using No ROM Correction Function
If the ROM correction function is not used, the ROM correction
vector can be used as normal RAM/ROM. When using as normal
RAM/ROM, be sure to set bits 1 and 0 of the ROM correction
enable register to “0” (disabled).
4. VL3 Pin
To use the LCD drive control circuit while VL3 is set to the
voltage equal to VCC, apply the VCC voltage to the VL3 pin and
write “1” to the VL3 connection bit (bit 1 of LCD mode register 2
(address 001416)).
Notes on Clock Generating Circuit
5. LCD Drive Power Supply
Power supply capacitor may be insufficient with the division
resistance for LCD power supply, and the characteristic of the
LCD panel. In this case, there is the method of connecting the
bypass capacitor about 0.1 -0.33 µ F to VL1 -VL3 pins. The
example of a strengthening measure of the LCD drive power
supply is shown below.
VL3
VL2
• Connect by the shortest
possible wiring.
• Connect the bypass capacitor
to the VL1 −VL3 pins as short
as possible.
(Referential value:0.1−0.33 µF)
VL1
Fig. 106 Strengthening measure example of LCD drive
power supply
Notes on ROM Correction Function
1. Returning to Main Program
To return to the main program from the correction program, use
the JMP instruction (3-byte instruction).
2. Using ROM Correction Function
If the ROM correction function is used, be sure to enable the
ROM correction enable bit after setting the ROM correction
register.
3. Address
Do not set addresses other than the ROM area in the ROM
correction address registers. Also, do not set the same address in
the ROM correction address 1 register and the ROM correction
address 2 register.
4. ROM Correction Process
Include the ROM correction process in the program beforehand.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 131 of 134
1. Oscillation Circuit Constants
The oscillation circuit constants vary depending on the resonator.
Use values recommended by the oscillator manufacturer.
A feed-back resistor is implemented between the XIN and XOUT
pins (an external feed-back resistor may be required depending
on conditions). As no feed-back resistor is implemented between
XCIN and XCOUT, add a feedback resistor of about 10 MΩ.
2. Transition between Modes
When the MCU transits between on-chip oscillator mode, XIN
mode, or low-speed mode, both the XIN and XCIN oscillations
must be stabilized. Be especially careful when turning the power
on and returning from stop mode. Refer to the clock state
transition diagram for a transition between each mode. Also, set
the frequency in the condition that f(XIN) ≥ 3 × (XCIN).
When X IN mode is not used (the X IN -X OUT oscillation or
external clock input to XIN is not performed), connect XIN to
VCC through a resistor.
3. Oscillation Stabilization
Before executing the STP instruction, set the values * to generate
the wait time required for oscillation stabilization to timer 1 latch
and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2).
*Referential values
(Set values according to your oscillator and system)
• OSCSEL = “L” in the flash memory and QzROM versions:
..................................................................... 000516 or more
• OSCSEL = “H” in the QzROM version:
.....................................................................01FF16 or more
4. Low-Speed Mode, XIN Mode
To use low-speed mode or X IN mode, wait until oscillation
stabilizes after enabling the X IN -X OUT and X CIN -X COUT
oscillation, then switch to the mode.
38D5 Group
Notes on Flash Memory Mode
• CPU Rewrite Mode
(1) Operating Speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the main clock division ratio selection bits (bits 6 and
7 of address 003B16).
(2) Prohibited Instructions
During CPU rewrite mode, the instructions which reference data
in the flash memory cannot be used.
(3) Interrupts
During CPU rewrite mode, interrupts cannot be used because
they reference data in the flash memory.
(4) Watchdog Timer
If the watchdog timer has been running already, the internal reset
by underflow will not occur because the watchdog timer is
continuously cleared during program or erase operation.
(5) Reset
Reset is always valid. If CNVSS = “H” when a reset is released,
boot mode is active. The program starts from the address stored
in addresses FFFC16 and FFFD16 in boot ROM area.
Notes on Watchdog Timer
1. Watchdog Timer Underflow
The watchdog timer does not operate in stop mode, but it
continues counting during the wait time to release the stop state
and in wait mode. Write to the watchdog timer control register so
that the watchdog timer will not underflow during these periods.
2. Stopping On-Chip Oscillator Oscillation
When the on-chip oscillator is selected by the watchdog timer
count source selection bit 2, the on-chip oscillator forcibly
oscillates and it cannot be stopped. Also, in this time, set the STP
instruction function selection bit to “1” at this time.
Select “0” (φ SOURCE) for the watchdog timer count source
selection bit 2 at the system which on-chip oscillator is stopped.
3. Watchdog Timer Control Register
Bits 7 to 5 can be rewritten only once after a reset. After writing,
rewriting is disabled because they are locked. These bits are set
to “0” after a reset.
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 132 of 134
Notes on Differences between Flash Memory Version
and QzROM Version
The flash memory and QzROM versions differ in their
manufacturing processes, built-in ROM, memory size, and
layout patterns. Because of these differences, characteristic
values, operation margins, noise immunity, and noise radiation
and oscillation circuit constants may vary within the specified
range of electrical characteristics.
When switching to the QzROM version, implement system
evaluations equivalent to those performed in the flash memory
version.
Confirm page 11 about the differences of functions.
Notes on Power Source Voltage
When the power supply voltage value of the MCU is less than
the value indicated in the recommended operating conditions, the
MCU may not operate normally and perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power is turned off, reset
the MCU when the power source voltage is less than the
recommended operating conditions, and design the system so
that this unstable operation does not cause errors to it.
Notes on Handling Power Source Pins
Before using the MCU, connect a capacitor suitable for high
frequencies as a bypass capacitor between the following:
The power source pin (VCC pin) and the GND pin (VSS pin)
The power source pin (VCC pin) and the analog power source
input pin (AVSS pin). As a bypass capacitor, a ceramic capacitor
of 0.01 µF to 0.1 µF is recommended.
Also, use the shortest possible wiring to connect a bypass
capacitor between the power source pin and the GND pin and
between the power source pin and the analog power source pin.
Notes on Memory
1. RAM
The RAM content is undefined at a reset. Be sure to set the initial
value before use.
38D5 Group
Notes on QzROM Version
Wiring to OSCSEL pin
(1) OSCSEL = L
Connect the OSCSEL pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer. In
addition connecting an approximately 5 kΩ resistor in series to
the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the V S S pin of the
microcomputer.
(2) OSCSEL = H
Connect the OSCSEL pin the shortest possible to the VCC pattern
which is supplied to the V CC pin of the microcomputer. In
addition connecting an approximately 5 kΩ resistor in series to
the VCC could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
VCC pattern which is supplied to the VCC pin of the
microcomputer.
<Reason>
The OSCSEL pin is the power source input pin for the built-in
QzROM.
When programming in the QzROM, the impedance of the
OSCSEL pin is low to allow the electric current for writing to
flow into the built-in QzROM. Because of this, noise can enter
easily. If noise enters the OSCSEL pin, abnormal instruction
codes or data are read from the QzROM, which may cause a
program runaway.
Termination of OSCSEL pin
(2) OSCSEL = H
(1) OSCSEL = L
(1)
(1)
The shortest
The shortest
VCC
OSCSEL
about 5 kΩ
about 5 kΩ
OSCSEL
VSS
(1)
The shortest
(1)
The shortest
Note 1: It shows the microcomputer’s pin
Fig. 107 Wiring for OSCSEL pin
Overvoltage in QzROM Version
Make sure that voltage exceeding the VCC pin voltage is not
applied to other pins. In particular, ensure that the state indicated
by bold lines in figure below does not occur for pin OSCSEL pin
(VPP power source pin for QzROM) during power-on or poweroff. Otherwise the contents of QzROM could be rewritten.
QzROM Version Product Shipped in Blank
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approximate
0.1% may occur.
Moreover, please note the contact of cables and foreign bodies on
a socket, etc. because a writing environment may cause some
writing errors.
Ordering QzROM Writing
1. Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .msk) which is made by the
mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “00 16 ”, “FE 16 ” and “FF 16 ” can not be
accepted.
• Set “FF16” to the ROM code protect address in ROM data
regardless of the presence or absence of a protect. When data
other than “FF 16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
2. Data Required for QzROM Ordering
The following are necessary when ordering a QzROM product
shipped after writing:
• QzROM Writing Confirmation Form*
• Mark Specification Form*
• ROM data: Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
3. QzROM Product Receiving Procedure
When writing to QzROM is performed by user side, the
receiving inspection by the following flow is necessary.
QzROM product shipped after writing
QzROM product shipped in blank
“protect disabled”
“protect enabled to the protect area 1”
Renesas
(1)
∼
∼
1.8V
(2)
Renesas
Programming
1.8V
Shipping
VCC pin voltage
Verify test
∼
∼
OSCSEL pin voltage
“H” input
User
Shipping
Receiving inspection
(Blank check)
User
∼
∼
OSCSEL pin voltage
“L” input
(1) Input voltage to other MCU pins rises before VCC pin voltage.
(2) Input voltage to other MCU pins falls after VCC pin voltage.
Note: The internal circuitry is unstable when VCC is below the minimum
voltage specification of 1.8 V (shaded portion), so particular care should
be exercised regarding overvoltage.
Fig. 108 Timing Diagram (Bold-lined periods are applicable)
Receiving inspection of
unprotected area (Verify test)
Programming
Programming to unprotected area
Verify test for all area
Verify test for unprotected area
Fig. 109 QzROM receiving procedure
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 133 of 134
38D5 Group
Notes on Flash Memory Version
CPU Rewrite Mode
1. Operating Speed
During CPU rewrite mode, set the system clock φ 4.0 MHz or
less using the main clock division ratio selection bits (bits 6 and
7 of address 003B16).
2. Prohibited Instructions
The instructions which refer to the internal data of the flash
memory cannot be used during the CPU rewrite mode.
3. Interrupts
The interrupts cannot be used during the CPU rewrite mode
because they refer to the internal data of the flash memory.
4. Watchdog Timer
In case of the watchdog timer has been running already, the
internal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
5. Reset
Reset is always valid. In case of CNVSS = “H” when reset is
released, boot mode is active. So the program starts from the
address contained in address FFFC16 and FFFD16 in boot ROM
area.
CNVSS Pin
The CNVSS pin determines the flash memory mode.
Connect the CNVSS pin the shortest possible to the GND pattern
which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ. resistor in series
to the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the V S S pin of the
microcomputer.
Note. When the boot mode or the standard serial I/O mode is used, a
switch of the input level to the CNVSS pin is required.
(1)
The shortest
CNVSS
Approx. 5kΩ
VSS
(1)
The shortest
Note 1: Shows the microcomputer’s pin.
Fig. 110 Wiring for CNVSS pin
Rev.3.04 May 20, 2008
REJ03B0158-0304
Page 134 of 134
REVISION HISTORY
38D5 Group Data Sheet
Rev.
Date
Description
1.00
Aug 12, 2005
−
First edition issued
2.00
Jan 23, 2006
−
Pin name revised: CNVss → OSCSEL
−
Frequency name revised: ROSC → OCO
−
Mode name revised: Middle-, High-speed mode → Frequency/2, 4, 8 mode
−
Bit names of some registers:
1. ROSC stop bit → On-chip oscillator stop bit
2. STP instruction disable bit → STP instruction function selection bit
3. Vector 1 enable bit (RC0) → ROM correction address 1 enable bit (RC0)
4. Vector 2 enable bit (RC1) → ROM correction address 2 enable bit (RC1)
5. Vector control bit (RC2) → ROM correction memory selection bit (RC2)
1
Description, Power source voltage and Power dissipation revised.
Page
Summary
6
Table 2 Pin description (1): Some description of Port P1 Function revised.
7
Table 3 Pin description (2): Description of OSCSEL added.
Fig. 5 Memory expansion plan, Table 4 Support products
M38D59GFFP/HP, M38D59GCFP/HP added.
13
Some description revised.
Fig. 8 Structure of CPU mode register: Note on on-chip oscillator added.
Fig. 9 Switch procedure of CPU mode register: Initial values of CPUM2 added and
initial value of CPUM revised.
14
Fig. 10 Memory map diagram:
Reserved ROM area FFD416 to FFDC16 → FFD016 to FFDC16
Note on ROM correction vector added.
15
Fig. 11 Memory map of special function register (SFR):
“Reserved area” is added to address 0FFD16, and Note added.
22
Table 8 Termination of unused pins: XIN and XOUT pin termination added.
52
ROM CORRECTION FUNCTION:
Description and some bit names revised and Fig. 47 Memory map of M38D58 added.
53
Initial Value of Watchdog Timer: Some description added.
Standard Operation of Watchdog Timer: Some description eliminated.
Bit 6 of Watchdog Timer Control Register added.
Note 2 revised.
Fig. 50 Structure of Watchdog timer control register:
Name of bit 6 and description of its function revised.
55
Fig. 55 Reset sequence revised.
57
Fig. 56 Internal state at reset: ROM correction address 1 (low-order), ROM
correction address 2 (high-order) and ROM correction address 2 (low-order)
revised.
58
Oscillation Control (1) Stop Mode: Some description revised.
59
Fig. 58 Clock generating circuit block diagram:
“or ROSC clock division ratio selection bit” eliminated.
60
Fig. 60 State transitions of system clock
on-chip oscillator mode: f(OCO) → f(OCO)/32,
Note 8 to Note 10 revised and Note 12 added.
61-65
QzROM programming mode (Overview, Pin description, Pin connection diagram,
Connection example) added.
68
(6) Wiring to OSCSEL pin revised.
69
QzROM Receive Flow added.
(1/7)
REVISION HISTORY
Rev.
Date
2.00
Jan 23, 2006
38D5 Group Data Sheet
Description
Page
2.01
2.02
Mar 24, 2006
Jul 10, 2006
Table 14 Recommended operating conditions
- Vcc (Power source voltage) and Note revised.
- VIH, VIL (RESET) revised.
73
Table 16 Recommended operating conditions: all revised, Power source voltage
graph added.
74
Table 17 Electrical characteristics: ROSC → f(OCO)
75
Table 18 Electrical characteristics: Icc revised.
Table 19 A/D converter recommended operating condition revised.
76
Table 20 A/D converter characteristics: test conditions revised.
AD Power source voltage graph added.
77
Table 21 Timing requirements 1: tc(XIN), twH(XIN), twL(XIN) revised and Note added.
81
PACKAGE OUTLINE revised.
1
FEATURES: Power source voltage revised.
4
Performance overview: Oscillation frequency and Power source voltage revised.
17
Table 7 Related SFRs of port P7 revised.
52
Fig. 46: Address revised.
53
Fig. 50: Note 1 revised.
58
(1)Stop mode: Description revised.
59
Fig. 59 φSOURCE added.
60
Fig. 60 State transitions of system clock: Note 3 revised.
71
Table 14 : Vcc (Power source voltage) and Note 3 revised.
73
Table 16: Power source voltage (Main clock XIN frequency) graph added.
76
Table 20 Description of f(OCO) and Note revised.
15
Fig. 11: Register names of ROM correction addresses 1 and 2 revised.
22
Termination of unused pins
23
Table 8
• Termination 1 (recommended) : Delete (recommended).
• Termination 1 to 3 of P70/C1/INT01 and P71/C2/INT11 : revised.
29
XCIN is selected as Timer 1, 2 count source : sentence is revised.
32
XCIN is selected as Timer X count source : sentence is revised.
33
Fig. 26: (TXCON1 bit 5 = “1”)→(TXCON1 bit 5 = “0”)
Aug 31, 2006
I/O ports : Description added.
35
XCIN is selected as Timer Y count source : sentence is revised.
43
Fig. 38: φSOURCE clock added.
52
Fig. 47: Border line in ROM area : revised.
53
Fig. 49: On chip oscillator → On chip oscillator/4
Fig. 50: b5 and b7 revised.
58
Frequency Control : Description added.
61
Table 12: Function of VREF and AVSS revised.
64 to 67
2.03
Summary
71
Fig. 63 to Fig. 66: Revised and added.
76
Table 17: Parameter of IIH and IIC added.
4
Table 1: Main clock and Sub-clock generating circuit : “feedback resistor”
eliminated.
7
Table 3: AVSS : GND → Analog power source
23
Table 8: P41/TxD : input port → output port
P42/SCLK1 : output port → input port
(2/7)
REVISION HISTORY
Rev.
Date
2.03
Aug 31, 2006
38D5 Group Data Sheet
Description
Page
2.04
Feb 02, 2007
Summary
75
Table 16: Max. of f(φ) : 2 × VCC – 4 → 4
76
Table 17: Test condition of VT+ – VT- : VCC = 2.0 V on RESET → VCC = 2.0 V to 5.5
V on RESET
13, 60
Table 24
Limits of twH (SCLK2), twL (SCLK2): tc (SCLK1)/2–80 → tc (SCLK2)/2–80
14
MEMORY
ROM: Description revised.
ROM Code Protect Address: Description revised and added.
Fig. 10: Reserved ROM area: FFD016 → FFDB16
15
Fig.8 and Fig.60: CPUM2 (bits 2 to 7) revised.
16
• Direction Resisters: Description revised.
Fig.11: ROM correction enable register →
ROM correction enable register(RCR)
23
Table 8: Terminations 1 and 2 of VL3 revised.
25
• Fig.13: PULL3 (bits 4 to 7), SEG2 (bits 4 to 7) revised.
31
Fig.19: INTEDGE(bit 6), ICON2(bit 7) revised.
34
Fig.25: revised.
35
Fig. 28: Note added and revised.
36
Fig. 27: TXCON(BITS 3,4) revised.
41
Fig. 36: Note added.
43
• Fig.29: TYM(bits 2,3) revised.
• [AD control Register], Fig.39:
43, 44
Fig. 38: Note added.
46
analog input selection bit → analog input pin selection bits
51
Fig. 45: 1/3 duty revised.
52
ROM CORRECTION FUNCTION: Description added.
Fig. 47: FFD016 → FFDB16.
53
Fig. 49: Note added and revised.
54
Fig.40: LM2(bits 1 to 7) revised.
Fig.51: CKOUT(bits 2 to 7 ) revised.
59
Fig. 59: Note 3 added and circuit expression is revised.
61
Table 12: ESDA input → ESDA input/output
64 to 66
Fig. 63 to Fig. 66: Revised.
71
Precautions Regarding Overvoltage: Description revised and Fig. 73 added.
72
Table 13
• VCC: Oscillation start voltage → When start oscillating
• VI: OSCSEL added.
• Vo: Conditions added.
73
Table 14
• VIL: OSCSEL added.
• Note 3 revised.
75
Table 16: Note 4 revised.
78
Table 20
• TCONV Limits: (Note) → (Notes 1, 2)
• Note 2 revised.
80
Note: ...set f(XIN) ≤ 500 kHz → ≥ 500 kHz
Table 22
tsu (RXD-SCLK2) → tsu (SIN2-SCLK2)
(3/7)
REVISION HISTORY
38D5 Group Data Sheet
Rev.
Date
Description
2.04
Feb 02, 2007
81
th (SCLK2-RXD) → th (SCLK2-SIN2)
Table 23
Limits of twH (SCLK2), twL (SCLK2): tc (SCLK1)/2–30 → tc (SCLK2)/2–30
3.01
Aug 08, 2007
−
38D5 Group (Flash Memory Version For Development) Datasheet (No.
REJ03B0197) is merged.
1
Flash memory version contents: added
DESCRIPTION: Description added
Memory size (QzROM version): 640 bytes → 1536 bytes
Power dissipation (Flash memory version): revised
2
Fig. 1: Flash memory version: “M38D59FFFP” added, Notes: added
3
Fig. 2: Flash memory version: “M38D59FFHP” added, Notes: added
4
Table 1: Flash memory version contents: added and separates to Table 2 (Next
page)
Memory size (QzROM version); 640 bytes → 1536 bytes
I/O port; 32 pins → 36 pins
Page
Summary
7
Table 3: I/O port P3, I/O port P4: revised
8
Table 4: OSCSEL → CNVSS/function: revised
9
Fig.4 “Memory type”: Flash memory version added
10
Memory Type: deleted
Memory size (QzROM version): 640 bytes → 1536 bytes
Fig. 5: Under development products → mass-produced
Table 5: Flash memory version products added
11
Table 6, Notes on Differences between QzROM and Flash Memory Versions: added
12
Central Processing Unit: revised
15
Fig. 8: Flash memory version contents: added
Notes: revised
16
Fig. 9: Flash memory version contents: added
Low/XIN mode? → Low-speed/XIN mode?
17
Memory: Flash memory version contents: added
• ROM is revised
• ROM code Protect Address in QzROM version is revised
Fig. 10: revised
18
Fig. 11: revised
19
Fig. 13: Do not write “1” → Not used (do not write “1”)
23
Fig. 16 (14) Port P60: Revised port Xc switch bit input to low-active
27 to 31
INTERRUPTS: revised
28
• Interrupt Source Selection: interrupt source selection register → interrupt edge
selection register
• External Interrupt Pin Selection: INT0, INT1 interrupt switch bit → INT0, INT1 input
port switch bit
29
Fig. 19: Do not write “1” → Not used (do not write “1”)
31
<Notes>: Related registers → Related bits, and its explain is revised
34
Fig. 25: Figure title is revised
P72 clock output control bit block is revised
35
• Frequency Divided For Timer: revised
<Notes on Timer 1 to Timer 4>: (2)Writing to Timer 2, Timer 3, Timer 4 → (2)Write
Timer 2, Timer 3, Timer4
37
Fig. 28: Figure title is revised
Timer X output 1 edge switch bit → Timer X output 1 active edge switch bit
(4/7)
REVISION HISTORY
Rev.
Date
3.01
Aug 08, 2007
38D5 Group Data Sheet
Description
Page
Summary
37
Fig. 28: Timer X output 2 edge switch bit → Timer X output 2 active edge switch bit
38
• Frequency Divided For Timer: revised
timer X1 output edge switch bit → timer X output 1 active edge switch bit
timer X2 output edge switch bit → timer X output 2 active edge switch bit
(6) Pulse Width Measurement Mode: revised
39
(1) Write Order to Timer X: description added
(2) Read Order to Timer X: revised
(3) Write to Timer X: revised
40
(7) When Timer X Pulse Width Measurement Mode Used: added
Fig. 30: Timer X output 1 edge switch bit → Timer X output 1 active edge switch bit
41
• Timer Y: revised
(5) Real Time Port Control: moved from <Notes on Timer Y>
42
• Real Time Port Control: moved to “• Timer Y”
47
• Serial I/O2: revised
Fig. 39: Serial I/O counter 2 → Serial I/O2 counter
Serial I/O shift register 2 → Serial I/O2 register
48
[Serial I/O2 Operation]: added
Fig. 40: revised
49
[Comparator and Control Circuit]: revised
50
ADKEY function: moved from the next page.
51
Fig. 43: Added the note number to each register
Do not write “1” → Not used (do not write “1”)
53
• Voltage Multiplier: revised
• Bias Control and Applied Voltage to LCD Power Input Pins: evised
Fig. 45: revised
title is revised
56
<Notes>: added
57
Fig. 50: revised
58
• Initial Value of Watchdog Timer: revised
<Notes>: revised
Fig. 52: Watchdog timer selection bit 2 → Watchdog timer count source selection bit
2
Fig. 53: revised
59
Title “[RRF register] RRFR”: added
60
RESET CIRCUIT: description added
Fig. 57, Fig. 58: revised
61
Fig. 59: (18) RRF register (RRFR) → (18) RRF register
Notes revised
62
CLOCK GENERATING CIRCUIT, and • Frequency Control: Description added
64
• Oscillation Control: Description added
65
Fig. 63: revised
66
Table 15: Function of VCC, VSS pins: 1.8 to 5.5 → 2.7 to 5.5
69, 70
73 to 91
92
Fig. 66 and 67: revised
FLASH MEMORY MODE: added
NOTES ON PROGRAMMING is merged to NOTES ON USE
93
NOTES ON QzROM VERSION is separated
94
NOTES ON FLASH MEMORY VERSION and NOTES ON DEFFAERENCES
BETWEEN QzROM VERSION AND FLASH MEMORY VERSION are added
(5/7)
REVISION HISTORY
Rev.
Date
3.01
Aug 08, 2007
38D5 Group Data Sheet
Description
Page
Summary
97, 108
Table 22 and 35: VI of OCESEL are added
VO of COM0-COM3 are added
VO of ports and SEG32-SEG35 are revised
98-106
Table 23 to 34: VSS=0V is added to test conditions
98
Table 24: VIH of RESET is revised
101
Table 27: VCC test conditions are revised
103
Table 30: At 10bitAD: 2.2V < VCC ≤ 4.0V → 2.2V ≤ VCC ≤ 4.0V
1.8V < VCC ≤ 5.5V → 2.0V ≤ VCC ≤ 5.5V
At 8bitAD: 2.0V < VCC ≤ 2.2V → 2.0V ≤ VCC ≤ 2.2V
1.8V < VCC ≤ 5.5V → 2.0V ≤ VCC ≤ 5.5V
104, 115 Table 31 and 45: Each main clock input condition (VCC) are revised.
105
Table 32: 2.0V ≤ VCC ≤ 4.0V → 2.0V ≤ VCC < 4.0V
VCC ≤ 2.0V → VCC < 2.0V
Note 1 is added
108
Table 35: CNVSS is added
Storage temperature is revised
112
Table 40: Limits value of IIL are revised
113
Table 41: All limits value are revised
113, 114
114
Table 43: 2.7V < VCC ≤ 4.0V → 2.7V ≤ VCC ≤ 4.0V
2.7V ≤ VCC ≤ 5.5V and test conditions of f(OCO)/8 and f(OCO)/32 are
added
115
Table 44 are added
Table 45: “Main clock input “L” pulse width” is added
Note 1 is revised
120-133
3.02
3.03
3.04
Sep 11, 2007
Oct 02 2007
May 20 2008
Table 41, 42, and 43: VSS=0V is added to test conditions
Appendix: added
10
Table 5: Latest revised date of products list
17
Fig. 10: Brancket indicates the ROM area is modified
53
Fig. 45: VL1 external capacitor → external power supply
98
Marge the “Recommended operating conditions (1)” table and “Recommended
operating conditions (2)”
109
Marge the “Recommended operating conditions (1)” table and “Recommended
operating conditions (2)”
125
2nd item of “8. Write Order to Timer X” is added
126
2nd item of “10. Write to Timer X” is deleted
40
“(7) When Timer X Pulse Width Measurement Mode Used” is revised
64
Fig. 62 is revised
65
Fig. 63 is revised
76
Fig. 73 is revised
Table 17 is revised
4
Table 1: LCD drive control circuit; Duty “Static” added
17
<Notes>: added
19
Fig. 11: 0FFE16, 0FFF16; “Reserved” added
20
• Direction Registers (Ports P0-P6, P72-P74) “Depending on the pin, .... may be
read.” is deleted
(6/7)
REVISION HISTORY
Rev.
Date
3.04
May 20 2008
38D5 Group Data Sheet
Description
Page
Summary
21”
Table 9: “P45/SIN2/(KW1)” → “P45/SOUT2/(KW1)”
“P42/SCLK2/(KW2)” → “P46/SCLK2/(KW2)”
“P43/SRDY2/(KW3)” → “P47/SRDY2/(KW3)”
22
Fig. 14 is revised
27
Table 10: “P20/SEG0-P27/SEG7” → “P20/SEG0/(KW4)-P27/SEG7”
68
Fig. 64: “P20/SEG0(KW4)” → “P20/SEG0/(KW4)”
“P21/SEG1(KW5)” → “P21/SEG1/(KW5)”
“P22/SEG2(KW6)” → “P22/SEG2/(KW6)”
“P23/SEG3(KW7)” → “P23/SEG3/(KW7)”
69
Fig. 65: “P22/SEG2(KW6)” → “P22/SEG2/(KW6)”
“P23/SEG3(KW7)” → “P23/SEG3/(KW7)”
“P56/AN10” → “P56/AN6”
77
Fig. 73 is revised
89
Fig. 81: “P56/AN10” → “P56/AN6”
94, 133
Notes On QzROM Writing Orders is revised
All trademarks and registered trademarks are the property of their respective owners.
(7/7)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2