LINER LT1641-1CS8 Positive high voltage hot swap controller Datasheet

LT1641-1/LT1641-2
Positive High Voltage
Hot Swap Controllers
U
FEATURES
DESCRIPTIO
■
The LT®1641-1/LT1641-2 are 8-pin Hot SwapTM controllers that allow a board to be safely inserted and removed
from a live backplane. Using an external N-channel pass
transistor, the board supply voltage can be ramped up at
a programmable rate. A high side switch driver controls an
N-channel gate for supply voltages ranging from 9V to
80V.
■
■
■
■
■
■
■
■
■
Allows Safe Board Insertion and Removal from a
Live Backplane
Controls Supply Voltage from 9V to 80V
Programmable Analog Foldback Current Limiting
High Side Drive for an External N-Channel
Latched Operation Mode (LT1641-1)
Automatic Retry (LT1641-2)
User Programmable Supply Voltage Power-Up Rate
Undervoltage Lockout
Overvoltage Protection
Both are available in 8-Lead SO Package
The chips feature a programmable analog foldback current limit circuit. If the chips remain in current limit for
more than a programmable time, the N-channel pass
transistor is either latched off (LT1641-1) or is set to
automatically restart after a time-out delay (LT1641-2).
U
APPLICATIO S
■
■
■
■
The PWRGD output indicates when the output voltage,
sensed by the FB pin, is within tolerance. The ON pin
provides programmable undervoltage lockout.
Hot Board Insertion
Electronic Circuit Breaker
Industrial High Side Switch/Circuit Breaker
24V/48V Industrial/Alarm Systems
The LT1641-1/LT1641-2 are available in the 8-lead SO
package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
24V Input Voltage Application
Q1
IRF530
RS
0.01Ω
VIN
24V
VOUT
SHORT
PIN
R1
49.9k
1%
D1
CMPZ
5248B
R5
10Ω
5%
CL
R3
59k
1%
C1
R6, 10nF
1k, 5%
VCC
*SMAT70A
SENSE
R7
24k
5%
GATE
ON
FB
LT1641-1/LT1641-2
R2
3.4k
1%
PWRGD
TIMER
R4
3.57k
1%
PWRGD
GND
C2
0.68µF
GND
*DIODES, INC.
1641-1 TA01
164112fc
1
LT1641-1/LT1641-2
U
W W
W
ABSOLUTE
AXI U RATI GS
(Note 1)
Supply Voltage (VCC) ...............................– 0.3V to 100V
Input Voltage (SENSE) .............................– 0.3V to 100V
Input Voltage (TIMER) ...............................– 0.3V to 44V
Input Voltage (FB, ON) ...............................– 0.3V to 60V
Output Voltage (PWRGD) ........................– 0.3V to 100V
Output Voltage (GATE) ............................– 0.3V to 100V
Operating Temperature Range
LT1641-1C, LT1641-2C ........................... 0°C to 70°C
LT1641-1I, LT1641-2I ........................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ON 1
8
VCC
FB 2
7
SENSE
PWRGD 3
6
GATE
GND 4
5
TIMER
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 110°C/W
S8 PART MARKING
16411
16411I
16412
16412I
ORDER PART NUMBER
LT1641-1CS8
LT1641-1IS8
LT1641-2CS8
LT1641-2IS8
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Vcc = 24V
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC
VCC Operating Range
ICC
VCC Supply Current
VLKO
VCC Undervoltage Lockout
VFBH
FB Pin High Voltage Threshold
VFBL
FB Pin Low Voltage Threshold
VFBHST
FB Pin Hysteresis Voltage
IINFB
FB Pin Input Current
∆VFB
FB Pin Threshold Line Regulation
9V ≤ VCC ≤ 80V
●
VSENSETRIP
SENSE Pin Trip Voltage (VCC – VSENSE)
VFB = 0V
VFB = 1V
●
●
8
39
12
47
17
55
IGATEUP
GATE Pin Pull-Up Current
Charge Pump On, VGATE = 7V
●
–5
– 10
– 20
µA
IGATEDN
GATE Pin Pull-Down Current
Any Fault Condition, VGATE = 2V
●
35
70
100
mA
∆VGATE
External N-Channel Gate Drive
VGATE – VCC, VCC = 10.8V to 20V
VCC = 20V to 80V
●
●
4.5
10
18
18
V
V
ITIMERUP
TIMER Pin Pull-Up Current
VTIMER = 0V
●
– 24
– 80
– 132
µA
ITIMERON
TIMER Pin Pull-Down Current
VTIMER = 1V
●
1.5
3
5
µA
VONH
ON Pin High Threshold
ON Low to High Transition
●
1.280
1.313
1.345
V
VONL
ON Pin Low Threshold
ON High to Low Transition
●
1.221
1.233
1.245
V
VONHYST
ON Pin Hysteresis
IINON
ON Pin Input Current
VON = GND
–1
µA
VOL
PWRGD Output Low Voltage
IO = 2mA
IO = 4mA
●
●
0.4
2.5
V
V
IOH
PWRGD Pin Leakage Current
VPWRGD = 80V
●
10
µA
●
ON = 3V
TYP
9
●
MAX
UNITS
80
V
2
5.5
mA
●
7.5
8.3
8.8
V
FB Low to High Transition
●
1.280
1.313
1.345
V
FB High to Low Transition
●
1.221
1.233
1.245
80
VFB = GND
V
mV
–1
0.05
80
µA
mV/V
mV
mV
mV
164112fc
2
LT1641-1/LT1641-2
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = 24V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tPHLON
ON Low to GATE Low
Figures 1, 2
6
µs
tPLHON
ON High to GATE High
Figures 1, 2
1.7
µs
tPHLFB
FB Low to PWRGD Low
Figures 1, 3
3.2
µs
tPLHFB
FB High to PWRGD High
Figures 1, 3
tPHLSENSE
(VCC – SENSE) High to GATE Low
Figures 1, 4
µs
1.5
0.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
1
µs
2
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs VCC
3.0
48V
85°C
3.0
1.250
2.5
25°C
2.5
FB PIN LOW VOLTAGE THRESHOLD (V)
3.5
24V
–45°C
2.0
2.0
ICC (mA)
ICC (mA)
FB Pin Low Voltage Threshold vs
Temperature
ICC vs Temperature
1.5
1.5
1.0
1.0
0.5
0.5
0
0
20
40
60
VCC (V)
80
0
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
1641-1 G01
1.230
1.225
1.220
1.215
1.210
1.205
1.200
–50
100
0.090
1.320
0.085
1.315
1.310
1.305
1.300
1.295
0.065
0.060
0.055
0.045
1641-1 G04
0.040
–50
100
VCC = 48V
–7
0.070
1.285
100
–6
0.075
0.050
75
75
–5
VCC = 48V
0.080
1.290
0
25
50
TEMPERATURE (°C)
0
25
50
TEMPERATURE (°C)
IGATE Pull Up vs Temperature
IGATE PULL UP (µA)
0.095
1.325
–25
–25
1641-1 G03
0.100
VCC = 48V
FB PIN HYSTERESIS (V)
FB PIN HIGH VOLTAGE THRESHOLD (V)
1.235
FB Pin Hysteresis vs Temperature
1.335
1.280
–50
1.240
1641-1 G02
FB Pin High Voltage Threshold vs
Temperature
1.330
VCC = 48V
1.245
–8
–9
–10
–11
–12
–25
0
25
50
TEMPERATURE (°C)
75
100
1641-1 G05
–13
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1641-1 G06
164112fc
3
LT1641-1/LT1641-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gate Drive vs Temperature
16
15
14
GATE DRIVE (VGATE – VCC) (V)
VCC = 48V
13
12
11
10
9
8
VCC = 10.8V
7
TA = 25°C
14
12
10
8
0
25
50
TEMPERATURE (°C)
75
0
100
20
40
VCC (V)
60
TA = –45°C
TA = 0°C
10
TA = 25°C
TA = 85°C
6
70
90
1.330
1.325
1.320
1.315
1.310
1.305
1.300
1.295
1.290
1.285
–50
ON Pin Voltage Hysteresis vs
Temperature
–25
0
25
50
TEMPERATURE (°C)
75
1.233
1.231
1.229
1.227
1.225
1.223
–50
0.080
0.070
0.060
14
12
10
8
TA = –45°C
6
4
TA = 25°C
TA = 85°C
2
75
100
1641-1 G13
75
100
50
16
0
25
50
TEMPERATURE (°C)
0
25
50
TEMPERATURE (°C)
SENSE Pin Regulation Voltage vs
VFEEDBACK
VCC = 48V
18
0.090
–25
–25
1641-1 G12
20
PWRGD VOUT LOW (V)
ON PIN LOW VOLTAGE HYSTERESIS (V)
100
1.235
PWRGD VOUT Low vs ILOAD
VCC = 48V
100
VCC = 48V
1.237
1641-1 G11
0.100
75
1.239
VCC = 48V
1641-1 G10
0.050
–50
0
25
50
TEMPERATURE (°C)
ON Pin Low Voltage Threshold vs
Temperature
ON PIN LOW VOLTAGE THRESHOLD (V)
ON PIN HIGH VOLTAGE THRESHOLD (V)
TIMER PIN PULL UP CURRENT (µA)
14
50
VCC (V)
–25
1641-1 G09
1.335
30
–90
ON Pin High Voltage Threshold vs
Temperature
16
10
–80
1641-1 G08
TIMER Pin Pull Up Current vs VCC
8
–70
–110
–50
80
1641-1 G07
12
–60
–100
6
–25
VCC = 48V
–50
0
SENSE PIN REGULATION VOLTAGE (mV)
6
–50
–40
TIMER PIN PULL UP CURRENT (µA)
16
GATE DRIVE (VGATE – VCC) (V)
TIMER Pin Pull Up Current vs
Temperature
Gate Drive vs VCC
VCC = 48V
TA = 25°C
45
40
35
30
25
20
15
10
5
0
10
30
50
ILOAD (mA)
70
90
1641-1 G14
0
0.2
0.4
0.6
VFEEDBACK (V)
0.8
1
1641-1 G15
164112fc
4
LT1641-1/LT1641-2
U
U
U
PI FU CTIO S
ON (Pin 1): The ON pin is used to implement undervoltage
lockout. When the ON pin is pulled below the 1.233V Highto-Low threshold voltage, an undervoltage condition is
detected and the GATE pin is pulled low to turn the
MOSFET off. When the ON pin rises above the 1.313V
Low-to-High threshold voltage, the MOSFET is turned on
again.
Pulsing the ON pin low after a current limit fault will reset
the fault latch and allow the part to turn back on.
FB (Pin 2): Power Good Comparator Input. It monitors the
output voltage with an external resistive divider. When the
voltage on the FB pin is lower than the High-to-Low
threshold of 1.233V, the PWRGD pin is pulled low and
released when the FB pin is pulled above the 1.313V Lowto-High threshold.
GATE (Pin 6): The High Side Gate Drive for the External
N-Channel. An internal charge pump guarantees at least
10V of gate drive for supply voltages above 20V and 4.5V
gate drive for supply voltages between 10.8V and 20V. The
rising slope of the voltage at the GATE is set by an external
capacitor connected from the GATE pin to GND and an
internal 10µA pull-up current source from the charge
pump output.
When the current limit is reached, the GATE pin voltage will
be adjusted to maintain a constant voltage across the
sense resistor while the timer capacitor starts to charge.
If the TIMER pin voltage exceeds 1.233V, the GATE pin will
be pulled low.
The FB pin also effects foldback current limit (see Figure 7
and related discussion).
The GATE pin is pulled to GND whenever the ON pin is
pulled low, the VCC supply voltage drops below the 8.3V
undervoltage lockout threshold or the TIMER pin rises
above 1.233V.
PWRGD (Pin 3): Open Collector Output to GND. The
PWRGD pin is pulled low whenever the voltage at the FB
pin falls below the High-to-Low threshold voltage. It goes
into a high impedance state when the voltage on the FB pin
exceeds the Low-to-High threshold voltage. An external
pull-up resistor can pull the pin to a voltage higher or lower
than VCC.
SENSE (Pin 7): The Current Limit Sense Pin. A sense
resistor must be placed in the supply path between VCC
and SENSE. The current limit circuit will regulate the
voltage across the sense resistor (VCC – VSENSE) to 47mV
when VFB is 0.5V or higher. If VFB drops below 0.5V, the
voltage across the sense resistor decreases linearly and
stops at 12mV when VFB is 0V.
GND (Pin 4): Chip Ground.
To defeat current limit, short the SENSE pin to the VCC pin.
TIMER (Pin 5): Timing Input. An external timing capacitor
at this pin programs the maximum time the part is allowed
to remain in current limit.
VCC (Pin 8): The Positive Supply Input ranges from 9V to
80V for normal operation. ICC is typically 2mA. An internal
undervoltage lockout circuit disables the chip for inputs
less than 8.3V.
When the part goes into current limit, an 77µA pull-up
current source starts to charge the timing capacitor. When
the voltage on the TIMER pin reaches 1.233V, the GATE
pin is pulled low; the pull-up current will be turned off and
the capacitor is discharged by a 3µA pull-down current.
When the TIMER pin falls below 0.5V, the GATE pin either
turns on automatically (LT1641-2) or turns on once the
ON pin is pulsed low to reset the internal fault latch
(LT1641-1). If the ON pin is not cycled low, the GATE pin
remains latched off. Use no less than 1.5nF for the timing
capacitor, C2.
164112fc
5
LT1641-1/LT1641-2
W
BLOCK DIAGRA
VCC
SENSE
VP
VP GEN
FB
–
12mV ~ 47mV
CHARGE
PUMP
AND
GATE
DRIVER
+
+
REF GEN
0.5V
GATE
+
–
PWRGD
1.233V
1.233V
–
+
ON
–
VCC
–
8.3V
+
UNDERVOLTAGE LOCKOUT
LOGIC
+
0.5V
VP
–
80µA
+
1.233V
–
TIMER
3µA
1641-1 BD
GND
TEST CIRCUIT
ON
FB
V+
5V
PWRGD
VCC
24V
SENSE
GATE
5k
GND
+
–
10nF
TIMER
1641-1 F01
Figure 1
164112fc
6
LT1641-1/LT1641-2
W
UW
TI I G DIAGRA S
1.313V
1.313V
1.233V
ON
tPLHON
FB
1.233V
tPLHFB
tPHLON
tPHLFB
1V
1V
PWRGD
GATE
5V
1V
1641-1 F03
1641-1 F02
Figure 2. ON to GATE Timing
Figure 3. FB to PWRGD Timing
VCC – SENSE
47mV
tPHLSENSE
VCC
GATE
1641-1 F04
Figure 4. SENSE to GATE Timing
U
W
U
U
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge up.
The transient currents can permanently damage the connector pins and glitch the system supply, causing other
boards in the system to reset.
The chip is designed to turn on a board’s supply voltage in
a controlled manner, allowing the board to be safely
inserted or removed from a live backplane. The chip also
provides undervoltage and overcurrent protection while a
power good output signal indicates when the output
supply voltage is ready.
Power-Up Sequence
The power supply on a board is controlled by placing an
external N-channel pass transistor (Q1) in the power path
(Figure 5). Resistor RS provides current detection and
capacitor C1 provides control of the GATE slew rate.
Resistor R6 provides current control loop compensation
while R5 prevents high frequency oscillations in Q1.
Resistors R1 and R2 provide undervoltage sensing.
After the power pins first make contact, transistor Q1 is
turned off. If the voltage at the ON pin exceeds the turn-on
threshold voltage, the voltage on the VCC pin exceeds the
undervoltage lockout threshold, and the voltage on the
TIMER pin is less than 1.233V, transistor Q1 will be turned
on (Figure 6). The voltage at the GATE pin rises with a slope
equal to 10µA/C1 and the supply inrush current is set at
IINRUSH = CL • 10µA/C1. If the voltage across the current
sense resistor RS gets too high, the inrush current will then
be limited by the internal current limit circuitry which
adjusts the voltage on the GATE pin to maintain a constant
voltage across the sense resistor.
Once the voltage at the output has reached its final value,
as sensed by resistors R3 and R4, the PWRGD pin goes
high.
164112fc
7
LT1641-1/LT1641-2
U
W
U
U
APPLICATIO S I FOR ATIO
RS
0.025Ω
VIN
24V
Q1
IRF530
SHORT
PIN
D1
CMPZ
5248B
R5
10Ω
5%
R1
49.9k
1%
VOUT
CL
R3
59k
1%
C1
R6, 10nF
1k, 5%
8
VCC
1
7
6
SENSE
GATE
R7
24k
5%
FB
ON
2
R4
3.57k
1%
LT1641-1
R2
3.4k
1%
PWRGD
TIMER
3
PWRGD
GND
5
GND
+
4
C2
0.68µF
1641-1 F05
Figure 5. Typical Application
Short-Circuit Protection
The chip features a programmable foldback current limit
with an electronic circuit breaker that protects against
short-circuits or excessive supply currents. The current
limit is set by placing a sense resistor between VCC (Pin 8)
and SENSE (Pin 7).
To prevent excessive power dissipation in the pass transistor and to prevent voltage spikes on the input supply
during short-circuit conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the FB pin (Figure 7).
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output voltage at the FB
pin increases, the voltage across the sense resistor increases until the FB pin reaches 0.5V, at which point the
voltage across the sense resistor is held constant at 47mV.
The maximum current limit is calculated as:
ILIMIT = 47mV/RSENSE
For a 0.025Ω sense resistor, the current limit is set at
1.88A and folds back to 480mA when the output is shorted
to ground.
Figure 6. Power-Up Waveforms
The IC also features a variable overcurrent response time.
The time required to regulate Q1’s drain current depends
on: Q1’s input capacitance; gate capacitor C1 and compensation resistor R6; and the internal delay from the
SENSE to the GATE pin. Figure 8 shows the delay from a
voltage step at the SENSE pin until the GATE voltage starts
falling, as a function of overdrive.
TIMER
The TIMER pin (Pin 5) provides a method for programming the maximum time the chip is allowed to operate in
current limit. When the current limit circuitry is not active,
the TIMER pin is pulled to GND by a 3µA current source.
After the current limit circuit becomes active, an 80µA pullup current source is connected to the TIMER pin and the
voltage will rise with a slope equal to 77µA/CTIMER as long
as the current limit circuit remains active. Once the desired
maximum current limit time is set, the capacitor value is:
C(nF) = 62 • t(ms).
If the current limit circuit turns off, the TIMER pin will be
discharged to GND by the 3µA current source.
Whenever the TIMER pin reaches 1.233V, either the internal fault latch is set (LT1641-1) or the autorestart latch is
set (LT1641-2). The GATE pin is immediately pulled to
GND and the TIMER pin is pulled back to GND by the 3µA
164112fc
8
LT1641-1/LT1641-2
U
U
W
U
APPLICATIO S I FOR ATIO
VCC – VSENSE
PROPAGATION DELAY
12µs
10µs
47mV
8µs
6µs
4µs
2µs
12mV
0V
0.5V
VFB
50mV
100mV
150mV
200mV
1641-1 F07
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
current source. When the TIMER pin falls below 0.5V, the
GATE pin either turns on automatically (LT1641-2) or once
the ON pin is pulsed low to reset the internal fault latch
(LT1641-1).
The waveform in Figure 9 shows how the output latches off
following a short-circuit. The drop across the sense resistor is held at 12mV as the timer ramps up. Since the output
did not rise bringing FB above 0.5V, the circuit latches off.
For Figure 9, CT = 100nF.
Undervoltage and Overvoltage Detection
The ON pin can be used to detect an undervoltage condition at the power supply input. The ON pin is internally
connected to an analog comparator with 80mV of hysteresis. If the ON pin falls below its threshold voltage (1.233V),
the GATE pin is pulled low and is held low until ON is high
again.
Figure 10 shows an overvoltage detection circuit. When
the input voltage exceeds the Zener diode’s breakdown
voltage, D2 turns on and starts to pull the TIMER pin high.
After the TIMER pin is pulled higher than 1.233V, the fault
latch is set and the GATE pin is pulled to GND immediately,
turning off transistor Q1. The waveforms are shown in
Figure 11. Operation is restored either by interrupting
power or by pulsing ON low.
VCC – VSENSE
1641-1 F08
Figure 8. Response Time to Overcurrent
Power Good Detection
The chip includes a comparator for monitoring the output
voltage. The noninverting input (FB pin) is compared
against an internal 1.233V precision reference and exhibits 80mV hysteresis. The comparator’s output (PWRGD
pin) is an open collector capable of operating from a pullup as high as 100V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 12
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accomplished by transistor Q2 and R7.
Supply Transient Protection
The IC is 100% tested and guaranteed to be safe from
damage with supply voltages up to 100V. However, spikes
above 100V may damage the part. During a short-circuit
condition, the large change in currents flowing through
the power supply traces can cause inductive voltage
spikes which could exceed 100V. To minimize the spikes,
the power trace parasitic inductance should be minimized
by using wider traces or heavier trace plating and a 0.1µF
bypass capacitor placed between VCC and GND. A surge
suppressor at the input can also prevent damage from
voltage surges.
164112fc
9
LT1641-1/LT1641-2
U
W
U
U
APPLICATIO S I FOR ATIO
RS
0.025Ω
VIN
24V
Q1
IRF530
SHORT
PIN
R1
49.9k
1%
D1
CMPZ
5248B
R5
10Ω
5%
8
VCC
7
R7
24k
5%
SENSE GATE
FB
2
R4
3.57k
1%
LT1641-1
R2
3.4k
1%
PWRGD
TIMER
3
PWRGD
GND
5
Figure 9. Short-Circuit Waveforms
CL
R3
59k
1%
6
ON
GND
VOUT
C1
R6, 10nF
1k, 5%
D2
30V
1N5256B
1
+
4
C2
0.68µF
1641-1 F10
Figure 10. Overvoltage Detection
Figure 11. Overvoltage Waveforms
GATE Pin Voltage
A curve of gate drive vs VCC is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applications over a 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
164112fc
10
LT1641-1/LT1641-2
U
U
W
U
APPLICATIO S I FOR ATIO
Layout Considerations
high current applications. To improve noise immunity, put
the resistor divider to the ON pin close to the chip and keep
traces to VCC and GND short. A 0.1µF capacitor from the
ON pin to GND also helps reject induced noise. Figure 14
shows a layout that addresses these issues.
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
Q1
IRF530
RS
0.01Ω
VIN
48V
SHORT
PIN
R5
10Ω
5%
R1
294k
1%
R6,
1k, 5%
8
VCC
UV = 37V
D1
CMPZ
5248B
1
7
6
SENSE
GATE
ON
+
R7
47k
5%
PWRGD
GND
5
VIN +
VOUT +
CL
220µF
VOUT
ON/OFF
VIN –
2
VOUT –
R4
4.22k
1%
LT1641-1
TIMER
ACTIVE LOW
ENABLE MODULE
C1
10nF
FB
R2
10.2k
1%
R3
143k
1%
3
Q2
MMBT5551LT1
4
C2
0.68µF
GND
1641-1 F12
Figure 12. Active Low Enable Module
18
ILOAD
16
R1
8
LT1641-1
GND
VCC
10
SENSE
SENSE
RESISTOR, RS
12
ON
VGATE – VCC (V)
14
6
4
R2
2
0
8
13
18
VCC (V)
23
ILOAD
1641-1 F13
Figure 13. Gate Drive vs Supply Voltage
1641-1 F14
Figure 14. Recommended Layout for R1, R2 and RS
164112fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1641-1/LT1641-2
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640A
Negative High Voltage Hot Swap Controller
Controls an N-FET at Negative Side to – 80V
LTC1421
Dual Channel Hot Swap Controller
Operates Two Supplies from 3V to 12V and a Third to –12V
LTC1422
High Side Drive Hot Swap Controller in SO-8
System Reset Output with Programmable Delay
LTC1643
PCI Hot Swap Controller
3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1642
Fault Protected Hot Swap Controller
Operates from 3V to 16.5V, Handles Surges to 33V
LT4250
Negative 48V Hot Swap Controller
Active Current Limiting for Supplies from – 20V to – 80V
164112fc
12
Linear Technology Corporation
LT/LWI 0706 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001