1. Features • • • • • • • • • • • • Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x 14 mm = 0.02" x 0.55" Image Array: 8 x 280 = 2240 pixels Pixel Pitch: 50 µm x 50 µm = 500 dpi Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second Die Size: 1.64 x 17.46 mm Operating Voltage: 3V to 3.6V Naturally Protected Against ESD: > 16 kV Air Discharge Power Consumption: 16 mW at 3.3V, 1 MHz, 25°C Operating Temperature Range: -40°C to +85°C Chip-on-Board (COB), Chip-on-Board (COB) with Connector Complies With the European Directive for Restriction of Hazardous Substances (RoHS Directive) 2. Applications • • • • • • • • PDA (Access Control, Data Protection) Notebook, PC-add on (Access Control, e-business) PIN Code Replacement Automated Teller Machines, POS Building Access Electronic Keys (Cars, Home) Portable Fingerprint Imaging for Law Enforcement TV Access Figure 2-1. Thermal Fingerprint Sensor with 0.4 mm x 14 mm (0.02" x 0.55") Sensing Area and Digital Output (On-chip ADC) FingerChip® Packages AT77C102B FingerChip® Chip-on-board Package with Connector Chip-on-board Package (COB) Actual size Rev. 5364A–BIOM–09/05 Table 2-1. Pin Description for Chip-on-Board Package: AT77C102B-CB01YV Pin Number Name Type 1 GND GND 2 AVE Analog output 3 AVO Analog output 4 TPP Power 5 TPE Digital input 6 VCC Power 7 GND GND 8 RST Digital input 9 PCLK Digital input 10 OE Digital input 11 ACKN Digital output 12 De0 Digital output 13 Do0 Digital output 14 De1 Digital output 15 Do1 Digital output 16 De2 Digital output 17 Do2 Digital output 18 De3 Digital output 19 Do3 Digital output 20 FPL GND 21 GND GND The die attach is connected to pins 1, 7 and 21, and must be grounded. The FPL pin must be grounded. 2 GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND 21 AT77C102B 5364A–BIOM–09/05 AT77C102B Table 2-2. Note: Pin Description for COB with Connector Package: AT77C102B-CB02YV(1) Pin Number Name Type 1 FPL GND 2 Not connected 3 Not connected 4 DE3 Digital output 5 DO3 Digital output 6 DE2 Digital output 7 DO2 Digital output 8 DE1 Digital output 9 DO1 Digital output 10 DE0 Digital output 11 DO0 Digital output 12 AVE Analog output 13 AVO Analog output 14 TPP Power 15 TPE Digital input 16 VCC Power 17 GND GND 18 RST Digital input 19 PCLK Digital input 20 OE Digital input 21 ACKN Digital output 1. Ref. Connector: FH18-21S-0.3SHW (HIROSE). 3 5364A–BIOM–09/05 Figure 2-2. COB with Flex(1) Flex with metallizations up Flex with metallizations down Figure 2-3. Flex Output Side Flex Output (FingerChip Connector Side) Metallizations Up 1 3 2 Note: 4 1. Flex is not provided by Atmel. AT77C102B 5364A–BIOM–09/05 AT77C102B 3. Description The AT77C102B is part of the Atmel FingerChip monolithic fingerprint sensor family for which no optics, no prism and no light source are required. The AT77C102B is a single-chip, high-performance, low-cost sensor based on temperature physical effects for fingerprint sensing. The AT77C102B has a linear shape, which captures a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary software can reconstruct a full 8-bit fingerprint image. The AT77C102B has a small surface combined with CMOS technology, and a Chip-on-Board package assembly. These facts contribute to a low-cost device. The device delivers a programmable number of images per second, while an integrated analogto-digital converter delivers a digital signal adapted to interfaces such as an EPP parallel port, a USB microcontroller or directly to microprocessors. No frame grabber or glue interface is therefore necessary to send the frames. These facts make AT77C102B an easy device to include in any system for identification or verification applications. Table 3-1. Absolute Maximum Ratings() Parameter Symbol Comments Value Positive supply voltage VCC GND to 4.6 Temperature stabilization power TPP GND to 4.6 Front plane FPL GND to VCC +0.5 Digital input voltage RST PCLK GND to VCC +0.5 Storage temperature Tstg -50 to +95 Lead temperature (soldering, 10 seconds) Table 3-2. Tleads Do not solder Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Forbidden Recommended Conditions Of Use Parameter Symbol Positive supply voltage VCC Front plane FPL Comments Min Typ Max Unit 3V 3.3V 3.6V V Must be grounded GND V Digital input voltage CMOS levels V Digital output voltage CMOS levels V 50 Digital load CL Analog load CA RA Not connected Operating temperature range Tamb V grade Maximum current on TPP ITPP pF pF kΩ -40°C to +85°C 0 °C 100 mA 5 5364A–BIOM–09/05 Table 3-3. Resistance Parameter Min Value Standard Method On pins. HBM (Human Body Model) CMOS I/O 2 kV MIL-STD-883 - method 3015.7 On die surface (Zapgun) Air discharge ±16 kV NF EN 6100-4-2 200 000 MIL E 12397B 4 hours Internal method ESD Mechanical Abrasion Number of cycles without lubricant multiply by an estimated factor of 20 for correlation with a real finger Chemical Resistance Cleaning agent, acid, grease, alcohol, diluted acetone Table 3-4. Specifications Explanation Of Test Levels I 100% production tested at +25°C II 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample) III Sample tested only IV Parameter is guaranteed by design and/or characterization testing V Parameter is a typical value only VI 100% production tested at temperature extremes D 100% probe tested on wafer at Tamb = +25°C Table 3-5. Physical Parameter Parameter Test Level Resolution IV 50 µm Size IV 8 x 280 Pixel Yield: number of bad pixels I Equivalent resistance on TPP pin I 6 Min 20 Typ 30 Max Unit 5 Bad pixels 47 Ω AT77C102B 5364A–BIOM–09/05 AT77C102B . Table 3-6. 3.3V Power supply The following characteristics are applicable to the operating temperature -40°C ≤ Ta ≤ +85°C Typical conditions are: VCC = +3.3 V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified Parameter Symbol Test Level Min Typ Max Unit 3.0 3.3 3.6 V Power Requirements Positive supply voltage VCC Active current on VCC pin, 1 MHz Current on VCC pin, in static mode Cload = 0 pF ICC I IV 5 4 7 5 mA mA Power dissipation on VCC Cload = 0 PCC I IV 16 13 25 18 mW mW ICCNAP I 10 µA VAVx IV 2.9 V Current on VCC in NAP mode Analog Output Voltage range 0 Digital Inputs Logic compatibility CMOS Logic “0” voltage VIL I 0 0.8 V Logic “1” voltage VIH I 2.3 VCC V Logic “0” current IIL I -10 0 µA Logic “1”current IIH I 0 10 µA TPE logic “0” voltage IILTPE 1 -10 0 µA TPE logic “1” voltage IIHTPE 1 0 300 µA 0.6 V Digital Outputs Logic compatibility VOL I (1) VOH I Logic “0” voltage Logic “1” voltage Note: CMOS (1) 2.4 V 1. With IOL = 1 mA and IOH = -1 mA 7 5364A–BIOM–09/05 . Table 3-7. Switching Performances The following characteristics are applicable to the operating temperature -40°C ≤ Ta ≤ +85°C Typical conditions are: nominal voltage; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital and analog outputs unless otherwise specified Parameter Symbol Test Level Min Typ Max Unit Clock frequency fPCLK I 0.5 1 2 MHz Clock pulse width (high) tHCLK I 250 ns Clock pulse width (low) tLCLK I 250 ns Clock setup time (high)/reset falling edge tSetup I No data change tNOOE IV 100 ns Reset pulse width high tHRST IV 50 ns Parameter Symbol Test Level Min Output delay from PCLK to ACKN rising edge tPLHACKN Output delay from PCLK to ACKN falling edge Table 3-8. 0 ns 3.3V ±10% Power Supply Max Unit I 145 ns tPHLACKN I 145 ns tPDATA I 120 ns tPAVIDEO I 250 ns Output delay from OE to data high-Z tDATAZ IV 34 ns Output delay from OE to data output tZDATA IV 47 ns Output delay from PCLK to data output Dxi Output delay from PCLK to analog output AVx Figure 3-1. Typ Reset Reset RST tHRST Clock PCLK tSETUP 8 AT77C102B 5364A–BIOM–09/05 AT77C102B Figure 3-2. Read One Byte/Two Pixels fPCLK tLCLK tHCLK Clock PCLK Acknowledge ACKN tPLHACKN Data output Do0-3, De0-3 Video analog output AVO, AVE tPHLACKN Data #N-1 Data #N Data #N+1 Data #N Data #N+1 t PDATA Data #N+2 tPAVIDEO Figure 3-3. Output Enable Output enable OE Data output Do0-3, De0 -3 Hi-Z tZDATA tDATAZ Data output Hi-Z 9 5364A–BIOM–09/05 Figure 3-4. No Data Change tNOOE PCLK OE Note: OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data are not driving current, so as to reduce the noise level on the power supply. Figure 3-5. AT77C102B Block Diagram Clock PCLK ACKN Reset RST Line sel Column selection Even 1 dummy column 1 8 lines of 280 columns of pixels TPP 3.1 TPE De0-3 8 Latches 8 Odd Chip temperature stabilization 4 Amp 2240 8 4-bit ADC Chip temperature sensor Analog output AVE AVO 4-bit ADC Do0-3 4 Output enable OE Functional Description The circuit is divided into two main sections: sensor and data conversion. One particular column among 280 plus one is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to the amplifiers (2) [one per line], then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4bit analog-to-digital converters (3), so two pixels can be read for each clock pulse (4). 10 AT77C102B 5364A–BIOM–09/05 AT77C102B Figure 3-6. Functional Description 1 2 Column selection 3 Line sel 8 lines of 280 columns of pixels Even 4-bit ADC 4 4 De0-3 8 latches Amp 8 1 dummy column Odd 4-bit ADC Do0-3 4 Chip temperature sensor 3.2 Sensor Each pixel is a sensor in itself. The sensor detects a temperature difference between the beginning of an acquisition and the reading of the information: this is the integration time. The integration time begins with a reset of the pixel to a predefined initial state. Note that the integration time reset has nothing to do with the reset of the digital section. Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature variation between the reset and the end of the integration time, and for the duration of the integration time, electrical charges are generated at the pixel level. 3.3 Analog-to-digital Converter/ Reconstructing an 8-bit Fingerprint Image An analog-to-digital converter (ADC) is used to convert the analog signal coming from the pixel into digital data that can be used by a processor. As the data rate for the parallel port and the USB is in the range of 1 MB per second, and at least a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping speed of the finger, two 4-bit ADCs have been used to output two pixels at a time on one byte. 3.4 Start Sequence A reset is not necessary between each frame acquisition. The start sequence must consist in: 1. Setting the RST pin to high. 2. Setting the RST pin to low. 3. Sending 4 clock pulses (due to pipe-line). 4. Sending clock pulses to skip the first frame. Note that after a reset it is recommended to skip the first 200 slices to stabilize the acquisition. Figure 3-7. Start Sequence 4 + 1124 clock pulses to skip the first frame Reset RST Clock PCLK 1 2 3 4 1 1124 1 11 5364A–BIOM–09/05 3.5 Reading the Frames A frame consists of 280 true columns plus one dummy column of eight pixels. As two pixels are output at a time, a system must send 281 x 4 = 1124 clock pulses to read one frame. Reset must be low when reading the frames. 3.6 Read One Byte/Output Enable The clock is taken into account on its falling edge and data is output on its rising edge. For each clock pulse, after the start sequence, a new byte is output on the Do0-3 and De0-3 pins. This byte contains two pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even pixels). To output the data, the output enable (OE) pin must be low. When OE is high, the Do0-3 and De0-3 pins are in high-impedance state. This facilitates an easy connection to a microprocessor bus without additional circuitry since the data output can be enabled using a chip select signal. Note that the AT77C102B always sends data: there is no data exchange to switch to read/write mode. 3.7 Power Supply Noise IMPORTANT: When a falling edge is applied on OE (that is when the Output Enable becomes active), then some current is drained from the power supply to drive the eight outputs, producing some noise. It is important to avoid such noise just after the PCLK clock’s falling edge, when the pixels’ information is evaluated: the timing diagram (Figure 3-2) and time TNOOE define the interval time when the power supply must be as quiet as possible. 3.8 Video Output An analog signal is also available on pins AVE and AVO. Note that video output is available one clock pulse before the corresponding digital output (one clock pipe-line delay for the analog to digital conversion). 3.9 Pixel Order After a reset, pixel 1 is located on the upper left corner, looking at the chip with bond pads to the right. For each column of eight pixels, pixels 1, 3, 5 and 7 are output on odd data Do0-3 pins, and pixels 2, 4, 6 and 8 are output on even data De0-3 pins. The Most Significant Bit (MSB) is bit 3, and the Least Significant Bit is bit 0. Figure 3-8. Pixel Order Pixel #1 (1,1) Pixel #2233 (280,1) B ond pads Pixel #8 (1,8) 12 Pixel #2240 (280,8) AT77C102B 5364A–BIOM–09/05 AT77C102B 3.10 Synchronization: The Dummy Column A dummy column has been added to the sensor to act as a specific pattern to detect the first pixel. Therefore, 280 true columns plus one dummy column are read for each frame. The four bytes of the dummy column contain a fixed pattern on the first two bytes, and temperature information on the last two bytes. Table 1. Dummy Column Description Dummy Byte Odd Even Dummy Byte 1 DB1: 111X 0000 Dummy Byte 2 DB2: 111X 0000 Dummy Byte 3 DB3: rrrr nnnn Dummy Byte 4 DB4: tttt pppp Note: x represents 0 or 1 The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock pulses), so it is an easy pattern to recognize for synchronization purposes. 3.11 Thermometer The dummy bytes DB3 and DB4 contain some internal temperature information. The even nibble nnnn in DB3 can be used to measure an increase or decrease of the chip’s temperature, using the difference between two measures of the same physical device. The following table gives values in Kelvin. Table 1. Temperature Table nnnn Decimal nnnn Binary Temperature differential with code 8 in Kelvin 15 1111 > 11.2 14 1110 8.4 13 1101 7 12 1100 5.6 11 1011 4.2 10 1010 2.8 9 1001 1.4 8 1000 0 7 0111 -1.4 6 0110 -2.8 5 0101 -4.2 4 0100 -5.6 3 0011 -7 2 0010 -8.4 1 0001 -11.2 0 0000 < -16.8 13 5364A–BIOM–09/05 For code 0 and 15, the absolute value is a minimum (saturation). When the image contrast becomes faint because of a low temperature difference between the finger and the sensor, it is recommended to use the temperature stabilization circuitry to increase the temperature by two codes (that is from 8 to 10), so as to obtain a sensor increase of at least >1.4 Kelvin. This enables enough contrast to obtain a proper fingerprint reconstruction. 3.12 Integration Time and Clock Jitter The AT77C102B is not very sensitive to clock jitters (clock variations). The most important requirement is a regular integration time that ensures the frame reading rate is also as regular as possible, so as to obtain consistent fingerprint slices. If the integration time is not regular, the contrast can vary from one frame to another. Note that it is possible to introduce some waiting time between each set of 1124 clock pulses, but the overall time of one frame read must be regular. This waiting time is generally the time needed by the processor to perform some calculation over the frame (to detect the finger, for instance). Figure 3-9. Read One Frame Reset RST is low 1 Column 1 2 3 Column 2 4 5 Column 280 6 1119 Dummy Column 281 1120 1121 1122 1123 1124 7&8 DB1 DB2 DB3 DB4 Clock PCLK Pixels 1 & 2 3&4 5&6 7&8 1&2 3&4 Figure 3-10. Regular Integration Time REGULAR INTEGRATION TIME Frame n Frame n+1 Frame n+2 Frame n+3 Clock PCLK 1124 pulses 1124 pulses 3.13 Power Management 3.14 Nap Mode 1124 pulses 1124 pulses Several strategies are possible to reduce power consumption when the device is not in use. The simplest and most efficient is to cut the power supply using external means. A nap mode is also implemented in the AT77C102B. To activate this nap mode, you must: 1. Set the reset RST pin to high. By doing this, all analog sections of the device are internally powered down. 2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section. 3. Set the TPE pin to low to stop the temperature stabilization feature. 4. Set the Output Enable OE pin to high, so that the output is forced in HiZ. 14 AT77C102B 5364A–BIOM–09/05 AT77C102B Figure 3-11. Nap Mode Nap mode Reset RST Nap Clock PCLK In nap mode, all internal transistors are in shut mode. Only leakage current is drained in the power supply, generally less than the tested value. 3.15 Static Current Consumption When the clock is stopped (set to 1) and the reset is low (set to 0), the device’s analog sections drain some current, whereas, if the outputs are connected to a standard CMOS input, the digital section does not consume any current (no current is drained in the I/O). In this case the typical current value is 5 mA. This current does not depend on the voltage (it is almost the same from 3 to 3.6V). 3.16 Dynamic Current Consumption When the clock is running, the digital sections, and particularly the outputs if they are heavily loaded, consume current. In any case, the current should be less than the testing machine (120 pF load on each I/O), and a maximum of 50 pF is recommended. The AT77C102B, running at about 1 MHz, consumes less than 7 mA on the VCC pin. 3.17 Temperature Stabilization Power Consumption (TPP Pin) When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by the internal equivalent resistance given in Table 3-4 on page 6 and a possible external resistor. Most of the time, TPE is set to 0 and no current is drained in TPP. When the image contrast becomes low because of a low temperature differential (less than 1 Kelvin), then it is recommended to set TPE to 1 for a short time so that the dissipated power in the chip elevates the temperature, allowing contrast recovery. The necessary time to increase the chip’s temperature by one Kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and its surroundings. As a rule of thumb, dissipating 300 mW in the chip elevates the temperature by 1 Kelvin in one second. With the 30Ω typical value, 300 mW is 3V applied on TPP. If the power supply is 3.6V, an external resistor must be added in the application to limit the current under 100 mA. 15 5364A–BIOM–09/05 4. Packaging: Mechanical Data Figure 4-1. Product Reference: AT77C102B-CB01YV 0.2 A Top View (all dimensions in mm) 0.89 ±0.3 14 TOP VIEW SCALE 10/1 0.32 2.33 ±0.5 2.95 ±0.50 5.90 max 9 ±0.3 A +0.07 1.64 -0.01 At 0.4 heigh from B ref. 0.82 ±0.50 0.2 min 5.20 max 26.6 ±0.3 Dam and Fill B 0.74 ±0.06 SIDE VIEW 1.5 max. SCALE 10/1 0.2 max 0.82 ±0.18 Figure 4-2. Product Reference: AT77C102B-CB01YV Bottom View (All dimensions in mm) 1 +_ 0.08 0.5+_ 0.08 1.15 +_ 0.15 3.5 +_ 0.08 2.15 +_ 0.15 1 +_ 0.15 1.5 +_ 0.08 6.30 +_ 0.1 +0.08 RO. 75 -0.12 (x3) 2 +_0.08 2 +_ 0.15 0.75+0.33 - 0.25 23.85 +_ 0.1 1.5 +0.15 (x3) - 0.23 16 AT77C102B 5364A–BIOM–09/05 AT77C102B Figure 4-3. Product Reference: AT77C102B-CB02YV All Dimensions in mm +0.04 5.2 max 14.32 -0.01 9.85 ±0.3 0.74 +_ 0.06 5.9 max 8.9 ±0.5 FLEX OUTPUT 4.1 ±0.2 8.8 ±0.2 2.9±0.5 +0.33 4.1±0.5 0.75 -0.25 1.25 ±0.5 +0.15 1.5-0.23 (x 3) 0.82 ± 0.18 1.9±0.4 1.5 MAX Scale 4/1 0.2 min 2.39 ±0.5 26.6 ±0.3 +0.08 4.1.1 FLEX OUTPUT 6.3 ±0.1 1.78 ±0.5 (x 2) +0.07 1.64 -0.01 4.1 A R0.75 -0.12 (x 3) A Package Information Electrical Disturbances When looking at the fingerchip device from the top with the glob top to the right, the right edge must never be in contact with customer casing or any component to avoid electrical disturbances. Figure 4-4. Epoxy Overflow Maximum epoxy overflow width: 0.55 mm on the die edge. Maximum epoxy overflow thickness: 0.33 mm. 0.55 0.33 AA Section Fingerchip Note: Epoxy Glue Overflow Refer to Figure 4-1 on page 16. 17 5364A–BIOM–09/05 5. Ordering Information 5.1 Package Device AT77C Atmel prefix FingerChip family 102B- CBXX Y V — Quality level: — : standard Device type Package CB01: Chip On Board (COB) CB02: COB with connector Temperature range o V: -40 C to +85o C RoHS compliant 18 AT77C102B 5364A–BIOM–09/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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