Intersil CA3130A 15mhz, bimos operational amplifier with mosfet input/cmos output Datasheet

CA3130, CA3130A
®
Data Sheet
August 1, 2005
15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply terminal, an important
attribute in single-supply applications.
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.
FN817.6
Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ)
- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers
• The CA3130A offers superior input characteristics over
those of the CA3130.
Ordering Information
PART NO.
(BRAND)
CA3130AE
CA3130AM
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
PKG.
DWG. #
E8.3
M8.15
(3130A)
CA3130AM96
-55 to 125
(3130A)
CA3130AMZ
-55 to 125
(3130AZ) (Note)
CA3130AMZ96
-55 to 125
(3130AZ) (Note)
CA3130E
CA3130EZ
(Note)
CA3130M
-55 to 125
-55 to 125
-55 to 125
8 Ld SOIC
Tape and Reel
8 Ld SOIC
(Pb-free)
8 Ld SOIC
Tape and Reel (Pb-free)
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
8 Ld SOIC
M8.15
M8.15
-55 to 125
(3130)
CA3130MZ
-55 to 125
(3130MZ) (Note)
CA3130MZ96
(3130MZ)
-55 to 125
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
• Peak Detectors
• Single-Supply Full-Wave Precision Rectifiers
• Photo-Diode Sensor Amplifiers
Pinout
CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW
M8.15
E8.3
E8.3
M8.15
(3130)
CA3130M96
• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
8 Ld SOIC
M8.15
Tape and Reel
8 Ld SOIC
M8.15
(Pb-free)
8 Ld SOIC
M8.15
Tape and Reel (Pb-free)
OFFSET
NULL
INV.
INPUT
NON-INV.
INPUT
1
V-
4
8
STROBE
2
-
7
V+
3
+
6
OUTPUT
5
OFFSET
NULL
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not
intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3130, CA3130A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . .
115
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
VS = ±7.5V
CA3130
CA3130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
8
15
-
2
5
mV
-
10
-
-
10
-
µV/oC
Input Offset Voltage
|VIO|
Input Offset Voltage
Temperature Drift
∆VIO/∆T
Input Offset Current
|IIO|
VS = ±7.5V
-
0.5
30
-
0.5
20
pA
II
VS = ±7.5V
-
5
50
-
5
30
pA
50
320
-
50
320
-
kV/V
94
110
-
94
110
-
dB
CMRR
70
90
-
80
90
-
dB
VICR
0
-0.5 to 12
10
0
-0.5 to 12
10
V
-
32
320
-
32
150
µV/V
Input Current
Large-Signal Voltage Gain
AOL
Common-Mode
Rejection Ratio
Common-Mode Input
Voltage Range
∆VIO/∆VS
Power-Supply
Rejection Ratio
Maximum Output Voltage
Maximum Output Current
VO = 10VP-P
RL = 2kΩ
VS = ±7.5V
VOM+
RL = 2kΩ
12
13.3
-
12
13.3
-
V
VOM-
RL = 2kΩ
-
0.002
0.01
-
0.002
0.01
V
VOM+
RL = ∞
14.99
15
-
14.99
15
-
V
VOM-
RL = ∞
-
0
0.01
-
0
0.01
V
IOM+ (Source) at VO = 0V
12
22
45
12
22
45
mA
IOM- (Sink) at VO = 15V
12
20
45
12
20
45
mA
Supply Current
2
I+
VO = 7.5V,
RL = ∞
-
10
15
-
10
15
mA
I+
VO = 0V,
RL = ∞
-
2
3
-
2
3
mA
CA3130, CA3130A
Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
Input Offset Voltage Adjustment Range
TEST CONDITIONS
10kΩ Across Terminals 4 and 5 or
4 and 1
CA3130,
CA3130A
UNITS
±22
mV
1.5
TΩ
Input Resistance
RI
Input Capacitance
CI
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
eN
BW = 0.2MHz, RS = 1MΩ
(Note 3)
23
µV
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability ≥47pF Required.)
CC = 0
15
MHz
fT
CC = 47pF
4
MHz
Slew Rate:
SR
Open Loop
CC = 0
30
V/µs
Closed Loop
CC = 56pF
10
V/µs
0.09
µs
10
%
1.2
µs
Transient Response:
Rise Time
tr
Overshoot
OS
Settling Time (To <0.1%, VIN = 4VP-P)
CC = 56pF,
CL = 25pF,
RL = 2kΩ
(Voltage Follower)
tS
NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
CA3130
CA3130A
UNITS
Input Offset Voltage
VIO
8
2
mV
Input Offset Current
IIO
0.1
0.1
pA
II
2
2
pA
CMRR
80
90
dB
100
100
kV/V
100
100
dB
0 to 2.8
0 to 2.8
V
VO = 5V, RL = ∞
300
300
µA
VO = 2.5V, RL = ∞
500
500
µA
200
200
µV/V
Input Current
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
AOL
Common-Mode Input Voltage Range
Supply Current
VO = 4VP-P, RL = 5kΩ
VICR
I+
∆VIO/∆V+
Power Supply Rejection Ratio
NOTE:
4. Operation at 5V is not recommended for temperatures below 25oC.
3
CA3130, CA3130A
Schematic Diagram
“CURRENT SOURCE
LOAD” FOR Q11
CURRENT SOURCE FOR
Q6 AND Q7
BIAS CIRCUIT
Q1
Q2
7
V+
Q3
D1
Z1
8.3V
D2
R1
D4
Q4
Q5
D3
40kΩ R
2
5kΩ
SECOND
STAGE
INPUT STAGE
NON-INV.
INPUT
D5
D6
(NOTE 5) D7
D8
OUTPUT
STAGE
3
+
INV.-INPUT
2
Q6
Q8
OUTPUT
Q7
-
6
R4
1kΩ
R3
1kΩ
Q9
Q10
Q12
Q11
R5
1kΩ
5
R6
1kΩ
OFFSET NULL
1
COMPENSATION
8
STROBING
4
V-
NOTE:
5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages.
Terminal 8 can be used both for phase compensation and to
strobe the output stage into quiescence. When Terminal 8 is
tied to the negative supply rail (Terminal 4) by mechanical or
electrical means, the output potential at Terminal 6
essentially rises to the positive supply-rail potential at
Terminal 7. This condition of essentially zero current drain in
4
the output stage under the strobed “OFF” condition can only
be achieved when the ohmic load resistance presented to
the amplifier is very high (e.g.,when the amplifier output is
used to drive CMOS digital circuits in Comparator
applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q6, Q7) working into a mirror-pair of bipolar
transistors (Q9, Q10) functioning as load resistors together
with resistors R3 through R6.
The mirror-pair transistors also function as a differential-tosingle-ended converter to provide base drive to the secondstage bipolar transistor (Q11). Offset nulling, when desired,
can be effected by connecting a 100,000Ω potentiometer
across Terminals 1 and 5 and the potentiometer slider arm to
Terminal 4.
CA3130, CA3130A
7
200µA
1.35mA
200µA
BIAS CKT.
8mA
(NOTE 5)
0mA
(NOTE 7)
+
3
INPUT
AV ≈
6000X
AV ≈ 5X
AV ≈
30X
OUTPUT
6
2
-
V4
5
CC
1
OFFSET
NULL
8
STROBE
COMPENSATION
(WHEN REQUIRED)
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with
output terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
Cascade-connected PMOS transistors Q2, Q4 are the
constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D5 through D8 provide gate-oxide protection
against high-voltage transients, including static electricity
during handling for Q6 and Q7.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascade-connected load resistance provided by
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z1 serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R1, diodes
D1 through D4, and PMOS transistor Q1. A tap at the junction
of resistor R1 and diode D4 provides a gate-bias potential of
about 4.5V for PMOS transistors Q4 and Q5 with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q1 with respect to Terminal
7 to provide gate bias for PMOS transistors Q2 and Q3. It
should be noted that Q1 is “mirror-connected (see Note 8)” to
both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1
establishes a similar current in Q2 and Q3 as constant current
5
sources for both the first and second amplifier stages,
respectively.
At total supply voltages somewhat less than 8.3V, zener
diode Z1 becomes nonconductive and the potential,
developed across series-connected R1, D1-D4, and Q1,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because largesignal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
NOTE:
8. For general information on the characteristics of CMOS
transistor-pairs in linear-circuit applications, see File Number
619, data sheet on CA3600E “CMOS Transistor Array”.
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
V+
CA3130
17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V
TA = 25oC
LOAD RESISTANCE = 5kΩ
15
12.5
2kΩ
1kΩ
10
500Ω
7.5
5
2.5
0
0
2.5
5
7.5
10
12.5
15
17.5
20
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
22.5
CA3130, CA3130A
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
TA = 25oC when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at TA = 25oC.
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage.
Although the finite resistance of the glass terminal-to-case
insulator of the metal can package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if
it is connected to Terminal 4 potential, and the Metal Can
case of the CA3130 is also internally tied to Terminal 4, input
Terminal 3 is essentially “guarded” from spurious leakage
currents.
INPUT VOLTAGE (V)
10
TA = 25oC
7.5
V+
15V
TO
5V
7
5
2
CA3130
PA
6
3
8
2.5
VIN
4
0V
TO
-10V
V-
0
-1
0
1
2
3
4
5
6
INPUT CURRENT (pA)
7
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer’s total range.
Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10oC
increase in temperature. Figure 4 provides data on the
6
typical variation of input bias current as a function of
temperature in the CA3130.
4000
VS = ±7.5V
1000
INPUT CURRENT (pA)
Input Current Variation with Common Mode Input
Voltage
100
10
1
-80
-60
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (oC)
FIGURE 4. INPUT CURRENT vs TEMPERATURE
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input
current variations.
Input Offset Voltage (VIO) Variation with DC Bias
and Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA3130 should be alert to the possible impacts
of this effect if the application of the device involves extended
operation at high temperatures with a significant differential
DC bias voltage applied across Terminals 2 and 3. Figure 5
shows typical data pertinent to shifts in offset voltage
encountered with CA3130 devices (metal can package)
during life testing. At lower temperatures (metal can and
plastic), for example at 85oC, this change in voltage is
considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2VDC differential voltage
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
CA3130, CA3130A
o
7
OFFSET VOLTAGE SHIFT (mV)
TA = 125oC FOR TO-5 PACKAGES
6
5
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
1
0
0
500
1000
1500
2000 2500
3000 3500
4000
TIME (HOURS)
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
SHIFT vs OPERATING LIFE
V+
7
3
CA3130
+
Q8
6
2
Q12
-
RL
4
V-
8
FIGURE 6A. DUAL POWER SUPPLY OPERATION
7
3
V+
CA3130
+
Q8
6
2
Q12
-
RL
4
8
FIGURE 6B. SINGLE POWER SUPPLY OPERATION
FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single-supply Operation: Initially, let it be assumed that the
value of RL is very high (or disconnected), and that the inputterminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
across Q8 and Q12 are of equal magnitude. Figure 20 shows
typical quiescent supply-current vs supply-voltage for the
CA3130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage-transfer characteristics (see Figure 2). If either
Q8 or Q12 are swung out of their linear regions toward cut-off
(a non-linear region), there will be a corresponding reduction
in supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q12 is completely cut off and the supply-current to
series-connected transistors Q8, Q12 goes essentially to zero.
The two preceding stages in the CA3130, however, continue
to draw modest supply-current (see the lower curve in Figure
20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming RL = ∞ by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q8 must now supply quiescent current to both RL
and transistor Q12, it should be apparent that under these
conditions the supply-current must increase as an inverse
function of the RL magnitude. Figure 22 shows the voltagedrop across PMOS transistor Q8 as a function of load
current at several supply voltages. Figure 2 shows the
voltage-transfer characteristics of the output stage for
several values of load resistance.
Wideband Noise
Power-Supply Considerations
Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B show the
CA3130 connected for both dual-and single-supply
operation.
Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
7
From the standpoint of low-noise performance
considerations, the use of the CA3130 is most advantageous
in applications where in the source resistance of the input
signal is on the order of 1MΩ or more. In this case, the total
input-referred noise voltage is typically only 23µV when the
test-circuit amplifier of Figure 7 is operated at a total supply
voltage of 15V. This value of total input-referred noise
remains essentially constant, even though the value of
source resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for
CA3130, CA3130A
values of source resistance very much greater than 1MΩ,
the total noise voltage generated can be dominated by the
thermal noise contributions of both the feedback and source
resistors.
+7.5V
0.01µF
Rs
7
3
+
1MΩ
NOISE
VOLTAGE
OUTPUT
6
2
4
8
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.
The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.
30.1kΩ
1
0.01
µF
47pF -7.5V
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)
1kΩ
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA3130, are particularly suited to service as voltage
followers. Figure 8 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA3130 in a split-supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 9A with
input-signal ramping. The waveforms in Figure 9B show that
the follower does not lose its input-to-output phase-sense,
even though the input is being swung 7.5V below ground
potential. This unique characteristic is an important attribute
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in which the CMOS output
stage permits the output signal to swing down to the
negative supply-rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of the CA3130 in
a single-supply voltage-follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3130 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
8
A single 15V supply provides a positive bus for the CA3130
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The linevoltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single-Supply, Absolute-Value, Ideal Full-Wave
Rectifier
The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fed
through the feedback network directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. During a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R2/R1. When the equality of the two equations
shown in Figure 11 is satisfied, the full-wave output is
symmetrical.
Peak Detectors
Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative
circuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
positive-going signal excursion at the collector of transistor
Q11, which is loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the other hand, during
a negative-going signal excursion at the collector of Q11, the
transistor functions in an active “pull-down” mode so that the
intrinsic capacitance can be discharged more expeditiously.
CA3130, CA3130A
+15V
+7.5V
0.01µF
0.01µF
7
3
+
2
-
3
7
+
10kΩ
10kΩ
6
6
2kΩ
4
-
2
4
8
1
0.01µF
-7.5V
CC = 56pF
1
25pF
8
56pF
2kΩ
5
100kΩ
OFFSET
ADJUST
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs
0.1µF
0.1µF
Top Trace: Output
Center Trace: Input
FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,
200ns/DIV.)
Top Trace: Output Signal; 2V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal; 2V/Div., 5µs/Div.
FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS
9
FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL
RAMPING (2V/DIV., 500µs/DIV.)
Top Trace: Output; 5V/Div., 200µs/Div.
Bottom Trace: Input Signal; 5V/Div., 200µs/Div.
FIGURE 9B. OUTPUT WAVEFORM WITH GROUND
REFERENCE SINE-WAVE INPUT
FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS. (E.G., FOR USE IN
SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9
IN AN6080)
CA3130, CA3130A
10V LOGIC INPUTS
+10.010V
LSB
9
8
7
6
3
10
14
11
6
5
4
3
2
MSB
1
6
3
10
6
3
10
BIT
1
2
3
4
5
6-9
2
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
NOTE: All resistances are in ohms.
9
13
1
13
1
8
5
8
4
5
402K
1%
806K
1%
200K
1%
806K
1%
1
12
8
806K
1%
750K
1%
5
(2)
806K
1%
(4)
806K
1%
(8)
806K
1%
PARALLELED
RESISTORS
62
10K
7
1
+
OUTPUT
2
+10.010V
CA3085
CA3130
6
8
3
LOAD
22.1k
1%
6
7
-
13
+15V
VOLTAGE
REGULATOR
2µF
25V
1%
806K
1%
100K
1%
806K
1%
+
12
806K
12
7
+15V
REQUIRED
RATIO-MATCH
STANDARD
±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS
4
1K
0.001µF
4
5
3
VOLTAGE
FOLLOWER
2
1
8
REGULATED
VOLTAGE
ADJ
100K
OFFSET
NULL 2K
3.83k
1%
56pF
0.1µF
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
R2
+15V
2kΩ
0.01
µF
R1
7
-
2
4kΩ
CA3130
+
3
6
4
1N914
0V
5.1kΩ
5
1
8
20pF
R3
100kΩ
OFFSET
ADJUST
PEAK
ADJUST
2kΩ
0V
R2
R3
Gain = ------- = X = ------------------------------------R1
R1 + R2 + R3
2
X+X
R 3 = R 1  ------------------
 1-X 
2KΩ R 2
For X = 0.5: ------------ = ------4kΩ R 1
0.75
R 3 = 4kΩ  ----------- = 6kΩ
 0.5 
Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
Time base on both traces: 0.2ms/Div.
20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
10
CA3130, CA3130A
6VP-P INPUT;
6VP-P INPUT;
+7.5V
BW (-3dB) = 1.3MHz
+7.5V
BW (-3dB) = 360kHz
0.3VP-P INPUT;
0.3VP-P INPUT;
BW (-3dB) = 240kHz
3
7
+
CA3130
2
-
10kΩ
0.01µF
BW (-3dB) = 320kHz
0.01µF
+DC
OUTPUT
7
3
+
CA3130
2
-
10kΩ
6
6
1N914
1N914
4
-DC
OUTPUT
4
100
kΩ
+
100
kΩ
5µF
-
-7.5V
2kΩ
-7.5V
FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT
FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 12. PEAK-DETECTOR CIRCUITS
CURRENT
LIMIT
ADJ
3Ω
+
R2
1kΩ
IC3
1kΩ
Q5
CA3086
10
7
Q4
12
Q1
3
Q3
9
8
11
Q2
6
2
1
13
14
4
5
+
56pF
5µF
25V
2.2kΩ
+
IC2
+20V
INPUT
OUTPUT
0 TO 13V
AT
40mA
20kΩ
1kΩ
390Ω
0.01µF
-
CA3086 10
11 1, 2
Q4
9
1
7
Q1
6
3
Q3
6
Q2
4
Q5
12
ERROR
AMPLIFIER
+
-
8
25µF
5
8, 7
13
-
CA3130
+
IC1
2
3
30kΩ
4
14
R1
50kΩ
62kΩ
100kΩ
VOLTAGE
ADJUST
0.01
µF
-
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz
FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
11
5µF
+
0.01µF
0.01µF
2kΩ
-
CA3130, CA3130A
2N3055
1Ω
Q2
+
+
10kΩ
2N2102
1kΩ
CURRENT
LIMIT
ADJUST
Q1
4.3kΩ
1W
Q3
3.3kΩ
1W
2N5294
+
+55V
INPUT
43kΩ
1000pF
100µF
-
2.2kΩ
1
5µF
IC2
CA3086
Q4
+
8
-
2N2102
9
8, 7
3
5
Q3
Q1
+
Q2
6
6
Q5
14
12
13
Q4
ERROR
AMPLIFIER
7
10, 11 1, 2
3
-
100µF
OUTPUT:
0.1 TO 50V
AT 1A
10kΩ
CA3130
IC1
+
2
4
8.2kΩ
4
1kΩ
50kΩ
62kΩ
VOLTAGE
ADJUST
-
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µVRMS UP TO 100kHz
FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
Error-Amplifier in Regulated-Power Supplies
The CA3130 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an erroramplifier when the regulated output voltage is required to
approach zero. Figure 13 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
13V. Q3 and Q4 in lC2 (a CA3086 transistor-array lC)
function as zeners to provide supply-voltage for the CA3130
comparator (IC1). Q1, Q2, and Q5 in IC2 are configured as a
low impedance, temperature-compensated source of
adjustable reference voltage for the error amplifier.
Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086
transistor-array lC) are connected in parallel as the seriespass element. Transistor Q5 in lC3 functions as a currentlimiting device by diverting base drive from the series-pass
transistors, in accordance with the adjustment of resistor R2.
Figure 14 contains the schematic diagram of a regulated
power-supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC1) and circuitry
associated with lC2 function as previously described,
although the output of lC1 is boosted by a discrete transistor
(Q4) to provide adequate base drive for the Darlington-
12
connected series-pass transistors Q1, Q2. Transistor Q3
functions in the previously described current-limiting circuit.
Multivibrators
The exceptionally high input resistance presented by the
CA3130 is an attractive feature for multivibrator circuit design
because it permits the use of timing circuits with high R/C
ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 15. Resistors R1
and R2 are used to bias the CA3130 to the mid-point of the
supply-voltage and R3 is the feedback resistor. The pulse
repetition rate is selected by positioning S1 to the desired
position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.
Function Generator
Figure 16 contains a schematic diagram of a function
generator using the CA3130 in the integrator and threshold
detector functions. This circuit generates a triangular or
square-wave output that can be swept over a 1,000,000:1
range (0.1Hz to 100kHz) by means of a single control, R1. A
voltage-control input is also available for remote sweepcontrol.
CA3130, CA3130A
The amplifier circuit in Figure 17 employs feedback to
establish a closed-loop gain of 48dB. The typical large-signal
bandwidth (-3dB) is 50kHz.
The heart of the frequency-determining system is an
operational-transconductance-amplifier (OTA) (see Note 10),
lC1, operated as a voltage-controlled current-source. The
output, IO, is a current applied directly to the integrating
capacitor, C1, in the feedback loop of the integrator lC2, using
a CA3130, to provide the triangular-wave output.
Potentiometer R2 is used to adjust the circuit for slope
symmetry of positive-going and negative-going signal
excursions.
NOTE:
9. See file number 619 for technical information.
+15V
0.01µF
Another CA3130, IC3, is used as a controlled switch to set the
excursion limits of the triangular output from the integrator
circuit. Capacitor C2 is a “peaking adjustment” to optimize the
high-frequency square-wave performance of the circuit.
R1
100kΩ
OFF-PERIOD
ADJUST
1MΩ
ON-PERIOD
ADJUST
1MΩ
2kΩ
2kΩ
R3
100kΩ
Potentiometer R3 is adjustable to perfect the “amplitude
symmetry” of the square-wave output signals. Output from
the threshold detector is fed back via resistor R4 to the input
of lC1 so as to toggle the current source from plus to minus
in generating the linear triangular wave.
7
3
+
CA3130
S1
1µF
R2
100kΩ
Operation with Output-Stage Power-Booster
The current-sourcing and-sinking capability of the CA3130
output stage is easily supplemented to provide power-boost
capability. In the circuit of Figure 17, three CMOS transistorpairs in a single CA3600E (see Note 12) lC array are shown
parallel connected with the output stage in the CA3130. In the
Class A mode of CA3600E shown, a typical device consumes
20mA of supply current at 15V operation. This arrangement
boosts the current-handling capability of the CA3130 output
stage by about 2.5X.
6
-
2
OUTPUT
4
0.1µF
2kΩ
0.001µF
0.01µF
FREQUENCY RANGE:
PULSE PERIOD
4µs to 1ms
40µs to 10ms
0.4ms to 100ms
4ms to 1s
POSITION OF S1
0.001µF
0.01µF
0.1µF
1µF
FIGURE 15. PULSE GENERATOR (ASTABLE MULTIVIBRATOR)
WITH PROVISIONS FOR INDEPENDENT CONTROL
OF “ON” AND “OFF” PERIODS
R4
INTEGRATOR
C1
270kΩ
VOLTAGE-CONTROLLED
CURRENT SOURCE
+7.5V
3
3kΩ
-
2
R2
100kΩ
-7.5V
5
10MΩ
IC2
IO
+
3kΩ
+7.5V
+7.5V
7
IC1
6
2
CA3080A
4 (NOTE 10)
3
+7.5V
150kΩ
+7.5V
7
IC3 7
C2
CA3130
+
+
3
6
39kΩ
4
-7.5V
THRESHOLD
DETECTOR
HIGH - FREQ.
ADJUST
3 - 30pF
100pF
CA3130
8
4
1
5
-7.5V
SLOPE
SYMMETRY 10kΩ
ADJUST
VOLTAGE
CONTROLLED
INPUT
R1
10kΩ
22kΩ
56pF
FREQUENCY
ADJUST
(100kHz MAX)
-7.5V
6
-
2
1
R3
100kΩ
AMPLITUDE
SYMMETRY
ADJUST
-7.5V
NOTE:
10. See file number 475 and AN6668 for technical information.
FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
13
CA3130, CA3130A
+15V
0.01µF
14
1MΩ
CA3600E
(NOTE 12)
1µF
QP1
2
11
QP3
QP2
7
750kΩ
3
+
CA3130
2kΩ
INPUT
2
6
13
1
3
10
-
500µF
1µF
8
6
12
4
RL = 100Ω
(PO = 150mW
AT THD = 10%)
8
AV(CL) = 48dB
QN1
LARGE SIGNAL
BW (-3 dB) = 50kHz
5
QN2
7
QN3
4
9
510kΩ
NOTES:
11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.
12. See file number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130
Typical Performance Curves
SUPPLY VOLTAGE: V+ = 15V; V- = 0
TA = 25oC
OPEN LOOP VOLTAGE GAIN (dB)
AOL
150
OPEN LOOP VOLTAGE GAIN (dB)
LOAD RESISTANCE = 2kΩ
140
130
120
110
100
90
80
-100
100
80
0
50
100
TEMPERATURE (oC)
4
60
2
-200
3
40
-100
3
2
1
102
103
104
105
106
FREQUENCY (Hz)
107
1 - CL = 9pF, CC = 0pF, RL = ∞
2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - CL = 30pF, CC = 150pF, RL = 2kΩ
FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE
14
-300
4
20
0
101
-50
φ OL
1
FIGURE 19. OPEN-LOOP RESPONSE
108
OPEN LOOP PHASE (DEGREES)
120
CA3130, CA3130A
Typical Performance Curves
∞
LOAD RESISTANCE =
TA = 25oC
OUTPUT VOLTAGE BALANCED = V+/2
V- = 0
12.5
10
7.5
5
OUTPUT VOLTAGE HIGH = V+
OR LOW = V2.5
14
QUIESCENT SUPPLY CURRENT (mA)
QUIESCENT SUPPLY CURRENT (mA)
17.5
(Continued)
6
8
10
12
14
16
25oC
8
125oC
6
4
2
0
18
0
2
TOTAL SUPPLY VOLTAGE (V)
10V
15V
POSITIVE SUPPLY VOLTAGE = 5V
1
0.1
0.01
0.001
0.001
0.01
0.1
1.0
10
100
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT
15
6
8
10
12
14
16
FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
VOLTAGE DROP ACROSS NMOS OUTPUT
STAGE TRANSISTOR (V)
VOLTAGE DROP ACROSS PMOS OUTPUT
STAGE TRANSISTOR (V)
10
NEGATIVE SUPPLY VOLTAGE = 0V
TA = 25oC
4
TOTAL SUPPLY VOLTAGE (V)
FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
50
TA = -55oC
10
0
4
OUTPUT VOLTAGE = V+/2
V- = 0
12
50
10
NEGATIVE SUPPLY VOLTAGE = 0V
TA = 25oC
15V
10V
POSITIVE SUPPLY VOLTAGE = 5V
1
0.1
0.01
0.001
0.001
0.01
0.1
1
10
100
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q12) vs LOAD CURRENT
CA3130, CA3130A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
16
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
8
6
7
4
9
Rev. 0 12/93
CA3130, CA3130A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
A
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
8
0°
1.27
8
8°
0°
6
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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17