64M DDR SDRAM K4D623238B-GC 64Mbit DDR SDRAM 512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.4 September 2002 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC Revision History Revision 1.4 (September 26, 2002) • Added tCK(min) and tCK(max) at CL=3 and CL=4 Revision 1.3 (March 5, 2002) • Changed tCK(max) of K4D623238B-GC40 from 7ns to 10ns. Revision 1.2 (September 1, 2001) • Added K4D623238B-GL* as a low power part (ICC6=1mA) • Added ICC7 (Operating current at 4bank interleaving) • Added 100MHz@CL2 Revision 1.1 (August 2, 2001) • Changed tCK(max) of K4D623238B-GC45/-50/-55/-60 from 7ns to 10ns. Revision 1.0 (June 22, 2001) • Changed VDD/VDDQ of K4D623238B-GC33 from 2.5V to 2.8V. Revision 0.4 (April 10,2001) - Preliminary Spec • Added K4D623238B-GC50 • Added K4D623238B-GC55 • Added K4D623238B-GC60 • Defined tWR_A that means write recovery time @ Auto precharge. Revision 0.3 (February 10, 2001) - Preliminary • Changed tDAL of K4D623238B-GC45 from 6tCK to 7tCK. Revision 0.2 (December 13, 2000) - Target Spec • Defined Target Specification Revision 0.0 (November 21, 2000) - 2 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC 512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL FEATURES • 2.5V + 5% power supply for device operation • 4 DQS’s ( 1DQS / Byte ) • VDD/VDDQ = 2.8V ± 5% for -33 • Data I/O transactions on both edges of Data strobe • VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40 • DLL aligns DQ and DQS transitions with Clock transition • SSTL_2 compatible inputs/outputs • Edge aligned data & data strobe output • 4 banks operation • Center aligned data & data strobe input • MRS cycle with address key programs • DM for write masking only -. Read latency 3,4,5 (clock) • Auto & Self refresh -. Burst length (2, 4, 8 and Full page) • 16ms refresh period (2K cycle) -. Burst type (sequential & interleave) • 144-Ball FBGA • Full page burst length for sequential burst type only • Maximum clock frequency up to 300MHz • Start address of the full page burst should be even • Maximum data rate up to 600Mbps/pin • All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Wrtie-Interrupted by Read Function ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D623238B-GC/L33 300MHz 600Mbps/pin K4D623238B-GC/L40 250MHz 500Mbps/pin K4D623238B-GC/L45 222MHz 444Mbps/pin K4D623238B-GC/L50 200MHz 400Mbps/pin K4D623238B-GC/L55 183MHz 366Mbps/pin K4D623238B-GC/L60 166MHz 333Mbps/pin Interface Package SSTL_2 144-Ball FBGA GENERAL DESCRIPTION FOR 512K x 32Bit x 4 Bank DDR SDRAM The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32 bits, fabricated with SAMSUNG ’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC PIN CONFIGURATION (Top View) 2 3 4 5 6 7 8 9 10 11 12 13 B DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 F DQ17 DQ16 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ13 DQ12 H DQS2 DM2 NC VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ NC DM1 DQS1 J DQ21 DQ20 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ11 DQ10 K DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 L CAS WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC M RAS NC NC BA1 A2 RFU3 A9 A5 RFU 2 CK CK MCL N CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. RFU3 is reserved for A11 4. VSS Thermal balls are optional PIN DESCRIPTION CK,CK Differential Clock Input BA 0 , BA 1 Bank Select Address CKE Clock Enable A 0 ~A 10 Address Input CS Chip Select D Q0 ~ DQ3 1 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe VS S Ground WE Write Enable V DDQ Power for DQ’s DQS Data Strobe V SSQ Ground for DQ’s DM Data Mask NC No Connection RFU Reserved for Future Use MCL Must Connect Low - 4 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function The differential system clock Input. CK, CK*1 Input CKE Input All of the inputs are sampled on the rising edge of the clock except D Q’s and DM ’s that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the com- CS Input mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input CAS Input WE Input DQS 0 ~ DQS 3 Input/Output Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. DQS 0 for DQ0 ~ DQ 7, DQS 1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ 23, DQS 3 for DQ2 4 ~ DQ 31. Data In mask. Data In is masked by DM Latency=0 when DM is high DM 0 ~ DM 3 Input in burst write. DM 0 for DQ 0 ~ DQ 7, DM 1 for DQ 8 ~ DQ 15, DM 2 for D Q1 6 ~ DQ 23, DM 3 for DQ24 ~ DQ 31. DQ 0 ~ DQ 31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA 0, BA 1 Input Selects which bank is to be active. A 0 ~ A 10 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA 0 ~ RA 1 0, Column addresses : CA 0 ~ CA7. Column address CA 8 is used for auto precharge. V DD/V SS Power Supply Power and ground for the input buffers and core logic. V DDQ/V SSQ Power Supply V REF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU No connection/ This pin is recommended to be left "No connection" on the device Isolated power supply and ground for the output buffers to provide improved noise immunity. Reserved for future use MCL Must Connect Low Must connect low *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply V REF to CK pin. - 5 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC BLOCK DIAGRAM (512Kbit x 32I/O x 4 Bank) 32 Intput Buffer I/O Control CK, CK Data Input Register LWE LDMi Serial to parallel Bank Select 64 512Kx32 32 Output Buffer 512Kx32 64 2-bit prefetch S ense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 512Kx32 x32 DQi 512Kx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LCKE LRAS LCBR Strobe G en. Programming Register Data Strobe (DQS0~DQS3) DLL LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6 - DMi Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. * 1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 5 6 7 8 9 10 11 CK,CK t RP 2 Clock min. 2 Clock min. tRP ~ Command precharge ALL Banks EMRS MRS DLL Reset precharge 1st Auto ALL Banks Refresh 12 - 7 - 14 15 16 tRFC t RFC 200 Clock min. Inputs must be stable for 200us 13 ~ ~ 4 2nd Auto Refresh ~ ~ ~ ~ 3 17 18 19 2 Clock min. Mode Register Set Any Command ~ ~ 2 ~ ~ 1 ~ ~ ~ 0 Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 1 0 and BA 0, BA 1 in the same cycle as CS, RAS, CAS and W E going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A 3, CAS latency(read latency from column address) uses A 4 ~ A 6. A 7 is used for test mode. A 8 is used for DLL reset. A 7, A 8, BA 0 and BA 1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA 1 BA 0 RFU 0 A 10 A9 RFU A8 A7 DLL TM DLL A8 A6 A5 A4 CAS Latency A2 BT A1 A0 Address Bus Burst Length Mode Register Burst Type Test Mode DLL Reset A3 A7 mode A3 Type 0 No 0 Normal 0 Sequential 1 Yes 1 Test 1 Interleave Burst Length CAS Latency BA 0 A1 A0 Sequential Interleave Reserved 0 0 0 Reserve Reserve Reserved 0 0 1 2 2 1 0 4 4 A6 A5 A4 Latency 0 MRS 0 0 0 1 EMRS 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle. Burst Type A2 An ~ A0 0 1 0 Reserved 0 0 1 1 3 0 1 1 8 8 1 0 0 4 1 0 0 Reserve Reserve 1 0 1 5 1 0 1 Reserve Reserve 1 1 0 Reserved 1 1 0 Reserve Reserve Reserved 1 1 1 Full page Reserve 1 1 1 MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS tRP NOP Any Command NOP NOP tMRD=2 t CK *1 : MRS can be issued only at all banks precharge state. *2 : Minimum t RP is required to issue MRS command. - 8 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A10 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA 1 BA 0 A1 0 A9 A8 A7 RFU 1 BA 0 An ~ A0 A6 A1 0 MRS 0 0 1 EMRS RFU A6 A5 D.I.C A4 A3 A2 RFU Output Driver Impedence Control N/A A1 A0 Address Bus D.I.C DLL Extended Mode Register A0 DLL Enable Do not use 0 Enable 1 Disable 0 1 Weak 60% 1 0 N/A Do not use 1 1 Matched impedance 30% * RFU(Reserved for future use) should stay "0" during EMRS cycle. Figure 7. Extended Mode Register set - 9 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit V IN, V OUT -0.5 ~ 3.6 V Voltage on V DD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation PD 2.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, T A =0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 2.375 2.50 2.625 V 1,7 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1,7 Device Supply voltage V DD 2.66 2.8 2.94 V 1,8 Output Supply voltage V DDQ 2.66 2.8 2.94 V 1,8 Reference voltage V REF 0.49*V DDQ - 0.51*V DDQ V 2 Termination voltage Vtt V REF-0.04 V REF V REF+0.04 V 3 Input logic high voltage V IH V REF+0.15 - V DDQ +0.30 V 4 Input logic low voltage V IL -0.30 - V REF-0.15 V 5 Output logic high voltage VO H Vtt+0.76 - - V IO H=-15.2mA Output logic low voltage V OL - - Vtt-0.76 V IOL =+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions V DDQ must be less than or equal to VDD. 2. V REF is expected to equal 0.50*V DDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ , VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. V tt of the transmitting device must track V REF of the receiving device. 4. V IH (max.)= V DDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. V IL (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < V IN < V DD is acceptable. For all other pins that are not under test V I N=0V. 7. For -40/-45/-50/-55/-60, V DD/ V DDQ=2.5V + 5% 8. For -33, V DD/V DDQ= 2.8V + 5% - 10 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T A=0 to 65 °C ) Version Parameter Symbol Test Condition -33 -40 -45 -50 -55 -60 Unit Note 1 Operating Current (One Bank Active) IC C 1 Burst Lenth=2 tRC ≥ t RC(min) I OL =0mA, t CC= t C C(min) 470 340 315 290 275 260 mA Precharge Standby Current in Power-down mode IC C 2P CKE ≤ V IL(max), tCC= tCC(min) 75 65 65 65 65 65 mA Precharge Standby Current in Non Power-down mode IC C 2N CKE ≥ V IH(min), CS ≥ V IH(min), t CC= t CC(min) 155 125 120 115 110 105 mA Active Standby Current power-down mode IC C 3P CKE ≤ V IL (max), t CC= tCC(min) 150 130 130 130 130 130 mA Active Standby Current in in Non Power-down mode IC C 3N CKE ≥ VIH(min), CS ≥ VIH(min), t CC= tCC(min) 270 220 210 200 190 180 mA Operating Current ( Burst Mode) IC C 4 IOL =0mA , tCC = tCC(min), Page Burst, All Banks activated. 900 700 650 600 550 520 mA Refresh Current IC C 5 tRC ≥ tRFC(min) 405 340 330 320 310 300 mA 2 Self Refresh Current IC C 6 CKE ≤ 0.2V 4.5 mA 3 mA 4 4 1 Operating Current ( 4Bank Interleaving) IC C 7 Burst Lenth=4 tRC ≥ t RC(min) I OL =0mA, t CC= t C C(min) 1050 850 800 750 700 670 mA Note : 1. Measured with outputs open. 2. Refresh period is 16ms. 3. K4D623238B-GC* 4. K4D623238B-GL* AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS =0V, V DD/ VDDQ =2.5V+ 5%, T A=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ V IH V REF +0.35 - - V Input Low (Logic 0) Voltage; DQ V IL - - V REF -0.35 V Clock Input Differential Voltage; CK and CK V ID 0.7 - V DDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK V IX 0.5*VDDQ-0.2 - 0.5*V DDQ +0.2 V 2 Note : 1. V I D is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of V IX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC AC OPERATING TEST CONDITIONS (V DD =2.5V±0.125V, TA = 0 to 65°C ) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*V DDQ V 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(V IH /V IL) 1.0 V/ns V REF +0.35/V REF -0.35 V V REF V V tt V Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 V tt =0.5*V DDQ R T=50Ω Output Z0=50Ω V REF =0.5*VDDQ C LOAD =30pF (Fig. 1) Output Load Circuit CAPACITANCE (V DD =3.3V, T A = 25°C, f=1MHz) Symbol Min Max Unit Input capacitance( CK, CK ) Parameter C IN1 1.0 5.0 pF Input capacitance(A 0 ~A10 , BA0 ~BA1 ) C IN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) C IN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ 0~ D Q31) C OUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.5 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Symbol Value Unit Decoupling Capacitance between V DD and V SS Parameter C DC1 0.1 + 0.01 uF Decoupling Capacitance between V DDQ and V SSQ C DC2 0.1 + 0.01 uF Note : 1. V DD and V DDQ pins are separated each other. All V DD pins are connected in chip. All VDDQ pins are connected in chip. 2. V SS and V SSQ pins are separated each other All V SS pins are connected in chip. All V SSQ pins are connected in chip. - 12 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC AC CHARACTERISTICS Parameter Symbol CL=3 CL=4 CK cycle time -40 Max Min - tCK CL=5 tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in tDQSS DQS-In setup time tWPRES DQS-in hold time tWPREH DQS write postamble tWPST DQS-In high level width tDQSH DQS-In low level width tDQSL Address and Control input setup tIS Address and Control input hold tIH DQ and DM setup time to DQS tDS DQ and DM hold time to DQS tDH tHP Data output hold time from DQS tQ H -45 Max 5.0 - Min -50 Max Min 5.0 4.0 7 3.3 CK high level width Clock half period -33 Min - Min 5.0 4.5 10 -55 Max -60 Max Min 5.5 Max 6.0 Unit Note ns 10 - 10 - 10 - 10 ns 0.45 0.55 0.45 0.55 tCK - ns 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 ns -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 ns - 0.35 - 0.4 - 0.45 - 0.45 - 0.5 - 0.5 ns 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.85 1.15 0.85 1.15 0.8 1.2 0.8 1.2 0.75 1.25 0.75 1.25 tCK 0 - 0 - 0 - 0 - 0 - 0 - ns 0.35 - 0.35 - 0.3 - 0.3 - 0.25 - 0.25 - tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.9 - 0.9 - 1.0 - 1.0 - 1.1 - 1.1 - ns 0.9 - 0.9 - 1.0 - 1.0 - 1.1 - 1.1 - ns 0.35 - 0.4 - 0.45 - 0.45 - 0.5 - 0.5 - ns 0.35 - 0.4 - 0.45 - 0.45 - 0.5 - 0.5 - ns - tCLmin or tCHmin - - tCLmin or tCHmin - tCLmin or tCHmin - ns 1 - tHP-0.4 - - tHP-0.5 - tHP-0.5 - ns 1 tCLmin or tCHmin tHP0.35 tCLmin or tCHmin tHP0.45 - - tCLmin or tCHmin tHP0.45 Simplified Timing @ BL=2, CL=4 tCH tCL tCK 0 1 2 3 4 5 6 7 8 CK, CK tIS CS tIH tDQSCK tDQSS DQS tRPRE tRPST t WPRES tDQSQ tDQSH tDQSL tWPREH tDS tDH tAC DQ Qa1 Db0 Qa2 Db1 DM WRITEB COMMAND READA - 13 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL4, BL2) tHP 0 1 3 2 4 5 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) Qa0 DQ COMMAND Qa1 READA - 14 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC AC CHARACTERISTICS (I) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Symbol tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD -33 Min Max 17 19 - -40 Min Max 15 17 - -45 Min Max 13 15 - -50 Min Max 12 14 - -55 Min Max 12 14 - -60 Unit Note Min Max 10 tCK 12 tCK 100K tCK 12 100K 10 100K 9 100K 8 100K 8 100K 7 6 - 5 - 4 - 4 - 4 - 3 - tCK 2 - 2 - 2 - tCK 4 2 - 4 2 - 3 2 - tCK tCK 4 5 3 5 3 - 2 4 3 - 2 - Last data in to Row precharge @Normal Precharge tWR 3 - 3 - 3 - 2 - 2 - 2 - tCK 1 Last data in to Row precharge @Auto Precharge tWR_A 3 - 3 - 3 - 3 - 3 - 3 - tCK 1 tCDLR tCCD tMRD 2 - 2 - 2 - 2 - 2 - 2 - tCK 1 1 1 2 - 1 2 - 2 - 1 2 - 1 2 - 1 2 - tCK tCK Auto precharge write recovery + Precharge Exit self refresh to read com- tDAL 8 - 8 - 7 - 7 - 7 - 6 - tCK 200 - 200 - 200 - 200 - 200 - 200 - tCK Power down exit time tPDEX tREF 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - ns us Last data in to Read command Col. address to Col. address Mode register set cycle time Refresh interval time tXSR 7.8 7.8 7.8 7.8 7.8 7.8 Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) (Unit : Number of Clock) K4D623238B-GC33 Frequency Cas Latency 333MHz ( 3.3ns ) 5 tRC 17 tRFC 19 tRAS 12 tRCDRD 6 tRCDWR 4 tRP 5 tRRD 3 tDAL 8 Unit K4D623238B-GC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 tRC 15 13 12 12 10 tRFC 17 15 14 14 12 tRAS 10 9 8 8 7 tRCDRD 5 4 4 4 3 tRCDWR 3 2 2 2 2 tRP 5 4 4 4 3 tRRD 3 2 2 2 2 tDAL 8 7 7 7 6 Unit K4D623238B-GC45 Frequency Cas Latency 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 tRC 13 12 12 10 tRFC 15 14 14 12 tRAS 9 8 8 7 tRCDRD 4 4 4 3 tRCDWR 2 2 2 2 tRP 4 4 4 3 tRRD 2 2 2 2 tDAL 7 7 7 6 Unit - 15 - tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC K4D623238B-GC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 12 10 tRFC 14 14 12 tRAS 8 8 7 tRCDRD 4 4 3 tRCDWR 2 2 2 tRP 4 4 3 tRRD 2 2 2 tDAL 7 7 6 Unit K4D623238B-GC55 Frequency Cas Latency 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 10 tRFC 14 12 tRAS 8 7 tRCDRD 4 3 tRCDWR 2 2 tRP 4 3 tRRD 2 2 tDAL 7 6 Unit K4D623238B-GC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 tRC 10 tRFC 12 tRAS 7 tRCDRD 3 tRCDWR 2 tRP 3 tRRD 2 tDAL 6 Unit tCK tCK tCK tCK tCK tCK Simplified Timing(2) @ BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BAa BAb BAa BAb Ra Rb Ra Rb Ca Cb 17 18 19 20 21 22 CK, CK B A [ 1 : 0 ] BAa A8/AP ADDR (A0~A7, A9,A10) BAa BAa Ra Ra Ra Ca WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COMMAND ACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 16 - Rev. 1.4 (Sep. 2002) 64M DDR SDRAM K4D623238B-GC PACKAGE DIMENSIONS (144-Ball FBGA) A1 INDEX MARK 12.0 12.0 <Top View> 0.8x11=8.8 A1 INDEX MARK 0.10 Max 0.8 B C D E F G H J K L M N 0.40 0.8x11=8.8 0.45 ± 0.05 0.8 13 12 11 10 9 8 7 6 5 4 3 2 0.35 ± 0.05 0.40 1.40 Max <Bottom View> Unit : mm - 17 - Rev. 1.4 (Sep. 2002)