CYK001M16ZCCA MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM Features (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). • Wide voltage range: 2.70V–3.30V • Access Time: 55 ns, 70 ns • Ultra-low active power Writing to the device is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). — Typical active current: 3 mA @ f = 1 MHz — Typical active current: 13 mA @ f = fmax • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power • Deep Sleep Mode • Offered in a 48-ball BGA Package Functional Description The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins Logic Block Diagram Reading from the device is accomplished by asserting Chip Enable (CE) and Output Enable (OE) inputs LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. This device incorporates a Low Power mode wherein data integrity is not guaranteed, but Power Consumption reduces to less than 100 µW. This mode (Deep Sleep Mode) is enabled by driving ZZ LOW.See the Truth Table for a complete description of Read, Write, and Deep Sleep mode. SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 1M × 16 RAM Array I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE WE Power-Down Circuit CE OE BLE ZZ BHE BLE CE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05454 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 15, 2004 CYK001M16ZCCA MoBL3™ Pin Configuration[2, 3, 4] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 ZZ A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 GND A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Product Portfolio[5] Power Dissipation Product CYK001M16ZCCAU Speed (ns) VCC Range (V) Min. Typ.[5] Max. 2.70 3.0 3.30 55 70 Operating ICC(mA) f = 1MHz Typ.[5] 3 f = fmax Standby ISB2(µA) Max. Typ.[5] Max. Typ.[5] Max. 5 13 22 80 150 17 Notes: 2. DNU pins have to be left floating. 3. Ball H6 can be used to upgrade to 32M density. 4. NC “no connect”—not connected internally to the die. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05454 Rev. *B Page 2 of 11 CYK001M16ZCCA MoBL3™ Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential ................. –0.4V to 4.6V DC Voltage Applied to Outputs in High Z State[6, 7, 8] ........................................–0.4V to 3.7V DC Input Voltage[6, 7, 8] .....................................–0.4V to 3.7V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC CYK001M16ZCCA Industrial –25°C to +85°C 2.70V to 3.30V DC Electrical Characteristics (Over the Operating Range) CYK001M16ZCCAU55 Parameter Description Test Conditions VCC Supply Voltage VOH Output HIGH Voltage IOH = –-0.1 mA VOL Output LOW Voltage IOL = 0.1mA VIH Input HIGH Voltage VCC= 2.7V to 3.3V VIL Input LOW Voltage IIX Input Leakage Current IOZ ICC CYK001M16ZCCAU70 Min. Typ.[5] Max. Min. 2.7 3.0 3.3 2.7 VCC – 0.4 Typ.[5] Max. Unit 3.3 V VCC – 0.4 V 0.4 0.4 V 0.8 * VCC VCC + 0.4V 0.8 * VCC VCC + 0.4V V –0.4 0.4 -0.4 0.4 V GND < VIN < VCC –1 +1 –1 +1 µA Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current — CMOS Inputs ISB2 IZZ 13 22 13 17 mA 3 5 3 5 mA VCC = 3.3V CE > VCC−0.2V VIN > VCC–0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.30V 100 525 100 525 µA Automatic CE Power-Down Current — CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V 80 150 80 150 µA Deep Sleep Current VCC = VCCMAX; ZZ = LOW 50 µA f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels VCC = 3.3V 50 Notes: 6. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 7. VIH(Max) = Vcc + 0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. Document #: 38-05454 Rev. *B Page 3 of 11 CYK001M16ZCCA MoBL3™ Capacitance[9] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[9] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions BGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 55 °C/W 17 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% ALL INPUT PULSES 90% 90% 10% Rise Time = 1 V/ns Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V VCC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 Note: 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05454 Rev. *B V Page 4 of 11 CYK001M16ZCCA MoBL3™ Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14] 55 ns[14] Parameter Description Min. 70 ns Max. Min. Max. Unit Read Cycle 55[14] tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns 55 [11, 13] tLZOE OE LOW to LOW Z tHZOE OE HIGH to High Z[11, 13] tLZCE CE LOW to Low Z[11, 13] tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z[11, 13] BLE/BHE HIGH to HIGH Write 70 5 55 5 Z[11, 13] Address Skew ns 25 25 ns ns 5 2 Z[11, 13] ns 5 25 CE HIGH to High tSK[14] 5 5 tHZCE tHZBE 70 ns ns 25 ns 70 ns 5 ns 10 25 ns 0 10 ns Cycle[12] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns tBW BLE/BHE LOW to Write End 50 60 ns tSD Data Set-up to Write End 25 45 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High-Z WE HIGH to [11, 13] Low-Z[11, 13] 25 5 25 5 ns ns Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle Document #: 38-05454 Rev. *B Page 5 of 11 CYK001M16ZCCA MoBL3™ Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[14, 16] ADDRESS CE tRC tSK tHZCE tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT 50% 50% ICC ISB Notes: 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read Cycle. Document #: 38-05454 Rev. *B Page 6 of 11 CYK001M16ZCCA MoBL3™ Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19] t WC ADDRESS tSCE CE tAW tSA tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA DON’T CARE tHZOE Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19] t WC ADDRESS tSCE CE tSA tHA tAW tPWE WE tBW BHE/BLE OE t HZOE DATA I/O DON’T CARE tSD tHD VALID DATA Notes: 17. Data I/O is high impedance if OE > VIH. 18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05454 Rev. *B Page 7 of 11 CYK001M16ZCCA MoBL3™ Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tSA tHA tPWE WE tHD tSD DATAI/O DON’T CARE VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA WE tPWE tSD DATA I/O DON’T CARE Document #: 38-05454 Rev. *B tHD VALID DATA Page 8 of 11 CYK001M16ZCCA MoBL3™ Deep Sleep Mode This mode can be used to lower the power consumption of the PSRAM in an application. In this mode, the data integrity of the PSRAM is not guaranteed. Deep Sleep Mode can be enabled by driving ZZ LOW. The device stays in the deep sleep mode until ZZ is driven HIGH. Deep Sleep Mode—Entry/Exit[20] Deep Sleep Mode ZZ tR tCDR CE or BLE / BHE Deep Sleep Access Timings[21, 22] Parameter Description Min. tCDR Chip Deselect to ZZ LOW 0 tR Operation Recovery Time Max. Unit ns µs 200 Truth Table[23] ZZ CE WE OE BHE BLE Inputs/Outputs Mode Power H H X X X X High Z Deselect/Power-down Standby (ISB) H X X X H H High Z Deselect/Power-down Standby (ISB) H L H L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC) H L H L H L Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Read (Lower Byte only) Active (ICC) H L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read (Upper Byte only) Active (ICC) H L H H L L High Z Output Disabled Active (ICC) H L H H H L High Z Output Disabled Active (ICC) H L H H L H High Z Output Disabled Active (ICC) H L L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) H L L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) Active (ICC) H L L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write (Upper Byte Only) Active (ICC) L H X X H H High Z Deep Power-down Deep Sleep (IZZ) Notes: 20. OE and the data pins are in a “don’t care” state while the device is in Deep Sleep Mode. 21. All other timing parameters are as shown in the switching characteristics section. 22. tR applies only in the Deep Sleep Mode. 23. H = Logic HIGH, L = Logic LOW, X = Don’t Care. Document #: 38-05454 Rev. *B Page 9 of 11 CYK001M16ZCCA MoBL3™ Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 55 CYK001M16ZCCAU-55BAI BA48K 48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm) Industrial 70 CYK001M16ZCCAU-70BAI BA48K 48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm) Industrial Package Diagram 48-Lead FBGA (6 x 8 x 1.2 mm) BA48K BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A1 CORNER 1 2 3 4 5 6 6 5 3 4 2 1 A A C E F G D E F 2.625 8.00±0.10 8.00±0.10 D 0.75 B C 5.25 B G H H A 0.75 6.00±0.10 B 3.75 B 0.15 C 0.21±0.05 0.53±0.05 0.25 C 1.875 A 6.00±0.10 0.15(4X) REFERENCE JEDEC MO-207 51-85150-*B C 1.20 MAX 0.36 SEATING PLANE 51-85193-*A MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05454 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. CYK001M16ZCCA MoBL3™ Document History Page Document Title: CYK001M16ZCCA MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 38-05454 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 132407 01/27/04 AWK New Data Sheet *A 220121 See ECN REF Changed the datasheet from AdvanceInformation to Final Added 55-ns speed bin and address skew restriction for 55-ns speed bin. Changed Izz from 30 µA to 50 µA. *B 230851 See ECN AJU Changed ball A6 from NC to ZZ Modified ordering code in “Ordering Information” table on page 10 Replaced package diagram Modified MAX limit on DC Input voltage in ‘Maximum Ratings’ section Document #: 38-05454 Rev. *B Page 11 of 11