ICSSSTUBF32866A Advance Information Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97ULP877 • Ideal for DDR2 667, and 800 1 2 3 4 5 6 A B C D Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSR and RESET inputs • Low voltage operation VDD = 1.7V to 1.9V • Available in 96 BGA package • Drop-in replacement for ICSSSTUA32864 • Green packages available E F G H J K L M N P R T Functionality Truth Table I nputs Outputs CK CK Dn, DODT, DCK E Qn QCS QODT, QCKE RST DCS CSR H L L L L L L H L L H H L H Q0 H L L X Q0 Q0 H L H L L L L H L H H H L H Q0 L or H L or H H L H X Q0 Q0 H H L L L H L H H L H H H H Q0 L or H L or H H H L X Q0 Q0 H H H L Q0 H L H H H H Q0 H H L or H L or H H H H L or H L or H X Q0 Q0 Q0 L X or Floating X or Floating X or Floating X or Floating X or Floating L L L 96 Ball BGA (Top View) 1240—07/17/06 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICSSSTUBF32866A Advance Information Ball Assignments 25 bit 1:1 Register A DCKE PPO V REF V DD QCKE NC B D2 D15 GND GND Q2 Q15 Q16 C D3 D16 V DD V DD Q3 D DODT QERR GND GND QODT NC E D5 D17 V DD V DD Q5 Q17 F D6 D18 GND GND Q6 Q18 G PAR_IN RST V DD V DD C1 C0 H CK DCS GND GND QCS NC J CK CSR V DD V DD ZOH ZOL K D8 D19 GND GND Q8 Q19 L D9 M D10 D20 V DD V DD Q9 Q20 D21 GND GND Q10 Q21 N D11 D22 V DD V DD Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 V DD V DD Q13 Q24 T D14 D25 V REF V DD Q14 1 2 3 4 Q25 5 6 C0 = 0, C1 = 0 14 bit 1:2 Registers A DCKE PPO V REF V DD QCKEA QCKEB A D1 PPO V REF V DD Q1A B D2 NC GND GND Q2A Q2B B D2 NC GND GND Q2A Q2B C D3 NC V DD V DD Q3A Q3B C D3 NC V DD V DD Q3A Q3B D D4 E D5 QERR GND GND Q4A Q4B NC V DD V DD Q5A Q5B F D6 NC D DODT QERR GND GND QODTA QODTB E D5 NC V DD V DD Q5A F D6 NC Q5B GND GND Q6A Q6B G PAR_IN RST V DD V DD C1 C0 H CK DCS GND GND QCSA QCSB J CK CSR V DD V DD ZOH ZOL K D8 NC GND GND Q8A Q8B J CK K D8 L D9 NC V DD V DD Q9A Q9B L G PAR_IN RST H CK DCS D9 Q1B GND GND Q6A Q6B V DD V DD C1 C0 GND GND QCSA QCSB CSR V DD V DD ZOH ZOL NC GND GND Q8A Q8B NC V DD V DD Q9A Q9B Q10B M D10 NC GND GND Q10A Q10B M D10 NC GND GND Q10A N D11 NC V DD V DD Q11A Q11B N DODT NC V DD V DD QODTA QODTB P D12 NC GND GND Q12A Q12B P D12 NC GND GND Q12A Q12B R D13 NC V DD V DD Q13A Q13B R D13 NC V DD V DD Q13A Q13B T D14 NC V REF V DD Q14A Q14B T DCKE NC V REF V DD QCKEA QCKEB 5 6 1 2 3 4 1 Register A (C0 = 0, C1 = 1) 2 3 4 5 6 Register B (C0 = 1, C1 = 1) 1240—07/17/06 2 ICSSSTUBF32866A Advance Information General Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUBF32866A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (CO1 = 0, CI1 = 1 and CO2 = 0, CI2 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for two cycles or until Reset is low. B - Single Configuration (CO = 0, C1 = 0) The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST is low all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the ICSSSTUBF32866A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). Parity and Standby Functionality Truth Table Inputs Rst DCS CSR CK CK H H H H H H H H L L L L H H H X X X X X L L H X ↑ ↑ ↑ ↑ ↑ ↑ ↑ L or H ↓ ↓ ↓ ↓ ↓ ↓ ↓ L or H L X or X or X or Floating Floating Floating X or Floating Outputs Sum of Inputs = H (D1 - D25) Even Odd Even Odd Even Odd X X X or Floating PAR_IN PPO QERR L L H H L H X X L H H L L H PPO0 PPO0 H L L H H L QERR0 QERR0 X or Floating L H 1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25. CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14 CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13 2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0. 3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1. 4. Assume QERR is high at the CK↑ and CK↓ crossing. If QERR is low it stays latched low for two clock cycles on until Rst is low. 1240—07/17/06 3 ICSSSTUBF32866A Advance Information Ball Assignment Terminal Name GND Description Electrical Characteristics Ground Ground input VDD Power supply voltage 1.8V nominal VREF Input reference voltage 0.9V nominal ZOH Reserved for future use Input ZOL Reserved for future use Input CK Positive master clock input Differential input CK Negative master clock input Differential input C0, C1 Configuration control inputs LVCMOS inputs Asynchronous reset input - resets registers and disables VREF data and clock differential-input receivers LV C M O S i n p u t RST CSR, DCS Chip select inputs - disables D1 - D24 outputs switching when both inputs SSTL_18 input are high D1 - D25 Data input - clock in on the crossing of the rising edge of CK and the falling edge of CK SSTL_18 input DODT The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input DCKE The outputs of this register bit will now be suspended by the DCS and CSR control SSTL_18 input Data ouputs that are suspended by the DCS and CSR control 1.8V CMOS Q1 - Q25 QCS Data output that will not be suspended by the DCS and CSR control 1.8V CMOS QODT Data output that will not be suspended by the DCS and CSR control 1.8V CMOS QCKE Data output that will not be suspended by the DCS and CSR control 1.8V CMOS Par tial parity out indicates off parity of inputs D1 - D25. 1.8V CMOS PAR_IN PPO Parity input arrives one clock cycle after the corresponding data input SSTL_18 input QERR Output error bit-generated one clock cycle after the corresponding data output Open drain output 1240—07/17/06 4 ICSSSTUBF32866A Advance Information Block Diagram for 1:1 mode (positive logic) RST CK CK VREF DCKE D C1 QCKEA C1 QODTA R DODT D R DCS 1D C1 QCSA R CSR D1 0 1 1D Q1A C1 R To 21 Other Channels *Note: Disabled in 1:1 configuration 1240—07/17/06 5 Q1B* ICSSSTUBF32866A Advance Information Block Diagram for 1:2 mode (positive logic) RST CK CK VREF DCKE 1D QCKEA C1 DODT R QCKEB* 1D QODTA C1 DCS R QODTB* 1D QCSA C1 R QCSB* 1D Q1A CSR D1 0 1 C1 R To 10 Other Channels *Note: Disabled in 1:1 configuration 1240—07/17/06 6 Q1B* ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST CK CK G2 H1 J1 LPS0 (internal node) D2•D3, D5•D6, D8-D25 V REF 22 A3, T3 D2•D3, D5•D6, D8•D25 CE D CK Q 22 22 R 22 Q2 Q3, Q5 Q6, Q8 Q25 D2•D3, D5•D6, D8•D25 Parity Generator C1 G5 1 0 Q D 1 CK R G1 PPO 0 Q D CK R PAR_IN Q D A2 CK R CE D2 QERR C0 G6 CK 2•Bit Counter R LPS1 (internal node) 0 D Q 1 CK R Figure 6 Parity logic diagram for 1:1 register configuration (positive logic): C0=0, C1=0 1240—07/17/06 7 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST CK CK G2 H1 J1 LPS0 (internal node) D2•D3, D5•D6, D8-D14 V REF 11 A3, T3 D2•D3, D5•D6, D8•D14 CE D CK Q 11 11 R 11 11 D2•D3, D5•D6, D8•D14 Q2A•Q3A, Q5A•Q6A, Q8A•Q14A Q2B•Q3B, Q5B•Q6B, Q8B•Q14B Parity Generator C1 G5 1 0 D Q D CK D Q CK R PAR_IN A2 PPO 1 R G1 0 Q CK R CE D2 QERR C0 G6 CK 2•Bit Counter R LPS1 (internal node) 0 D Q 1 CK R Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1 1240—07/17/06 8 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST CK CK G2 H1 J1 LPS0 (internal node) D1•D6, D8-D13 V REF 11 A3, T3 11 D1•D6, D8•D13 CE D CK Q1A•Q6A, Q8A•Q13A Q 11 R 11 11 D1•D6, D8•D13 Q1B•Q6B, Q8B•Q13B Parity Generator C1 G5 D Q 0 1 1 0 PPO D CK D Q CK R PAR_IN A2 R G1 Q CK R CE D2 QERR C0 G6 CK 2•Bit Counter R LPS1 (internal node) 0 D Q 1 CK R Figure 8 Parity logic diagram for 1:2 register-B configuration (positive logic); CO=1, C1=1 1240—07/17/06 9 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST DCS CSR n n +1 n +2 n+3 n+4 CK CK tact tsu th D1•D25 † tpdm , t pdmss CK to Q Q1•Q25 tsu th PAR_IN † t pd CK to PPO PPO tPHL CK to QERR QERR ‡ tPHL , t PLH CK to QERR Data to QERR Latency H, L, or X H or L Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; RST Switches from L to H † After RST is switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t max, to avoid false error. ‡ If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 1240—07/17/06 10 ACT ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST DCS CSR n n +1 n +2 n+3 n+4 CK CK tsu th D1•D25 tpdm , t pdmss CK to Q1•Q25 tsu th PAR_IN tpd CK to PPO PPO Data to PPO Latency tPHL or t PLH CK to QERR QERR † Data to QERR Latency Unknown input event Figure 10 † Output signal is dependent on the prior unknown input event H or L Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; RST being held high If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RST is driven low. 1240—07/17/06 11 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST tinact DCS † CSR † CK † CK † D1•D25 † tRPHL RST to Q Q1•Q25 PAR_IN † tRPHL RST to PPO PPO QERR tRPLH RST to QERR H, L, or X H or L Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; RST switches from H to L † After RST is switched from high to low, all data and clock unouts signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT max. 1240—07/17/06 12 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST DCS CSR n n+1 n+2 n+3 n +4 CK CK tact t su th D1•D14 † tpdm , t pdmss CK to Q Q1•Q14 tsu th PAR_IN † t pd CK to PPO PPO QERR# ‡ (not used) tPHL CK to QERR t PHL , t PLH CK to QERR Data to QERR# Latency H, L, or X H or L Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in pair; C0=0, C1=1; RST switches from L to H † After RST is switched from low to high, all data and PAIR_IN inputs signals must be set and held low for a minimum time of tACT max, to avoid false error ‡ If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. 1240—07/17/06 13 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST DCS CSR n n +1 n+2 n+3 n+4 CK CK tsu th D1•D14 tpdm , t pdmss CK to Q Q1•Q14 tsu th PAR_IN tpd CK to PPO PPO tPHL or t PLH CK to QERR Data to PPO Latency QERR † (not used) Data to QERR Latency Unknown input event Output signal is dependent on the prior unknown input event H or L Figure 13 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in pair; C0=0, C1=1; RST being held high † If the data is clocked in on the clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RST is driven low. 1240—07/17/06 14 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST# t inact DCS# † CSR# † CK † CK# † D1•D14 † tRPHL RST# to Q Q1•Q14 PAR_IN † tRPHL RST# to PPO PPO QERR# (not used) tRPLH RST# to QERR# H, L, or X H or L Figure 14 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in pair; C0=0, C1=1; RST# switches from H to L † After RST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a minimum time of t IN ACT max 1240—07/17/06 15 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST# DCS# CSR# n n+1 n+2 n+ 3 n +4 CK CK# t act t su th D1•D14 † tpdm , t pdmss CK to Q Q1•Q14 tsu th PAR_IN †‡ tpd CK to PPO PPO (not used) t PHL CK to QERR# t PHL , t PLH CK to QERR# QERR# § Data to QERR# Latency H, L, or X H or L Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in pair; C0=1, C1=1; RST# switches from L to H † After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t ACT max, to avoid false error. ‡ PAR_IN is driven from PPO of the first SSTU32866 device. § If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 1240—07/17/06 16 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST# DCS# CSR# n n+1 n+2 n+3 n+4 CK CK# t su th D1•D14 tpdm , t pdmss CK to Q Q1•Q14 tsu th PAR_IN tpd CK to PPO PPO Data to PPO Latency t PHL or t PLH CK to QERR# QERR# † (not used) Data to QERR# Latency Unknown input event Output signal is dependent on the prior unknown input event H or L Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B cofiguration) device used in pair; C0=1, C1=1; RST# being held high † PAR_IN is driven from PPO of the first SSTU32866 device ‡ If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an erro occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or until RST# is driven low. 1240—07/17/06 17 ICSSSTUBF32866A Advance Information 2. Device standard (cont'd) RST# t inact DCS# † CSR# † CK † CK# † D1•D14 † t RPHL RST# to Q Q1•Q14 PAR_IN † tRPHL RST# to PPO PPO (not used) QERR# tRPLH RST# to QERR# H, L, or X H or L Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in pair; C0=1, C1=1; RST# switches from H to L † After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a munimum time of t INACT max. 1240—07/17/06 18 ICSSSTUBF32866A Advance Information * Register Configurations DATA INPUT: DATA OUTPUT: CO CI D2, D3, D5, D6, D8 - D25 D2, D3, D5, D6, D8 - D25 0 0 D2, D3, D5, D6, D8 - D14 D2, D3, D5, D6, D8 - D14 0 1 D1 - D6, D8 D10, D12, D13 D1 - D6, D8 D10, D12, D13 1 1 1240—07/17/06 19 ICSSSTUBF32866A Advance Information Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD or GND Current/Pin . . . . . . . . . . . . . . . . –65°C to +150°C -0.5V to 2.5V -0.5V to +2.5V -0.5V to VDD + 0.5V ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance3 36°C ............... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER VDDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (AC) VIH VIL VICR VID IOH IOL TA DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RST# Input Low Voltage Level Common mode Input Range CK, CK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 1 MIN TYP 1.7 1.8 0.49 x VDD 0.5 x VDD V REF - 0.04 VREF 0 VREF + 0.125 VREF + 0.250 MAX 1.9 0.51 x V DD VREF + 0.04 VDDQ VREF - 0.125 VREF - 0.250 UNITS V 0.65 x VDDQ 0.675 0.600 0 0.35 x VDDQ 1.125 -8 8 70 mA °C Guaranteed by design, not 100% tested in production. Note: Rst# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Rst# is low. 1240—07/17/06 20 ICSSSTUBF32866A Advance Information Electrical Characteristics - DC TA = 0 - 70°C; VDD = 1.8 +/-0.1V (unless otherwise stated) SYMBOL PARAMETERS VIK VOH VOL All Inputs II Standby (Static) I DD Operating (Static) IDDD Ci CONDITIONS I I = -18mA I OH = -6mA I OL = 6mA V I = VDD or GND RESET# = GND V I = VIH(AC) or VIL(AC), RESET# = V DD RESET# = V DD, Dynamic operating V I = VIH(AC) or V IL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 Dynamic Operating RESET# = V DD, (per each data input) V I = VIH(AC) or V IL (AC), CLK and CLK# switching 1:1 mode 50% duty cycle. One data Dynamic Operating input switching at half (per each data input) clock frequency, 50% 1:2 mode duty cycle V I = VREF ±350mV Data Inputs V ICR = 1.25V, VI(PP) = 360mV CLK and CLK# RESET# V I = VDD or GND VDD MIN 1.7V 1.7V 1.9V 1.2 TYP 0.5 5 100 -5 1.9V 40 mA 19 µA/ clock MHz/data 35 2.5 2 3.5 3 2.5 Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V ± 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_∆ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate) 21 µA µA µ/clock MHz 39 1.8V UNITS V Notes: 1 - Guaranteed by design, not 100% tested in production. 1240—07/17/06 MAX -1.2 pF ICSSSTUBF32866A Advance Information Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) fclock tW tACT tINACT V DD = 1.8V ±0.1V MIN MAX 410 PARAMETERS SYMBOL Clock frequency 1 - ns Differential inputs active time (See Notes 1 and 2) - 10 ns - 15 ns Differential inputs inactive time (See Notes 1 and 3) Setup time tsu Setup time tsu Setup time tsu Setup time tsu Setup time Hold time DCS# before CK↑, CK#↓, CSR# high CSR# before CK↑, CK#↓, DCS# high DCS# before CK↑, CK#↓, CSR# low DODT, DCKE and data before CK↑, CK#↓ tH 0.55 ns 0.55 ns 0.35 ns 0.35 ns PAR_IN before CK↑, CK#↓ 0.35 ns DCS#, DODT, DCKE and Q after CK↑, CK#↓ 0.35 ns 0.35 ns PAR_IN after CK↑, CK#↓ Hold time 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax MHz Pulse duration, CK, CK HIGH or LOW tsu Notes: UNITS Max input clock frequency 410 Propagation delay, single CK↑ to CK#↓ QN bit switching Propagation delay CK↑ to CK#↓ to PPO t PD Low to High propagation CK↑ to CK#↓ to QERR# tLH delay High to low propagation tHL CK↑ to CK#↓ to QERR# delay Propagation delay tPDMSS CK↑ to CK#↓ QN simultaneous switching High to low propagation t PHL Rst# ↓ to QN↓ delay High to low propagation t PHL Rst# ↓ to PPO↓ delay Low to High propagation Rst# ↓ to QERR#↑ t PLH delay 2. Guaranteed by design, not 100% tested in production. t PDM 1240—07/17/06 22 Units MHz 1.1 1.5 ns 0.5 1.7 ns 1.2 3 ns 1 2.4 ns - 1.6 ns 3 ns 3 ns 3 ns ICSSSTUBF32866A Advance Information VDD DUT TL=50Ω • CK Inputs CK# CK RL = 1000Ω • TL=350p s, 50Ω Out Test Point CL = 30 pF (see Note 1) Test Point RL = 1000Ω • RL = 100Ω • LOAD CIRCUIT Test Point VCMOS RST# Inp ut VDD VDD /2 VDD/2 t in act IDD (see Note 2) VID 0V CK CK t PL H 90% t PH L 10% VOH Ou tput VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR VTT VTT VICR VOLTAGE WAVEFORMS – PULSE DURATION LVCMOS RST# Input VID CK VIH VDD /2 VIL VICR t RPHL CK t su Inpu t VOL VOLTAGE WAVEFORMS – PROPAGATION DELA TIMES VID tw Inpu t VIC R VICR t act VREF VOH th Ou tput VREF VIH VTT VOL VOLTAGE WAVEFORMS – PROPAGATION DELA TIMES VIL VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES Figure 6 — Parameter M easurement I nfor mation (V DD = 1.8 V ± 0.1 V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM. 1240—07/17/06 23 ICSSSTUBF32866A Advance Information VDD DUT RL = 50Ω Out Test Point C L = 10 pF (see Note 1) LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOH 80% 20% dv _f VOL dt _f VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT DUT Out Test Point CL = 10 pF (see Note 1) RL = 50Ω LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT dt _r dv _r 80% VOH 20% Output VOL VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 - Output Slew - Rate Measurement Information (V DD = 1.8 V ± 0.1 V) Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 1240—07/17/06 24 ICSSSTUBF32866A Advance Information 3 Test circuits and switching waveforms (cont’d) 3.3 Error output load circuit and voltage measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. 10 MHz; VDD DUT RL = 1K Ω Out Test Point CL = 10 pF (see Note 1) LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT (1) CL includes probe and jig capacitance. Figure 28 — Load circuit, error output measurements LVCMOS RST# Input V CC V CC /2 0V t PLH V OH Output Waveform 2 V _ _ _ _ _ _ _ _ _0.15 __ 0V Figure 29 — Voltage waveforms, open-drain output low-to-high transition time with respect to reset input V I(PP) Timing Inputs V ICR VICR tPHL Output Waveform 1 ___________ V CC /2 V CC V OL Figure 30 — Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs V I(PP) Timing Inputs VICR VICR tPHL Output Waveform 2 V OH 0.15 V 0V Figure 31 — Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs 1240—07/17/06 25 ICSSSTUBF32866A Advance Information Test circuits and switching waveforms (cont’d) 3.4 Partial-parity-out load circuit and voltage measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 Ω input slew rate = 1 V/ns ± 20%, unless otherwise specified. 10 MHz; DUT Test Point Out CL = 5 pF (see Note A) RL = 1 k Ω (1) CL includes probe and jig capacitance. Figure 32 — Partial-parity-out load circuit, CK VICR VICR tPLH tPHL Vi(p-p) CK VOH VTT OUTPUT VOL 002aaa375 VTT = VDD /2 tPLH an tPHL are the same as tPD . VI(PP) = 600 mV Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs LVCMOS RST# VIH INPUT VDD /2 VIL tPHL VOH OUTPUT VTT VOL 002aaa376 VTT = VDD /2 tPLH an tPHL are the same as tPD . VIH = VRE F + 250 mV (AC voltage levels for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VRE F - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs. Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input 1240—07/17/06 26 ICSSSTUBF32866A Advance Information C Seating Plane A1 T Numeric Designations for Horizontal Grid b REF 4 3 2 1 A B C D D Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) d TYP D1 - e - TYP TOP VIEW E c REF h TYP 0.12 C - e - TYP E1 ALL DIMENSIONS IN MILLIMETERS ----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E h Min/Max 0.25/0.41 0.25/0.35 REF. DIMENSIONS b c 0.75 0.875 * Source Ref.: JEDEC Publication 95, 10-0055C Ordering Information ICSSSTUBF32866Az(LF)T Example: ICS XXXX y z (LF) T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type H = LFBGA (standard size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) Revision Designator (will not correlate with datasheet revision) Device Type 1240—07/17/06 Prefix ICS = Standard Device 27 0.75 0.875 MO-205 ICSSSTUBF32866A Advance Information Revision History Rev. 0.1 Issue Date Description 6/29/2006 Initial Release Page # - 1240—07/17/06 28