Holt HI-3587PCTF Arinc 429 transmitter with spi interface Datasheet

HI-3587
ARINC 429
Transmitter with SPI Interface
June 2009
GENERAL DESCRIPTION
44
43
42
41
40
39
38
37
36
35
34
N/C
N/C
N/C
N/C
N/C
N/C
MR
SI
CS
N/C
N/C
3.3V or 5.0V logic supply operation
On-chip analog line driver connects directly to
ARINC 429 bus
BOUT27
BOUT37
N/C
VN/C
TFLAG
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
SCK
N/C
GND
N/C
ACLK
SO
N/C
N/C
- N/C
- N/C
- N/C
- N/C
- VDD
- N/C
- V+
- N/C
- AOUT27
- AOUT37
- N/C
44
43
42
41
40
39
38
37
36
35
34
N/C - 1
N/C - 2
N/C - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
HI-3587PQI
HI-3587PQT
33 - BOUT27
32 - BOUT37
31 - N/C
30 - V29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - N/C
24 - N/C
23 - N/C
32 x 32 Transmit Data FIFO
Programmable data rate selection
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
·
·
·
·
·
·
·
ARINC specification 429 compliant
-
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
The HI-3587 applies the ARINC 429 protocol to the
transmitter. ARINC 429 databus timing comes from a 1
MHz clock input, or an internal counter can derive it from
higher clock frequencies having certain fixed values,
possibly the external host processor clock.
·
·
·
HI-3587PCI
HI-3587PCT
33
32
31
30
29
28
27
26
25
24
23
-
The Serial Peripheral Interface minimizes the number of
host interface signals and provides a small footprint device
that can be interfaced to a wide variety of industrystandard microcontrollers supporting SPI. Alternatively,
the SPI signals may be controlled using four general
purpose I/O port pins from a microcontroller or custom
FPGA. The SPI and all control signals are CMOS and TTL
compatible and support 3.3V or 5V operation.
FEATURES
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
12
13
14
15
16
17
18
19
20
21
22
The HI-3587 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to an ARINC 429 serial bus.
The device provides one ARINC 429 transmitter with 32 X
32 Transmit FIFO and built-in line driver. Transmit FIFO
status can be monitored using the programmable external
interrupt pin, or by polling the HI-3587 Status Register.
Other features include a programmable option of data or
parity in the 32nd bit, and the ability to switch the bitsignifiance of ARINC 429 labels. Line driver output pins
are available with different values of output resistance to
provide flexibility when using external lightning protection
circuitry.
N/C
N/C
N/C
N/C
VDD
N/C
V+
N/C
AOUT27
AOUT37
N/C
PIN CONFIGURATIONS (Top View)
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
32nd transmit bit can be data or parity
44 - Pin Plastic Quad Flat Pack (PQFP)
Low power
Industrial & extended temperature ranges
(DS3587 Rev. D)
HOLT INTEGRATED CIRCUITS
www.holtic.com
06/09
HI-3587
BLOCK DIAGRAM
VDD
ARINC 429
Line Driver
ARINC
Clock
Divider
ACLK
V+
10 Ohm
ARINC 429
Transmit
Data FIFO
ARINC 429
Transmit
Formatter
27 Ohm
AOUT27
27 Ohm
BOUT27
10 Ohm
SI
BOUT37
V-
SCK
CS
AOUT37
TFLAG
SPI
Interface
SO
Control Register
Status Register
GND
PIN DESCRIPTIONS
SIGNAL
FUNCTION
MR
SI
CS
SCK
GND
ACLK
SO
TFLAG
VBOUT37
BOUT27
AOUT27
AOUT37
V+
VDD
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
DESCRIPTION
Master Reset. A positive pulse clears the Transmit data FIFO and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when CS is low.
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply
Master timing source for the ARINC 429 transmitter
SPI interface serial data output
Goes high when ARINC 429 transmit FIFO is empty (CR14=0), or full (CR14=1)
Minus 5V power supply to ARINC 429 Line Driver
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 10 ohm resistor
Alternate ARINC line driver positive output. Requires external 10 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Positive 5V power supply to ARINC 429 Line Driver
3.3V or 5.0V logic power
HOLT INTEGRATED CIRCUITS
2
PULL UP / DOWN
10K ohm pull-down
10K ohm pull-down
10K ohm pull-up
10K ohm pull-down
10K ohm pull-down
HI-3587
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI3587. When CS goes low, the next 8 clocks at the SCK pin shift
an instruction op code into the decoder, starting with the first
rising SCK edge. The op code is fed into the SI pin, most
significant bit first.
Table 1 lists all instructions. Instructions that perform a reset or
set, or enable transmission are executed after the last SI bit is
received while CS is still low.
Example:
For write instructions, the most significant bit of the data word
must immediately follow the instruction op code and is clocked
into its register on the next rising SCK edge. Data word length
varies depending on word type written: 16-bit writes to Control
Register or 32-bit ARINC word writes to transmit FIFO.
For read instructions, the most significant bit of the requested
data word appears at the SO pin after the last op code bit is
clocked into the decoder, at the next falling SCK edge. As in
write instructions, read instruction data field bit-length varies with
read instruction type.
one SPI Instruction
CS
SCK
SI
op code 07hex
MSB
data field 02hex
LSB MSB
LSB
TABLE 1. DEFINED INSTRUCTION OP CODES
DESCRIPTION
OP CODE
Hex
DATA FIELD
00
None
No instruction implemented
01
None
After the 8th op-code bit is received, perform Master Reset (MR)
02
None
No instruction implemented
03
None
No instruction implemented
04
None
No instruction implemented
05
None
No instruction implemented
06
None
No instruction implemented
07
8 bits
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC transmitter operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no
clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock."
08
[Note 1]
Reserved [Note 1]
09
[Note 1]
Reserved [Note 1]
0A
8 bits
Read the Status Register
0B
16 bits
Read the Control Register
0C
8 bits
Read the ACLK divide value programmed previously using op code 07 hex
0D
[Note 1]
0E
N x 32 Bits
0F
None
No instruction implemented
10
16 bits
Write the Control Register
11
None
Reset the Transmitter FIFO. After the 8th op-code bit is received, the Xmit FIFO will be empty
12
None
Transmission enabled by this instruction only if Control Register bit 13 is zero
Reserved [Note 1]
Write up to 32 words into the next empty position of the Transmitter FIFO
Note 1: This instruction is reserved for factory test only. If executed, up to 1,024 data bits may be output from the SO pin.
HOLT INTEGRATED CIRCUITS
3
HI-3587
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
STATUS REGISTER
The HI-3587 has a 16-bit Control Register which configures the
device. Control Register bits CR15 - CR0 are loaded from a 16-bit
data value appended to SPI instruction 10 hex. The Control
Register contents may be read using SPI instruction 0B hex. Each
bit of the Control Register has the following function:
The HI-3587 contains an 8-bit Status Register which can be
interrogated to determine status of the ARINC Transmit FIFO. The
Status Register is read using SPI instruction 0A hex. Unused bits
are undefined and may be read as either “1” or “0”. The following
table defines the Status Register bits.
CR
Bit FUNCTION STATE
DESCRIPTION
SR
Bit
FUNCTION
STATE
DESCRIPTION
CR0
(LSB)
-
X
Not used
SR0
(LSB)
Not used
X
Undefined
CR1
ARINC Clock
Source Select
0
ARINC CLK = ACLK input frequency
SR1
Not used
X
Undefined
1
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
SR2
Not used
X
Undefined
SR3
Transmit FIFO
Empty
0
Transmit FIFO not empty.
Sets to One when all data has
been sent. TFLAG pin reflects the
state of this bit when CR14=0
1
Transmit FIFO is empty.
0
Transmit FIFO contains less than 16
words
1
Transmit FIFO contains at least 16
words
0
Transmit FIFO not full. TFLAG pin
reflects the state of this bit when
CR14=1
1
Transmit FIFO full.
CR2
-
X
Not used
CR3
Transmitter
Parity Bit
Enable
0
Transmitter 32nd bit is data
1
Transmitter 32nd bit is parity
CR4
-
X
Not used
CR5
-
X
Not used
CR6
-
X
Not used
CR7
-
X
Not used
CR8
-
X
Not used
CR9
Transmitter
Parity
Select
0
Transmitter 32nd bit is Odd parity
1
Transmitter 32nd bit is Even parity
SR6
Not used
0
Always 0
Transmitter
Data Rate
0
Data rate=CLK/10, O/P slope=1.5u
SR7
(MSB)
Not used
0
Always 0
CR10
CR11 ARINC Label
Bit Order
CR12
Disable
Line Driver
CR13 Transmission
Enable Mode
Cr14
CR15
(MSB)
TFLAG
Definition
-
1
Data rate=CLK/80, O/P slope=10us
0
Label bit order reversed (See Table 2)
1
Label bit order same as transmitted
(See Table 2)
0
Line Driver enabled
1
Line Driver disabled (force outputs to Null state)
0
Start transmission by SPI
instruction12h
1
Transmit whenever data is available
in the Transmit FIFO
0
TFLAG goes high when transmit FIFO is empty
1
TFLAG goes high when transmit FIFO is full
X
Not used
SR4
SR5
Transmit FIFO
Half Full
Transmit FIFO
Full
HOLT INTEGRATED CIRCUITS
4
HI-3587
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
transmitted ARINC word are mapped to the HI-3587 SPI data word
bits during data read or write operations. The following table
describes this mapping:
Table 2. SPI / ARINC bit-mapping
23 24 25 26 27 28 29 30 31 32
. ARINC bit 32
31 - 11
10
9
1
2
3
4
5
6
7
8
Data
SDI
SDI
Label (MSB)
Label
Label
Label
Label
Label
Label
Label (LSB)
31 - 11
10
9
8
7
6
5
4
3
2
1
Data
SDI
Label (LSB)
Label
Label
Label
Label
Label
Label
CR11=0
CR11=1
Parity
ARINC bit 32
Label (MSB)
2 - 22
Parity
1
SDI
SPI
Order
TRANSMITTER
FIFO OPERATION
The Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op code 0E hex writes up to 32 ARINC words into
the FIFO, starting at the next available FIFO location. If Status
Register bit SR3 equals “1” (FIFO empty), then up to 32 words
(32 bits each) may be loaded. If Status Register bit SR3 equals “0”
then only the available positions may be loaded. If all 32 positions
are full, Status Register bit SR5 is asserted. Further attempts to load
the Transmit FIFO are ignored until at least one ARINC word is
transmitted.
The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”
when the Transmit FIFO contains less than 16 words. When SR4
equals “0”, the system microprocessor can safely initiate a 16-word
ARINC block-write sequence.
In normal operation (Control Register bit CR3 = ”1”), the 32nd bit
transmitted is a word parity bit. Odd or even parity is selected by
programming Control Register bit CR9 to a “0” or “1” respectively. If
Control Register bit CR3 equals “0”, all 32 bits loaded into the
Transmit FIFO are treated as data and are transmitted.
SPI op code 11 hex asynchronously clears all data in the Transmit
FIFO.
DATA TRANSMISSION
If Control Register bit CR13 equals “1”, ARINC 429 data is
transmitted immediately following the CS rising edge of the SPI
instruction that loaded data into the Transmit FIFO. Loading
Control Register bit CR13 to “0” allows the software to control
transmission timing; each time a 12 hex SPI op code is executed,
all loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 12 hex instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
AOUT and BOUT. The 31 or 32 bits in the data transmission shift
register are presented sequentially to the outputs in the ARINC 429
format with the following timing:
CR3, CR9
32 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
AOUT
BOUT
CR12
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
START
SEQUENCE
32 x 32 FIFO
ADDRESS
WORD COUNTER
AND
FIFO CONTROL
LOAD
SR3
SR4
SR5
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
SCK
SPI COMMANDS
CS
SI
SPI INTERFACE
SPI COMMANDS
DATA
CLOCK
SO
CR10, CR1
FIGURE 1.
DATA CLOCK
DIVIDER
TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
ACLK
HI-3587
FUNCTIONAL DESCRIPTION (cont.)
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions have been
transmitted and sets the Status Register transmitter ready flag,
SR3, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If control
register bit CR9 is set to a “0”, the 32nd bit transmitted will make
parity odd. If the control bit is a “1”, the parity is even. Setting CR3
to “0” bypasses the parity generator, and allows 32 bits of data to be
transmitted.
LINE DRIVER OPERATION
The line driver in the HI-3587 directly drives the ARINC 429 bus.
The two ARINC outputs (AOUT37 and BOUT37) provide a
differential voltage to produce a +10V One, a -10V Zero, and a 0
Volt Null. Control Register bit CR10 controls both the transmitter
data rate and the slope of the differential output signal. No
additional hardware is required to control the slope.
Transmit timing is derived from a 1MHz reference clock. Control
register bit CR1 determines the reference clock source. If CR1
equals ”0,” a 50% duty cycle 1MHz clock should be applied to the
ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to
generate the 1 MHz ARINC clock. SPI op code 07 hex provides the
HI-3587 with the correct division ratio to generate a 1 MHZ
reference from ACLK.
Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data
rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to
“1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is
set by an on-chip resistor and capacitor and tested to be within
ARINC 429 requirements.
LINE DRIVER OUTPUT PINS
The HI-3587 AOUT37 and BOUT37 pins have 37.5 Ohms in
series with each line driver output, and may be directly connected
to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins
have 27 ohms of internal series resistance and require external 10
ohm resistors at each pin. AOUT27 and BOUT27 are for
applications where external series resistance is applied, usually
for lightning protection.
POWER SUPPLY SEQUENCING
Power supply sequencing should be controlled to prevent large
currents during supply turn-on and turn-off. The recommended
sequence is V+ followed by VDD, always ensuring that V+ is the
most positive supply. The V- supply is not critical and can be
applied at any time.
MASTER RESET (MR)
Application of a Master Reset causes immediate termination of
data transmission. The transmit FIFO is cleared. Status Register
FIFO flags and FIFO status output signal TFLAG is also cleared.
The Control Register is not affected by a Master Reset.
TIMING DIAGRAMS
SERIAL INPUT TIMING DIAGRAM
t CPH
t CYC
CS
tCHH
t SCKF
t CES
t CEH
SCK
t DS
t DH
SI
t SCKR
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
t CYC
CS
t SCKH
tSCKL
SCK
t
SO
Hi Impedance
t CHZ
DV
MSB
HOLT INTEGRATED CIRCUITS
6
LSB
Hi Impedance
HI-3587
TIMING DIAGRAMS (Cont.)
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
NULL
DATA
DATA
DATA
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
TRANSMITTING DATA
CS
SPI INSTRUCTION 0Eh, (or 12h)
SI
t TFLG
tDATT
TFLAG (CR14=0)
ARINC BIT
DATA
BIT 1
t SDAT
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 32
+5V
+5V
AOUT
-5V
+5V
BOUT
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(AOUT - BOUT)
tfx
10%
trx
one level
trx
10%
zero level
90%
null level
-10V
HEAT SINK - CHIP-SCALE PACKAGE ONLY
The HI-3587PCI and HI-3587PCT use a 44-pin plastic
chip-scale package. This package has a metal heat sink
pad on its bottom surface. This heat sink is electrically
connected to the die. To enhance thermal dissipation, the
heat sink can be soldered to matching circuit board pad.
The heat sink may be connected to V+ or left floating.
Do not connect heat sink pad to VDD, GND or V-.
HOLT INTEGRATED CIRCUITS
7
HI-3587
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VDD ......................................... -0.3V to +7.0V
V+ ......................................................... +7.0V
V- ......................................................... -7.0V
Power Dissipation at 25°C
Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C
Voltage at any logic pin ................................-0.3V to VDD +0.3V
Storage Temperature Range ........................ -65°C to +150°C
DC Current Drain per pin ..............................................
Operating Temperature Range (Industrial): .... -40°C to +85°C
(Hi-Temp): .....-55°C to +125°C
±10mA
Solder temperature (Leads) .................... 280°C for 10 seconds
(Package) .......................................... 220°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5.0V , V+ = +5V, V- = -5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS
Input Voltage:
Input Current:
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
Pull-down Current (MR, SI, SCK, ACLK pins)
Pull-up Current (CS pin)
IIH
IIL
IPD
IPU
80% VDD
20% VDD
1.5
-1.5
250
-600
V
V
600
-300
µA
µA
µA
µA
ARINC OUTPUTS - Pins AOUT37, BOUT37, (or AOUT27, BOUT27 with external 10 Ohms)
ARINC output voltage (Ref. To GND)
One or zero
Null
VDOUT
VNOUT
No load and magnitude at pin,
4.50
-0.25
5.00
5.50
0.25
V
V
ARINC output voltage (Differential)
One or zero
Null
VDDIF
VNDIF
No load and magnitude at pin,
9.0
-0.5
10.0
11.0
0.5
V
V
IOUT
Momentary current
80
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
90%VDD
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
ARINC output current
mA
LOGIC OUTPUTS
Output Voltage:
Output Current:
(All Outputs & Bi-directional Pins)
Output Capacitance:
CO
10% VDD
V
V
-1.0
mA
mA
15
pF
Operating Voltage Range
VDD
3.15
5.25
V
V+
4.75
5.5
V
V-
-4.75
-5.5
V
Operating Supply Current
VDD
IDD1
2.5
7
mA
V+
IDD2
4
14
mA
V-
IEE1
4
12
mA
HOLT INTEGRATED CIRCUITS
8
HI-3587
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5.0V, V+=+5V, V-=-5V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 60/40
duty cycle
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI INTERFACE TIMING
SCK clock period
CS active after last SCK rising edge
CS setup time to first SCK rising edge
CS hold time after last SCK falling edge
CS inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK rise time
SCK fall ime
SCK pulse width high
SCK pulse width low
SO valid after SCK falling edge
SO high-impedance after SCK falling edge
tCYC
tCHH
tCES
tCEH
tCPH
tDS
tDH
tSCKR
tSCKF
tSCKH
tSCKL
tDV
tCHZ
SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full)
SPI instruction to ARINC 429 data output - Hi Speed
SPI instruction to ARINC 429 data output - Lo Speed
Delay TFLAG high after enable transmit - Hi Speed
Delay TFLAG high after enable transmit - Lo Speed
Line driver transition differential times:
high to low
(High Speed, control register CR10 = Logic 0)
low to high
(Low Speed, control register CR10 = Logic 1)
high to low
low to high
tTFLG
tSDAT
tSDAT
tDATT
tDATT
200
10
10
40
35
30
30
95
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
17
118
14
114
ns
µs
µs
µs
µs
2.0
2.0
15
15
µs
µs
µs
µs
10
10
90
80
TRANSMITTER TIMING
tfx
trx
tfx
trx
1.0
1.0
5.0
5.0
1.5
1.5
10
10
ORDERING INFORMATION
HI - 3587 xx x x
PART
NUMBER
LEAD
FINISH
Blank
F
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
PART
NUMBER
PACKAGE
DESCRIPTION
PC
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)
PQ
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)
HOLT INTEGRATED CIRCUITS
9
HI-3587
REVISION HISTORY
Revision
Date
DS3587, Rev. NEW 05/08/08
Rev. A 06/09/08
Rev. B 10/10/08
Rev. C 05/22/09
Rev. D 06/09/09
Description of Change
Initial Release
Clarified the FIFO description
Revised AC Electrical Characteristics
Clarified the relationship between SPI bit order and the ARINC 429 bit order
Clarified the written description of CR1 and its relationship with ACLK.
HOLT INTEGRATED CIRCUITS
10
HI-3587 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 44PCS
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
.020 BSC
(0.50)
.276
BSC
(7.00)
.203 ± .006
(5.15 ± .15)
Top View
Bottom
View
.010
(0.25) typ
.039
max
(1.00)
.008 typ
(0.2)
.016 ± .002
(0.40 ± .05)
Heat sink pad on bottom of package.
Heat sink must be left floating or
connected to V+
DO NOT connect to GND, VDD or V-.
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PTQS
.006 MAX.
(.15)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.547 ± .010
(13.90 ± .25)
SQ.
.014 ± ..002
(.35 ± .05)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.055 ± .002
(1.4 ± .05)
.063
MAX.
(1.6)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.005
R MIN. Detail A
(.13)
HOLT INTEGRATED CIRCUITS
11
0° £ Q £ 7°
Similar pages