LDLN025 250 mA ultra low noise LDO Datasheet - production data Description The LDLN025 is a 250 mA low-dropout voltage regulator, able to work with an input voltage range from 1.5 V to 5.5 V. The typical dropout voltage at 250 mA load is 120 mV. The very low quiescent current, which is just 12 μA at no-load, extends battery-life of applications requiring very long standby time. Features Ultra low output noise: 6.5 μVRMS Operating input voltage range: 1.5 V to 5.5 V Output current up to 250 mA Very low quiescent current: 12 μA at no-load Controlled Iq in dropout condition Very low-dropout voltage: 250 mV at 250 mA Very high PSRR: 80 dB@100 Hz, 60 dB@100 kHz Output voltage accuracy: 2% across line, load and temperature Output voltage versions: from 1 V to 5 V, with 50 mV step Logic-controlled electronic shutdown Output discharge feature Internal soft-start Overcurrent and thermal protections Temperature range: from -40 °C to +125 °C Packages: Flip-Chip4, DFN4-1x1 Thanks to its ultra low noise value and high PSRR, the LDLN025 provides a very clean output, suitable for ultra-sensitive loads. It is stable with ceramic capacitors. The enable logic control function puts the device into shutdown mode allowing a total current consumption lower than 1 μA. The device also includes short-circuit and thermal protection. Typical applications are noise sensitive loads such as ADC, VCO in mobile phones and tablets, wireless LAN devices. The LDLN025 is designed to keep the quiescent current under control and at a low value also during dropout operation, extending the operating time of battery-powered devices. Several small package options are available. Applications Smartphones/tablets Image sensors Instrumentation VCO and RF modules November 2016 DocID029566 Rev 4 This is information on a product in full production. 1/22 www.st.com Contents LDLN025 Contents 1 Block diagram.................................................................................. 3 2 Pin configuration ............................................................................. 4 3 Typical application diagram ........................................................... 5 4 5 Maximum ratings ............................................................................. 6 Electrical characteristics ................................................................ 7 6 Typical characteristics .................................................................... 9 7 Package information ..................................................................... 14 8 7.1 Flip-Chip4 package information....................................................... 15 7.2 Flip-Chip4 packing information ........................................................ 17 7.3 DFN4-1x1 package information....................................................... 18 7.4 DFN4-1x1 packing information ........................................................ 19 Ordering information..................................................................... 20 8.1 9 2/22 Marking information ......................................................................... 20 Revision history ............................................................................ 21 DocID029566 Rev 4 LDLN025 1 Block diagram Block diagram Figure 1: Block diagram DocID029566 Rev 4 3/22 Pin configuration 2 LDLN025 Pin configuration Figure 2: Pin configuration Table 1: Pin description Symbol DFN4-1x1 Flip-Chip4 Description VIN 4 A1 LDO Supply voltage VOUT 1 A2 LDO Output voltage GND 2 B2 Ground B1 Enable input: set VEN = high to turn on the device; VEN = low to turn off the device EN 3 This pin is internally pulled down via 1 MΩ resistor 4/22 NC - - Not internally connected: can be connected to GND Exposed pad Exposed pad - Must be connected to GND DocID029566 Rev 4 LDLN025 3 Typical application diagram Typical application diagram Figure 3: Typical application diagram DocID029566 Rev 4 5/22 Maximum ratings 4 LDLN025 Maximum ratings Table 2: Absolute maximum ratings Symbol VIN Parameter Unit -0.3 to 7 V VOUT Output voltage -0.3 to VIN +0.3 V IOUT Output current Internally limited A EN Enable pin voltage -0.3 to VIN +0.3 V PD Power dissipation Internally limited W ESD Input supply voltage Value Charge device model ±1000 Human body model ±2000 TJ-OP Operating junction temperature TJ-MAX Maximum junction temperature TSTG Storage temperature V -40 to 125 °C 150 °C -55 to 150 °C Table 3: Thermal data Symbol Rthja 6/22 Parameter Thermal resistance, junction-to-ambient DocID029566 Rev 4 DFN4-1x1 Flip-Chip4 Unit 220 210 °C/W LDLN025 5 Electrical characteristics Electrical characteristics (TJ = 25 °C, VIN = VOUT(nom) + 1 V or 1.5 V, whichever is greater; VEN = 1.2 V; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA) Table 4: Electrical characteristics Symbol VIN VOUT Parameter Test conditions Operating input voltage range VOUT + 1 V(1) < VIN < 5.5 V, 1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V, -40 °C < TJ < 125 °C Output voltage accuracy VOUT + 1 V(1) < VIN < 5.5 V, 1 mA < IOUT < 0.25 A, VOUT < 1.8 V, -40 °C < TJ < 125 °C Min. Max. Unit 1.5 5.5 V -2.0 2.0 % -3.0 VOUT + 1 V(1) < VIN < 5.5 V -40 °C < TJ < 125 °C ∆VOUT/∆VIN ∆VIN = +/- 0.6 V, trise = tfall = 30 μs Line transient(2) ∆VOUT VDROP eN SVR +3.0 0.02 Static line regulation ∆VOUT/∆IOUT Typ. ∆IOUT = 1 mA to 250 mA and back, trise = tfall = 10 μs Overshoot on startup(2) Percentage of VOUT(nom) voltage(3) Supply voltage rejection(2) +1 0.007 -40 +40 5 IOUT = 0.1 A 50 IOUT = 0.25 A 120 IOUT = 0.25 A, -40 °C < TJ < 125 °C (Flip-Chip4) 200 IOUT = 0.25 A, -40 °C < TJ < 125 °C (DFN4-1x1) 250 f = 10 Hz to 100 kHz; IOUT = 1 mA %/V mV 0.002 -40 °C < TJ < 125 °C Load transient(2) Output noise voltage (2) -1 1 mA < IOUT < 0.25 A Static load regulation Dropout 0.06 %/mA mV % mV 10 µVRMS f = 10 Hz to 100 kHz; IOUT = 250 mA 6.5 f = 100 Hz; IOUT = 20 mA 80 f = 1 kHz; IOUT = 20 mA 80 f = 10 kHz; IOUT = 20 mA 75 f = 100 kHz; IOUT = 20 mA 60 DocID029566 Rev 4 dB 7/22 Electrical characteristics Symbol LDLN025 Parameter Test conditions Min. Typ. IOUT = 0 A Quiescent current(4) µA IOUT = 0 A; -40 °C < TJ < 125 °C 25 250 µA IOUT = 0.25 A; -40 °C < TJ < 125 °C ISC RLOW Shutdown current VEN = 0 V Short-circuit current VOUT = 0 V Output discharge resistance VEN = 0 V VIL, enable input logic low VEN IEN tON TSHDN 425 0.2 250 VOUT + 1 V (1)< VIN < 5.5 V -40 °C < TJ < 125 °C VIH, enable input logic high 1 µA 500 mA 230 Ω 0.4 V 1.2 VIN = VEN = 5.5 V Enable pin input current Unit 12 IOUT = 0.25 A IQ Max. 5.5 µA VIN = 5.5 V; VEN = 0 V 0.001 Turn-on time(2) From VEN > VIH to VOUT = 95 % of VOUT(nom) 80 Thermal shutdown(2) IOUT > 1 mA 160 150 µs °C Hysteresis 20 Notes: (1) VIN = VOUT + 1 V or 1.5 V, whichever is greater. Not applicable for 5 V output voltage versions. (2) Guaranteed by design. (3) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. (4) The quiescent current is defined as IIN-IOUT and does not include the EN pin current. Table 5: Recommended input and output capacitors Symbol CIN 8/22 Parameter Test conditions Input capacitance COUT Output capacitance ESR Output/input capacitance Min. Typ. 0.7 1 0.7 1 Max. μF Stability DocID029566 Rev 4 5 Unit 10 500 mΩ LDLN025 6 Typical characteristics Typical characteristics (The following plots are referred to LDLN025J2925R in the typical application circuit and, unless otherwise noted, at TA = 25 °C). Figure 4: Output voltage vs temperature (VIN = 3.925 V) Figure 5: Output voltage vs temperature (VIN = 5.5 V) Figure 6: Load regulation vs temperature Figure 7: Line regulation vs temperature DocID029566 Rev 4 9/22 Typical characteristics LDLN025 Figure 8: Quiescent current vs temperature (IOUT = 0 mA) Figure 9: Quiescent current vs temperature (IOUT = 250 mA) Figure 10: GND current vs input voltage Figure 11: Off-state current vs temperature Figure 12: Quiescent current vs output current Figure 13: Quiescent current vs output current (zoom) 10/22 DocID029566 Rev 4 LDLN025 Typical characteristics Figure 14: Dropout voltage vs temperature Figure 15: Dropout voltage vs load current Figure 16: Output voltage vs input voltage Figure 17: Short circuit current vs dropout voltage Figure 18: Enable threshold vs temperature Figure 19: Stability region vs COUT and ESR DocID029566 Rev 4 11/22 Typical characteristics 12/22 LDLN025 Figure 20: PSRR vs frequency Figure 21: Noise density Figure 22: Line transient (IOUT = 1 mA) Figure 23: Line transient (IOUT = 250 mA) DocID029566 Rev 4 LDLN025 Typical characteristics Figure 24: Load transient Figure 25: Inrush current Figure 26: Enable transient (IOUT = 0 mA) Figure 27: Enable transient (IOUT = 250 mA) DocID029566 Rev 4 13/22 Package information 7 LDLN025 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 14/22 DocID029566 Rev 4 LDLN025 7.1 Package information Flip-Chip4 package information Figure 28: Flip-Chip4 package outline DocID029566 Rev 4 15/22 Package information LDLN025 Table 6: Flip-Chip4 mechanical data mm Dim. Min. Typ. Max. A 0.375 0.410 0.445 A1 0.145 0.160 0.175 A2 0.230 0.250 0.270 b 0.189 0.210 0.231 D 0.598 0.628 0.658 D1 E 0.350 0.598 0.628 E1 0.350 SD 0.175 SE 0.175 f 0.139 ccc 0.075 Figure 29: Flip-Chip4 recommended footprint 16/22 DocID029566 Rev 4 0.658 LDLN025 7.2 Package information Flip-Chip4 packing information Figure 30: Flip-Chip4 carrier tape DocID029566 Rev 4 17/22 Package information 7.3 LDLN025 DFN4-1x1 package information Figure 31: DFN4-1x1 package outline 18/22 DocID029566 Rev 4 LDLN025 Package information Table 7: DFN4-1x1 package mechanical data mm Dim. Min. Max. A 0.36 0.40 A1 0.00 0.05 A2 0.15 A3 0.25 0.35 0.125 b 0.15 0.20 0.25 D 0.95 1.00 1.05 D2 0.38 0.48 0.58 e 7.4 Typ. 0.65 E 0.95 1.00 1.05 E2 0.38 0.48 0.58 L 0.15 0.35 K 0.25 0.15 N 4 DFN4-1x1 packing information Figure 32: DFN4 (1x1x0.38 pitch 4 mm) carrier tape DocID029566 Rev 4 19/22 Ordering information 8 LDLN025 Ordering information Table 8: Order code Order code Package Output voltage Marking LDLN025PU18R 1.8 V 18 LDLN025PU25R 2.5 V 25 LDLN025PU275R 2.75 V 2Z LDLN025PU28R 2.8 V 28 2.9 V 29 LDLN025PU30R 3.0 V 30 LDLN025PU32R 3.2 V 32 LDLN025PU33R 3.3 V 33 LDLN025PU50R 5.0 V 50 LDLN025J12R 1.2 V M LDLN025J18R 1.8 V E LDLN025J25R 2.5 V H LDLN025J28R 2.8 V I 2.925 V K LDLN025J30R 3.0 V G LDLN025J32R 3.2 V N LDLN025J33R 3.3 V F LDLN025J50R 5.0 V P LDLN025PU29R LDLN025J2925R 8.1 DFN4-1x1 Flip-Chip4 Packing Tape and reel Marking information Figure 33: Flip-Chip marking composition (marking view) the symbol # indicates the marking digit, as per Table 8: "Order code". 20/22 DocID029566 Rev 4 LDLN025 9 Revision history Revision history Table 9: Document revision history Date Revision Changes 03-Aug-2016 1 First release. 01-Sep-2016 2 Updated Table 8: “Order code”. Minor text changes. 24-Oct-2016 3 Updated Table 2: "Absolute maximum ratings". Minor text changes. 17-Nov-2016 4 Updated Section 8: "Ordering information". Minor text changes. DocID029566 Rev 4 21/22 LDLN025 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 22/22 DocID029566 Rev 4