LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 LP3853/LP3856 3A Fast Response Ultra Low Dropout Linear Regulators Check for Samples: LP3853, LP3856 FEATURES DESCRIPTION • • • • • • • • • • • • The LP3853/LP3856 series of fast ultra low-dropout linear regulators operate from a +2.5V to +7.0V input supply. Wide range of preset output voltage options are available. These ultra low dropout linear regulators respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor applications. The LP3853/LP3856 are developed on a CMOS process which allows low quiescent current operation independent of output load current. This CMOS process also allows the LP3853/LP3856 to operate under extremely low dropout conditions. 1 2 Ultra Low Dropout Voltage Stable with Selected Ceramic Capacitors Low Ground Pin Current Load Regulation of 0.08% 10nA Quiescent Current in Shutdown Mode Ensured Output Current of 3A DC Available in TO-263 and TO-220 Packages Output Voltage Accuracy ± 1.5% Error Flag Indicates Output Status Sense Option Improves Load Regulation Overtemperature/overcurrent Protection −40°C to +125°C Junction Temperature Range Ground Pin Current: Typically 4mA at 3A load current. APPLICATIONS • • • • • • • • • Dropout Voltage: Ultra low dropout voltage; typically 39mV at 300mA load current and 390mV at 3A load current. Microprocessor Power Supplies Stable with Ceramic Output Capacitors GTL, GTL+, BTL, and SSTL Bus Terminators Power Supplies for DSPs SCSI Terminator Post Regulators High Efficiency Linear Regulators Battery Chargers Other Battery Powered Applications Shutdown Mode: Typically 10nA quiescent current when the shutdown pin is pulled low. Error Flag:Error flag goes low when the output voltage drops 10% below nominal value. SENSE: Sense pin improves regulation at remote loads. Precision Output Voltage: Multiple output voltage options are available ranging from 1.8V to 5.0V with a ensured accuracy of ±1.5% at room temperature, and ±3.0% over all conditions (varying line, load, and temperature). Typical Application Circuits INPUT 3.3V ± 10% VIN CIN* 10 PF VOUT COUT* LP3853-1.8 SD** SD ERROR GND ERROR** VOUT 1.8V, 3.0A 10 PF * TANTALUM OR CERAMIC **SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See Application Hints for more information. INPUT 3.3V ± 10% VIN CIN* 10 PF VOUT LP3856-1.8 SD** SD SENSE GND COUT* VOUT 1.8V, 3.0A 10 PF * TANTALUM OR CERAMIC **SD pin must be pulled high through a 10kΩ pull-up resistor. See Application Hints for more information. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 1. Top View TO220-5 Package Bent, Staggered Leads Figure 2. Top View TO263-5 Package Table 1. Pin Description for TO220-5 and TO263-5 Packages Pin # LP3853 Name LP3856 Function Name Function 1 SD Shutdown SD Shutdown 2 VIN Input Supply VIN Input Supply 3 GND Ground GND Ground 4 VOUT Output Voltage VOUT Output Voltage 5 ERROR ERROR Flag SENSE Remote Sense Pin Block Diagram LP3853 Figure 3. 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 LP3856 Figure 4. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 5 sec.) ESD Rating 260°C (2) Power Dissipation 2 kV (3) Internally Limited −0.3V to +7.5V Input Supply Voltage (Survival) −0.3V to 7.5V Shutdown Input Voltage (Survival) Output Voltage (Survival), (4) (5) −0.3V to +6.0V , IOUT (Survival) Short Circuit Protected Maximum Voltage for ERROR Pin VIN Maximum Voltage for SENSE Pin VOUT (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surfacemount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints. If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground. The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp of peak current. Operating Ratings (1) 2.5V to 7.0V Shutdown Input Voltage −0.3V to 7.0V Input Supply Voltage Maximum Operating Current (DC) 3A −40°C to +125°C Junction Temperature (1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 3 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Electrical Characteristics LP3853/LP3856 Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V. Symbol VO ΔV OL ΔVO/ ΔIOUT VIN - VOUT IGND Parameter Output Voltage Tolerance (3) Output Voltage Line Regulation (3) Output Voltage Load Regulation (3) Dropout Voltage Conditions Typ (1) LP3853/6 Min Max -1.5 -3.0 +1.5 +3.0 Units VOUT +1V ≤ VIN ≤ 7.0V 10 mA ≤ IL ≤ 3A 0 VOUT +1V ≤ VIN ≤ 7.0V 0.02 0.06 % 10 mA ≤ IL ≤ 3A 0.08 0.14 % IL = 300 mA 39 50 65 IL = 3A 390 450 600 IL = 300 mA 4 9 10 IL = 3A 4 9 10 0.01 10 (4) Ground Pin Current In Normal Operation Mode (2) IGND Ground Pin Current In Shutdown Mode VSD ≤ 0.3V IO(PK) Peak Output Current VO ≥ VO(NOM) - 4% -40°C ≤ TJ ≤ 85°C 50 % mV mA µA 4.5 A 6 A Short Circuit Protection ISC Short Circuit Current Shutdown Input VSDT Shutdown Threshold VSDT Rising from 0.3V until Output = ON 1.3 VSDT Falling from 2.0V until Output = OFF 1.3 2 V 0.3 TdOFF Turn-off delay IL = 3A 20 µs TdON Turn-on delay IL = 3A 25 µs SD Input Current VSD = VIN 1 nA ISD Error Flag Threshold (5) VTH Threshold Hysteresis (5) VEF(Sat) Error Flag Saturation VT (4) (5) 4 5 5 2 0.02 16 % 8 % 0.1 V Td Flag Reset Delay 1 µs Ilk Error Flag Pin Leakage Current 1 nA 1 mA Imax (1) (2) (3) Isink = 100µA 10 Error Flag Pin Sink Current VError = 0.5V Typical numbers are at 25°C and represent the most likely parametric norm. Limits are ensured by testing, design, or statistical correlation. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.5V. Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 Electrical Characteristics LP3853/LP3856 (continued) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V. Symbol Parameter Conditions Typ (1) LP3853/6 Min (2) Max Units AC Parameters PSRR Ripple Rejection ρn(l/f Output Noise Density en Output Noise Voltage VIN = VOUT + 1V COUT = 10uF VOUT = 3.3V, f = 120Hz 73 VIN = VOUT + 0.5V COUT = 10uF VOUT = 3.3V, f = 120Hz 57 f = 120Hz 0.8 BW = 10Hz – 100kHz VOUT = 2.5V 150 BW = 300Hz – 300kHz VOUT = 2.5V 100 dB µV µV (rms) Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 5 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA. Ground Current vs Output Load Current VOUT = 5V Dropout Voltage vs Output Load Current 600 o 12 5 4.9 C o 25 400 300 o -40 GROUND PIN CURRENT (mA) DROPOUT VOLTAGE (mV) 500 C C 200 100 0 0 1 2 3 4.85 4.8 4.75 4.7 125oC 4.65 25oC 4.6 4.55 -40oC 4.5 4.45 4.4 LOAD CURRENT (A) 0 0.5 1 1.5 2 2.5 3 OUTPUT LOAD CURRENT (A) Figure 5. Figure 6. Ground Current vs Output Voltage IL = 3A Shutdown IQ vs Junction Temperature 10 5 1 SHUTDOWN IQ (PA) GROUND PIN CURRENT (mA)_ 6 4 3 2 0.1 0.01 1 0 1.8 2.3 2.8 3.3 3.8 4.3 0.001 -40 -20 5.0 0 20 40 60 80 100 125 TEMPERATURE (oC) Figure 7. Figure 8. Errorflag Threshold vs Junction Temperature DC Load Reg. vs Junction Temperature 14 3 12 2.5 DC LOAD REGULATION (mV/A) ERROR THRESHOLD (% of VOUT) OUTPUT VOLTAGE (V) 10 8 6 4 2 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 125 0 -40 -20 0 20 40 60 80 100 125 o JUNCTION TEMPERATURE ( C) o JUNCTION TEMPERATURE ( C) Figure 9. 6 Figure 10. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA. VIN vs VOUT Over Temperature 3 3.0 2.5 2.5 2 2.0 VOUT (V) ' VOUT/VOLT CHANGE in VIN (mV) DC Line Regulation vs Temperature 1.5 1.5 -40oC 1 1.0 0.5 0.5 0 -40 25oC 125oC 0.0 -20 0 20 40 60 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 125 VIN (V) o JUNCTION TEMPERATURE ( C) Figure 11. Figure 12. Noise vs Frequency Load Transient Response CIN = COUT = 10µF, OSCON 3.000 VOUT 100mV/DIV 2.500 MAGNITUDE NOISE (PV/ Hz ( IL = 100mA CIN = COUT = 10PF 2.000 1.500 1.000 ILOAD 1A/DIV 0.500 0.000 100 1k 10k TIME (50Ps/DIV) 100k FREQUENCY (Hz) Figure 13. Figure 14. Load Transient Response CIN = COUT = 100µF, OSCON Load Transient Response CIN = COUT = 100µF, POSCAP VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 7 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA. Load Transient Response CIN = COUT = 10µF, TANTALUM Load Transient Response CIN = COUT = 100µF, TANTALUM VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 17. Figure 18. Load Transient Response CIN = COUT = 10µF, OSCON Load Transient Response CIN = COUT = 100µF, OSCON VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 3A/DIV ILOAD 3A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 19. Figure 20. Load Transient Response CIN = COUT = 100µF, POSCAP Load Transient Response CIN = COUT = 10µF, TANTALUM VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 3A/DIV 8 ILOAD 3A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA. Load Transient Response CIN = COUT = 100µF, TANTALUM Load Transient Response CIN = 4 x 10µF CERAMIC, COUT = 3 x 10µF CERAMIC VOUT 100 mV/DIV VOUT 100mV/DIV VOUT = 2.5V 1 MAGNITUDE T IOUT 1A/DIV ILOAD 3A/DIV T 2 TIME (50Ps/DIV) TIME (5 Ps/DIV) Figure 23. Figure 24. Load Transient Response CIN = 4 x 10µF CERAMIC, COUT = 3 x 10µF CERAMIC Load Transient Response CIN = 2 x 10µF CERAMIC, COUT = 2 x 10µF CERAMIC VOUT 100 mV/DIV VOUT 100 mV/DIV VOUT = 2.5V T 1 IOUT 1A/DIV T VOUT = 2.5V 1 T IOUT 1A/DIV T IOUT @ 1A 2 2 TIME (2 Ps/DIV) TIME (1 Ps/DIV) Figure 25. Figure 26. Load Transient Response CIN = 2 x 10µF CERAMIC, COUT = 2 x 10µF CERAMIC 1 VOUT @ 2.5V T IOUT @ 1A T 2 TIME (1 Ps/DIV) Figure 27. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 9 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION Application Hints EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor of at least 10µF is required. Ceramic or Tantalum may be used, and capacitance may be increased without limit OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them (see PCB Layout section). The minimum amount of output capacitance that can be used for stable operation is 10µF. For general usage across all load currents and operating conditions, the part was characterized using a 10µF Tantalum input capacitor. The minimum and maximum stable ESR range for the output capacitor was then measured which kept the device stable, assuming any output capacitor whose value is greater than 10µF (see Figure 28 below). 10 STABLE REGION COUT > 10PF COUT ESR (:) 1.0 0.1 .01 .001 0 1 2 3 LOAD CURRENT (A) Figure 28. ESR Curve for COUT (with 10µF Tantalum Input Capacitor) It should be noted that it is possible to operate the part with an output capacitor whose ESR is below these limits, assuming that sufficient ceramic input capacitance is provided. This will allow stable operation using ceramic output capacitors (see next section). OPERATION WITH CERAMIC OUTPUT CAPACITORS LP385X voltage regulators can operate with ceramic output capacitors if the values of input and output capacitors are selected appropriately. The total ceramic output capacitance must be equal to or less than a specified maximum value in order for the regulator to remain stable over all operating conditions. This maximum amount of ceramic output capacitance is dependent upon the amount of ceramic input capacitance used as well as the load current of the application. This relationship is shown in Figure 29, which graphs the maximum stable value of ceramic output capacitance as a function of ceramic input capacitance for load currents of 1A, 2A, and 3A. For example, if the maximum load current is 1A, a 10µF ceramic input capacitor will allow stable operation for values of ceramic output capacitance from 10µF up to about 500µF. 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 CERAMIC INPUT CAPACITANCE (PF) 100 3A 2A 1A 10 10 100 1000 MAX. ALLOWABLE CERAMIC OUTPUT CAPACITANCE (PF) Figure 29. Maximum Ceramic Output Capacitance vs Ceramic Input Capacitance If the maximum load current is 2A and a 10µF ceramic input capacitor is used, the regulator will be stable with ceramic output capacitor values from 10µF up to about 50µF. At 3A of load current, the ratio of input to output capacitance required approaches 1:1, meaning that whatever amount of ceramic output capacitance is used must also be provided at the input for stable operation. For load currents between 1A, 2A, and 3A, interpolation may be used to approximate values on the graph. When calculating the total ceramic output capacitance present in an application, it is necessary to include any ceramic bypass capacitors connected to the regulator output. SELECTING A CAPACITOR It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also typically have large temperature variation of capacitance value. Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics, as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors. Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so severe they may not be feasible for some applications (see Capacitor Characteristics Section). CAPACITOR CHARACTERISTICS CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. TANTALUM: Solid Tantalum capacitors are typically recommended for use on the output because their ESR is very close to the ideal value required for loop compensation. Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X going from the high to low temperature limits. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 11 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if the ESR of the capacitor is near the upper limit of the stability range at room temperature). ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in physical size, not widely available in surface mount, and have poor AC performance (especially at higher frequencies) due to higher ESR and ESL. Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X when going from 25°C down to −40°C. It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP385X. Derating must be applied to the manufacturer's ESR specification, since it is typically only valid at room temperature. Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating temperature where ESR is maximum. TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V are not affected by this behavior. PCB LAYOUT Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground". It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it's capacitors fixed the problem. Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. RFI/EMI SUSCEPTIBILITY RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's performance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator. If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC. If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor(s). In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly across the load. 12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. OUTPUT NOISE Noise is specified in two waysSpot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low frequency component and a high frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP3853/LP3856 achieves low noise performance and low quiescent current operation. The total output noise specification for LP3853/LP3856 is presented in the Electrical Characteristics table. The Output noise density at different frequencies is represented by a curve under typical performance characteristics. SHORT-CIRCUIT PROTECTION The LP3853 and LP3856 are short circuit protected and in the event of a peak over-current condition, the shortcircuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations. ERROR FLAG OPERATION The LP3853/LP3856 produces a logic low signal at the Error Flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing diagram in Figure 30 shows the relationship between the ERROR flag and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the Error Flag. The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull up resistor. Although the ERROR flag pin can sink current of 1mA, this current is energy drain from the input supply. Hence, the value of the pull up resistor should be in the range of 10kΩ to 1MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 13 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com Figure 30. Error Flag Operation SENSE PIN In applications where the regulator output is not very close to the load, LP3856 can provide better remote load regulation using the SENSE pin. Figure 31 depicts the advantage of the SENSE option. LP3853 regulates the voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the voltage at the remote load will be 3V with 3A of load current, ILOAD. The LP3856 regulates the voltage at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in Figure 31. If the sense option pin is not required, the sense pin must be connected to the VOUT pin. Figure 31. Improving remote load regulation using LP3856 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 SHUTDOWN OPERATION A CMOS Logic low level signal at the Shutdown (SD) pin will turn-off the regulator. Pin SD must be actively terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. The Shutdown (SD) pin threshold has no voltage hysteresis. If the Shutdown pin is actively driven, the voltage transition must rise and fall cleanly and promptly. DROPOUT VOLTAGE The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET. REVERSE CURRENT PATH The internal MOSFET in LP3853 and LP3856 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200mA continuous and 1A peak. POWER DISSIPATION/HEATSINKING LP3853 and LP3856 can deliver a continuous current of 3A over the full operating temperature range. A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND where IGND is the operating ground current of the device (specified under Electrical Characteristics). The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD LP3853 and LP3856 are available in TO-220 and TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 15 LP3853, LP3856 SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 www.ti.com HEATSINKING TO-263 PACKAGE The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. Figure 32 shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Figure 32. θJA vs Copper (1 Ounce) Area for TO-263 package As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W. Figure 33 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 33. Maximum power dissipation vs ambient temperature for TO-263 package 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 LP3853, LP3856 www.ti.com SNVS173G – FEBRUARY 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3853 LP3856 17 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3853ES-1.8 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3853ES -1.8 LP3853ES-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -1.8 LP3853ES-2.5 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3853ES -2.5 LP3853ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -2.5 LP3853ES-3.3 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3853ES -3.3 LP3853ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -3.3 LP3853ES-5.0/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -5.0 LP3853ESX-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -1.8 LP3853ESX-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -2.5 LP3853ESX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -3.3 LP3853ESX-5.0/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3853ES -5.0 LP3853ET-1.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3853ET -1.8 LP3853ET-2.5/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3853ET -2.5 LP3853ET-3.3/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3853ET -3.3 LP3853ET-5.0/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3853ET -5.0 LP3856ES-1.8 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3856ES -1.8 LP3856ES-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -1.8 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3856ES-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -2.5 LP3856ES-3.3 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3856ES -3.3 LP3856ES-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -3.3 LP3856ES-5.0 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3856ES -5.0 LP3856ES-5.0/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -5.0 LP3856ESX-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -1.8 LP3856ESX-2.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -2.5 LP3856ESX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -3.3 LP3856ESX-5.0/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3856ES -5.0 LP3856ET-1.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3856ET -1.8 LP3856ET-2.5/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3856ET -2.5 LP3856ET-3.3/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3856ET -3.3 LP3856ET-5.0/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3856ET -5.0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3853ESX-1.8/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3853ESX-2.5/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3853ESX-3.3/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3853ESX-5.0/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3856ESX-1.8/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3856ESX-2.5/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3856ESX-3.3/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP3856ESX-5.0/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3853ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3853ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3853ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3853ESX-5.0/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3856ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3856ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3856ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3856ESX-5.0/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDH0005D www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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