1. Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) Internally Organized as 16,384 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5.5V, 2.5V), and 400 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 64-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years • Lead-free/Halogen-free • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Tape and Reel and Bumped Wafers • • • • • • • • • Two-wire Serial EEPROM 128K (16,384 x 8) AT24C128B 2. Description The AT24C128B provides 131,072 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V) version. 8-lead PDIP Table 0-1. Pin Configurations Pin Name Function A0–A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND A0 A1 A2 GND 1 2 3 4 8 7 6 5 8-lead SOIC VCC WP SCL SDA A0 A1 A2 GND 8-lead dBGA2 1 8 VCC 2 7 3 6 4 5 WP SCL SDA 8-lead TSSOP VCC 8 1 A0 WP 7 2 A1 SCL 6 3 A2 SDA 5 4 GND A0 A1 A2 GND 8 7 6 5 1 2 3 4 VCC WP SCL SDA Bottom View Ground 8-lead Ultra Lead Frame Land Grid Array 8-lead Ultra Thin Mini MAP VCC 8 1 A0 VCC 8 1 A0 WP 7 2 A1 WP 7 2 A1 SCL 6 3 A2 SCL 6 3 A2 SDA 5 4 GND SDA 5 4 GND Bottom View Bottom View Rev. 5296A–SEEPR–1/08 3. Absolute Maximum Ratings* *NOTICE: Operating Temperature......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 3-1. Block Diagram VCC GND WP START STOP LOGIC SERIAL CONTROL LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W EN H.V. PUMP/TIMING COMP LOAD DATA RECOVERY INC DATA WORD ADDR/COUNTER Y DEC X DEC SCL SDA EEPROM SERIAL MUX DOUT/ACK LOGIC DIN DOUT 2 AT24C128B 5296A–SEEPR–1/08 AT24C128B 4. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 128K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. 3 5296A–SEEPR–1/08 5. Memory Organization AT24C128B, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages of 64 bytes each. Random word addressing requires a 14-bit data word address. Table 5-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V to 5.5V Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 5-2. DC Characteristics Applicable over recommended operating range from: TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition Min VCC1 Supply Voltage ICC1 Supply Current VCC = 5.0V READ at 400 kHz ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz ISB1 Standby Current (1.8V option) VCC = 1.8V ILI Input Leakage Current VCC = 5.0V VIN = VCC or VSS ILO Output Leakage Current VCC = 5.0V VOUT = VCC or VSS VIL Input Low Level(1) Typ Max Units 5.5 V 1.0 2.0 mA 2.0 3.0 mA 1.0 µA 6.0 µA 0.10 3.0 µA 0.05 3.0 µA − 0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V 1.8 VCC = 5.5V VIN = VCC or VSS (1) VIH Input High Level VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V Notes: 4 1. VIL min and VIH max are reference only and are not tested. AT24C128B 5296A–SEEPR–1/08 AT24C128B Table 5-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.3 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs ti Noise Suppression Time(1) tAA Clock Low to Data Out Valid 0.05 tBUF Time the bus must be free before a new transmission can start(1) 1.3 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Set-up Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 100 100 ns tR Min 2.5, 5.5-volt Inputs Rise Time Max Min 400 100 (1) (1) 0.9 0.05 Max Units 1000 kHz 50 ns 0.55 µs 0.3 0.3 µs 300 100 ns tF Inputs Fall Time tSU.STO Stop Set-up Time 0.6 0.25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time Endurance(1) 25°C, Page Mode, 3.3V Notes: 5 5 1,000,000 ms Write Cycles 1. This parameter is ensured by characterization and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC 5 5296A–SEEPR–1/08 6. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 6-1). Data changes during SCL high periods will indicate a start or stop condition as defined below. Figure 6-1. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 6-2). Figure 6-2. Start and Stop Definition SDA SCL START STOP STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 6-2). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C128B features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 6 AT24C128B 5296A–SEEPR–1/08 AT24C128B cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 6-3. Software Reset Dummy Clock Cycles Start bit SCL 1 2 3 Start bit 8 Stop bit 9 SDA Figure 6-4. Bus Timing tHIGH tF tR tLOW SCL tSU.STA tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 6-5. Write Cycle Timing SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION Note: START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5296A–SEEPR–1/08 Figure 6-6. Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START ACKNOWLEDGE 7. Device Addressing The 128K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. Figure 7-1. Device Address 1 MSB 0 1 0 A2 A1 A0 R/W LSB The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C128B has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC. 8 AT24C128B 5296A–SEEPR–1/08 AT24C128B 8. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-1). Figure 8-1. Note: Byte Write * = DON’T CARE bit PAGE WRITE: The 128K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-2). Figure 8-2. Note: Page Write * = DON’T CARE bit The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue. 9 5296A–SEEPR–1/08 9. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read, and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 9-1). Figure 9-1. Current Address Read RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 9-2). Figure 9-2. Note: Random Read * = DON’T CARE bit SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The 10 AT24C128B 5296A–SEEPR–1/08 AT24C128B sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 9-3). Figure 9-3. Sequential Read 11 5296A–SEEPR–1/08 10. AT24C128B Ordering Information Ordering Code AT24C128B-PU (Bulk Form Only) Voltage Package 1.8 8P3 (1) (NiPdAu Lead Finish) 1.8 8S1 (2) (NiPdAu Lead Finish) 1.8 8S1 (NiPdAu Lead Finish) 1.8 8A2 AT24C128B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2 AT24C128BN-SH-B AT24C128BN-SH-T (1) AT24C128B-TH-B (2) (NiPdAu Lead Finish) 1.8 8Y6 (2) (NiPdAu Lead Finish) 1.8 8D3 AT24C128BU2-UU-T 1.8 8U2-1 AT24C128B-W-11(3) 1.8 Die Sale AT24C128BY6-YH-T AT24C128BD3-DH-T (2) Notes: Operation Range Lead-free/Halogen-free Industrial Temperature (−40°C to 85°C) Industrial Temperature (−40°C to 85°C) 1. “-B” denotes bulk. 2. “-T” denotes and tape and reel. SOIC = 4K. TSSOP, dBGA2, and Mini MAP = 5k. SAP = 3K. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini MAP, Dual No Lead Package, (DFN), (MLP2x3mm) 8D3 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) Options −1.8 12 Low-voltage (1.8V to 5.5V) AT24C128B 5296A–SEEPR–1/08 AT24C128B 11. Part marking scheme 11.1 8-PDIP TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 D B 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 52 = Week 52 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 11.2 WW = SEAL WEEK 02 = Week 2 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-SOIC Seal Year | Seal Week TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 |---|---|---|---|---|---|---|---| 2 D B 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 13 5296A–SEEPR–1/08 11.3 8-TSSOP TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 2 D B Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: WW = SEAL WEEK 2010 2011 2012 2013 1 * 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: 50 = Week 50 |---|---|---|---|---| 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| C 0 0 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator 11.4 C00 = Country or Origin AAA = Atmel Lot Number 8-Ultra Thin Mini-MAP TOP MARK Y = YEAR OF ASSEMBLY |---|---|---| 2 D B |---|---|---| H 1 XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,...AX, AY, AZ) |---|---|---| Y X X |---|---|---| * | Pin 1 Indicator (Dot) Y = 6: 7: 8: SEAL YEAR 2006 0: 2010 2007 1: 2011 2008 2: 2012 9: 2009 14 3: 2013 AT24C128B 5296A–SEEPR–1/08 AT24C128B 11.5 8-ULA TOP MARK Y = YEAR OF ASSEMBLY |---|---|---| 2 D B |---|---|---| Y X XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,...AX, AY, AZ) X |---|---|---| * | Pin 1 Indicator (Dot) Y = 6: 7: 8: BUILD YEAR 2006 2007 2008 Etc... 11.6 dBGA2 TOP MARK LINE 1-------> LINE 2-------> 2DBU PYMTC |<-- Pin 1 This Corner P = COUNTRY OF ORIGIN Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009 M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBER TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK) 15 5296A–SEEPR–1/08 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL A b2 b3 b 4 PLCS Side View L NOM MAX NOTE – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC L Notes: MIN 0.115 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B AT24C128B 5296A–SEEPR–1/08 AT24C128B 8S1 - JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Note: SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 θ 0° – 8° These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C 17 5296A–SEEPR–1/08 8A2 - TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN 2.90 E e D A2 3.00 3.10 2, 5 3, 5 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 L 4 0.65 BSC 0.45 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 18 NOTE E1 L1 Notes: MAX 6.40 BSC e Side View NOM 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT24C128B 5296A–SEEPR–1/08 AT24C128B 8Y6 – MAP D2 A b (8X) E E2 Pin 1 Index Area Pin 1 ID L (8X) D A2 e (6X) A1 1.50 REF. COMMON DIMENSIONS (Unit of Measure = mm) A3 SYMBOL MIN D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 L b NOTE 0.20 REF 0.20 e R MAX E2 A3 Notes: NOM 0.30 0.40 0.50 BSC 0.20 0.25 0.30 2 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) DRAWING NO. 8Y6 10/16/07 REV. D 19 5296A–SEEPR–1/08 8D3 - ULA D 8 7 e1 6 b 5 L E PIN #1 ID 0.10 PIN #1 ID 0.15 1 2 3 4 A1 A TOP VIEW b e BOTTOM VIEW SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 0.40 A1 0.00 – 0.05 D 1.70 1.80 1.90 E 2.10 2.20 2.30 b 0.15 0.20 0.25 SYMBOL e 0.40 TYP e1 1.20 REF L 0.25 0.30 NOTE 0.35 11/15/05 R 20 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe Land Grid Array (ULA) D3 DRAWING NO. 8D3 REV. 0 AT24C128B 5296A–SEEPR–1/08 AT24C128B 8U2-1 - dBGA2 D A1 BALL PAD CORNER 1. b E A1 A2 Top View A A1 BALL PAD CORNER 2 Side View 1 A B e C D (e1) d (d1) COMMON DIMENSIONS (Unit of Measure = mm) Bottom View SYMBOL MIN NOM MAX 8 Solder Balls A 0.81 0.91 1.00 A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.35 BSC 1. Dimension 'b' is measured at the maximum solder ball diameter. E 3.73 BSC This drawing is for general information only. e 0.75 BSC e1 0.74 REF d 0.75 BSC d1 0.80 REF NOTE 1 6/24/03 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2) DRAWING NO. PO8U2-1 REV. A 21 5296A–SEEPR–1/08 Revision History 22 Doc. Rev. Date Comments 5296A 1/2008 AT24C128B product with date code 2008 work week 14 (814) or later supports 5Vcc operation Initial document release AT24C128B 5296A–SEEPR–1/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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